HK1133960A - Multi-modulus divider retiming circuit - Google Patents

Description

Multi-modulus divider retiming circuit

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims priority to provisional application No.60/833,156 filed 2006, 7, 24, § 119 based on 35 u.s.c., which is incorporated herein by reference.

Technical Field

The disclosed embodiments relate to a multi-mode divider (MMD).

Background

Receiver and transmitter circuits within a cellular telephone typically include one or more local oscillators. For example, such a local oscillator may include a Phase Locked Loop (PLL) for receiving a stable but relatively low frequency signal (e.g., 20MHz) from a crystal oscillator and generating an output signal at a selected relatively high frequency (e.g., 900 MHz). The feedback loop of the PLL includes a frequency divider that receives a high frequency signal and divides the high frequency signal to obtain a low frequency signal having the same phase and frequency as the signal from the crystal oscillator.

A divider, referred to herein as a "multi-modulus divider" (MMD), is often used to implement a frequency divider. The MMD receives a high frequency input signal SIN and divides the signal by a divisor value DV to generate a low frequency output signal SOUT. The MMD includes a plurality of Modulus Divider Stages (MDSs) that are linked together to form the MMD. Each MDS (except the last MDS) receives a feedback modulus control signal from the next MDS in the chain. Each MDS also receives a modulus divisor control signal S. The MDS operates in a divide-by-two mode if the modulus divisor control signal S of a particular MDS has a first digital logic value, otherwise the MDS operates in a divide-by-three mode. The modulus divisor control signal values S of the various MDS stages of the MMD together determine the divisor value DV by which the MMD divides.

In many MMD applications, the MMD output signal will have a duty cycle of about fifty percent. The output signal will also have a lower jitter with respect to the high frequency MMD input signal. Each MDS stage introduces an amount of jitter. Due to the cascading of the MDS stages, jitter of the various MDS stages of the MMD accumulates. In one cellular telephone application, including the cellular telephone standard, using the output of the last MDS as the MMD output results in a large amount of accumulated jitter that fails to meet the noise requirements imposed on the MMD by the cellular telephone standard.

One conventional way to solve this problem is to use a jitter-free high frequency MMD input signal to synchronize (to "retime") the jittered low frequency MMD output signal with a high speed flip-flop. This makes the output of the flip-flop almost jitter free. However, this solution typically requires a well-defined phase relationship between the high frequency MMD input signal and the low frequency MMD output signal. Due to the MMD structure, it is difficult to maintain a sufficiently constant phase relationship between the two signals when the divisor value DV is large.

A second conventional approach to solving the jitter problem includes three flip-flops. The first flip-flop synchronizes a modulus control signal used to control the first MDS stage with the high frequency MMD input signal. The modulus control signal is a signal used to determine whether the first MDS stage divides by two or divides by three. The synchronized output of the first flip-flop is provided to the clock input of the second flip-flop. The D input of the second flip-flop is coupled to receive a fixed digital logic high value such that an edge of the synchronized output of the first flip-flop clocks the digital logic high value into the second flip-flop. The remaining inputs of the second flip-flop are coupled to receive a reset signal that is a logical combination of the signal outputs from the MDSs in the middle of the MMD. Thus, the reset signal resets the second flip-flop to a digital logic low. The output of the second flip-flop is provided to the D input of the third flip-flop and the third flip-flop is clocked using the high frequency MMD input signal to synchronize the output of the second flip-flop with the high frequency MMD input signal. The reset input of the third flip-flop is coupled to receive the reset signal. The Q output of the third flip-flop outputs the desired low jitter, low frequency signal with a duty cycle of approximately fifty percent. Unfortunately, this second conventional solution consumes a large amount of power since two of the three flip-flops are clocked using the high frequency MMD input signal as a clock. Therefore, the power consumption is very high.

Disclosure of Invention

A multi-mode divider (MMD) receives an MMD input signal, divides the MMD input signal by a divisor value, and outputs an MMD output signal SOUT. The MMD includes a novel retiming circuit (e.g., sequential logic element) and a chain of Modulus Divider Stages (MDSs). Each MDS receives an input signal, divides it by two or three pairs, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether the MDS divides by two or divides by three. The sequential logic element outputs the MMD output signal SOUT. The modulus control signal of one of the first MDS stages in the chain is used to place the sequential logic element in a first state. The output signal of one MDS in the middle of the chain is used to place the sequential logic element into a second state. In one example, the sequential logic element is a flip-flop. The modulus control signal SETs the flip-flop so that it is in a SET (SET) state and asserts (assert) the output signal SOUT to a digital logic high value. The output signal of the MDS in the middle of the chain RESETs the flip-flop so that it is in a "RESET" state and deasserts (deasserts) the output signal SOUT to a digital logic low value.

It should be appreciated that the modulus control signal used to place the sequential logic element in the first state has a small amount of accumulated jitter relative to the MMD input signal. The modulus control signal is gated (gate) by the low jitter output signal of the preceding MDS in the chain. Because the edges of the pulses of the modulus control signal have a low jitter, the corresponding edges of the output signal SOUT also have a low jitter. Further, it should also be appreciated that the output signal of one of the MDS stages transitions approximately midway between edges of the analog-to-digital signal. Thus, this one MDS stage output signal is used to place the sequential logic element back into the second state approximately midway between each pair of adjacent pulses of the modulus control signal, so that the output signal SOUT has a duty cycle of approximately 50/50.

In one advantageous aspect, the sequential logic elements used to generate the output signals SOUT are not clocked at the higher frequency of the MMD input signals. The signals used to set and reset the sequential logic elements have a longer minimum pulse width than the MMD input signal. Accordingly, the novel retiming circuit consumes significantly less power than a conventional retiming circuit that uses a higher frequency MMD input signal to retime the MMD output signal.

The foregoing is a summary and thus contains, by necessity, simplifications, generalizations, and omissions of detail; accordingly, those skilled in the art will appreciate that the summary is illustrative only and is not intended to be in any way limiting. Other aspects, inventive features, and advantages of the devices and/or methods described herein, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth herein.

Drawings

Figure 1 is a simplified diagram of a mobile communication device, in this example a cellular telephone, in accordance with one novel aspect;

FIG. 2 is a diagram of an RF transceiver integrated circuit within the mobile communication device of FIG. 1;

fig. 3 is a diagram of a local oscillator in the RF transceiver integrated circuit of fig. 2;

FIG. 4 is a diagram of a frequency divider, which is a multi-modulus divider (MMD), of the local oscillator of FIG. 3, the diagram being a diagrammatic view using a logic gate symbol;

FIG. 5 gives a formula indicating in which order the values of S [6:0] should be for the seven-order MMD of FIG. 4 divided by the desired divisor;

FIG. 6 is a diagrammatic view of one MDS of the MMD of FIG. 4;

FIG. 7 is a waveform diagram illustrating the operation of the MMD of FIG. 4;

FIG. 8A is a diagram of a first example of retiming circuit 149 of the MMD of FIG. 4;

FIG. 8B is a simplified waveform diagram showing how the retiming circuit of FIG. 8A generates the MMD output signal SOUT;

FIG. 9A is a diagram of a second example of retiming circuit 149 of the MMD of FIG. 4;

FIG. 9B is a simplified waveform diagram showing how the retiming circuit of FIG. 9A generates the MMD output signal SOUT;

FIG. 10 is a circuit diagram of a differential latch that may be used in the circuit of FIG. 9A instead of and instead of the CML-CMOS buffer 179;

figure 11 is a flow chart of a method in accordance with one novel aspect.

Detailed Description

Figure 1 is a simplified diagram of a mobile communication device 100 in accordance with one novel aspect. The mobile communication device 100 in this example is a cellular telephone. Cellular telephone 100 includes an antenna 101 and several integrated circuits including a novel Radio Frequency (RF) transceiver integrated circuit 102 and a digital baseband integrated circuit 103. Digital baseband integrated circuit 103 includes primarily digital circuitry and includes a digital processor. An example of a digital baseband integrated circuit 103 is MSM6280 available from Qualcomm corporation. The novel RF transceiver integrated circuit 102 includes circuitry for processing analog signals.

Fig. 2 is a more detailed diagram of RF transceiver integrated circuit 102 of fig. 1. The receiver "signal chain" 104 includes a Low Noise Amplifier (LNA) module 105, a mixer 106, and a baseband filter 107. When receiving in GSM (global system for mobile communications) mode, the signal on antenna 101 passes through a switchplexer 108, then through path 109, through SAW 110, and then into LNA 105. When receiving in CDMA (code division multiple access) mode, the signal on antenna 101 passes through Switchplexer 108, through duplexer 111 and through path 112 and then into LNA 105. In all modes, LNA 105 amplifies high frequency signals. A Local Oscillator (LO)113 provides a local oscillator signal of an appropriate frequency to the mixer 106 in order to tune the receiver to receive a signal of the appropriate frequency. The mixer 106 demodulates the high frequency signal down to a low frequency signal. The unwanted high frequency noise is filtered out by a baseband filter 107. The analog output of baseband filter 107 is provided to an analog-to-digital converter (ADC)114 in digital baseband integrated circuit 103. ADC 114 digitizes the analog signal into digital information, which is then further processed by a digital processor in digital baseband integrated circuit 103.

The transmitter "signal chain" 115 includes a baseband filter 115, a mixer 117, and a power amplifier module 118. The digital information to be transmitted is converted to an analog signal by a digital-to-analog converter (DAC)119 within digital baseband integrated circuit 103. The resulting analog signal is provided to baseband filter 116 within RF transceiver integrated circuit 102. Baseband filter 116 filters out unwanted high frequency noise. Mixer 117 modulates the output of baseband filter 116 onto a high frequency carrier. A Local Oscillator (LO)120 provides a local oscillator signal to the mixer 117 so that the high frequency carrier has the correct frequency for the channel being used. The high frequency output of the mixer 117 is then amplified by a power amplifier module 118. When transmitting in GSM mode, power amplifier module 118 outputs a signal on to antenna 101 through switchplexer 108 via path 121. When transmitting in CDMA mode, power amplifier module 118 outputs a signal to duplexer 111 via path 122. The signal passes through duplexer 111, through switchplexer 108, and to antenna 101. A duplexer 111 that allows for communication for non-duplex (e.g., GSM) and for duplex (e.g., CDMA1X) and switchplexer 108 are typically used. The specific circuit of fig. 2 is only one possible implementation given here for the purpose of example.

The operation of local oscillators 113 and 120 is described below in connection with the operation of Local Oscillator (LO)113 in the receiver. Fig. 3 is a more detailed diagram of local oscillator 113. The local oscillator 113 includes a crystal oscillator signal source 123 and a fractional-N Phase Locked Loop (PLL) 124. In this example, the crystal oscillator signal source 123 is a connection to an external crystal oscillator module. Alternatively, the crystal oscillator signal source is an oscillator disposed on RF transceiver integrated circuit 102, where the crystal is external to integrated circuit 102 but connected to the oscillator via terminals of integrated circuit 102.

PLL 124 includes Phase Detector (PD)125, charge pump 126, loop filter 127, Voltage Controlled Oscillator (VCO)128, signal conditioning output divider 129, and novel frequency divider 130 (sometimes referred to as a "loop divider"). The frequency divider 130 receives a frequency divider input signal SIN having a frequency of the first high frequency F1, divides the signal by a divisor D, and outputs a frequency divider output signal SOUT having a frequency of the second low frequency F2. F2 is F1/D when the PLL is locked over multiple count periods of divider 130. When locked, the frequency F2 and phase of the SOUT signal match the frequency and phase of the reference clock signal provided from the crystal oscillator signal source 123.

The frequency divider 130 includes a novel multi-modulus divider (MMD)131, a summer 132, and a sigma-delta modulator 133. During one count period, multi-modulus divider 131 divides frequency divider input signal SIN on input node 134 by divisor value DV and generates frequency divider output signal SOUT on output node 135. The divisor value DV is the sum of the first digital value at the first digital input port 136 of the adder 132 and the second digital value at the second digital input port 137 of the adder 132. Sigma-delta modulator 133 changes the value on second numerical input port 137 over time such that F2 is F1/D over multiple count periods of the MMD.

High-level description of the multi-modulus divider:

fig. 4 is a more detailed illustration of the novel MMD 131 of fig. 3. MMD 131 includes an input buffer 141, a chain of seven multi-mode divider stages (MDS stages) 142 and 148, and a novel retiming circuit 149. The first three MDS stages 142-144 are implemented in Current Mode Logic (CML). The last four MDS stages 145-148 are implemented in Complementary Metal Oxide Semiconductor (CMOS) logic. Buffer and inverter 150 and 153 convert from CMOS logic signals and levels to CML logic signals and levels. Each MDS stage receives an input signal and divides the signal by a divisor of 2 or 3 to frequency divide the signal, and outputs the result as an output signal. In fig. 4, the seven MDS stages are labeled DIV23CELL0 through DIV23CELL 6. The output signals output by the seven MDS stages are labeled O0 through O6, respectively. Each MDS stage of figure 4 can be divided by 2 or by 3 depending on the values of the modulus divisor control signal S and the feedback modulus control signal FMC. Here the letters FMC stand for "feedback modulus control". The divisor value DV by which the total MMD 131 is divided is determined using the values of the seven S modulus divisor control signals S [6:0 ].

FIG. 5 gives a formula indicating in which order the modulus divisor control signals S [6:0] should be for MMD 131 to divide by the desired divisor value DV. For example, if MMD 131 were to be divided by divisor value 181, S [6:0] would be the numerical value [0110101 ].

High level description of one MDS stage:

figure 6 is a simplified diagram of the first MDS stage 142 of the MMD 131 of figure 4. The first MDS stage 142 has a structure that is representative of the structures of the other MDS stages 143-148. First MDS 142 includes a first stage 157 and a second stage 158. First stage 157 includes a D-type flip-flop 159, OR gate 160, exclusive-OR (NOR) gate 161, and buffer 150. The OR gate 160, NOR gate 161, and buffer 150 in fig. 8 are the same as the OR gate 160, NOR gate 161, and buffer 150 shown in fig. 4. In one implementation, the functionality of gates 160 and 161 is incorporated into the circuitry of flip-flop 159, where flip-flop 159 is a CML flip-flop. Second stage 158 includes D-type flip-flop 162 and NOR gate 163. In one implementation, the function of NOR gate 163 is incorporated into the circuitry of flip-flop 162, where flip-flop 162 is a CML flip-flop.

MDS stage 142 receives differential input signals SINBUF and SINBUFB on input leads 164 and 165 and outputs differential output signals O0 and O0B on output leads 166 and 167. Input lead 168 is an input lead for receiving a feedback modulus control signal FMC1 from MDS stage 143. Input lead 169 is an input lead for receiving a modulus divisor control signal S [0], where S [0] is used to determine whether MDS 142 is to be in a "divide-by-2 mode" or a "divide-by-3 mode". Input leads 170 and 171 are used to receive a signal that is used to turn off first stage 159 when the first stage is outputting constant digital logic in an unchanged state. In this case, power is saved by not powering the first stage 159. When first stage 159 is turned off, a transistor (not shown) is used to couple the output lead of first stage 159 to the appropriate digital logic value that flip-flop 159 would output if powered.

In operation, if the modulus divisor control signal S [0] is a digital logic high, then MDS stage 142 is in divide-by-2 mode. On the other hand, if the modulus divisor control signal S [0] is a digital logic low, then MDS 142 is in a "divide by 3 mode".

In the divide-by-2 mode, MDS stage 142 divides the input signal by 2 regardless of the digital logic level of the feedback modulus control signal FMC 1. S [0] is a digital logic high, which causes buffer 150 to provide a digital logic high to the leftmost input lead of NOR gate 161. Therefore, NOR gate 161 outputs a digital logic low regardless of the signal output by OR gate 160. Because this digital logic low signal is the "modulus control signal," it is labeled MC 0B. MC0B is a digital logic low, which results in flip-flop 159 having a clock in digital logic low value. Thus, the signal Q1 output by flip-flop 159 remains at a digital logic low value. Because a digital logic low value is present on the upper input lead of NOR gate 163, NOR gate 163 functions to invert the signal on its lower input lead and provide the inverted signal on the D input lead of flip-flop 162. Accordingly, NOR gate 163 inverts the value output on the Q output lead of flip-flop 162 and provides the inverted signal value back onto the D input lead of flip-flop 162. Thus, flip-flop 162 functions as a toggle flip-flop to divide the frequency of the input signal SINBUF by 2.

In the divide-by-3 mode, MDS 142 is divided by 2 or divided by 3 depending on the state of flip-flop 162 and the logic level of feedback modulus control signal FMC 1. If the feedback modulus control signal FMC1 and the Q2B signal output from flip-flop 162 both have digital logic low levels, MDS 142 is divided by 3 during three subsequent input signal SINBUF periods. If FMC1 and Q2B both have digital logic low values, OR gate 160 outputs a digital logic low value. Thus, both outputs of NOR gate 161 are digital logic low values. NOR gate 161 asserts modulus control signal MC0B to a digital logic high value. The digital logic high value is then clocked into flip-flop 159. When a digital logic high value appears on the Q output lead of flip-flop 159, then the output of NOR gate 163 is forced low. NOR gate 163 outputs a digital logic low value regardless of the digital logic value provided on the lower input lead of NOR gate 163. The digital logic low value on the D input lead of flip-flop 162 is clocked into flip-flop 162, effectively extending the current low pulse period by one clock cycle during flip-flop 162 toggling. The low value of the Q output of flip-flop 162 is used to remove the digital logic low value of Q2B from the upper input lead of OR gate 160, causing OR gate 160 to output a digital logic high value, which causes NOR gate 161 to force analog-to-digital control signal MC0B back to a digital logic low level. Accordingly, the low pulse of FMC1 causes a one-cycle delay to be inserted in the toggling of flip-flop 162. Unlike a conventional flip operation that would result in dividing the input signal SINBUF by 2, a flip operation with one cycle extension effectively divides the input signal SINBUF by 3. In divide-by-3 mode, if MDS stage 142 does not receive a low pulse of signal FMC1, flip-flop 159 always outputs a digital logic low onto the upper input lead of NOR gate 163, and flip-flop 162 of the second stage continues to toggle and perform a divide-by-2 operation. It can thus be seen that the value of the modulus control signal MC0B determines whether MDS 142 is divided by 2 or divided by 3 during the next clock cycle.

MMD and retiming circuit operation:

fig. 7 is a waveform diagram illustrating the operation of the MMD 131 of fig. 4. Signals O0 through O6 are output signals of MDS stages 142 through 148. Signal MC0B is the modulus control signal discussed above in connection with fig. 6. The signals MC0B through MC5B and MC6 are the modulus control signals shown in fig. 4. The input signal SIN provided to the MMD 131 is represented as a block because its frequency is too high for the single transition shown in the waveform diagram of fig. 7. Output signal SOUT is the output signal of novel retiming circuit 149 of fig. 4. The signal labeled DCC is a "duty cycle correction signal" that is used to correct the duty cycle of the analog to digital control signal. One example of a DCC signal is MDS output signal O5.

Figure 8A is a more detailed diagram of one example of retiming circuit 149 of MMD 131 of figure 4. Retiming circuit 149 includes an inverter 172 and a CMOS (complementary metal oxide semiconductor) sequential logic element 173. In this example, sequential logic element 173 is a D-type flip-flop. In addition to inverting the logic value, the inverter 172 converts from the CML signal level to the CMOS signal level. In the example of fig. 8A, the duty cycle correction signal is output signal O5 output from MDS 147.

Fig. 8B is a simplified waveform diagram illustrating the operation of retiming circuit 149 of fig. 8A. When the modulo control signal MC1B transitions high at time T1, a digital logic low value is provided to the asynchronous active low SET input lead 174 of the flip-flop 173. In the example of fig. 4, the modulus control signal MC1B is the CML signal within the second MDS stage 143. When the modulus control signal MC1B transitions high, then flip-flop 173 is asynchronously placed into the first state (i.e., the SET state). In this state, flip-flop 173 asserts signal SOUT on output node 135 to a digital logic high value. Next, at time T3, the output signal O5 output from MDS stage 147 transitions to a digital logic high value. MDS stage 147 is implemented in a CMOS circuit and signal O5 has a CMOS signal level. The low-to-high signal transition of signal O5 at time T3 is provided onto clock input lead 175 of flip-flop 173. The low-to-high signal transition causes flip-flop 173 to clock in a digital logic low value onto the D input lead 176 of flip-flop 173. Thus, flip-flop 173 is placed in the second state (i.e., the RESET state). In this state, flip-flop 173 deasserts signal SOUT on output node 135 to a digital logic low value. Because the low-to-high transition of the signal O5 occurs approximately midway between adjacent high pulses of the analog-to-digital control signal MC1B as shown in fig. 7 (and as shown in the simplified diagram of fig. 8B), the resulting MMD output signal SOUT has a duty cycle of approximately 50/50.

In a conventional MMD retiming circuit, the high speed MMD input signal passed to the MMD is typically the signal used to synchronize the MMD output signal in order to reduce jitter in the MMD output signal. The high speed signal is used for synchronization, which causes the retiming circuit to consume a large amount of power. In one advantageous aspect, it should be appreciated that analog-to-digital control signal MC1B of fig. 4 is a low jitter signal that transitions at the period at which the desired output signal SOUT should transition. Therefore, the MC1B signal is used in the circuit of fig. 8A to switch the logic level of the signal SOUT. The analog-to-digital control signal MC1B is only converted twice during each cycle of the output signal SOUT. The rising edge of the output signal SOUT generated by the retiming circuit of fig. 8A has a lower jitter with respect to the SIN input signal of the MMD 131 because the MC1B modulus control signal has a smaller jitter with respect to the input signal SIN. Because the MDS stage, MDS 143, that generates the MC1B signal is the previous MDS stage in the chain of MDS stages, MC1B has less jitter. Because there is only one previous MDS stage, MDS stage 142, the accumulated jitter caused in the MC1B signal due to the previous MDS stage is small. The circuit of fig. 8A does not include any flip-flops or other sequential logic elements that are clocked with the higher frequency of the MMD input signal SIN. Flip-flop 173 is clocked at the same frequency as the low frequency output signal SOUT and therefore consumes less switching power than sequential logic elements in a conventional MMD retiming circuit, which is clocked with the higher frequency of the input signal SIN. MC1B has substantially no pulse with a pulse width as short as the shortest pulse of the input signal SIN. Because flip-flop 173 is clocked at a lower frequency than SIN and has a longer minimum pulse width than SIN, flip-flop 173 may be implemented in CMOS circuitry. By implementing the sequential logic elements of the retiming circuit in a CMOS circuit, the DC power consumption of the retiming circuit is reduced compared to conventional retiming circuits that include CMLs or other high speed sequential logic elements that consume a larger DC current. Furthermore, this technique of using the modulus control signal to assert the output signal SOUT to a first digital logic level and then using the appropriate MDS stage output signal to deassert the output signal SOUT at the appropriate time does not require any phase relationship between the modulus control signal and the MDS output signal. There is no need for a phase relationship that is difficult to achieve, which simplifies circuit design.

Fig. 9A is a detailed diagram of another example of retiming circuit 149 of MMD 131 of fig. 4. Retiming circuit 149 of fig. 9A includes sequential logic element 177 (in this example, a flip-flop), CMOS inverter 178, and non-inverting CML to CMOS buffer 179.

Fig. 9B is a simplified waveform diagram illustrating the operation of retiming circuit 149 of fig. 9A. When the analog-to-digital control signal MC1B makes a low-to-high transition at time T1, the signal transitions from the CML signal level to the CMOS signal level and is provided to the clock input lead 181 of the flip-flop 177. The low-to-high transition of the signal on the clock input lead 181 of flip-flop 177 causes flip-flop 177 to clock in a digital logic low level onto D input lead 182. This places flip-flop 177 in a first state (i.e., the RESET state) and causes flip-flop 177 to force the MMD output signal SOUT on output node 135 to a digital logic low level. The inverter 178 inverts the MDS output signal O5 such that the rising edge output signal O5 at time T3 is provided as a falling edge to the active low asynchronous SET input lead 180 of the flip-flop 177. The low level of this signal places flip-flop 177 in the second state (i.e., the SET state) at time T3 and forces MMD output signal O5 to a digital logic high level. Thus, the example of retiming circuit 149 of fig. 9A utilizes the same technique of using a modulus control signal to assert the output signal SOUT to a first digital logic level (in this example, a digital logic low level) and then, at an appropriate time, using the output signal of the appropriate MDS stage to deassert the output signal SOUT to a second digital logic level (in this example, a digital logic high level) such that the signal SOUT has a duty cycle of approximately 50/50.

FIG. 10 is a circuit diagram of a differential latch that can be used in the circuit of FIG. 9A instead of the CML to CMOS buffer 179. The difference in impedance between node 183 providing the impedance of conductor 185 and node 184 providing the impedance of conductor 185 is dependent on the differential voltage between the MC1B and MC1 input leads of the differential latch. For example, if the voltage on the input lead of MC1B were to increase relative to the voltage on node MC1, the voltage on node 183 would decrease. This reduction reduces the voltage on the gate of P-channel transistor 186. P-channel transistor 186 will be made more conductive which in turn increases the voltage on node 184. Due to the cross-coupled nature of P-channel transistors 186 and 187, P-channel transistor 186 will be made more conductive than P-channel transistor 187. The difference between node 183 providing the impedance of conductor 185 and node 184 providing the impedance of conductor 185 enhances the effect of the different conductance of transistors 188 and 189. In this sense, the circuit can be considered to have a latching characteristic. The retiming circuit of fig. 9A, using the differential latch of fig. 10, is derived by simulation, consuming less than 3 milliamps for synchronizing the same MMD output signal, as compared to a conventional retiming circuit, which would consume about 10 milliamps of current to retime an MMD output signal of a particular frequency. The differential latch receives signals having CML signal levels on input leads 190 and 191 and outputs signals having CMOS logic levels onto output lead 192.

Figure 11 is a flow chart of a method in accordance with one novel aspect. A multi-modulus divider (MMD) is used (step 200) to perform a frequency division operation. The MMD consists of a chain of elements divided by 2/3. Each divide-by-2/3 cell is responsive to its own modulus control signal that controls whether the divide-by-2/3 cell is a divide-by-2 or a divide-by-3 cell. In one example, MDS stage 142-148 of figure 4 is a divide-by-2/3 unit. The MMD output signal SOUT is generated by placing a sequential logic element in a first state using (step 201) one of the modulus control signals, and the MMD output signal SOUT is generated by placing the sequential logic element in a second state using (step 202) the divide 2/3 cell output signal. In one example, the modulus control signal used to place the sequential logic element in the first state is modulus control signal MC1B identified in FIG. 4, and the output signal used to place the sequential logic element in the second state is output signal O5 identified in FIG. 4. When the sequential logic element is in a first state, the sequential logic element forces the output signal SOUT to a first digital logic level. When the sequential logic element is in the second state, the sequential logic element forces the output signal SOUT to the second digital logic level. In operation of the multi-mode divider, the sequential logic element is alternately placed in a first state and a second state, such that the SOUT signal repeatedly transitions between the first and second digital logic levels and has a duty cycle of approximately 50/50.

Although certain specific embodiments are described above for instructional purposes, the teachings of this patent document are of general applicability and are not limited to the specific embodiments described above. Although the illustrated example uses one particular modulus control signal MC1B to place the sequential logic elements of the retiming circuit in the first state, other modulus control signals (e.g., another one of MC0B through MC 5B) may be used. Although the illustrated example uses one particular MDS output signal O5 as the duty cycle correction signal, other MDS output signals may be used. In some applications, a duty cycle correction signal that is a combinational logic function of the plurality of MDS output signals may be used. The retiming circuit may be followed by other signals that clock the sequential logic elements with the low frequency signal. Although the retiming circuit described above employs flip-flops as its sequential logic elements, other embodiments of the novel retiming circuit may employ latches as their sequential logic elements. Accordingly, various modifications, adaptations, and combinations of the various features of the described specific embodiments can be practiced without departing from the scope of the claims that are set forth below.

Claims (21)

1. A multi-modulus divider (MMD), comprising:

a chain of divide 2/3 cells, wherein each divide 2/3 cell in the chain receives an input signal and outputs an output signal, wherein each divide 2/3 cell in the divide 2/3 cell is responsive to a modulus control signal for controlling whether the divide 2/3 cell is a divide by 2 or a divide by 3; and

a sequential logic element, wherein a change in one of the modulus control signals causes the sequential logic element to be placed in a first state, and wherein a change in one of the output signals causes the sequential logic element to be placed in a second state.

2. The MMD of claim 1, wherein the sequential logic element has an input lead, and wherein the one of the modulus control signals is provided to the sequential logic element via the input lead.

3. The MMD of claim 1, wherein the sequential logic element has an input lead, and wherein an inverted version of the one of the modulus control signals is provided to the sequential logic element via the input lead.

4. The MMD of claim 1, wherein the sequential logic element has input leads, and wherein the one of the output signals is provided to the sequential logic element via the input leads.

5. The MMD of claim 1, wherein the sequential logic element has an input lead, and wherein an inverted version of the one of the output signals is provided to the sequential logic element via the input lead.

6. The MMD of claim 1, further comprising:

a differential latch having an input lead and an output lead, the input lead coupled to receive the one of the modulus control signals, and wherein the output lead of the differential latch is coupled with an input lead of the sequential logic element.

7. The MMD of claim 1, wherein the sequential logic element has an output lead, wherein the sequential logic element outputs an MMD output signal to the output lead, and wherein a duty cycle of the MMD output signal is approximately 50/50.

8. The MMD of claim 1, wherein the one of the modulus control signals is a modulus control signal for controlling whether one of the divide-by-2/3 cells divide-by-2/3 cells is a divide-by-2 or a divide-by-3.

9. The MMD of claim 1, wherein the MMD receives an MMD input signal having a frequency F, divides the MMD input signal, and outputs an MMD output signal, wherein the MMD input signal is received on the divide-by-2/3 CELL DIV23CELL0, and wherein the sequential logic element does not receive any signal having a frequency equal to or greater than F.

10. The MMD of claim 1, wherein a first portion of the MMD is implemented in a CML (current mode logic) logic circuit, and wherein a second portion of the MMD is implemented in a CMOS (complementary metal oxide semiconductor) logic circuit, and wherein the sequential logic elements are implemented in CMOS logic circuits.

11. A method, comprising:

(a) performing a divide operation using a chain of divide-by-2/3 cells, wherein each divide-by-2/3 cell receives an input signal and outputs an output signal, wherein each divide-by-2/3 cell divides by 2/3 cell is responsive to a modulus control signal for controlling whether the divide-by-2/3 cell divides by 2 or by 3;

(b) placing a sequential logic element in a first state using one of the modulus control signals; and

(c) placing the sequential logic element in a second state using one of the output signals.

12. The method of claim 11, wherein the one modulus control signal used in step (b) is a modulus control signal for controlling whether a first one of the divide-by-2/3 cells divide-by-2/3 cells is a divide-by-2 or a divide-by-3.

13. The method of claim 11, wherein the one modulus control signal used in step (b) is a modulus control signal for controlling whether a second one of the divide-by-2/3 cells divide-by-2/3 cells divide-by-2 or divide-by-3.

14. The method of claim 11, wherein step (b) comprises providing the one of the modulus control signals to a first input lead of the sequential logic element, and wherein step (c) comprises providing the one of the output signals to a second input lead of the sequential logic element.

15. The method of claim 11, wherein step (b) comprises placing the sequential logic element in the first state in response to the one of the modulus control signals transitioning from a first digital logic level to a second digital logic level.

16. The method of claim 11, wherein step (c) comprises placing the sequential logic element in the second state in response to the one of the output signals transitioning from a first digital logic level to a second digital logic level.

17. A circuit, comprising:

a chain of modulus divider stages constituting a divider, wherein the divider is capable of dividing an input signal by an optional divisor value to output an output signal, wherein each of the modulus divider stages performs a divide-by-2 operation or performs a divide-by-3 operation; and

means for generating the output signal, wherein the duty cycle of the output signal is approximately fifty percent, and wherein the means receives an analog-to-digital control signal from the chain and causes the output signal to transition to a digital logic level in response to the transition of the analog-to-digital control signal.

18. The circuit of claim 17, wherein the input signal comprises pulses having a first pulse width, and wherein the modulus control signal comprises substantially no pulses having a pulse width as short as the first pulse width.

19. The circuit of claim 17, wherein the input signal has a frequency F, and wherein the means for generating the output signal does not receive a signal having a frequency of F or greater.

20. The circuit of claim 17, wherein the analog-to-digital control signal is only converted twice during each period of the output signal.

21. The circuit of claim 17, wherein the means for generating the output signal does not receive a signal that transitions more than twice during each cycle of the output signal.