HK1131469B - Epitaxial silicon germanium for reduced contact resistance in field-effect transistors - Google Patents

Description

Epitaxial silicon germanium for reducing contact resistance in field effect transistors

Technical Field

The invention relates to a silicon germanium region in a field effect transistor.

Background

In semiconductor devices, silicide metals are typically formed on semiconductor regions to reduce resistance. At the interface between the silicide and the semiconductor, such as silicon, the schottky barrier is the source of resistance. This can be reduced by lowering the band gap, as is present when silicon germanium (SiGe) is used as the material in which the silicide (silicide) and salicide (salicide) are formed. The use of SiGe source and drain regions and a silicide nickel metal (nickel silicide metal) is described in us patent 6949482. The bandgap diagrams and related text in this patent describe the advantages of using nickel silicide, in particular, on SiGe. (see FIGS. 5, 6, and 7, and related text.)

It is known that performance in PMOS transistors may be improved when uniaxial compressive strain is applied directly to the channel region of the transistor from, for example, embedded SiGe source and drain regions. It is also known that performance improvement can be obtained in NMOS transistors when uniaxial tensile strain is applied to the channel. This aspect is described in application Ser. No. 11/323688, assigned to the assignee of the present application, "A tension Strained NMOS Transistor Using Group III-N Source/Drain regions", filed on 29.12.2005.

Drawings

Fig. 1 is a two-stage cross-sectional elevation view of an upper portion of a silicon substrate in which isolation trenches are formed.

Figure 2 shows the structure of figure 1 with a gate structure and a recess etched into the silicon adjacent to the gate structure.

Fig. 3 shows the structure of fig. 2 after SiGe source and drain regions have been grown in the recesses.

Fig. 4 shows the structure of fig. 3 during ion implantation of an n-channel transistor after masking the p-channel transistor.

Fig. 5 shows the structure of fig. 3 in an alternating process, wherein after the masking step, a portion of the material in the isolation trenches is etched.

Figure 6 shows the structure of figure 5 after forming a silicide on the source and drain regions.

Fig. 7 shows another embodiment in which SiGe does not enter the recess for the n-channel transistor.

Detailed Description

A method for fabricating p-channel and n-channel transistors is described in which silicon germanium (SiGe) source and drain regions are used and silicides are formed in these regions. In the following description, numerous specific details are set forth, such as implant levels, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known manufacturing processes have not been described in detail in order not to unnecessarily obscure the present invention.

In fig. 1, an upper portion of a single crystal silicon substrate is shown. Two separate segments identified as 10a and 10b in the substrate are shown. As will be described, in the segment 10a, an n-channel transistor is formed in the region 15. In substrate segment 10b, a p-channel transistor is fabricated in region 16. The region 15 is delimited by two isolation trenches 11 and 12. Similarly, the region 16 is delimited by two isolation trenches 13 and 14. The trenches 11-14 are shallow isolation trenches formed by etching in the upper region of the substrate and filling the trenches with a dielectric. In some cases, after the trenches are etched, silicon dioxide is grown to form a dielectric liner in the trenches. These trenches may then be filled with a material such as deposited silicon dioxide.

In fig. 1, only half of each of the four trenches 11-14 is shown. As will be discussed, in some of the embodiments described below, the material filling the trench is etched. In some cases, the material is etched over the entire trench, while in other cases, the etching is performed over less than the entire width of the trench. The trench widths shown in the drawings are not drawn to scale, for example, they are not to scale with gate structures. For convenience, the trenches are illustrated as being much narrower than in an actual integrated circuit, relative to the gate structure.

Gate structures are formed in regions 15, 16, etc. of the substrate. Each of the resulting gate structures shown in fig. 2 includes a gate dielectric 21 separating the gate 20 from the channel region in the substrate and a hard mask 23 over the gate 20. Sidewall spacers 22 are provided on both sides of the gate 20. Processing steps such as n-type and p-type dopant tip implants (tip implants) and the formation of sidewall spacers are not described herein. These steps are known in the prior art. In addition, the particular gate structure shown is by way of example only and is not critical to the invention.

After the gate structure is formed, recesses 30 are etched into the silicon substrate at the locations of the source and drain regions of the n-channel and p-channel transistors. In fig. 2, the recess 30 extends substantially from the gate structure to the isolation trench. Note that the recess 30 in each case extends slightly below the sidewall spacer and is bounded by the isolation trench.

Epitaxial growth is now used to grow the SiGe source and drain regions for both n-channel and p-channel transistors. The source and drain regions may be raised above the original height of the substrate as shown. Note that these regions are directly adjacent to the isolation trenches.

The growth of SiGe in the recesses causes compressively strained channel regions for both the n-channel and p-channel transistors. In the case of a p-channel transistor, this strain is beneficial because it can improve hole mobility in the transistor. However, in the case of an n-channel transistor, the same strain may deteriorate electron mobility. However, once the silicide or salicide is formed, both n-channel and p-channel transistors will benefit from the lower silicide barrier height associated with SiGe.

Fig. 4 illustrates a process to relieve strain on the channel region of an n-channel transistor while leaving strain on a p-channel transistor. First, a mask (masking member), which may be a photoresist 41, is formed over the p-channel transistors, covering the source and drain regions of these transistors. Ions 40 are then implanted into the SiGe source and drain regions of the n-channel transistor to create dislocation defects that act as relaxed sites within the SiGe, as shown in fig. 4. This reduces the strain on the channel region, thus improving electron mobility in the channel region. The ion bombardment can be relatively shallow because the channel region of the n-channel transistor is close to the silicon surface (directly under the gate insulator) and, therefore, there is no need to disrupt the crystal lattice deep in the recesses. The implanted ions are not nominally charge carriers and therefore do not affect the semiconductor properties of the source and drain regions. For example, carbon may be used. An implant energy level of 0.5-1.5Kev is sufficient, with a dose of about 1E16-5E16 atoms per square centimeter.

After this implantation, a silicide is formed in the usual way, for example with nickel. Lattice damage to the n-channel source and drain regions facilitates silicide formation as compared to the drain and drain regions of a p-channel transistor.

As shown in fig. 4, the entire isolation trench 13 is contained under the mask, while only half of the isolation trench 14 is under the mask 41. This indicates that the alignment of the mask to the isolation regions is not critical to this embodiment. It is important to protect the SiGe source and drain regions of the p-channel transistor from implantation.

In an alternative embodiment, stress in the n-channel transistor is relieved by removing some or all of the material in the isolation trench. Referring to fig. 5, a mask (mask 50) is also placed over the p-channel transistors. The trenches defining the n-channel transistors, such as trenches 11 and 12 of figure 5, are at least partially exposed. The material in the trench, such as silicon dioxide, is then etched from the photo-path using an isotropic or anisotropic etching process. As shown by openings 52 and 53 in fig. 5, it is not necessary to etch away all of the material at the bottom of the trench. Except that the strain in the channel region near the surface needs to be relieved.

In the case where an isolation trench separates an n-channel transistor from a p-channel transistor, etching the entire width of the trench may relieve strain on both the p-channel and n-channel transistors. This would eliminate one of the benefits of using SiGe in p-channel transistors, specifically the higher hole mobility caused by the strained channel.

In this case, the mask should prevent the entire trench from being etched. For example, mask 51 of fig. 5 protects a portion of the material in trench 11. Similarly, the mask 50 protects a portion of the trench 14. Specifically, when an anisotropic etchant is used, masks 50 and 51 prevent all of the material filling trenches 14, 11, respectively, from being etched away. Therefore, if a p-channel transistor is provided on the side of the isolation region 11 opposite to the n-channel transistor shown in fig. 5, the strain in the channel thereof is not relieved. Similarly, opening 55 may relieve strain in an n-channel transistor disposed on a side of trench 14 opposite region 16. In the case where the p-channel transistors do not share an isolation trench with the n-channel transistors, or where the entire trench can be etched for some reason, the mask need not fall onto the trench. This is represented in fig. 5 by the trench 12.

As shown in fig. 6, once the strain has been relieved from the channel region of the n-channel transistor, a silicide 57 may be formed on the SiGe surface. The trenches are then refilled, for example with an interlayer dielectric (ILD). This refilling of the trench does not create strain on the channel. Note that in fig. 6, openings 52 and 53 have been refilled with medium 58.

In fig. 7, an additional embodiment is shown. Rather than forming a recess for the n-channel transistor, the silicon is doped as shown by the source and drain regions 62 of the n-channel transistor on the substrate segment 10 a. For a p-channel transistor, a recess such as that shown in FIG. 2 is etched for the embodiment of FIG. 7. SiGe is then epitaxially grown, forming a region 60 for p-channel transistors and a region 63 for n-channel transistors. Region 63 is taller than the height of the channel region and therefore does not induce strain on the channel region of an n-channel transistor. Silicide 65 is also formed on the SiGe surface as is the case in other embodiments. Thereby obtaining the benefits of reduced silicon/silicide resistance that are obtained in other embodiments.

Thus, various procedures to relieve strain in n-channel transistors using SiGe source/drain regions have been described above. This allows the advantages of using a silicide formed of SiGe on both p-channel and n-channel transistors to be exploited.

Claims (12)

1. A method of fabricating n-channel and p-channel transistors, comprising:

forming a recess in the silicon substrate for source and drain regions of the n-channel and p-channel transistors adjacent to the gate structure;

growing SiGe in the recess part to form a source region and a drain region of the n-channel and p-channel transistors; and

the strain in the channel region of the n-channel transistor due to the growth of the SiGe is relieved by etching dielectric material from isolation trenches provided on one side of the source region and one side of the drain region of the n-channel transistor, but does not affect the strain in the channel region of the p-channel transistor.

2. The method of claim 1 wherein not all of the dielectric in all of the trenches is etched.

3. The method of claim 1, comprising forming a metal silicide on the source and drain regions.

4. The method of claim 3, wherein the metal silicide comprises nickel.

5. A method of forming an n-channel transistor, comprising:

forming an isolation trench filled with a dielectric material in a silicon substrate;

growing SiGe epitaxial source and drain regions in recesses formed in the substrate adjacent to the isolation trenches;

etching the dielectric material from at least a portion of the trenches to relieve strain in the SiGe source and drain regions; and

and forming metal silicide on the source region and the drain region.

6. The method of claim 5, wherein the metal silicide is formed with nickel.

7. The method of claim 6 wherein said dielectric material in said trench is silicon dioxide.

8. The method of claim 5, comprising: masking a portion of at least one of the trenches such that the masked portion of the trench is not etched while the exposed portion of the trench is etched.

9. An integrated circuit having n-channel and p-channel transistors, comprising:

strain inducing means for inducing strain in both the source and drain regions of the n-channel and p-channel transistors; and

strain relief means for preventing strain in the source and drain regions of the n-channel transistor from causing strain on the channel region of the n-channel transistor without impeding strain in the channel region of the p-channel transistor, the strain relief means comprising isolation trenches provided on one side of the source and drain regions of the n-channel transistor that are recessed relative to isolation trenches provided on one side of the source and drain regions of the p-channel transistor.

10. The integrated circuit of claim 9, wherein the strain inducing devices are SiGe source and drain regions.

11. The integrated circuit of claim 9, comprising a metal silicide on source and drain regions of the n-channel and p-channel transistors.

12. The integrated circuit of claim 10, comprising a metal silicide on SiGe source and drain regions of the n-channel and p-channel transistors.