HK1130990B - Led current controller and method therefor - Google Patents

Description

LED current controller and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

Background

In the past, the semiconductor industry utilized various methods and structures to fabricate boost-mode drive circuits for Light Emitting Diodes (LEDs). Boost mode drive circuits are used to regulate the current through the LED in order to control the light intensity of the LED. For some applications, the boost mode driver circuit has a control pin that is pulsed to control the current and thus the light intensity of the LED. During operation, there is a current spike or inrush current. In some cases, the inrush current interferes with the control circuit operation and reduces the accuracy of the current control. The inrush current increases the power consumption of the system and may also cause undesirable electromagnetic radiation (EMI).

Therefore, it is desirable to have an LED controller that minimizes inrush current, minimizes EMI, and more accurately controls the current through the LED.

Disclosure of Invention

According to an aspect of the present invention, there is provided a current controller for an LED, comprising: a switch control circuit configured to form a switch drive signal to control a current through an LED in response to a sense signal representative of the current through the LED; a first control circuit configured to receive a control signal and responsively activate the switch control circuit to form the switch drive signal, the control signal having a first state during a first time interval and a second state during a second time interval; an error amplifier coupled to receive the sense signal and form an error signal; and a sample and hold circuit configured to sample a value of the error signal in response to a first portion of a first time interval during which the control signal is in a first state and hold the value of the error signal in response to a portion of a second time interval during which the control signal is in a second state to form a held value of the error signal, the sample and hold circuit configured to couple the held value to the switch control circuit in response to a second portion of a first time interval during which the control signal is in the first state and to couple the error signal to the switch control circuit after the second portion of the first time interval.

According to another aspect of the invention, there is provided a method of forming a current controller for an LED, comprising the steps of: coupling a control circuit to control the sample and hold circuit; the control circuit is configured to receive a control signal and responsively control the sample and hold circuit to sample an input signal received at an input of the sample and hold circuit in response to a portion of a first state of the control signal, to hold the sampled value of the input signal in response to a second state of the control signal to form a held value, and to couple the held value to an output of the sample and hold circuit for a first time interval after the control signal transitions to the first state.

Drawings

Fig. 1 schematically illustrates an embodiment of a portion of an LED system including an LED controller according to the present invention;

FIG. 2 is a graph showing some of the signals of the LED controller of FIG. 1 in accordance with the present invention; and

fig. 3 schematically shows an enlarged plan view of a semiconductor device including the LED controller of fig. 1 according to the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. As used herein current carrying electrode means an element of a device that carries current through the device, such as a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode; the control electrode represents an element of the device that controls the current through the device, such as the gate of a MOS transistor or the base of a bipolar transistor. Although these devices are explained herein as certain N-channel or P-channel devices, one of ordinary skill in the art will recognize that complementary devices are also possible in accordance with the present invention. Those skilled in the art will recognize that the word "during …, at …, at …" as used herein is not an exact term to indicate that an action occurs immediately when the onset action occurs, but rather that there may be some small and reasonable delay, such as a propagation delay, between reactions initiated by the initial action.

Detailed Description

Fig. 1 schematically illustrates an embodiment of a portion of an LED system 10 including an exemplary form of a boost mode LED controller 27. In an exemplary embodiment, controller 27 includes a sample and hold circuit that samples the input signal and holds the sampled value of the input signal to form a held value in response to a state of the control signal and couples the held value to the output for a first time interval after the control signal transitions to another state. System 10 generally receives power from a DC power source, such as a battery, between a power input terminal 11 and a power return terminal 12. The system 10 is generally configured to control the value of the current 14 flowing through the LED (e.g., the plurality of LEDs 16 and 17) in order to control the intensity of the light produced by the LEDs 16 and 17. The system 10 may also include a storage inductor 19, a rectifier such as a diode 21, a storage capacitor 22, a power switch such as a transistor 24, and a current sensing element such as a resistor 23.

Controller 27 may receive operating power between a voltage input 28 and a voltage return 29, typically connected to terminals 11 and 12, respectively. Controller 27 is configured to receive a control signal on control input 30 and form a switch drive signal on output 31 having a series of pulses with a duty cycle that varies in response to the control signal on input 30 and in response to a sense signal received on input 32 to control transistor 24 and form current 14 to a desired value. The switching of transistor 24 also causes the current 20 supplied by the power supply connected between terminals 11 and 12 to change. In a preferred embodiment, transistor 24 switches at a frequency of no greater than about two megahertz (2 Mhz). The sense signal received on input 32 is representative of the value of current 14. An exemplary form of controller 27 includes a timing control circuit or timing controller 48, a switch control circuit 37, a reference generator or reference 52, an error amplifier 54, a sample/hold circuit 59, and a sample/hold logic circuit or sample/hold logic 74. In most embodiments, controller 27 also includes a soft-start circuit or soft-start 53 and an internal voltage regulator 35, internal voltage regulator 35 being coupled between input 28 and return 29 to receive the voltage from input 28 and form an internal operating voltage on output 36 suitable for operating elements of controller 27, such as elements of logic 74. Circuit 37 generally includes a clock generator or clock 38, control logic such as an and gate 39, a ramp generator or ramp 42, a comparator 43, a latch 44, and a buffer driver 46. The exemplary form of sample/hold logic 74 includes a delay circuit or delay 76, an inverter 77, an or gate 83, a latch 85, an and gate 87, an inverter 90, and gates 89 and 91, and timing circuits such as one-shot (one-shots)78, 81, 82, and 86. The sample/hold circuit 59 includes a buffer amplifier 61, a sampling capacitor 67, a reference generator (ref)73, a sample/hold amplifier 68, an inverter 71, and a plurality of switches, such as transistors 62, 63, 64, 65, and 66.

Fig. 2 is a graph with plots of some of the signals during operation of controller 27. The abscissa represents increasing time and the ordinate of each curve represents increasing values of the signal shown. Curve 100 shows the received control signal on input 30. Curves 102 and 103 show the start-up PWM control signal (EP) and the sampling control Signal (SC) formed on outputs 49 and 50, respectively, of controller 48. Curves 104 and 105 show the state of signals received by the set and reset inputs, respectively, of latch 85, while curve 106 shows the state of the Q output of latch 85. Curve 107 shows the output of one-shot 86. Plot 108 shows the sample select control signal (SS) formed by gate 87 on node 70, while plot 109 shows the sample/hold (SH) control signal formed by gate 89 on node 60. Curve 112 shows the error signal on output 55 of amplifier 54, curve 113 shows the sampled error signal on output 69 of amplifier 68, and curve 114 shows the combined error signal on output 72 of circuit 59. Curve 115 shows the sensed signal on input 32 and curve 116 shows current 20. The signal illustrated by the curve 100 and 109 is a digital signal and the signal illustrated by the curve 112 and 116 is an analog signal. This description refers to fig. 1 and 2.

The control signals on input 30 are used to enable and disable controller 27 in addition to controlling the intensity of light from LEDs 16 and 17. As shown by curve 100, the control signal is pulsed at a particular frequency that is generally less than the frequency of clock 38. For example, the clock signal of clock 38 may have a frequency of approximately two (2) Mhz and the control signal may have a frequency of approximately one (1) Khz. The length of time that the control signal operates at the above-described frequencies determines the amount of light produced by LEDs 16 and 17. When the control signal goes high, controller 27 begins forming a switch drive signal to regulate the value of current 14. Controller 27 continues to form the switch drive signal as long as the control signal continues to transition. Thus, the longer the duration of the pulse of the control signal, the more intense the light emitted by the LEDs 16 and 17. As shown at time T6, when the control signal on input 30 is low for an extended period of time (referred to as a timeout period), controller 27 stops generating the switch drive signal and prevents current 14 from flowing through LEDs 16 and 17. A timeout period typically occurs if the control signal remains low for longer than the period of the control signal. In a preferred embodiment, the timeout period is approximately two hundred and fifty microseconds.

The controller 27 is configured to operate in two modes of operation, a soft start mode and a normal mode, controlled by a control signal. When the control signal goes high after being low for at least the timeout period, the controller 27 begins operating in the soft-start mode, shown between times T0 and T1. In the soft start mode, controller 48 does not convert the SC signal and the SS signal at node 70 remains low to couple the output of amplifier 54 to comparator 43. After the soft start mode is terminated at about time T1, controller 27 begins operating in the normal mode and begins switching SC to follow the control signal. The soft start mode typically continues until the sense signal on input 32 reaches a steady state. In a preferred embodiment, the soft start mode continues until the sense signal reaches approximately two hundred and fifty millivolts. As will be seen further hereinafter, in the normal mode, circuit 59 is configured to operate in either the sampling phase or the holding phase in response to a corresponding valid or invalid value of the sample/hold control Signal (SH) formed by logic 74 on node 60. Additionally, circuit 59 is configured to bypass the sample/hold portion of circuit 59 and select output 55 of amplifier 54 to comparator 43 in response to an invalid value of the sample select control signal (SS) formed on node 70 by logic 74, and select the sample signal on output 69 of amplifier 68 to comparator 43 in response to an valid value of SS.

In operation, assuming that the control signal remains low for a time greater than the timeout period, the controller 27 begins operating in the soft start mode when the control signal first goes high to begin the light control cycle. Controller 48 forces the enable PWM signal (EP) on output 49 high to enable circuit 37 to generate the switch drive signal on output 31. The controller 48 holds EP high to generate the switch drive signal until the control signal goes low and remains for at least the timeout period. Logic 74 holds the SS signal on node 70 low during the soft start mode to avoid placing circuit 59 in the hold phase during the soft start mode of operation. The high EP signal enables gate 39 and enables circuit 37 to form the switch drive signal. The high EP signal also enables reference 52 to provide a reference signal to the non-inverting input of amplifier 54 via soft starter 53. Soft-start 53 receives the reference signal and gradually increases the value of the reference signal applied to error amplifier 54 during the time of the soft-start mode to gradually increase the value of current 14. The high EP signal also enables one-shot 82, which resets latch 85 and forces the SS signal on node 70 low. The low SS signal bypasses the sample/hold portion of circuit 59 by enabling transistor 66 to couple output 55 of amplifier 54 to output 72 and to comparator 43. Error amplifier 54 receives the sense signal from input 32 and forms an error signal representing the difference between the value of the sense signal and the slowly increasing reference signal from soft-starter 53, thereby slowly increasing current 14. The high SC signal is received by inverter 77 at time T0, forcing the output of inverter 77 low. This has no effect on one-shot 78 or latch 85. The SC signal also propagates through delay 76 and triggers one-shot 81 to force the reset input of latch 85 high, which has no effect because the EP signal has previously reset latch 85. The SC signal also triggers one-shot 86 (curve 107), which has no effect on gate 87 or node 70 because latch 85 has been reset. The SC signal delayed by delay 76 forces the output of gate 89 and the SH control signal on node 60 high as shown by plot 109. The high SH signal forces the output of inverter 90 low and the output of gate 91 low to disable transistor 64. The high SH signal also enables transistors 62 and 63 to couple the error signal from amplifier 54 to one side of capacitor 67 and to couple the output of amplifier 68 to the other side of capacitor 67. This is a sampling pattern that charges capacitor 67 to a value that is approximately equal to the value of reference 73 (Vref) minus the dc value of the error signal from output 55 (Vref-V1, where V1 is the dc value of the error signal on output 55). During the soft start period, SC is held high to ensure that the error signal applied from amplifier 54 reaches its full value and charges capacitor 67 to the same full value.

After the soft start period expires at about time T1, controller 48 converts the sampling control Signal (SC) on output 50 into a conversion of the tracking control signal. It has been found that each transition of the control signal after the soft start period has expired disturbs the value of the error signal formed by amplifier 54 and causes a change in the value of current 14. This also causes an inrush current of current 20 originating from the voltage source connected to terminal 11. These inrush currents cause EMI that interferes with the operation of other circuits connected to the terminal 11. Circuitry 59 and logic 74 are configured to minimize these variations. Sample/hold logic 74 and sample/hold circuit 59 are configured to minimize overshoot in the error signal received by comparator 43 for each subsequent transition of the control signal received on input 30. After the soft start period, the SC starts following the control signal and becomes low at time T2 in response to the control signal. The low SC signal forces the output of inverter 77 high and sets latch 85 forcing the Q output high which has no effect on node 70 because one-shot 86 is still low. The low SC signal propagates through delay 76 and forces the output of gate 89 and node 60 low to cause circuit 59 to transition to hold mode in a manner that enables transistor 64 by disabling transistors 62 and 63 and forcing the output of gate 91 high. Disabling transistors 62 and 63 and enabling transistor 64 causes circuit 59 to hold on node 69 (V1- (Vref-V1)) ═ V1, and therefore, when node 60 goes low, the value on output 55 is held. Node 70 remains low and transistor 66 remains enabled to couple the error signal on output 55 to output 72 and comparator 43.

The next control signal goes high at approximately time T3, which forces the SC signal of controller 48 high. The high SC signal enables one-shot 86, which one-shot 86 forces SS on node 70 high because latch 85 is set. SS being high disables transistor 66 and enables transistor 65 to couple the stored error signal from output 69 of amplifier 68 to comparator 43. After expiration of the timeout of one-shot 86, SS goes low to enable transistor 66 and disable transistor 65, and the error signal from amplifier 54 is coupled to comparator 43. This facilitates the use of the stored value of the error signal during and just after the rising edge of the control signal and minimizes the disturbance to the error signal used by comparator 43. Thus, the timeout of one-shot 86 is selected to be greater than the amount of time that the error signal from amplifier 54 is disturbed after the rising edge of the control signal. Using the stored value of the error signal (V1) for a time interval after the rising edge of the control signal before going to the value on the use output 55 helps to minimize the disturbance to the error signal received by comparator 43. The high SC signal from controller 48 also propagates through delay 76 and then activates one-shot 81 to reset latch 85. Note that the delay of delay 76 is at least equal to the period of one-shot 86 to ensure that latch 85 does not reset SS until after one-shot 86 times out and before the disturbance to the error signal ends. The high from delay 76 also forces node 60 high to restart the sampling phase of circuit 59, as shown at time T4. During the sampling phase, transistors 62 and 63 are enabled and transistor 64 is disabled, which causes output 69 of amplifier 68 to be at the value of Ref 73. The value of Ref73 is applied by output 69 to one side of capacitor 67 and the error signal from amplifier 54 is applied to the other side of capacitor 67, thereby storing the value of the error signal on capacitor 67, as shown by curve 113 at time T2. The value of ref73 is used to form an offset that helps prevent the output of amplifier 54 from swinging between the values of the supply rails, such as the value provided by regulator 35. Subsequently, the control signal on input 30 goes low and forces the SC signal low. The low SC signal forces the output of inverter 77 high which enables one-shot 78 and sets latch 85 at time T5 which has no effect on SS because one-shot 86 is low. However, latch 85 enables gate 87 so that the next rising edge of the control signal will trigger one-shot 86 and force SS high again to mask the disturbance to the error signal caused by the transition of the control signal. The low SC signal also forces SH low through gate 89 and forces the output of gate 91 high to begin the hold phase to hold the previous value of the error signal. This hold phase holds the previous value in preparation for the next cycle.

The above-described sequence continues for each cycle of the control signal received on input 30 until the control signal remains low for the timeout period, as shown at time T6. When the control signal remains low for the timeout period, controller 48 forces both outputs 49 and 50 low as shown at time T6. The low signal on output 49 disables controller 27. In addition, the low on output 49 disables the generation of switching cycles of the drive signal in such a way that the clock signal is masked off by gate 39. To disable the switch drive signal after a timeout period, timing controller 48 forces the enable PWM signal (EP) on output 49 low, which disables gate 39 and prevents controller 27 from beginning to generate the drive signal for the switch. At time T7, another startup phase begins.

Overshoot in the value of current 20 is minimized using the sampled value of the error signal in response to a positive transition of the control signal, error in the value of current 14 is minimized, and power consumption for operation of controller 27 is reduced. Sampling the error signal after the value of current 14 has stabilized helps to use the stabilized value of the error signal during the next transition of the control signal. It is believed that controller 27 reduces overshoot of current 20 by at least approximately fifty percent (50%).

To facilitate this function of controller 27, regulator 35 is connected to receive power between input 28 and return 29 and provide an operating voltage on output 36. A controller 48 has a first input connected to receive the control signal on input 30 and a second input commonly connected to an output of clock 38 and a first input of gate 39. Output 49 of controller 48 is commonly connected to a second input of gate 39, an input of reference 52, a first input of gate 89, an input of one-shot 82, and a first input of gate 91. The output of gate 39 is commonly connected to a set input of latch 44 and an input of ramp 42. The output of ramp 42 is connected to the inverting input of comparator 43, and the output of comparator 43 is connected to the reset input of latch 44. The Q output of latch 44 is connected to an input of driver 46, and an output of driver 46 is connected to output 31. Output 50 of controller 48 is commonly connected to an input of delay 76, an input of one-shot 86, and an input of inverter 77. The output of one-shot 86 is connected to a first input of gate 87. The output of inverter 77 is connected to the input of one-shot 78, and the output of one-shot 78 is connected to the set input of latch 85. The Q output of latch 85 is connected to a second input of gate 87. The output of gate 87 is commonly connected to the gate of transistor 65 and the input of inverter 71. The output of inverter 71 is connected to the gate of transistor 66. The output of delay 76 is commonly connected to a second input of gate 89 and an input of one-shot 81. The output of one-shot 81 is connected to a first input of gate 83. The output of one-shot 82 is connected to a second input of gate 83, and the output of gate 83 is connected to the reset input of latch 85. The output of gate 89 is commonly connected to the input of inverter 90, the gate of transistor 62, and the gate of transistor 63. The output of inverter 90 is connected to a second input of gate 91, and the output of gate 91 is connected to the gate of transistor 64. An input of amplifier 61 is commonly connected to output 55 and to a source of transistor 66. The output of amplifier 61 is connected to a source of transistor 62, and a drain of transistor 62 is commonly connected to a first terminal of capacitor 67 and a source of transistor 64. A second terminal of capacitor 67 is commonly connected to a source of transistor 63 and an inverting input of amplifier 68. The non-inverting output of amplifier 68 is connected to the output of ref 73. An output 69 of amplifier 68 is commonly connected to a source of transistor 65, a drain of transistor 63, and a drain of transistor 64. A drain of transistor 66 is commonly connected to output 72, a drain of transistor 65, and a non-inverting input of comparator 43. The output of reference 52 is connected to the input of soft starter 53. The output of soft-starter 53 is connected to the non-inverting input of amplifier 54. An inverting input of amplifier 54 is commonly connected to a first terminal of impedance 57 and a first terminal of impedance 56. A second terminal of impedance 57 is connected to input 32. The output of impedance 56 is connected to output 55 of amplifier 54.

Fig. 3 schematically illustrates an enlarged plan view of a portion of an embodiment of a semiconductor device or integrated circuit 120 formed on a semiconductor wafer 121. Controller 27 is formed on wafer 121. Wafer 121 may also include other circuitry not shown in FIG. 3 for simplicity of the drawing. Controller 27 and device or integrated circuit 120 are formed on wafer 121 by semiconductor fabrication techniques that are well known to those of ordinary skill in the art. In one embodiment, controller 27 is formed on a semiconductor substrate as an integrated circuit having 5 external leads as illustrated by fig. 3.

In view of all of the above, it is evident that a novel device and method is disclosed. Included, among other features, is sampling the error signal from the error amplifier when the load current is not causing disturbances in the output of the error amplifier, and using this stored value to operate the PWM section when the load current is likely to cause disturbances in the output of the error amplifier.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. For example, the configuration of logic 74 and circuit 59 may have other configurations as long as the error signal is sampled and stored when current 14 is stable and the stored value is used when current 14 is unstable, or another configuration may use a different element to delay circuit 59 for the time interval after the control signal transitions high. In addition, the one-shot 78, 81, and 82 may be replaced with other edge detection circuits. The delay 76 may be any circuit that forms a delay as described in the explanation of fig. 1 and 2. One shot 86 may be replaced by any circuit that forms a pulse having a width that is longer than the overshoot time of current 20. Further, the word "connect" is used throughout for clarity of description, however, it is intended to have the same meaning as the word "couple". Accordingly, "connected" should be interpreted to include direct connections or indirect connections.

Claims (15)

1. A current controller for an LED, comprising:

a switch control circuit configured to form a switch drive signal to control a current through an LED in response to a sense signal representative of the current through the LED;

a first control circuit configured to receive a control signal and responsively activate the switch control circuit to form the switch drive signal, the control signal having a first state during a first time interval and a second state during a second time interval;

an error amplifier coupled to receive the sense signal and form an error signal; and

a sample and hold circuit configured to sample a value of the error signal in response to a first portion of a first time interval during which the control signal is in a first state and hold the value of the error signal in response to a portion of a second time interval during which the control signal is in a second state to form a held value of the error signal, the sample and hold circuit configured to couple the held value to the switch control circuit in response to a second portion of the first time interval during which the control signal is in the first state and to couple the error signal to the switch control circuit after the second portion of the first time interval.

2. The current controller of claim 1, wherein the sample-and-hold circuit is configured to sample the value of the error signal in response to the first time interval after the control signal transitions to the first state.

3. The current controller of claim 2, wherein the sample-and-hold circuit comprises a delay element forming a second portion of the first time interval.

4. The current controller of claim 1, wherein the sample-and-hold circuit is configured to hold the value of the error signal in response to the second time interval after the control signal transitions to the second state.

5. The current controller of claim 4, further comprising a first transistor having a first current carrying electrode coupled to receive the error signal, a second current carrying electrode coupled to charge a capacitor, and a control electrode; the second transistor having a first current carrying electrode coupled to receive a signal from the capacitor, a second current carrying electrode, and a control electrode coupled to the control electrode of the first transistor and operably coupled to activate the first transistor and the second transistor in response to the first time interval after the control signal transitions to the first state; and the third transistor has a first current carrying electrode coupled to the second current carrying electrode of the first transistor, a second current carrying electrode coupled to the second current carrying electrode of the second transistor, and a control electrode operably coupled to enable the third transistor in response to the second time interval after the control signal transitions to the second state.

6. The current controller of claim 1, wherein the sample-and-hold circuit is configured to couple the held value of the error signal to the switch control circuit until the second portion of the first time interval, and to couple the error signal to the switch control circuit after the first portion of the first time interval.

7. The current controller of claim 6, further comprising a timing circuit coupled to form the second portion of the first time interval in response to the control signal transitioning to the first state.

8. The current controller of claim 7, wherein the sample-and-hold circuit comprises a latch configured to be set in response to the second state of the control signal and reset in response to the second portion of the first time interval.

9. The current controller of claim 8, wherein a delay element is coupled to form the second portion of the first time interval.

10. The current controller of claim 8, further comprising a first transistor having a first current carrying electrode coupled to receive the error signal, a second current carrying electrode, and a control electrode operably coupled to enable the first transistor after the second portion of the first time interval; and the second transistor has a first current carrying electrode coupled to receive the held value of the error signal, a second current carrying electrode coupled to the second current carrying electrode of the first transistor and to the switch control circuit, and a control electrode operatively coupled to activate the second transistor during the second portion of the first time interval.

11. A method of forming a current controller for an LED, comprising the steps of:

coupling a control circuit to control the sample and hold circuit;

the control circuit is configured to receive a control signal and responsively control the sample and hold circuit to sample an input signal received at an input of the sample and hold circuit in response to a portion of a first state of the control signal, to hold the sampled value of the input signal in response to a second state of the control signal to form a held value, and to couple the held value to an output of the sample and hold circuit for a first time interval after the control signal transitions to the first state.

12. The method of claim 11, wherein configuring the control circuit to receive a control signal and responsively control the sample-and-hold circuit comprises: configuring the control circuit to form the first time interval, the first time interval having a length greater than a time required for the input signal on the input to stabilize.

13. The method of claim 11, wherein configuring the control circuit to receive a control signal and responsively control the sample-and-hold circuit comprises: configuring the control circuit to form the first time interval as three microseconds.

14. The method of claim 11, wherein configuring the control circuit to receive a control signal and responsively control the sample-and-hold circuit comprises: configuring the control circuit to couple the output of the sample-and-hold circuit to a PWM circuit.

15. The method of claim 11, wherein configuring the control circuit to receive a control signal and responsively control the sample-and-hold circuit comprises: configuring the current controller to begin a control cycle in response to the first state of the control signal.