HK1128169B - Signal line drive circuit, light emitting device, and its drive method - Google Patents

Description

Signal line driving circuit, light emitting device and driving method thereof

Technical Field

The present invention relates to a signal line driver circuit, and also relates to a technique of a light emitting device including the signal line driver circuit.

Background

In recent years, development of display devices for displaying images has been promoted. As a display device, a liquid crystal display device that displays an image using a liquid crystal element is widely used because of its advantages such as high image quality, thinness, and light weight.

On the other hand, in recent years, development of a light-emitting device using a self-light-emitting element has been promoted. The light-emitting device has characteristics such as a high response speed, a low voltage, and low power consumption suitable for moving image display, in addition to advantages of the conventional liquid crystal display device, and has attracted much attention as a next-generation display device.

As a method of expressing gradation when displaying an image of multi-gradation on a light-emitting device, an analog gradation method and a digital gradation method are given. The former analog gray scale method is a method of obtaining gray scales by analog control of the magnitude of a current flowing through a light emitting element. The latter digital gray scale system is a system in which the light emitting element is driven only in 2 states, i.e., an on state (a state where the luminance is approximately 100%) and an off state (a state where the luminance is approximately 0%). In the digital luminance method, since only 2 gradations can be directly displayed, a method of displaying an image of a plurality of gradations in combination with another method is proposed.

Further, as a driving method of the pixel, a voltage input method and a current input method can be given as a classification according to the kind of a signal inputted to the pixel. The former voltage input method is a method in which a video signal (voltage) input to a pixel is input to a gate of a driving element, and the luminance of a light-emitting element is controlled by using the driving element. The latter current input method is a method of controlling the luminance of a light-emitting element by causing a set signal current to flow through the light-emitting element.

Here, an example of a pixel circuit and a driving method thereof of a light-emitting device using a voltage driving method will be briefly described with reference to fig. 16 (a). The pixel shown in fig. 16(a) has a signal line 501, a scanning line 502, a switching TFT503, a driving TFT504, a capacitor element 505, a light-emitting element 506, and power supplies 507 and 508.

When the potential of the scanning line 502 changes to turn on the switching TFT503, a video signal inputted to the signal line 501 is inputted to the gate of the driving TFT 504. The voltage between the gate and the source of the driving TFT504 is determined according to the potential of the input video signal, and the current flowing between the source and the drain of the driving TFT504 is determined. The current is supplied to the light emitting element 506, and the light emitting element 506 emits light. As a semiconductor element for driving a light emitting element, a polysilicon transistor can be used. However, in the polysilicon transistor, dispersion of electrical characteristics such as a threshold value and an on-current is likely to occur due to a grain boundary defect. In the pixel shown in fig. 16(a), when the characteristics of the driving TFT504 are varied for each pixel, the luminance of the light-emitting element 506 is varied when the same video signal is input because the magnitude of the drain current of the corresponding driving TFT504 is different.

In order to solve the above problem, a desired current can be supplied to the light emitting element without being influenced by the TFT characteristics for driving the light emitting element. From this viewpoint, a current input method is proposed which can control the magnitude of the current supplied to the light emitting element without being affected by the TFT characteristics.

Next, an example of a pixel circuit in a light-emitting device using a current input method and a driving method thereof will be briefly described with reference to fig. 16(B) and 17. The pixel shown in fig. 16(B) includes a signal line 601, 1 st to 3 rd scan lines 602 to 604, a current line 605, TFTs 606 to 609, a capacitor 610, and a light emitting element 611. The current source circuit 612 is disposed in each signal line (each column).

The operation from writing of a video signal to light emission will be described with reference to fig. 17. In fig. 17, reference numerals indicating respective portions shall be made to fig. 16. Fig. 17(a) to (C) schematically show the paths of the currents. Fig. 17(D) shows a relationship between currents flowing through the paths during writing of a video signal, and fig. 17(E) shows a voltage accumulated in the capacitor element 610 during writing of a video signal, that is, a voltage between the gate and the source of the TFT 608.

First, pulses are input to the 1 st and 2 nd scan lines 602 and 603, and the TFTs 606 and 607 are turned on. At this time, the signal current flowing through the signal line 601 is denoted by Idata. Since the signal current Idata flows through the signal line 601, the current flows in two paths I1 and I2 in the pixel as shown in fig. 17 (a). The relationship is shown in fig. 17(D), and is of course: idata ═ I1+ I2.

At the moment when the TFT606 is turned on, the capacitor element 610 does not store any charge, and therefore the TFT608 is turned off. Therefore, I2 ═ 0 and Idata ═ I1. Meanwhile, a current flows between both electrodes of the capacitor element 610, and charges are accumulated in the capacitor element 610.

Next, the capacitor element 610 gradually accumulates charges, and a potential difference starts to occur between both electrodes (fig. 17E). When the potential difference between the two electrodes reaches Vth (point a in fig. 17(E)), the TFT608 is turned on to generate I2. As described above, since Idata is I1+ I2, I1 gradually decreases, but a current still flows, and the capacitor element 610 further accumulates charges.

The capacitor element 610 continues to accumulate charges until the gate-source voltage of the TFT608 reaches a desired voltage. That is, the charge accumulation is continued until the voltage at which only the Idata current can flow to the TFT608 is reached. After that, when the accumulation of the charge is terminated (point B in fig. 17E), the current I2 does not flow. Since the TFT608 is fully turned on, Idata ═ I2 (fig. 17 (B)). Through the above operation, the operation of writing the signal to the pixel is completed. Finally, the selection of the 1 st and 2 nd scanning lines 602 and 603 is ended, and the TFTs 606 and 607 are turned off.

Subsequently, a pulse is input to the 3 rd scanning line 604, and the TFT609 is turned on. Since the capacitor element 610 holds VGS which has been written just before, the TFT608 is turned on, and a current equal to Idata flows through the current line 605. Thus, the light emitting element 611 emits light. In this case, when the TFT608 operates in the saturation region, the light-emitting current IEL flowing through the light-emitting element 611 does not change even if the voltage between the source and drain of the TFT608 changes.

As described above, the current input method is a method in which the drain current of the TFT609 is set to the same current value as the signal current Idata set by the current source circuit 612, and the light-emitting element 611 emits light at a luminance corresponding to the drain current. By using the pixel having the above configuration, it is possible to supply a desired current to the light-emitting element while suppressing the influence of the variation in characteristics of the TFTs constituting the pixel.

However, in the light emitting device using the current input method, it is necessary to accurately input a current corresponding to a video signal to a pixel. When a signal line driver circuit (corresponding to the current source circuit 612 in fig. 16) for inputting a signal current to a pixel is formed of a polysilicon transistor, dispersion occurs in characteristics thereof, and thus dispersion also occurs in the signal circuit.

That is, in the light-emitting device using the current input method, it is necessary to suppress the influence of the characteristic variation of the TFTs constituting the pixels and the signal line driver circuit. However, although the use of the pixel having the structure shown in fig. 16(B) can suppress the influence of variation in characteristics of TFTs constituting the pixel, it is difficult to suppress the influence of variation in characteristics of TFTs constituting the signal line driver circuit.

Here, the configuration and operation of a current source circuit provided in a signal line driver circuit for driving a pixel of a current input method will be described in brief with reference to fig. 18.

The current source circuit 612 in fig. 18(a) (B) corresponds to the current source circuit 612 shown in fig. 16 (B). The current source circuit 612 has constant current sources 555 to 558. The constant current sources 555 to 558 are controlled by signals inputted through terminals 551 to 554. The magnitude of the current supplied from the constant current sources 555 to 558 is different, and the ratio is set to 1: 2: 4: 8.

Fig. 18(B) shows a circuit configuration of the current source circuit 612, and the constant current sources 555 to 558 in the figure correspond to transistors. The on-state currents of the transistors 555 to 558 depend on the ratio of L (gate length)/W (gate width) (12: 4: 8) to 1: 2: 4: 8. Thus, the current source circuit 612 may be as 2⁴The size of the control current is 16 grades. That is, for a 4-bit digital video signal, a current having an analog value of 16-level gray scale can be output. The current source circuit 612 is formed of a polysilicon transistor, and is formed integrally with the pixel portion over the same substrate.

In this way, a signal line driver circuit including a current source circuit therein has been proposed. (see, for example, non-patent documents 1 and 2)

In the digital gray scale method, a method of combining a digital gray scale method and an area gray scale method (hereinafter referred to as an area gray scale method) and a method of combining a digital gray scale method and a time gray scale method (hereinafter referred to as a time gray scale method) are used to express an image of multiple gray scales. The area gray scale method is a method in which one pixel is divided into a plurality of sub-pixels, light emission and non-light emission are selected for each sub-pixel, and gray scale is expressed by using a difference between a light emission area and the other area in one pixel. The time gray scale method is a method of expressing gray scales by controlling the time during which a light emitting element emits light. Specifically, the 1-frame period is divided into a plurality of sub-frame periods having different lengths, and the light emission or non-light emission of the light emitting element in each period is selected, so that gradation is expressed by the difference in the light emission time length within the 1-frame period. In order to express an image with multiple gradations in the digital gradation method, a method in which the digital gradation method and the time gradation method are combined (hereinafter referred to as a time gradation method) is proposed. (see, for example, patent document 1)

[ non-patent document 1 ]

Department of clothing, the rest 3, "signal technical report", ED2001-8, Current-specifying polysilicon TFT active matrix drive organic LED display Circuit simulation, p.7-14

[ non-patent document 2 ]

ReijiH etal.“AM-LCD’01”，OLED-4，p.223-226

[ patent document 1 ]

Japanese unexamined patent application publication No. 2001-5426

The current source circuit 612 sets the on-current of the transistor to 1: 2: 4: 8 by designing L/W. However, the transistors 555 to 558 have variations in threshold value and mobility due to variations in gate length, gate width, and film thickness of the gate insulating film caused by differences in manufacturing processes and substrates used. Therefore, it is difficult to set the on-currents of the transistors 555-558 to exactly 1: 2: 4: 8 as designed. That is, the current supplied to the pixel varies depending on the column.

In order to make the on-currents of the transistors 555 to 558 as designed to be exactly 1: 2: 4: 8, it is necessary to make the characteristics of the current source circuits of all columns identical. That is, it is necessary to make the characteristics of the current source circuits including the signal line driver circuit completely the same, but it is very difficult to realize the current source circuits.

Disclosure of Invention

The present invention has been made in view of the above problems, and an object thereof is to provide a signal line driver circuit capable of supplying a desired signal current to a pixel while suppressing the influence of variation in characteristics of TFTs. Further, it is an object of the present invention to provide a light-emitting device which can supply a desired signal current to a light-emitting element while suppressing the influence of the characteristic variation of TFTs constituting both a pixel and a driver circuit by using a pixel having a circuit configuration capable of suppressing the influence of the characteristic variation of TFTs.

The invention provides a signal line driver circuit having a circuit (current source circuit) structure capable of suppressing the influence of the characteristic variation of a TFT so as to flow a desired constant current. Further, the present invention provides a light-emitting device including the signal line driver circuit.

The invention provides a signal line driving circuit in which a current source circuit is arranged for each column.

In the signal line driver circuit of the present invention, the current source circuit disposed on each signal line (each column) having the signal line driver circuit is designed to supply a predetermined signal current using a reference constant current source. The current source circuit in which the signal current is set has a capability of supplying a current proportional to the reference constant current source. As a result, by using the current source circuit described above, the influence of the variation in the characteristics of the TFTs of the signal line driver circuit can be suppressed. Then, a switch for determining whether or not a set signal current is supplied from the current source circuit to the pixel is controlled by a video signal.

That is, when it is necessary to cause a signal current proportional to a video signal to flow through the signal line, a switch that determines whether or not the signal current is supplied from the current source circuit to the signal line driver circuit is provided, and the switch is controlled by the video signal. Here, a switch that determines whether or not a signal current is supplied from the current source circuit to the signal line driver circuit is referred to as a signal current control switch.

The reference constant current source may be formed integrally with the signal line driver circuit over the substrate. Further, an IC or the like may be provided outside the substrate, and a constant current may be input as the reference current.

The signal line driver circuit of the present invention will be described in brief with reference to fig. 1 and 2. In fig. 1 and 2, a peripheral signal line driver circuit having 3 signal lines in total from the i-th column to the (i +2) column is shown.

First, a case where a signal current proportional to a video signal needs to be supplied to a signal line will be described.

In fig. 1, the signal line driver circuit 403 has a current source circuit 420 provided in a signal line (each column). The current source circuit 420 has a terminal a, a terminal b, and a terminal c. The terminal a inputs a setting signal. A current (reference current) is supplied to the terminal b from a reference constant current source 109 connected to a current line. Further, the terminal c outputs the signal held in the current source circuit 420 via the switch 101 (signal current control switch). That is, the current source circuit 420 is controlled by the setting signal input from the terminal a, supplies a current (reference current) from the terminal b, and outputs a current (signal current) proportional to the current (reference current) from the terminal c. A switch 101 (signal current control switch) is disposed between the current source circuit 420 and the pixel, and the on/off of the switch 101 (signal current control switch) is controlled by a video signal.

Next, a signal line driver circuit of the present invention having a different configuration from that of fig. 1 will be described with reference to fig. 2. In fig. 2, the signal line driver circuit 403 has 2 or more current source circuits for each signal line (each column). Further, the current source circuit 420 has a plurality of current source circuits. Here, assuming that 2 current source circuits are arranged for each column, the current source circuit 420 has a1 st current source circuit 421 and a2 nd current source circuit 422. The 1 st current source circuit 421 and the 2 nd current source circuit 422 have a terminal a, a terminal b, a terminal c, and a terminal d. The terminal a inputs a setting signal. A current (reference current) is supplied to the terminal b from a reference constant current source 109 connected to a current line. The terminal c outputs a signal (signal current) held by the 1 st current source circuit 421 and the 2 nd current source circuit 422 via the switch 101 (signal current control switch). A control signal is input from the terminal d. That is, the current source circuit 420 is controlled by the setting signal input from the terminal a and the control signal input from the terminal d, supplies a current (reference current) from the terminal b, and outputs a current (signal current) proportional to the current (reference current) from the terminal c. A switch 101 (signal current control switch) is disposed between the current source circuit 420 and the pixel, and the on/off of the switch 101 (signal current control switch) is controlled by a video signal.

An operation of ending writing of a signal current into the current source circuit 420 (the signal current is set by the set signal current and the signal current is set by the reference current, and the signal current which can be output from the current source circuit 420 is determined) is referred to as a set operation, and an operation of inputting a signal current into a pixel (an operation of outputting a signal current from the current source circuit 420) is referred to as an input operation. In fig. 2, since control signals to be input to the 1 st current source circuit 421 and the 2 nd current source circuit 422 are different from each other, the 1 st current source circuit 421 and the 2 nd current source circuit 422 perform a setting operation and the other performs an input operation. Thus, each column can simultaneously perform 2 operations.

The setting operation of the current source circuit may be performed at any time and any number of times at any timing. In the signal line driver circuits shown in fig. 1 and 2, a case where a signal current proportional to a video signal is supplied to a signal line is described. The invention is not so limited. For example, it is necessary to supply a current to a different line from the signal line. At this time, the switch 101 (signal current control switch) does not have to be provided. Fig. 34 corresponds to fig. 1, and fig. 35 corresponds to fig. 2, in the case where the switch is not provided. At this time, a current is output to the pixel current line. And outputting the video signal to the signal line.

In the present invention, 1 shift register has 2 functions. The 1 function is to control a current source circuit, and the other function is to control a circuit for controlling a video signal, that is, a circuit for operating to display an image, and has a function of controlling a latch circuit, a sampling switch, a switch 101 (signal current control switch), and the like, for example. In the present invention having the above configuration, since it is not necessary to provide each circuit for controlling the current source circuit, the video signal control circuit, and the like, the number of elements of the circuit to be provided can be reduced, and further, the number of elements can be reduced, and therefore, the area of the circuit diagram can be reduced. Thus, the yield in manufacturing can be improved, and the cost can be reduced. In addition, if the area of the circuit pattern can be reduced, the frame can be reduced in size because the frame is narrow.

The shift register is constituted by a flip-flop circuit, a decoder circuit, or the like. When the shift register is formed of a flip-flop circuit, usually, a plurality of wirings are sequentially selected from the 1 st column to the last 1 st column. On the other hand, when the shift register is constituted by a decode circuit, a plurality of wirings are selected either sequentially from the 1 st column to the last 1 st column or randomly. The shift register may have a structure having a function of sequentially selecting a plurality of wirings or a structure having a function of randomly selecting a plurality of wirings depending on the purpose of the shift register.

However, when a configuration having a function of randomly selecting a plurality of wirings is selected, a setting signal to be supplied to the current source circuit can be randomly output. Therefore, the setting operation of the current source circuit is not performed in the order from the 1 st column to the last 1 st column, but may be performed randomly. Thus, the period during which the current source circuit performs the setting operation can be freely set. Further, the influence of the leakage of the electric charge held in the capacitive element of the current source circuit can be reduced. In this way, if the setting operation of the current source circuit can be performed at random, if a problem occurs in the setting operation of the current source circuit, the influence of the problem can be reduced.

In the present invention, the TFT can be used instead of a transistor using a normal single crystal, a transistor using SOI, an organic transistor, or the like.

The present invention provides a signal line driver circuit having the current source circuit. Further, the present invention provides a light-emitting device which can supply a desired signal current to a light-emitting element while suppressing the influence of the variation in characteristics of TFTs constituting both a pixel and a driver circuit by using a pixel having a circuit structure in which the influence of the variation in characteristics of TFTs is suppressed.

Drawings

Fig. 1 is a diagram of a signal line driver circuit.

Fig. 2 is a diagram of a signal line driver circuit.

Fig. 3 is a diagram (1 bit) of the signal line driver circuit.

Fig. 4 is a diagram (1 bit) of the signal line driver circuit.

Fig. 5 is a diagram (1 bit) of the signal line driver circuit.

Fig. 6 is a diagram (1 bit) of the signal line driver circuit.

Fig. 7 is a diagram (3 bits) of the signal line driver circuit.

Fig. 8 is a diagram (3 bits) of the signal line driver circuit.

Fig. 9 is a diagram showing a time sequence.

Fig. 10 is a diagram showing a time sequence.

Fig. 11 is a diagram showing a time sequence.

Fig. 12 is a view showing an external appearance of the light-emitting device.

Fig. 13 is a circuit diagram of a pixel of a light emitting device.

Fig. 14 is a diagram for explaining the driving method of the present invention.

Fig. 15 is a view showing a light-emitting device of the present invention.

Fig. 16 is a circuit diagram of a pixel of a light-emitting device.

Fig. 17 is a diagram illustrating an operation of a pixel of the light-emitting device.

Fig. 18 is a diagram of a current source circuit.

Fig. 19 is a diagram illustrating an operation of the current source circuit.

Fig. 20 is a diagram illustrating an operation of the current source circuit.

Fig. 21 is a diagram illustrating an operation of the current source circuit.

Fig. 22 is a diagram showing an electronic apparatus using the present invention.

Fig. 23 is a circuit diagram of a current source circuit.

Fig. 24 is a circuit diagram of a current source circuit.

Fig. 25 is a circuit diagram of a current source circuit.

Fig. 26 is a diagram (3 bits) of the signal line driver circuit.

Fig. 27 is a diagram (3 bits) of the signal line driver circuit.

Fig. 28 is a timing chart for explaining a driving method of the current source circuit.

Fig. 29 is a diagram (3 bits) of the signal line driver circuit.

Fig. 30 is a circuit diagram of a reference constant current source.

Fig. 31 is a circuit diagram of the reference constant current source.

Fig. 32 is a circuit diagram of the reference constant current source.

Fig. 33 is a circuit diagram of the reference constant current source.

Fig. 34 is a diagram of a signal line driver circuit.

Fig. 35 is a diagram of a signal line driver circuit.

Fig. 36 is a circuit diagram of a current source circuit.

Fig. 37 is a circuit diagram of a current source circuit.

Fig. 38 is a circuit diagram of a current source circuit.

Fig. 39 is a circuit diagram of a current source circuit.

Fig. 40 is a circuit diagram of a current source circuit.

Fig. 41 is a circuit diagram of a current source circuit.

Fig. 42 is a diagram of a signal line driver circuit.

Fig. 43 is a diagram of a shift register.

Fig. 44 is a diagram of shift registers and timing.

Fig. 45 is a diagram showing a time sequence.

Fig. 46 is a diagram of a shift register.

Fig. 47 is a diagram of a signal line driver circuit.

Fig. 48 is a diagram of a signal line driver circuit.

Fig. 49 is a diagram of a signal line driver circuit.

Fig. 50 is a diagram of a signal line driver circuit.

Fig. 51 is a diagram of a signal line driver circuit.

Fig. 52 is a diagram of a signal line driver circuit.

Fig. 53 is a diagram of a signal line driver circuit.

Fig. 54 is a diagram of a signal line driver circuit.

Fig. 55 is a diagram of a signal line driver circuit.

Fig. 56 is a diagram of a signal line driver circuit.

Fig. 57 is a diagram of a signal line driver circuit.

Fig. 58 is a diagram of a signal line driver circuit.

Fig. 59 is a diagram of a signal line driver circuit.

Fig. 60 is a diagram of a signal line driver circuit.

Fig. 61 is a diagram of a signal line driver circuit.

Fig. 62 is a diagram of a signal line driver circuit.

Fig. 63 is a diagram of a signal line driver circuit.

Fig. 64 is a diagram of a signal line driver circuit.

Fig. 65 is a diagram of a signal line driver circuit.

Fig. 66 is a diagram of a signal line driver circuit.

Fig. 67 is a diagram of a signal line driver circuit.

Fig. 68 is a diagram of a signal line driver circuit.

Fig. 69 is a diagram of a signal line driver circuit.

Fig. 70 is a diagram of a signal line driver circuit.

Fig. 71 is a circuit diagram of a pixel.

Fig. 72 is a diagram showing a timing sequence.

Fig. 73 is a diagram showing a timing sequence.

Fig. 74 is a diagram showing a timing sequence.

Fig. 75 is a diagram showing a time sequence.

Fig. 76 is a diagram showing a time sequence.

Fig. 77 is a diagram showing a time sequence.

Fig. 78 is a diagram showing a time sequence.

Fig. 79 is a diagram showing a time sequence.

Fig. 80 is a diagram showing a time sequence.

Fig. 81 is a diagram showing a time sequence.

Fig. 82 is a diagram showing a time sequence.

Fig. 83 is a diagram showing a time sequence.

Fig. 84 is a diagram showing a time sequence.

Fig. 85 is a diagram showing a time sequence.

Fig. 86 is a diagram showing a time sequence.

Fig. 87 is a wiring diagram of the current source circuit.

Fig. 88 is a circuit diagram of a current source circuit.

Detailed Description

(embodiment 1)

In this embodiment, a configuration of a current source circuit provided in a signal line driver circuit according to the present invention and an operation thereof will be described.

In the present invention, the signal inputted from the terminal a corresponds to a sampling pulse supplied from the shift register. However, the sampling pulse is not directly input due to the configuration of the current source circuit, the driving method, or the like, but a signal supplied from an output terminal of a logic operator connected to a setting control line (not shown in fig. 1) is input. One of the 2 input terminals of the logic operator receives a sampling pulse, and the other receives a signal supplied from a setting control line. That is, the current source circuit 420 is set at the timing of the sampling pulse or the signal supplied from the output terminal of the logical operator connected to the setting control line.

The shift register has a configuration using a multi-column flip-flop circuit (FF) or the like. Further, a clock signal (S-CLK), a start pulse (S-SP), and a clock inversion signal (S-CLKb) are input to the shift register, and signals sequentially output in accordance with the timing of these signals are referred to as sampling pulses.

In addition, a sampling pulse is input to one of the 2 input terminals of the logical operator, and a signal supplied from a setting control line is input to the other input terminal. In the logic operator, the input 2 signals are logically operated, and the signals are output from the output terminal. If the logical operator is a NAND, in the timing chart shown in fig. 14C, a High (High) signal may be input from the control line to the NAND in the period Tb, and a Low (Low) signal may be input from the control line to the NAND in the remaining period.

The shift register is constituted by a flip-flop circuit, a decoder circuit, or the like. When the shift register is formed of a flip-flop circuit, a plurality of wirings are usually selected in order from the 1 st column to the last column. On the other hand, when the shift register is configured by a decoder circuit, a plurality of wirings are selected in order from the 1 st column to the last column, or are selected at random. The shift register may have a structure having a function of sequentially selecting a plurality of wirings or a structure having a function of randomly selecting a plurality of wirings depending on the purpose of the shift register.

In fig. 23a, a circuit including switches 104, 105a, and 116, a transistor 102 (n-channel type), and a capacitor element 103 for holding a gate-source voltage VGS of the transistor 102 corresponds to the current source circuit 420.

In the current source circuit shown in fig. 23(a), the switches 104 and 105a are turned on by a sampling pulse input through the terminal a. Thus, a current (reference current) is supplied from a reference constant current source 109 (hereinafter referred to as a constant current source 109) connected to the current line via a terminal b, and the capacitor element 103 holds a predetermined charge. The capacitor element 103 holds the charge until the current (reference current) flowing from the constant current source 109 and the drain current of the transistor 102 become equal to each other.

Next, the switches 104 and 105a are turned off by a signal input through the terminal a. Since the capacitor element 103 holds a predetermined charge in this manner, the transistor 102 has a capability of flowing a current having a magnitude corresponding to a current (reference current). When the switches 101 (signal current control switches) and 116 are turned on, a current flows through the pixel connected to the signal line via the terminal c. This is because the gate voltage of the transistor 102 is set to a predetermined gate voltage by the capacitor element 103, and a drain current corresponding to a current (reference current) flows through the drain region of the transistor 102. Therefore, the magnitude of the current input to the pixel can be controlled regardless of the characteristic dispersion of the transistors constituting the signal line driver circuit.

When the switch 101 (signal current control switch) is not provided, a current is supplied to the pixel connected to the signal line through the terminal c when the switch 116 is turned on.

The connection structure of the switches 104 and 105a is not limited to the structure shown in fig. 23 (a). For example, one end of the switch 104 may be connected to the terminal b, the other end may be connected to the gate of the transistor 102, one end of the switch 105a may be connected to the terminal b via the switch 104, and the other end may be connected to the switch 116.

Alternatively, the switch 104 is arranged between the terminal b and the gate of the transistor 102, and the switch 105a is arranged between the terminal b and the switch 116. That is, the number of switches, the number of wirings, and the connections of the wirings arranged in the current source are not particularly limited. However, the switches may be arranged as shown in fig. 36(a) so as to be connected as shown in fig. 36(a1) in the setting operation and connected as shown in fig. 36(a2) in the input operation.

In the current source current shown in fig. 23a, the operation of setting a signal (setting operation) and the operation of inputting a signal to a pixel (input operation) cannot be performed simultaneously.

In fig. 23B, a circuit including switches 124 and 125, a transistor 122 (n-channel type), a capacitor 123 for holding a gate-source voltage VGS of the transistor 122, and a transistor 126 (n-channel type) corresponds to the current source circuit 420.

The transistor 126 functions as a switch or a part of a transistor for a current source.

In the current source circuit shown in fig. 23(B), the switches 124 and 125 are turned on by a sampling pulse input through the terminal a. Thus, a current (reference current) is supplied from the constant current source 109 connected to the current line through the terminal b, and the capacitor element 123 holds a predetermined charge. Further, the capacitor element 123 holds the charge until the current (reference current) flowing from the constant current source 109 and the drain current of the transistor 122 become equal to each other. When the switch 124 is turned on, the transistor 126 is turned off because the gate-source voltage VGS of the transistor 126 becomes 0V.

Next, the switches 124 and 125 are turned off by a signal input through the terminal a. Since the capacitor element 123 holds a predetermined charge, the transistor 122 can flow a current having a magnitude corresponding to a current (reference current). Then, if the switch 101 (signal current control switch) is in an on state, a current is supplied to the pixel connected to the signal line via the terminal c. This is because the gate voltage of the transistor 122 is set to a predetermined gate voltage by the capacitor element 123, and a drain current corresponding to the signal current Idata flows to the drain region of the transistor 122. Therefore, the magnitude of the current input to the pixel can be controlled regardless of the characteristic dispersion of the transistors constituting the signal line driver circuit.

When the switches 124 and 125 are turned off, the gate and source of the transistor 126 have different potentials. As a result, the electric charge held in the capacitor element 123 is also distributed to the transistor 126, and the transistor 126 is automatically turned on. Here, the transistors 122, 126 are connected in series, and the gates are connected to each other. Therefore, the transistors 122 and 126 operate as multi-gate transistors. That is, the gate length L of the transistor is different between the set operation and the input operation. Therefore, the current value supplied from the terminal b during the setting operation can be larger than the current value supplied from the terminal c during the input operation. Therefore, various loads (wiring resistance, cross capacitance, and the like) arranged between the terminal b and the reference constant current source can be charged more quickly. Therefore, the setting operation can be completed quickly. When the switch 101 (signal current control switch) is not arranged, the transistor 126 is turned on, and a current is supplied to the pixel connected to the signal line through the terminal c.

The number of switches, the number of wires, and the connections of the switches and the wires arranged in the current source are not particularly limited. That is, the wiring or the switch may be arranged as shown in fig. 36(B) so as to be connected as shown in fig. 36(B1) in the setting operation and connected as shown in fig. 36(B2) in the input operation. In particular, in fig. 36(B2), the electric charge held in the capacitor element 107 may be prevented from leaking.

In the current source circuit shown in fig. 23B, the setting operation performed by making the current source circuit capable of flowing a signal current and the input operation (outputting a current to a pixel) of supplying the signal current to the pixel cannot be performed simultaneously.

In fig. 23C, a circuit including switches 108 and 110, transistors 105b and 106 (n-channel type), and a capacitor element 107 for holding a gate-source voltage VGS of the transistors 105b and 106 corresponds to the current source circuit 420.

In the current source circuit shown in fig. 23(C), the switches 108 and 110 are turned on by a sampling pulse input through the terminal a. Thus, a current (reference current) is supplied from the constant current source 109 connected to the current line through the terminal b, and the capacitor element 107 holds a predetermined charge. Further, the capacitor element 107 holds the charge until a current (reference current) flowing from the constant current source 109 and the drain current of the transistor 105b become equal to each other. At this time, since the gates of the transistor 105b and the transistor 106 are connected to each other, the gate voltages of the transistor 105b and the transistor 106 can be held by the capacitor 107.

Next, the switches 108 and 110 are turned off by a signal input through the terminal a. At this time, since the capacitor element 107 holds a predetermined charge, the transistor 106 has a capability of flowing a current having a magnitude corresponding to a current (reference current). Then, if the switch 101 (signal current control switch) is in an on state, a current is supplied to the pixel connected to the signal line via the terminal c. This is because the gate voltage of the transistor 106 is set to a predetermined gate voltage by the capacitor element 107, and a drain current corresponding to a current (reference current) flows through the drain region of the transistor 106. Therefore, the magnitude of the current input to the pixel can be controlled regardless of the characteristic dispersion of the transistors constituting the signal line driver circuit.

When the switch 101 (signal current control switch) is not arranged, a current flows through the pixel connected to the signal line via the terminal c.

In this case, in order to accurately cause the drain current corresponding to the signal current to flow to the drain region of the transistor 106, it is necessary to make the characteristics of the transistor 105b and the transistor 106 the same. In more detail, the mobility, threshold value, and the like of the transistor 105b and the transistor 106 must be the same. In fig. 23(C), the values of W/L of the transistor 105b and the transistor 106 can be arbitrarily set, and a current proportional to the current supplied from the constant current source 109 can be supplied to the pixel.

In addition, in the transistor 105b and the transistor 106, by setting the W/L of the transistor connected to the constant current source 109 to be large, a large current can be supplied from the constant current source 109, and the writing speed can be increased.

In the current source circuit shown in fig. 23, the setting operation performed by making the current source circuit capable of outputting the signal current and the input operation for inputting the signal current to the pixel can be performed simultaneously.

The current source circuit shown in fig. 23(D) and (E) has the same configuration as that of the current source circuit of fig. 23(C) except that the connection of the switch 110 is different. The operation of the current source circuit 420 shown in fig. 23(D) and (E) is referred to the operation of the current source circuit shown in fig. 23(C), and therefore, the description thereof is omitted.

The number of switches, the number of wires, and the connections of the wires in the current source current arrangement are not particularly limited. That is, the wiring or the switch may be arranged as shown in fig. 36(C) so as to be connected as shown in fig. 36(C1) in the setting operation and connected as shown in fig. 36(C2) in the input operation. In particular, in fig. 36(C2), the electric charge held in the capacitor element 107 may be prevented from leaking.

In fig. 37(a), a circuit including switches 195b, 195c, 195d, and 195f, a transistor 195a, and a capacitor element 195e corresponds to a current source circuit. In the current source circuit shown in fig. 37(a), the switches 195b, c, d, and f are turned on by a signal input through the terminal a. Thus, a current is supplied from the constant current source 109 connected to the current line through the terminal b, and the capacitor 195e holds a predetermined charge until the signal current supplied from the constant current source 109 becomes equal to the drain current of the transistor 195 a.

Next, the switches 195b, 195c, 195d, 195f are turned off by a signal input through the terminal a. At this time, since the capacitor element 195e holds a predetermined charge, the transistor 195a has a capability of flowing a current having a magnitude corresponding to the signal current. This is because the gate voltage of the transistor 195a is set to a predetermined gate voltage by the capacitor element 195e, and a drain current corresponding to a current (reference current) flows through the drain region of the transistor 195 a. In this state, a current is supplied to the outside through the terminal c. In the current source circuit shown in fig. 37(a), the setting operation for making the current source circuit capable of flowing a signal current and the input operation for inputting the signal current to the pixel cannot be performed simultaneously. However, when the switch to be controlled is turned on by a signal input through the terminal a and a current does not flow through the terminal c, the terminal c needs to be connected to a wiring having another potential. When the potential of the wiring is Va, Va may take any value as long as it is a potential at which a current flowing from the terminal B directly flows. As an example, it may be a supply voltage Vdd.

The number of switches, the number of wires, and the connections thereof are not particularly limited. That is, the switches may be arranged as shown in fig. 37(B) and (C) so as to be connected as shown in fig. 37(B1) (C1) in the setting operation and connected as shown in fig. 37(B2) (C2) in the input operation.

In the current source circuit 420 in fig. 23(a), (C) and (E), the direction in which current flows (the direction from the pixel to the signal line driver circuit) is the same, and the conductivity type of the transistors 102, 105b, and 106 may be p-channel type.

Accordingly, fig. 24a shows a circuit diagram in which the direction in which a current flows (the direction from the pixel to the signal line driver circuit) is the same, and the transistor 102 shown in fig. 23a is of a p-channel type. In fig. 23(a), by disposing a capacitor element between the gate and the source, the voltage between the gate and the source can be maintained even if the source potential changes. Fig. 24(B) to (D) show circuit diagrams in which the transistors 105B and 106 shown in fig. 23(C) to (E) are of the p-channel type, with the same direction of current flow (direction from the pixel to the signal line driver circuit).

Fig. 38(a) shows a case where the transistor 105a is formed in a p-channel type in the structure shown in fig. 37. Fig. 38(B) shows a case where the transistors 122 and 126 are formed to have a p-channel type in the structure shown in fig. 23 (B).

In fig. 40, a circuit including switches 104 and 116, a transistor 102, a capacitor element 103, and the like corresponds to a current source circuit.

Fig. 40(a) corresponds to a circuit obtained by modifying a part of fig. 23 (a). In the current source circuit shown in fig. 40(a), the gate width W of the transistor is different between the setting operation and the input operation of the current source. That is, the gate width w differs between the setting operation and the input operation, as shown in fig. 40(B) and 40 (C). Therefore, the current value supplied from the terminal b during the setting operation can be larger than the current value supplied from the terminal c during the input operation. For this reason, various loads (wiring resistance, cross capacitance, and the like) arranged between the terminal b and the reference constant current source can be charged more quickly. Therefore, the setting operation can be completed quickly. Fig. 40 shows a circuit obtained by modifying a part of fig. 23 (a). However, the present invention is also easily applicable to circuits other than fig. 23 and circuits such as fig. 24, 37, 39, and 38.

In the current source circuits shown in fig. 23, 24, and 37, a current flows from the pixel to the signal line driver circuit. However, the current may flow not only from the pixel to the signal line driver circuit but also from the signal line driver circuit to the pixel. Which direction the current flows depends on the pixel composition. When a current flows from the signal line driver circuit to the pixel, Vss (low potential power supply) may be changed to Vdd (high potential power supply) in fig. 23, and the transistors 102, 105b, 106, 122, and 126 may be of a p-channel type. In fig. 24, Vss may be changed to Vdd, and the transistors 102, 105b, and 106 may be n-channel transistors.

Note that, the capacitor element provided in all the current source circuits described above may be replaced with a transistor gate capacitor or the like, and therefore, may not be provided.

The circuits in fig. 23(a) to (E) and 38(a) and (B) may be provided with wires or switches, and may be connected as in fig. 39(a1) to (D1) in the setting operation and connected as in fig. 39(a2) to (D2) in the input operation. The number of switches and the number of wirings are not particularly limited.

The following describes in detail the operation of the current source circuits in fig. 23(a) and 24(a), and fig. 23(C) to (E) and 23(B) to (D). First, the operation of the current source circuit in fig. 23(a) and 24(a) will be described with reference to fig. 19.

Fig. 19(a) to (C) typically show paths through which current flows between circuit elements. Fig. 19(D) shows a relationship between a current flowing through each path and time when a signal current is written into the current source circuit, and fig. 19(E) shows a relationship between a voltage accumulated in the capacitor element 16, that is, a gate-source voltage of the transistor 15 and time when a signal current is written into the current source circuit. In the circuit diagrams shown in fig. 19(a) to (C), reference constant current source 11, switches 12 to 14 are elements having a switching function, transistors 15, capacitance elements 16, and pixels 17. The circuit including the switch 14, the transistor 15, and the capacitor element 16 corresponds to the current source circuit 20.

The transistor 15 has a source region connected to Vss and a drain region connected to the constant current source 11. One electrode of the capacitor element 16 is connected to Vss (the source of the transistor 15), and the other electrode is connected to the switch 14 (the gate of the transistor 15). The capacitor element 16 functions to hold the gate-source voltage of the transistor 15.

The pixel 17 is formed of a light emitting element, a transistor, or the like. The light-emitting element includes an anode, a cathode, and a light-emitting layer interposed between the anode and the cathode. The light-emitting layer is formed using a known light-emitting material, and the light-emitting layer has 2 kinds of structures, i.e., a single-layer structure and a stacked structure. Further, the light emission in the light-emitting layer includes light emission (fluorescence) when returning from a singlet excited state to a ground state and light emission (phosphorescence) when returning from a triplet excited state to a ground state, and either one or both of them may be used. The light-emitting layer is made of a known material such as an organic material or an inorganic material.

Actually, the current source circuit 20 is provided in the signal line driver circuit, and a current corresponding to the signal current is supplied from the current source circuit 20 provided in the signal line driver circuit to the light emitting element via a circuit element having a signal line or a pixel or the like. However, in fig. 19, the detailed configuration is not shown for the sake of simplicity in describing the relationship between the constant current source 11, the current source current 20, and the pixel 17.

First, an operation (setting operation) of the current source circuit 20 for holding the signal current Idata will be described with reference to fig. 19(a) and (B). In fig. 19(a), the switches 12 and 14 are on, and the switch 13 is off. A signal current is supplied from the constant current source 11, and a current flows from the constant current source 11 in the direction of the current source circuit 20. At this time, as shown in fig. 19(a), the current path in the current source circuit 20 is divided into two paths I1 and I2. As shown in fig. 19(D), the signal current satisfies the relationship Idata of I1+ I2.

At the moment when the constant current source 11 starts to flow a current, the capacitor element 16 does not hold a charge, and therefore the transistor 15 is turned off. Therefore, I2 ═ 0 and Idata ═ I1.

Next, the capacitor element 16 gradually accumulates electric charges, and a potential difference starts to occur between both electrodes of the capacitor element 16 (fig. 19E). When the potential difference between the two electrodes reaches Vth (point a in fig. 19(E)), the transistor 15 is turned on, I2 > 0. As described above, since Idata ═ I1+ I2, I1 gradually decreases, but a current still flows. The capacitive element 16 further accumulates electric charges.

The potential difference between the electrodes of the capacitor element 16 becomes a voltage between the gate and the source of the transistor 15. Therefore, the capacitor element 16 continues to accumulate the charge until the voltage between the gate and the source of the transistor 15 reaches a desired voltage, that is, the voltage between the gate and the source when the current Idata can flow through the transistor 15. When the accumulation of the charge is terminated (point B in fig. 19E), the current I2 does not flow, and the transistor 15 is completely turned on, so that Idata becomes I2 (fig. 19B).

Next, an operation (input operation) of inputting the signal current Idata to the pixel will be described with reference to fig. 19C. In fig. 19(C), the switch 13 is on, and the switches 12 and 14 are off. Since the capacitor element 16 holds a predetermined charge, the transistor 15 is turned on, and a current corresponding to the signal current flows in the Vss direction through the switch 13 and the transistor 15, thereby supplying a predetermined signal current to the pixel. In this case, when the transistor 15 is operated in the saturation region, a constant current can be supplied to the light-emitting element even if the voltage between the source and drain of the transistor 15 changes.

As shown in fig. 19a to 19C, the current source circuit 20 shown in fig. 19 is first divided into an operation (setting operation, corresponding to fig. 19a and B) of ending writing of the signal current Idata to the current source circuit 20 and an operation (input operation, corresponding to fig. 19C) of inputting the signal current Idata to the pixel. Then, a current is supplied to the light emitting element in accordance with the signal current Idata input to the pixel.

In the current source circuit 20 shown in fig. 19, the setting operation and the input operation cannot be performed simultaneously. Therefore, when it is necessary to perform the setting operation and the input operation simultaneously, it is preferable to provide at least 2 current source circuits for each of the signal lines connected to the plurality of pixels and the plurality of signal lines arranged in the pixel portion. If the setting operation can be performed during a period in which the signal current Idata is not input to the pixel, only 1 current source circuit may be provided for each signal line (each column).

Note that the transistor 15 in fig. 19(a) to (C) is of an n-channel type, but the transistor 15 may be of a p-channel type. Fig. 19(F) shows a circuit diagram when the transistor 15 is of a p-channel type. In fig. 19(F), 31 denotes a reference constant current source, switches 32 to 34 denote elements having a switching function, 35 denotes a transistor, 36 denotes a capacitor, and 37 denotes a pixel. The circuit having the switch 34, the transistor 35, and the capacitance element 36 corresponds to the current source circuit 24.

The transistor 35 is of a p-channel type, and a source region and a drain region of the transistor 35, one of which is connected to Vdd and the other of which is connected to the constant current source 31. One electrode of the capacitor element 36 is connected to Vdd, and the other electrode is connected to the switch 36. The capacitor element 36 functions to hold the gate-source voltage of the transistor 35.

The operation of the current source circuit 24 shown in fig. 19(F) is the same as that of the current source circuit 20 described above except for the direction in which the current flows, and therefore, the description thereof is omitted here. Note that, when designing a current source circuit in which the polarity of the transistor 15 is changed without changing the direction of current flow, the circuit diagram shown in fig. 23 can be referred to.

In fig. 41, the direction of current flow is the same as in fig. 19(F), and the transistor 35 is an n-channel type. The capacitive element 36 is connected between the gate and the source of the transistor 35. The source potential of the transistor 35 is different between the set operation and the input operation. However, even if the source potential of the transistor 35 changes, the gate-source voltage is held, and therefore the operation is normal.

Next, the operation of the current source circuit in fig. 23(C) to (E) and fig. 24(B) to (D) will be described with reference to fig. 20 and 21. Fig. 20(a) to (C) typically show paths through which current flows between circuit elements. Fig. 20(D) shows the relationship between the current flowing through each path and the time when the signal current is written into the current source circuit, and fig. 20(E) shows the relationship between the voltage accumulated in the capacitor element 46, that is, the gate-source voltage of the transistors 43 and 44 and the time when the signal current is written into the current source circuit. In the circuit diagrams shown in fig. 20(a) to (C), reference constant current source 41, switch 42, transistors 43 and 44, capacitance element 46, and pixel 47 are elements having a switching function (hereinafter referred to as constant current source 41). The circuit having the switch 42, the transistors 43 and 44, and the capacitance element 46 corresponds to the current source circuit 25.

The n-channel transistor 43 has a source region connected to Vss and a drain region connected to the constant current source 41. The n-channel transistor 44 has a source region connected to Vss and a drain region connected to a terminal 48 of the pixel 47. One electrode of the capacitor element 46 is connected to Vss (the sources of the transistors 43 and 44), and the other electrode is connected to the gates of the transistors 43 and 44. The capacitor element 46 functions to hold the gate-source voltage of the transistors 43 and 44.

In actuality, the current source circuit 25 is provided in a signal line driver circuit, and a current corresponding to the signal current flows from the current source circuit 25 provided in the signal line driver circuit to the light emitting element via a circuit element having a signal line or a pixel or the like. However, in fig. 20, the detailed configuration is not shown for the sake of simplicity in describing the relationship between the constant current source 41, the current source current 25, and the pixel 47.

In the current source circuit 25 of fig. 20, the sizes of the transistor 43 and the transistor 44 are important. Therefore, the case where the transistor 43 and the transistor 44 have the same or different sizes will be described by reference numerals. In fig. 20(a) to 20(C), when the transistor 43 and the transistor 44 have the same size, the signal current Idata is used for description. When the sizes of the transistor 43 and the transistor 44 are different, description is made using the signal current Idata1 and the signal current Idata 2. Note that the sizes of the transistor 43 and the transistor 44 are determined using the value of W (gate width)/L (gate length) of each transistor.

First, a case where the transistor 43 and the transistor 44 have the same size will be described. Next, an operation of first holding the signal current Idata in the current source circuit 20 will be described with reference to fig. 20(a) and (B). In fig. 20(a), when the switch 42 is turned on, the signal current Idata is set by using the reference constant current source 41, and a current flows from the constant current source 41 in the direction of the current source circuit 25. At this time, since the signal current Idata flows from the reference constant current source 41, the current flows through the current source circuit 25 while being divided into two paths I1 and I2, as shown in fig. 20 (a). As shown in fig. 20(D), the signal current satisfies the relationship Idata of I1+ I2.

At the moment when the constant current source 41 starts to flow a current, the capacitor element 46 does not hold a charge, and therefore the transistors 43 and 44 are turned off. Therefore, I2 ═ 0 and Idata ═ I1.

Next, the capacitor element 46 gradually accumulates electric charges, and a potential difference starts to occur between both electrodes of the capacitor element 46 (fig. 20E). When the potential difference between the two electrodes reaches Vth (point a in fig. 20(E)), the transistors 43 and 44 are turned on, I2 > 0. As described above, since Idata ═ I1+ I2, I1 gradually decreases, but a current still flows. The capacitive element 46 further accumulates electric charges.

The potential difference between the electrodes of the capacitor element 46 becomes a voltage between the gates and the sources of the transistors 43 and 44. Therefore, the capacitor element 46 continues to accumulate the charge until the gate-source voltage of the transistors 43 and 44 reaches a desired voltage, that is, the gate-source voltage when the transistor 15 is allowed to flow the current Idata. When the accumulation of the charge is terminated (point B in fig. 20E), the current I2 does not flow, and further, since the transistors 43 and 44 are completely turned on, Idata becomes I2 (fig. 20B).

Next, an operation of inputting the signal current Idata to the pixel will be described with reference to fig. 20 (C). First, the switch 42 is turned off. Since the capacitor element 46 holds a predetermined charge, the transistors 43 and 44 are turned on, and a current equal to the signal current Idata flows from the pixel 47. Thereby inputting a signal current Idata to the pixel. In this case, when the transistor 44 is operated in the saturation region, even if the voltage between the source and drain of the transistor 44 changes, the current flowing through the pixel can be kept constant.

In the current mirror circuit shown in fig. 20, even when the switch 42 is turned off, a current can be caused to flow through the pixel 47 by the current supplied from the constant current source 41. That is, the operation of setting a signal to the current source circuit 25 (setting operation) and the operation of inputting a signal to the pixel (input operation) can be performed simultaneously.

Next, a case where the transistor 43 and the transistor 44 have different sizes will be described. The operation of the current source circuit 25 is the same as the above-described operation, and therefore, the description thereof is omitted here. If the transistor 43 and the transistor 44 are different in size, the signal current Idata1 set in the constant current source 41 is necessarily different from the signal current Idata2 flowing through the pixel 47. The difference between the two depends on the difference in the values of W (gate width)/L (gate length) of the transistor 43 and the transistor 44.

In general, it is desirable to make the W/L value of transistor 43 larger than the W/L value of transistor 44. This is because the signal current Idata1 can be increased when the W/L value of the transistor 43 is increased. At this time, when the current source circuit is set by the signal current Idata1, the load (cross capacitance, wiring resistance) can be charged, and thus the setting operation can be performed quickly.

The transistors 43 and 44 of the current source circuit 25 shown in (a) to (C) of fig. 20 are of an n-channel type, but the transistors 43 and 44 of the current source circuit 25 may be of a p-channel type. Here, fig. 21 shows a circuit diagram when the transistors 43 and 44 are of a p-channel type.

In fig. 21, 41 denotes a constant current source, a switch 42 denotes a semiconductor element having a switching function, 43 and 44 denote transistors (p-channel type), 46 denotes a capacitor element, and 47 denotes a pixel. In the present embodiment, the switch 42, the transistors 43 and 44, and the capacitor element 46 are circuits corresponding to the current source circuit 26.

The p-channel transistor 43 has a source region connected to Vdd and a drain region connected to the constant current source 41. The p-channel transistor 44 has a source region connected to Vdd and a drain region connected to a terminal 48 of the pixel 47. One electrode of the capacitor element 46 is connected to Vdd (source), and the other electrode is connected to the gates of the transistors 43 and 44. The capacitor element 46 functions to hold the gate-source voltage of the transistors 43 and 44.

The operation of the current source circuit 24 shown in fig. 21 is the same as that of the current source circuits 20(a) to (C) described above except for the direction in which the current flows, and therefore, the description thereof is omitted here. Further, when designing a current source circuit in which the direction of current flow is not changed but the polarities of the transistors 43 and 44 are changed, the circuit diagram shown in fig. 23 can be referred to.

In addition, the polarity of the transistor may be changed without changing the direction of current flow. Since the operation is described with reference to fig. 36, the description thereof will be omitted.

To summarize the above, in the current source circuit of fig. 19, a current of the same magnitude as the signal current Idata set by the constant current source flows in the pixel. In other words, the signal current Idata set by the constant current source is the same as the current value flowing through the pixel, and is not affected by the characteristic variation of the transistor provided in the current source circuit.

In the current source circuit of fig. 19 and the current source circuit of fig. 6(B), the signal current Idata cannot be output from the current source circuit to the pixel during the setting operation. Therefore, it is preferable that 2 current source circuits are provided for each signal line, and an operation (setting operation) of setting a signal is performed for one current source circuit, and an operation (input operation) of inputting a current Idata to a pixel is performed using the other current source circuit.

However, when the setting operation and the input operation cannot be performed simultaneously, only 1 current source circuit may be provided for each column. The current source circuits in fig. 37(a) and 38(a) have the same configuration as that in fig. 19 except that the connection and the path through which current flows are different. The current source circuit in fig. 40(a) and the current source circuit in fig. 19 have the same configuration except that the magnitude of the current supplied from the constant current source and the magnitude of the current flowing from the current source circuit are different. The current source circuits in fig. 23(B) and 38(B) and the current source circuit in fig. 19 have the same configuration except that the magnitude of the current supplied from the constant current source and the magnitude of the current flowing from the current source circuit are different. That is, the configuration of fig. 40(a) is the same as that of the current source circuit of fig. 19 except that the gate width W of the transistor is different between the setting operation and the input operation, and the gate length L of the transistor is different between the setting operation and the input operation in the configurations of fig. 23(B) and 38 (B).

On the other hand, in the current source circuits of fig. 20 and 21, the signal current Idata set in the constant current source and the value of the current flowing through the pixel depend on the size of 2 transistors provided in the current source circuit. That is, the size (W (gate width)/L (gate length)) of the 2 transistors provided in the current source circuit can be arbitrarily designed to arbitrarily change the signal current Idata set in the constant current source and the current flowing through the pixel. However, when the characteristics such as the threshold value and the mobility of 2 transistors are varied, it is difficult to output a correct signal current Idata to a pixel.

In the current source circuits of fig. 20 and 21, a signal can be input to the pixel during the setting operation. That is, the operation of setting a signal (setting operation) and the operation of inputting a signal to a pixel (input operation) can be performed simultaneously. Therefore, as in the current source circuit of fig. 19, it is not necessary to provide 2 current source circuits for 1 signal line.

The present invention having the above structure can supply a desired current to the outside while suppressing the influence of variation in characteristics of the TFT.

(embodiment 2)

As described above, in the current source circuits shown in fig. 19 (and fig. 40(a), 23(B), 38(B), etc.), it is preferable to provide 2 current source circuits for each signal line (each column), and to perform the setting operation for one current source circuit and the input operation (output current to the pixel) for the other current source circuit. This is because the setting operation and the input operation cannot be performed simultaneously. In the present embodiment, the configuration and operation of the 1 st current source circuit 421 or the 2 nd current source circuit 422 shown in fig. 2 will be described with reference to fig. 25.

The signal line driver circuit includes a current source circuit 420, a shift register, a latch circuit, and the like.

In the present invention, the signal input from the terminal a represents a sampling pulse from the shift register. That is, the set signal in fig. 2 corresponds to a sampling pulse from the shift register. In the present invention, the current source circuit 420 is set according to the timing of the sampling pulse from the shift register.

However, the sampling pulse is not directly input due to the configuration of the current source circuit, the driving method, or the like, but a signal supplied from an output terminal of a logic operator connected to a setting control line (not shown in fig. 2) is input. One of the 2 input terminals of the logic operator receives a sampling pulse, and the other receives a signal supplied from a setting control line.

The current source circuit 420 is controlled by a setting signal input through a terminal a, supplies a current (reference current) from a terminal b, and outputs a current proportional to the current (reference current) from a terminal c.

In fig. 25a, a circuit including switches 134 to 139, a transistor 132 (n-channel type), and a capacitor 133 for holding a gate-source voltage VGS of the transistor 132 corresponds to the 1 st current source circuit 421 or the 2 nd current source circuit 422.

In the 1 st current source circuit 421 or the 2 nd current source circuit 422, the switches 134 and 136 are turned on by a signal input through the terminal a. The switches 135 and 137 are turned on by a signal input from the control line via the terminal d. Thus, a current (reference current) is supplied from the reference constant current source 109 connected to the current line through the terminal b, and the capacitor element 133 holds a predetermined charge. Further, the capacitor 133 holds the charge until the current (reference current) flowing from the constant current source 109 and the drain current of the transistor 132 become equal to each other.

Then, the switches 134 to 137 are turned off by signals inputted through the terminals a and d. Since the capacitor element 133 holds a predetermined charge, the transistor 132 can flow a current having a magnitude corresponding to the signal current Idata. When the switches 101 (signal current control switches), 138, and 139 are turned on, a current is supplied to the pixel connected to the signal line via the terminal c. At this time, the gate voltage of the transistor 132 is maintained at a predetermined gate voltage by the capacitor element 133, and a drain current corresponding to the signal current Idata flows to the drain region of the transistor 132. Therefore, the magnitude of the current flowing through the pixel can be controlled regardless of the characteristic dispersion of the transistor constituting the signal line driver circuit.

When the switch 101 (signal current control switch) is not provided, the switches 138 and 139 are turned on, and a current flows through the pixel connected to the signal line via the terminal c.

In fig. 25B, a circuit including switches 144 to 147, a transistor 142 (n-channel type), a capacitor 143 for holding a gate-source voltage VGS of the transistor 142, and a transistor 148 (n-channel type) corresponds to the 1 st current source circuit 421 and the 2 nd current source circuit 422.

In the 1 st current source circuit 421 and the 2 nd current source circuit 422, the switches 144 and 146 are turned on by a signal input through the terminal a. The switches 145 and 147 are turned on by a signal input from the control line via the terminal d. Thus, a current (reference current) is supplied from the constant current source 109 connected to the current line through the terminal b, and the capacitor 143 holds an electric charge. The capacitor 143 holds the charge until the current (reference current) flowing from the constant current source 109 and the drain current of the transistor 142 become equal to each other. When the switches 144 and 145 are turned on, the transistor 148 is automatically turned off because the gate-source voltage VGS of the transistor 148 is 0V.

Then, the switches 144 to 147 are turned off by signals inputted through the terminals a and d. Thus, since the capacitor element 143 holds a predetermined charge, the transistor 142 has a capability of flowing a current having a magnitude corresponding to the signal current Idata. Then, if the switch 101 (signal current control switch) is in an on state, a current is supplied to the pixel connected to the signal line via the terminal c. At this time, the gate voltage of the transistor 142 is maintained at a predetermined gate voltage by the capacitor element 143, and a drain current corresponding to the signal current Idata flows to the drain region of the transistor 142. Therefore, the magnitude of the current flowing through the pixel can be controlled regardless of the characteristic dispersion of the transistor constituting the signal line driver circuit.

When the switches 144 and 145 are turned off, the gate and source of the transistor 142 have different potentials. As a result, the electric charge held by the capacitance element 143 is also distributed to the crystal 148, and the transistor 148 is automatically turned on. Here, the transistors 142, 148 are connected in series, and the gates are connected to each other. Therefore, the transistors 142 and 148 operate as multi-gate transistors. That is, the gate length L of the transistor is different between the set operation and the input operation. Therefore, the current value supplied from the terminal b during the setting operation can be larger than the current value supplied from the terminal c during the input operation. Therefore, various loads (wiring resistance, cross capacitance, and the like) arranged between the terminal b and the reference constant current source can be charged more quickly. Therefore, the setting operation can be completed quickly. When the switch 101 (signal current control switch) is not arranged, the transistors 144 and 145 are turned off, and a current flows through the pixel connected to the signal line via the terminal c.

Here, the configuration of fig. 25(a) corresponds to the addition of the terminal d to the configuration of fig. 23 (a). The configuration of fig. 25(B) corresponds to the addition of the terminal d to the configuration of fig. 23 (B). In this way, by adding a switch connected in series to the configuration of fig. 23(a) and (B) and correcting it, the configuration shown in fig. 25(a) and (B) to which d is added is achieved. Further, by arranging 2 switches connected in series in the 1 st current source circuit 421 or the 2 nd current source circuit 422, the configurations of the current source circuits shown in fig. 23, 24, 38, 37, 40, and the like can be arbitrarily used.

In fig. 2, the current source circuit 420 having two current source circuits, i.e., the 1 st current source circuit 421 and the 2 nd current source circuit 422, is provided for each signal line, but the present invention is not limited thereto. The number of current source circuits per signal line is not particularly limited and may be set arbitrarily. The plurality of current source circuits may be set so that the corresponding constant current sources are provided, respectively, and the signal current may be set to the current source circuit in accordance with the constant current source. For example, 3 current source circuits 420 may be provided for each signal line, and the signal current may be set in each current source circuit 420 according to a different reference constant current source 109. For example, the signal current is set using a 1-bit reference constant current source for 1 current source current 420, the signal current is set using a 2-bit reference constant current source for 1 current source current 420, and the signal current is set using a 3-bit reference constant current source for 1 current source current 420. Thereby, 3-bit display is possible.

The present invention having the above-described configuration can suppress the influence of variation in characteristics of the TFT, and can supply a desired current to the outside.

This embodiment can be arbitrarily combined with embodiment 1.

(embodiment 3)

In this embodiment, a structure of a light-emitting device including a signal line driver circuit according to the present invention will be described with reference to fig. 15.

In fig. 15(a), the light-emitting device includes a pixel portion 402 in which a plurality of pixels are arranged in a matrix over a substrate 401, and a signal line driver circuit 403 and1 st and 2 nd scan line driver circuits 404 and 405 are provided around the pixel portion 402. In fig. 15(a), there are a signal line driver circuit 403 and 2 sets of scan line driver circuits 404, 405, but the present invention is not limited thereto. The number of the driving circuits can be arbitrarily designed according to the structure of the pixel. Signals are supplied from the outside to the signal line driver circuit 403 and the 1 st and 2 nd scan line driver circuits 404 and 405 through the FPC 406.

The configuration and operation of the 1 st and 2 nd scanning line driving circuits 404 and 405 will be described with reference to fig. 15 (B). The 1 st and 2 nd scan line driver circuits 404 and 405 include a shift register 407 and a buffer 408. The shift register 407 sequentially outputs sampling pulses in accordance with a clock signal (G-CLK), a start pulse (S-SP), and an inverted clock signal (G-CLKb). Then, the sampling pulse amplified by the buffer 408 is input to the scanning line so as to be changed into a selected state row by row. Signals are sequentially written from the signal lines to the pixels controlled by the selected scanning line.

Further, a level shift circuit may be provided between the shift register 407 and the buffer 408. By configuring the level shift circuit, the voltage amplitude can be made large.

This embodiment can be arbitrarily combined with embodiments 1 and 2.

(embodiment 4)

In the present embodiment, a detailed configuration of the signal line driver circuit 403 shown in fig. 15(a) and its operation will be described. In this embodiment, a signal line driver circuit 403 used for performing 1-bit digital gradation display will be described.

First, a case corresponding to fig. 1 will be described. Here, a case of driving in the order of lines will be described.

Fig. 6(a) shows a schematic diagram of the signal line driver circuit 403 when 1-bit digital gradation display is performed. The signal line driver circuit 403 has a shift register 411, a1 st latch circuit 412, a2 nd latch circuit 413, and a constant current source circuit 414.

To explain the operation, the shift register 411 is configured using a plurality of flip-flop circuits (FF) and the like, and sequentially outputs sampling pulses at the timings of the clock signal (S-CLK), the start pulse (S-SP), and the inverted clock signal (S-CLKb).

The sampling pulse output from the shift register 411 is input to the 1 st latch circuit 412. The 1 st latch circuit 412 receives a digital video signal and holds the video signal in each column at the timing of the input of the sampling pulse.

In the 1 st latch circuit 412, when the holding of the digital video signal is completed until the last column, a latch pulse is input to the 2 nd latch circuit 413 during the horizontal retrace line period, and the video signals held by the 1 st latch circuit 412 are transferred to the 2 nd latch circuit 413 all at once. In this way, the video signals held by the 2 nd latch circuit 413 are supplied to the constant current circuits 414 simultaneously for the entire line.

While the video signal held by the 2 nd latch circuit 413 is supplied to the constant current circuit 414, the shift register 411 outputs a sampling pulse again. Thereafter, this operation is repeated, and the processing of the 1-frame video signal is performed. The constant current circuit 411 may convert a digital signal into an analog signal.

In the present invention, the sampling pulse output from the shift register 411 is input to the constant current circuit 414.

Further, the constant current circuit 414 is provided with a plurality of current source circuits 420. Fig. 6(B) schematically shows a signal line driver circuit for 3 signal lines from the i-th column to the (i +2) -th column.

The current source circuit 420 is controlled by a signal input through the terminal a. Further, a current is supplied from a reference constant current source 109 connected to a current line via a terminal b. A switch 101 (signal current control switch) is provided between the current source circuit 420 and the pixel connected to the signal line Sn, and the switch 101 (signal current control switch) is controlled by a video signal. When the video signal is a bright signal, a current is supplied from the current source circuit 420 to the pixel. In contrast, when the video signal is a dark signal, the switch 101 (signal current control switch) is controlled so that no current is supplied to the pixel. That is, the current source circuit 420 has a capability of flowing a predetermined current, and whether or not the current is supplied to the pixel is controlled by the switch 101 (signal current control switch).

In the present invention, the signal input to the current source circuit 420 via the terminal a corresponds to a sampling pulse supplied from the shift register. Depending on the configuration of the current source circuit, the driving method, and the like, the sampling pulse is not directly input, but a signal supplied from an output terminal of a logic operator connected to a setting control line (not shown in fig. 6) is input.

In addition, 2 input terminals of the logical operator receive 1 sampling pulse, and the other input terminal receives a signal supplied from a setting control line. That is, the current source circuit 420 is set at the timing of the sampling pulse or the signal supplied from the output terminal of the logical operator connected to the setting control line.

Fig. 42 shows a signal line driver circuit including a setting control line and a logic operator. In the configuration shown in fig. 42, a switch or the like may be provided instead of the logic operator.

Note that the configuration of the current source circuit 420 shown in fig. 23, 24, 38, 37, and 40 can be arbitrarily used as the configuration of the current source circuit 420.

Further, the current source circuit 420 may have not only 1 configuration but also a plurality of configurations. When the current source circuit 420 has the configuration shown in fig. 23(a) and 24(a), the setting operation cannot be performed during the input operation. Therefore, it is necessary to perform the setting operation while the input operation is not performed. However, in 1 frame, the periods during which the input operation is not performed may be dispersed, and in this case, it is preferable that the respective columns are not sequentially selected, and that any column be selected. Therefore, as the shift register, a decoding circuit or the like capable of random selection is preferably used. As an example, fig. 43 shows a decoding circuit. When the decoding circuit shown in fig. 43 is used, the setting operation of the current source circuit is not performed sequentially from the 1 st column to the last 1 st column, but may be performed randomly. Thus, the length of time for performing the setting operation can be set arbitrarily long.

In addition to the above-described decoding circuit, a circuit shown in fig. 44(a) can be used. In fig. 44a, a pulse output from the shift register and signals supplied from the output control lines (1 st to 3 rd output control lines) are input to the logic operator. As shown in fig. 44(B), by controlling the pulses of the respective output control lines, sampling pulses can be sequentially output from the 1 st column to the last 1 st column. That is, the same waveform as in the past can be output.

When an operation different from the previous operation is desired, as shown in fig. 45(a), the 1 st output control line is set to the selected state, and the 2 nd and 3 rd output control lines are set to the non-selected state. Thus, the sampling pulse of the 1 st column can be output for a longer period than in the past. Therefore, after the 1 st column sampling pulse is output, the 4 th column sampling pulse is output. Similarly, as shown in fig. 45(B), in a state where the 2 nd output control line is placed in a selected state, the 1 st and 3 rd output control lines are placed in a non-selected state. Thus, the sampling pulse of the 2 nd column can be output for a longer period than in the past. Further, after the 2 nd column sampling pulse is output, the 5 th column sampling pulse is output. In the above configuration, the selection from the 1 st column to the last 1 st column is not completely random, but only a specific 1 st column may be selected in a longer period than usual. Therefore, the setting operation of the current source circuit can be performed more freely.

Further, a circuit shown in fig. 46 may be used. In fig. 46, the operation is controlled according to control 1 and control 2. When control 1 and control 2 are set to the selected state, the switch disposed between shift register 1 and shift register 2 is turned on, and the switch disposed between shift register 2 and shift register 3 is turned on. That is, the 1 st, 2 nd, and 3 rd shift registers become on states. In this state, when the start pulse signal SP is input, the pulse from the 1 st shift register is shifted to the 2 nd shift register, and the pulse from the 2 nd shift register is shifted to the 3 rd shift register. That is, the same waveform as in the past can be output. When an operation different from the past is desired, the control 1 is set to the non-selection state. Thus, the switch disposed between the 1 st shift register and the 2 nd shift register is in a non-conductive state, and the switch disposed between the 2 nd shift register and SP1 is in a conductive state. Also, the start pulse signal is input to the SP1 instead of the SP. Thus, a sampling pulse is output from the 2 nd shift register. That is, in the 1 st column to the last 1 st column, the sampling pulse is output from the middle column. When another operation is further desired, the control 2 is set to the non-selection state. Thus, the switch disposed between the 2 nd shift register and the 3 rd shift register is in a non-conductive state, and the switch disposed between the 3 rd shift register and SP2 is in a conductive state. Also, a start pulse signal is input to SP 2. Thus, the sampling pulse is output from the 3 rd shift register. Thus, in the structure of fig. 46, the selection from the 1 st column to the last column is not completely random, but only a specific range of columns may be selected. In this case, by lowering the frequency of the clock signal, selection can be made for a longer period than in the past. Therefore, the setting operation of the current source circuit can be performed more freely.

Thus, various advantages are provided, such as the possibility of selecting a column or a current source circuit at random or freely to some extent and performing a setting operation of the current source circuit. For example, when the period in which the setting operation is possible is divided into 1 frame, an arbitrary column can be selected, and the degree of freedom can be improved and the time for the setting operation can be extended. Further, there is another advantage that the influence of charge leakage in the capacitive element (for example, the capacitive element 103 in fig. 23(a), the capacitive element 123 in fig. 23(B), the capacitive element 107 in fig. 23(B), or the like) in the current source circuit 420 can be made less conspicuous.

A capacitance element is provided in the current source circuit 420. However, the capacitor element may be replaced with a gate capacitance of a transistor or the like. The capacitor element accumulates electric charge by a setting operation of the current source circuit. The setting operation of the current source circuit is ideally performed only 1 time at the time of power input. That is, when the signal line driver circuit is operated, the operation may be performed only 1 time in the first period of the operation. This is because the amount of charge accumulated in the capacitor element does not change, and it is not necessary to change the amount of charge with the operating state or time. In fact, in the capacitor element, either various noises are generated or a leakage current flows through a transistor connected to the capacitor element. As a result, the amount of charge accumulated in the capacitor element may change with time. When the amount of charge changes, the current output from the current source circuit, that is, the current input to the pixel also changes. As a result, the luminance of the pixel varies. Therefore, in order to keep the charge stored in the capacitor element unchanged, it is necessary to perform a setting operation of the current source circuit periodically at a certain cycle, to recharge the charge, to restore the changed charge again, and to hold the correct charge amount again.

If the amount of charge fluctuation of the capacitor element is large, the current source circuit is set to recharge the charge, restore the changed charge again, and hold the correct charge amount again, and accordingly, the amount of current output from the current source circuit also fluctuates greatly. Therefore, when the setting operation is performed in order from the 1 st column, the variation in the amount of current output from the current source circuit may disturb the display or may make the display invisible. That is, the change in the pixel luminance occurring in the order from the 1 st column may disturb the display or may make the display invisible. In this case, if the setting operation is performed at random instead of sequentially from the 1 st column, the variation in the amount of current output from the current source circuit can be made less conspicuous. Thus, by randomly selecting a plurality of wirings, various advantages can be brought about.

On the other hand, when the current source current 420 has the configuration shown in fig. 23(C) to (E), the setting operation and the input operation can be performed simultaneously. However, when a current source circuit in which the setting operation and the input operation can be performed simultaneously is used, it is possible to realize either a change in the amount of current output from the current source circuit that is not significant or a long period of time during which the setting operation is performed, and therefore it is effective to select the current source circuit at random.

In fig. 6(B), the setting operation is performed in a row-by-row manner, but the present invention is not limited thereto. As shown in fig. 47, the setting operation may be performed in a plurality of rows at the same time. Here, the simultaneous setting operation of a plurality of rows is referred to as multiphase operation. In fig. 47, 2 reference constant current sources 109 are arranged, but the setting operation may be performed by a reference constant current source arranged separately from the 2 reference constant current sources.

Next, the detailed configuration and operation of the constant current circuit 414 shown in fig. 6(B) will be described.

Here, fig. 5 shows a circuit in which a part of the current source circuit has the configuration of fig. 23 (C). Fig. 48 shows a circuit in which a part of the current source circuit uses the configuration of fig. 23 (a). Fig. 3 and 4 show a circuit in which a plurality of (2) current source circuits are arranged in 1 column as shown in fig. 2, and show a circuit in which a part of the current source circuits is configured as shown in fig. 23 a. First, the configuration shown in fig. 3 and 4 will be described.

First, the constant current circuit 414 having the current source circuit having the configuration shown in fig. 6(a) will be described. In the configuration shown in fig. 6a, the setting operation for holding a signal in the current source circuit and the operation for inputting a signal from the current source circuit to the pixel (input operation) cannot be performed simultaneously. Therefore, it is preferable that 2 current source circuits are provided for each signal line, 1 current source circuit performs a setting operation, and the other current source circuit performs an input operation.

In the current source circuits 420 provided in the respective columns of FIGS. 3 and 4, whether or not a predetermined signal current is output to the signal line Si (1. ltoreq. i. ltoreq. n) is controlled by information including the digital video signal input from the 2 nd latch circuit 413.

In fig. 3, the current source circuit 420 has a1 st current source circuit 421 and a2 nd current source circuit 422. Then, one of the 1 st current source circuit 421 and the 2 nd current source circuit 422 performs a setting operation, and the other performs an input operation. The 1 st current source circuit 421 and the 2 nd current source circuit 422 have a plurality of circuit elements. The 1 st current source circuit 421 includes a NAND70, an inverter 71, an inverter 72, an analog switch 73, an analog switch 74, transistors 75 to 77, and a capacitor 78. The 2 nd current source circuit 422 includes a NAND80, an inverter 81, an inverter 82, an inverter 89, an analog switch 83, an analog switch 84, transistors 85 to 87, and a capacitor 88. In the present embodiment, transistors 75 to 77 and transistors 85 to 87 are all of n-channel type.

In the 1 st current source circuit 421, an input terminal of the NAND70 is connected to the shift register 411 and the control line 92, and an output terminal of the NAND70 is connected to an input terminal of the inverter 71. An output terminal of the inverter 71 is connected to gates of the transistor 75 and the transistor 76.

The analog switch has 4 terminals. And the remaining 2 terminals are turned on or off according to signals input to 2 terminals out of the 4 terminals.

The analog switch 73 is selectively turned on or off in accordance with a signal input from the output terminal of the NAND70 and a signal input from the output terminal of the inverter 71. The input terminal of the inverter 72 is connected to the control line 92. The analog switch 74 is selectively turned on or off in accordance with a signal input from the control line 92 and the output terminal of the inverter 72.

The source and drain regions of transistor 75, one connected to current line 93, and the other connected to one of the source and drain regions of transistor 77. A source region and a drain region of the transistor 76 are connected to the current line 93, and the other is connected to one terminal of the capacitive element 78 and the gate of the transistor 77. The source and drain regions of the transistor 77, one connected to Vss, and the other connected to the analog switch 73.

A reference constant current source (not shown) is connected to the current line 93.

One electrode of the capacitor element 78 is connected to Vss, and the other electrode is connected to the gate of the transistor 77. The capacitor element 78 functions to hold the gate-source voltage of the transistor 77.

In the 2 nd current source circuit 422, an input terminal of the inverter 89 is connected to the control line 89. An output terminal of the inverter 89 is connected to one input terminal of the NAND 80. The other output terminal of the NAND80 is connected to the shift register 411. An output terminal of the NAND80 is connected to an input terminal of the inverter 81. An output terminal of the inverter 81 is connected to gates of the transistor 85 and the transistor 86.

The analog switch 83 is selectively turned on or off in accordance with a signal input from the output terminal of the NAND80 and a signal input from the output terminal of the inverter 81. The input terminal of the inverter 82 is connected to the control line 92. The analog switch 84 is selectively turned on or off in accordance with a signal input from the control line 92 and the output terminal of the inverter 82.

The source and drain regions of transistor 85, one connected to current line 93, and the other connected to one of the source and drain regions of transistor 87. A source region and a drain region of the transistor 86 are connected to the current line 93, and the other is connected to one terminal of the capacitive element 88 and the gate of the transistor 87. The source region and the drain region of the transistor 87 are connected to Vss, and the other is connected to the analog switch 83.

One electrode of the capacitor element 88 is connected to Vss, and the other electrode is connected to the gate of the transistor 87. The capacitor element 88 functions to hold the gate-source voltage of the transistor 87.

Here, the operation of the current source circuit of fig. 3 will be described with reference to fig. 28.

FIG. 28 is a timing chart showing the setting control line 92 and the scanning lines of the 1 st to 3 rd rows. The operation of the current source circuit 420 in the period a will be described with reference to fig. 3, and the operation of the current source circuit 420 in the period B will be described with reference to fig. 4. In the period a, the 1 st current source circuit 421 performs the setting operation, and the 2 nd current source circuit 422 performs the input operation. In the period B, the 1 st current source circuit 421 performs an input operation, and the 2 nd current source circuit 422 performs a setting operation.

First, the operation of the current source circuit 420 in the period a is explained. The operation of the 1 st current source circuit 421 that performs the setting operation will be described.

In the period a, the signal inputted from the setting control line 92 is High. Then, a sampling pulse (corresponding to a High signal) is sequentially input from each column of the shift register 411. The NAND70 performs a logic operation on signals (both High) input from the shift register 411 and the setting control line 92, and outputs Low. The inverter 71 performs a logical operation on the input signal (Low) and outputs High.

A signal (High) is input from the output terminal of the inverter 71 to the gates of the transistors 75 and 76, and the transistors 75 and 76 are turned on. Thus, the current supplied from the current line 93 flows through the transistors 75 and 76, through the capacitance element 78, and to Vss. The capacitive element 78 begins to accumulate charge.

Then, the capacitor element 78 gradually accumulates electric charges, and a potential difference starts to occur between both electrodes. When the potential difference reaches Vth, the transistor 77 is turned from off to on. The capacitor element 78 accumulates charges until the potential difference between both electrodes, that is, the gate-source voltage of the transistor 77 reaches a desired voltage. In other words, the charge accumulation is continued until the voltage at which the signal current can flow in the transistor 77 is reached. Then, after a certain time, the accumulation of the electric charge is terminated.

At this time, the analog switches 73 and 74 are turned on.

Next, the operation of the 2 nd current source circuit 422 which performs an input operation (outputs a current to a pixel) will be described. In the 2 nd current source circuit 422, the setting operation is performed, and the capacitor element 88 holds a predetermined charge.

In the period a, the signal inputted from the setting control line 92 is High. The inverter 89 performs a logical operation on the input signal (High) and outputs Low. The NAND80 performs a logical operation on the signals input from the inverter 89 and the shift register 411, and outputs a High signal. The inverter 81 performs a logical operation on the input signal (High) and outputs Low.

A signal (Low) is input from the output terminal of the inverter 81 to the gates of the transistors 85 and 86, and the transistors 85 and 86 are turned off.

On the other hand, the analog switch 83 is turned on by a signal (High) input from the output terminal of the NAND80 and a signal (Low) input from the output terminal of the inverter 81. The analog switch 84 is turned on by a signal (High) input from the setting control line 92 and a signal (Low) input from the output terminal of the inverter 82.

The capacitor element 88 holds a predetermined charge, and the transistor 87 is turned on. In this state, the drain current and the signal current of the transistor 87 are equal.

The analog switch 90 is turned on or off according to a signal input from the 2 nd latch circuit 413 and a signal input from the inverter 90. In the configuration shown in fig. 3, when a High signal is input from the 2 nd latch circuit 413, the analog switch 90 is turned on, and when a Low signal is input from the 2 nd latch circuit 413, the analog switch 90 is turned off.

Here, it is assumed that a High signal is input from the 2 nd latch circuit 413 and the analog switch 90 is turned on. Thus, a current flows from the signal line (Si) through the transistor 87 to Vss. The current value and the signal current are equal. In other words, a predetermined signal current is supplied to the pixel connected to the signal line (Si).

In this case, when the transistor 87 is operated in the saturation region, the current supplied to the pixel is not changed even when the voltage between the source and drain of the transistor 87 is changed.

Next, the operation of the current source circuit 420 in the period B will be described with reference to fig. 4. First, the operation of the 1 st current source circuit 421 which performs an input operation (outputs a current to a pixel) will be described. In the 1 st current source circuit 421, the setting operation is performed, and the capacitor element 78 holds a predetermined charge.

In the period B, the signal input from the setting control line 92 is Low. The NAND70 performs a logical operation on signals input from the shift register 411 and the setting control line 92, and outputs a High signal. The inverter 71 performs a logical operation on the input signal (High) and outputs Low.

A signal (Low) is input from the output terminal of the inverter 71 to the gates of the transistors 75 and 76, and the transistors 75 and 76 are turned off.

On the other hand, the analog switch 73 is turned on by a signal (High) input from the output terminal of the NAND70 and a signal (Low) input from the output terminal of the inverter 71. The analog switch 74 is turned on by a signal (Low) input from the setting control line 92 and a signal (High) input from the output terminal of the inverter 72.

The capacitor element 78 holds a predetermined charge, and the transistor 77 is turned on. In this state, the drain current and the signal current of the transistor 77 are equal.

Here, it is assumed that a High signal is input from the 2 nd latch circuit 413 and the analog switch 90 is turned on. Thus, a current flows from the signal line (S1) through the transistor 77 to Vss. The current value and the signal current are equal. In other words, a predetermined signal current is supplied to the pixel connected to the signal line (S1).

In this case, when the transistor 77 operates in the saturation region, the current supplied to the pixel does not change even if the voltage between the source and drain of the transistor 77 changes.

Next, the operation of the 2 nd current source circuit 422 in which the setting operation is performed in the period B will be described.

In the period B, the signal input from the setting control line 92 is Low. The inverter 89 performs a logical operation on the input signal (Low) and outputs High. The NAND80 performs a logical operation on signals (one is High) input from the inverter 89 and the shift register 411, and outputs Low. Then, the inverter 81 performs a logical operation on the input signal (Low) and outputs High.

A signal (High) is input from the output terminal of the inverter 81 to the gates of the transistors 85 and 86, and the transistors 85 and 86 are turned on. Thus, the current supplied from the current line 93 flows through the transistors 85 and 86, flows through the capacitance element 88, and reaches Vss. Next, the capacitor element 88 starts to accumulate electric charge.

Then, the capacitor element 88 gradually accumulates electric charges, and a potential difference starts to occur between both electrodes. When the potential difference reaches Vth, the transistor 87 is turned on from off. The capacitor element 88 accumulates charges until the potential difference between both electrodes, that is, the gate-source voltage of the transistor 87 reaches a desired voltage. In other words, the charge accumulation is continued until the voltage at which only the signal current can flow in the transistor 87 is reached. At this time, the analog switches 83 and 84 are turned off.

In the above-described operation described with reference to fig. 28, the setting operation and the input operation are switched for each line. However, the present invention is not limited thereto. The setting operation and the input operation may be switched every several lines.

Here, all the transistors included in the current source circuit 420 shown in fig. 3 and 4 are of an n-channel type, but the present invention is not limited thereto. In the current source circuit 420 shown in fig. 3 and 4, a p-channel transistor may be used. The operation of the current source circuit 420 when a p-channel transistor is used is the same as the above operation except that the direction of current flow is changed and the capacitance element is not connected to Vss but to Vdd.

When the current source circuit 420 shown in fig. 3 and 4 uses a p-channel transistor, Vss and Vdd are switched, that is, when the direction of current flow is not changed, it is easy to use the current source circuit in comparison with fig. 23 and 24. In addition, a transistor used simply as a switch may have any polarity.

Next, the structure and operation of the constant current circuit 414, which are different from those described above, will be described with reference to fig. 5. Whether or not the current source circuit 420 provided in each column outputs a predetermined signal current to the signal line Si (1 ≦ i ≦ n) is controlled by having information included in the digital video signal inputted from the 2 nd latch circuit 413.

The configuration of fig. 5 is a circuit in which 1 current source circuit is arranged in 1 column as shown in fig. 1.

In fig. 5(a) to (C), the current source circuit 420 includes transistors 94 to 97 and a capacitor element 99. In the present embodiment, all of the transistors 94 to 97 are of an n-channel type.

The gate of the transistor 94 receives a signal from the 2 nd latch circuit 413. The source region and the drain region of the transistor 94, one is connected to the source signal line (S1), and the other is connected to one of the source region and the drain region of the transistor 95.

The sampling pulses from the shift register 411 are input to the gates of the transistor 97 and the transistor 98. A source region and a drain region of the transistor 97, one of which is connected to one of the source region and the drain region of the transistor 96, and the other of which is connected to one electrode of the capacitive element 99. The source and drain regions of transistor 98, one connected to current line 93, and the other connected to one of the source and drain regions of transistor 96.

One electrode of the capacitor element 99 is connected to the gates of the transistors 95 and 96, and the other electrode is connected to Vss. The capacitor element 99 functions to hold the gate-source voltage of the transistor 95 and the transistor 96.

The source and drain regions of transistor 95 are connected one to Vss and the other to one of the source and drain regions of transistor 94.

Here, the operation of the current source circuit 420 shown in fig. 5 will be described with reference to fig. 5(a) to 5 (C).

First, a sampling pulse is input from the shift register 411 to the gates of the transistors 97 and 98, and both the transistors are turned on. Thus, the current supplied from the current line 93 flows to the capacitor 99 through the transistors 98 and 97. At this time, the 2 nd latch circuit 413 does not input a signal to the gate of the transistor 94, and the transistor 94 is turned off.

Then, the capacitor element 99 gradually accumulates electric charges, and a potential difference starts to be generated between both electrodes. When the potential difference reaches Vth, the transistors 95 and 96 are turned on.

Next, the capacitor element 99 accumulates charges until the potential difference between the electrodes, that is, the gate-source voltage of the transistors 95 and 96 reaches a desired voltage. In other words, the accumulation of the electric charges is continued until the voltage at which only the current corresponding to the signal current can flow through the transistors 95 and 96 is reached (fig. 5 a).

Then, after a certain time, the accumulation of the electric charge is terminated (fig. 5B).

Next, the transistor 94 is turned on by a signal (corresponding to a digital video signal) input from the 2 nd latch circuit 413. At this time, the shift register 411 does not input the sampling pulse to the gate of the transistor 94, and the transistors 97 and 98 are turned off. Since the capacitor element 99 holds a predetermined charge, the transistors 95 and 96 are turned on. Thus, current flows from the signal line (S1) to Vss via transistors 94 and 95. The current value and the signal current are equal. In other words, a predetermined signal current is supplied to the pixel connected to the signal line (S1).

At this time, if the transistor 95 operates in the saturation region, the current supplied to the pixel does not change even if the voltage between the source and drain of the transistor 95 changes.

In the present embodiment, all the transistors including the current source circuit 420 shown in fig. 5 are of an n-channel type, but the present invention is not limited thereto. In the current source circuit 420 shown in fig. 5, a p-channel transistor may be used. The operation of the current source circuit 420 when a p-channel transistor is used is the same as the above operation except that the direction of current flow is changed and the capacitance element is not connected to Vss but to Vdd.

As shown in fig. 21, 23(C) to 23(E), 24(B) to 24(D), and the like, circuit elements including the current source circuit 420 may have different connection structures. Since the operation of the current source circuit 420 in this case is the same as the operation of the current source circuit 420 described with reference to fig. 5, the description thereof is omitted in the present embodiment.

When the current source circuit 420 shown in fig. 5 uses a p-channel transistor, Vs s and Vdd are interchanged with each other, that is, the direction of current flow is not changed, and the current source circuit can be used easily in comparison with fig. 23 and 24. Further, the polarity of the transistor used simply as a switch may be any.

The configuration of fig. 5 is a circuit in which 1 current source circuit is arranged in 1 column as shown in fig. 1. In this case, if the current source circuit 420 has the configuration shown in fig. 23(a) and 24(a), the setting operation cannot be performed during the period in which the input operation (current output to the pixel) is performed. Therefore, the setting operation must be performed during a period in which the input operation (current output to the pixel) is not performed. On the other hand, when the current source circuit 420 has the configuration shown in fig. 23(C) to (E), the setting operation and the input operation can be performed simultaneously even if 1 current source circuit is arranged in 1 column.

Next, fig. 49, 50, and 51 show the detailed configuration of the constant current circuit 414 shown in fig. 42(a) and (B). Here, fig. 49 shows a configuration in which the circuit shown in fig. 1 is used for a portion corresponding to the constant current circuit 414 in fig. 42(B), and further shows a configuration in which the circuit shown in fig. 23(C) is used for a portion corresponding to the current source circuit. Fig. 50 shows a configuration in which the circuit shown in fig. 1 is used for a portion corresponding to the constant current circuit 414 in fig. 42(B), and a configuration in fig. 23(a) is used for a portion corresponding to the current source circuit. Fig. 51 shows a configuration in which the circuit shown in fig. 2 is used for a portion corresponding to the constant current circuit 414 in fig. 42(B), and further shows a configuration in which fig. 23(a) is used for a portion of the current source circuit.

In the configurations shown in fig. 49 and 50, the logical operator is disposed, but a switch or the like may be disposed instead of the logical operator. The logic operator controls whether or not to switch the setting operation of the current source circuit, and therefore, any circuit can be used as long as it can control the switching of the setting operation. In fig. 51, whether or not the setting operation of the current source circuit is performed is switched by controlling a signal supplied from the 1 st setting control line. Further, by controlling the signal supplied from the 2 nd setting control line, which current source circuit is used for the setting operation and which current source circuit is used for the input operation is controlled among the 2 current source circuits arranged for each 1 column.

Next, a case corresponding to fig. 34 will be described. Up to this point, the case of line-sequential driving has been described. Next, a case of driving in the order of dots will be described. In fig. 52(a), the video signal supplied from the video line is sampled at the timing of the sampling pulse supplied from the shift register 411. The current source circuit 420 is set according to the timing of the sampling pulse supplied from the shift register 411. As an example, when the configuration of fig. 52(a) is provided, driving is performed in the order of dots.

The signal input to the current source circuit 420 via the terminal a is not directly input with a sampling pulse due to the configuration of the current source circuit, the driving method, or the like, but is input with a signal supplied from an output terminal of a logic arithmetic unit connected to a setting control line (not shown in fig. 52 a). One of the 2 input terminals of the logic operator receives a sampling pulse, and the other receives a signal supplied from a setting control line. That is, the current source circuit 420 is set at the timing of the sampling pulse or the signal supplied from the output terminal of the logical operator connected to the setting control line.

Note that the switch 101 (signal current control switch) is turned on only during the period when the sampling pulse is output and the video signal is supplied from the video line, and the switch 101 (signal current control switch) is turned off when the sampling pulse is not output and the video signal is not supplied from the video line. This is because the switch for inputting current in the pixel is always in the on state. In this state, when the switch 101 (signal current control switch) is turned off, a current cannot be input to the pixel, and thus an accurate signal cannot be input.

Therefore, the latch circuit 452 is arranged to hold the video signal supplied from the video line and maintain the state of the switch 101 (signal current control switch). The latch circuit 452 may be constituted by a capacitor element and a switch alone, or may be constituted by an SRAM circuit. In this way, by outputting sampling pulses, supplying video signals sequentially from the video line for every 1 column, turning on or off the switch 101 (signal current control switch) in accordance with the video signals, and controlling the current supply to the pixels, dot sequential driving can be realized.

However, when the selection is performed from the 1 st column to the last 1 st column in order, the period of inputting a signal to a pixel is long in the first column from the 1 st column to the last 1 st column. On the other hand, in the 1 st column to the last 1 st column, even if a video signal is input in the last column, pixels of the next row are selected soon. As a result, the period of time for inputting a signal to the pixel becomes short. In this case, as shown in fig. 52(B), the period of time for inputting a signal to the pixel can be made longer by dividing the scanning line disposed in the pixel portion 402 from the center. In this case, 1 scan line driver circuit is disposed on each of the left and right sides of the pixel portion 402, and the pixels are driven by the scan line driver circuits. Thus, even in the same row of pixels, the period of signal input to the right-side pixel and the left-side pixel can be shifted. Fig. 52(C) shows output waveforms of the scanning line driving circuits arranged on the right and left sides of the 1 st and 2 nd rows and the start pulse (S-SP) of the shift register 411. By operating in this manner, even for the left-side pixel, the period for which a signal is input to the pixel can be made longer, and thus dot sequential driving is facilitated.

The setting operation of the current source circuit 420 may be performed at an arbitrary timing and an arbitrary number of times for the current source circuits arranged in an arbitrary column, regardless of whether the line-sequential driving or the dot-sequential driving is performed. However, it is preferable that the setting operation is performed only 1 time as long as the capacitor element connected between the gate and the source of the transistor arranged in the current source circuit 420 holds a predetermined charge. Alternatively, the discharge (change) may be performed when a predetermined charge held in the capacitor element is discharged. In addition, as for the setting operation of the current source circuits 420, the setting operation of the current source circuits 420 of all the columns may be performed regardless of the required period. That is, the setting operation of the current source circuits 420 of all columns can be performed within 1 frame period. Alternatively, the setting operation of the current source circuits 420 in several rows may be performed within 1 frame period, and as a result, the setting operation of the current source circuits 420 in all the rows may be performed over several frames.

In the present embodiment, the case where 1 current source circuit is arranged for each column has been described, but the present invention is not limited to this, and a plurality of current source circuits may be arranged.

In addition, as for the current source circuit in the signal line driver circuit of the present invention, fig. 87 shows a circuit diagram thereof, and fig. 88 shows a corresponding circuit diagram.

The present invention having the above-described structure can supply a desired current to the outside while suppressing the influence of variation in characteristics of the TFT.

This embodiment can be arbitrarily combined with embodiments 1 to 3.

(embodiment 5)

In the present embodiment, the detailed configuration and operation of the signal line driver circuit shown in fig. 15(a) will be described, but only the signal line driver circuit 403 used when performing 3-bit digital gradation display will be described.

Fig. 26 shows a schematic diagram of a signal line driver circuit 403 used for 3-bit digital gradation display. The signal line driver circuit 403 has a shift register 411, a1 st latch circuit 412, a2 nd latch circuit 413, and a constant current circuit 414.

To explain the operation simply, the shift register 411 is configured by using a plurality of flip-flop circuits (FF) and the like, and receives a clock signal (S-CLK), a start pulse (S-SP), and an inverted clock signal (S-CLKb). The sampling pulses are sequentially output in accordance with the timings of these signals.

The sampling pulse output from the shift register 411 is input to the 1 st latch circuit 412. The 1 st latch circuit 412 receives 3-bit digital video signals (digital data1 to digital data 3) and holds the video signals in the respective columns at the timing of the input sampling pulse.

In the 1 st latch circuit 412, when the holding of the digital video signal is completed until the last column, a latch pulse is input to the 2 nd latch circuit 413 during the horizontal retrace line period, and the 3-bit video signals (digital data1 to digital data 3) held by the 1 st latch circuit 412 are transferred to the 2 nd latch circuit 413 at once. In this way, the 3-bit video signals (digital data1 to digital data 3) held by the 2 nd latch circuit 413 are simultaneously input to the constant current circuit 414 in a row.

While the 3-bit digital video signals (digital data1 to digital data 3) held by the 2 nd latch circuit 413 are input to the constant current circuit 414, the shift register 411 outputs a sampling pulse again. Thereafter, this operation is repeated, and the processing of the 1-frame video signal is performed.

The constant current circuit 411 may convert a digital signal into an analog signal. Further, the constant current circuit 414 is provided with a plurality of current source circuits 420. Fig. 27 shows a schematic diagram of a signal line driver circuit for 3 signal lines from the ith row to the (i +2) th row.

Fig. 27 shows a case where the reference constant current sources 109 are arranged corresponding to each bit.

The current source circuit 420 has a terminal a, a terminal b, and a terminal c. The current source circuit 420 is controlled by a signal input through the terminal a. Further, a current is supplied from a reference constant current source 109 connected to a current line via a terminal b. Switches (signal current control switches) 111 to 113 are provided between the current source circuit 420 and the pixels connected to the signal line Sn, and the switches (signal current control switches) 111 to 113 are controlled by 1-3-bit video signals. When the video signal is a bright signal, a current is supplied from the current source circuit 420 to the pixel. On the other hand, when the video signal is a dark signal, the switches (signal current control switches) 111 to 113 are controlled so that no current is supplied to the pixels. That is, the current source circuit 420 has a capability of flowing a predetermined current, and whether or not to supply the current to the pixel is controlled by the switches (signal current control switches) 111 to 113.

The signal input to the current source circuit 420 through the terminal a corresponds to a sampling pulse supplied from the shift register. Depending on the configuration of the current source circuit, the driving method, and the like, the sampling pulse is not directly input, but a signal supplied from an output terminal of a logic operator connected to a setting control line (not shown in fig. 27) is input. The logic operator has 2 input terminals, 1 of which receives a sampling pulse, and the other of which receives a signal supplied from a setting control line. That is, the current source circuit 420 is set at the timing of the sampling pulse or the signal supplied from the output terminal of the logical operator connected to the setting control line.

In fig. 27, when the current source circuit 420 arranged in each signal line is configured by the circuit shown in fig. 23(a) and (B), a signal input from the output terminal of the logical operator connected to the control line corresponds to the setting signal. When the current source circuit 420 provided for each signal line is configured by the circuits shown in fig. 23(C) to (E), the sampling pulse from the shift register corresponds to the setting signal.

Here, fig. 53 shows a configuration in which the above-described setting control line and logic operator are used in the configuration shown in fig. 27. In fig. 53, a logic operator is disposed, but a switch or the like may be disposed instead of the logic operator.

In fig. 27 or 53, the current line and the reference constant current source are arranged corresponding to each bit. The sum of the current values supplied from the current sources of the respective bits is supplied to the signal line. That is, the current circuit 414 has a function of digital-to-analog conversion.

In the signal line driver circuit shown in fig. 27 or 53, the reference constant current source 109 is provided for each of 1 bit to 3 bits, but the present invention is not limited to this. As shown in fig. 54, the number of the reference constant current sources 109 may be smaller than the number of bits. For example, only the reference constant current source 109 of the highest bit (here, the 3 rd bit) is arranged, and1 current source circuit selected from a plurality of current source circuits arranged in 1 column is set. Then, the current source circuit that has performed the setting operation is used to perform the operation of the other current source circuit. In other words, the setting information can be shared among a plurality of current source circuits arranged in 1 column.

For example, only the current source circuit 420 for 3 bits is set. Then, the current source circuit 420 having performed the setting operation is used, and the other current source circuits 420 for 1 bit and 2 bits share information. More specifically, in the current source circuit 420, the gate terminal and the source terminal of a transistor (corresponding to the transistor 102 in fig. 23 a) for supplying current are connected. As a result, the voltages between the gates and the sources of the transistors sharing information (transistors supplying current) are equal.

In fig. 54, the setting operation is performed not for the current source circuit of the lowest bit (here, 1 bit) but for the current source circuit of the highest bit (here, 3 bits). The current source circuit of the highest bit that has performed the setting operation is used to share information with other current source circuits. In this way, by performing the setting operation for the current source circuit of the bit having the largest value, the influence of the characteristic variation of the current source circuit between bits can be reduced. If the setting operation is performed for the current source circuit of the lowest order (here, 1 bit) and information is shared with the current source circuit of the highest order, the current value of the higher order bit is not an accurate value if the characteristics of the current source circuits are varied. Since the current value output from the current source circuit for high bits is large, if the characteristics are slightly varied, the influence of the variation is large. The variation in the output current value is also large. On the other hand, when the setting operation is performed for the current source circuit of the highest order bit (here, 3 bits) and information is shared with the current source circuit of the lowest order bit, even if the characteristics of the respective current source circuits are varied, the output current value is small, and therefore the difference in current value due to the variation is small, and the influence is small.

In the present embodiment, 3 current source circuits 420 are provided for each signal line in order to exemplify the case of performing 3-bit digital gray scale display. When the signal currents supplied from the 3 current source circuits 420 connected to 1 signal line are set to 1: 2: 4, the magnitude of the current can be controlled in 23 to 8 steps.

The configuration of the current source circuit 420 shown in fig. 23, 24, 37, 38, 40, and the like can be arbitrarily used. The current source circuit 420 may have not only 1 type of configuration but also a plurality of types of configurations.

Next, the detailed configuration and operation of the constant current source circuit 414 shown in fig. 27 and 54 will be described using fig. 7, 8, 29, and 55 as an example. Whether or not the current source circuit 420 provided in each column of fig. 7 outputs a predetermined signal current to the signal line Si (1 ≦ i ≦ n) is controlled by information included in the digital video signal input from the 2 nd latch circuit 413.

Fig. 55 is a circuit diagram showing a configuration in which the reference constant current sources 109 having the same number as the number of bits are arranged, the current source circuit shown in fig. 1 is used for the signal line driving circuit shown in fig. 27, and the current source circuit shown in fig. 23(a) is used for the current source circuit. In fig. 55, in the setting operation, the transistors a to C are turned off in order to prevent current leakage. Alternatively, a switch may be provided in series with the transistors a to C so as to be turned off during the setting operation. Fig. 7 is a circuit diagram showing the arrangement of the reference constant current sources 109 having the same number as the number of bits, the current source circuit shown in fig. 2 being used in the signal line driver circuit shown in fig. 27, and the configuration shown in fig. 23(a) being used in the current source circuit. Fig. 8 shows a circuit diagram in which the reference constant current sources 109 having a smaller number of bits are arranged, the constant current circuit shown in fig. 1 is used for the signal line driver circuit shown in fig. 54, and the configuration shown in fig. 23(C) is used for the current source circuit. Fig. 29 is a circuit diagram in which the reference constant current source 109 having a smaller number of bits is arranged, the constant current circuit shown in fig. 1 is used for the signal line driver circuit shown in fig. 54, and the configuration shown in fig. 23(a) is used for the current source circuit.

The current source circuit 420 has a1 st current source circuit 423a and a2 nd current source circuit 424a controlled by a 1-bit digital video signal, a1 st current source circuit 423b and a2 nd current source circuit 424b controlled by a 2-bit digital video signal, and a1 st current source circuit 423c and a2 nd current source circuit 424c controlled by a 3-bit digital video signal. Further, the current source circuit 420 has an analog switch 170a and an inverter 171a, an analog switch 170b, an inverter 171b, an analog switch 170c, and an inverter 171 c.

The 1 st current source circuits 423a to 423c and the 2 nd current source circuits 424a to 424c perform a setting operation, and perform an operation (an input operation, an input current to a pixel) of inputting a signal to a pixel. The 1 st current source circuits 423a to 423c and the 2 nd current source circuits 424a to 424c have a plurality of circuit elements. Fig. 7 shows the 1 st current source circuit 423a and the 2 nd current source circuit 424a, and the circuit diagrams of the 1 st current source circuits 423b and 423c and the 2 nd current source circuits 424b and 424c refer to the 1 st current source circuit 423a and the 2 nd current source circuit 424a, and therefore, the illustration thereof is omitted in the present embodiment.

The 1 st current source circuit 423a includes a NAND150a, an inverter 151a, an inverter 152a, an analog switch 153a, an analog switch 154a, transistors 155a to 157a, and a capacitor 158 a. The 2 nd current source circuit 424a includes a NAND160a, an inverter 161a, an inverter 162a, an inverter 169a, an analog switch 163a, an analog switch 164a, transistors 165a to 167a, and a capacitor 168 a. In this embodiment, the transistors 155a to 157a and the transistors 165a to 167a are all n-channel type transistors.

In the 1 st current source circuit 423a, an input terminal of the NAND150a is connected to the shift register 411 and the 1 st control line 425a, and an output terminal of the NAND150a is connected to an input terminal of the inverter 151 a. An output terminal of the inverter 151a is connected to gates of the transistor 155a and the transistor 156 a.

The analog switch 153a selects conduction or non-conduction according to a signal input from the output terminal of the NAND150a and a signal input from the output terminal of the inverter 151 a. The input terminal of the inverter 152a is connected to the 1 st control line 425 a. The analog switch 154a selects conduction or non-conduction according to signals input from the 1 st control line 425a and the output terminal of the inverter 152 a.

The source and drain regions of transistor 155a, one connected to current line 426a, 1, and the other connected to one of the source and drain regions of transistor 157 a. The source and drain regions of the transistor 156a are connected to the 1 st current line 426a, and the other is connected to one terminal of the capacitive element 158a and the gate of the transistor 157 a. The source and drain regions of the transistor 157a, one connected to Vss, and the other connected to the analog switch 153 a.

One terminal of the capacitor element 158a is connected to Vss, and the other terminal is connected to the gate of the transistor 157 a. The capacitor element 158a functions to hold the gate-source voltage of the transistor 157 a.

In the 2 nd current source circuit 424a, the input terminal of the inverter 169a is connected to the 1 st control line 425 a. The output terminal of the inverter 169a is connected to one input terminal of the NAND160 a. The other input terminal of the NAND160a is connected to the shift register 411. The output terminal of the NAND160a is connected to the input terminal of the inverter 161 a. The output terminal of the inverter 161a is connected to the gates of the transistor 165a and the transistor 166 a.

The analog switch 163a selects conduction or non-conduction according to a signal input from the output terminal of the NAND160a and a signal input from the output terminal of the inverter 161 a. The input terminal of the inverter 162a is connected to the 1 st control line 425 a. The analog switch 164a selects conduction or non-conduction according to signals input from the 1 st control line 425a and the output terminal of the inverter 162 a.

The source and drain regions of transistor 165a, one connected to current line 426a, No. 1, and the other connected to one of the source and drain regions of transistor 167 a. The source and drain regions of the transistor 166a are connected to the 1 st current line 426a, and the other is connected to one terminal of the capacitive element 168a and the gate of the transistor 167 a. The source and drain regions of the transistor 167a, one connected to Vss, and the other connected to the analog switch 163 a.

One terminal of the capacitor element 168a is connected to Vss, and the other terminal is connected to the gate of the transistor 167 a. The capacitor element 168a functions to hold the gate-source voltage of the transistor 167 a.

The operation of the 1 st current source circuit 423a and the 2 nd current source circuit 424a shown in fig. 7 is the same as the operation of the 1 st current source circuit 421 and the 2 nd current source circuit 422 shown in fig. 3 and 4, and therefore, the description thereof is omitted in the present embodiment.

In the current source circuit 420 shown in fig. 7, the sum of the signal current supplied from the 1 st current source circuit 423a or the 2 nd current source circuit 424a, the signal current supplied from the 1 st current source circuit 423b or the 2 nd current source circuit 424b, and the signal current supplied from the 1 st current source circuit 423c or the 2 nd current source circuit 424c flows into the signal line Si. That is, if the signal current supplied from the 1 st current source circuit 423a or the 2 nd current source circuit 424a, the signal current supplied from the 1 st current source circuit 423b or the 2 nd current source circuit 424b, and the signal current supplied from the 1 st current source circuit 423c or the 2 nd current source circuit 424c are set to be 1: 2: 4, the magnitude of the current can be controlled in the order of 23 to 8.

In the current source circuit 420 shown in fig. 7, the on/off of the analog switches 170a to 170c is selected by a 3-bit digital video signal. When all of the analog switches 170a to 170c are assumed to be turned on, the current supplied to the signal line becomes the sum of the signal current supplied from the 1 st current source circuit 423a or the 2 nd current source circuit 424a, the signal current supplied from the 1 st current source circuit 423b or the 2 nd current source circuit 424b, and the signal current supplied from the 1 st current source circuit 423c or the 2 nd current source circuit 424 c. When it is assumed that only the analog switch 170a is turned on, only the signal current supplied from the 1 st current source circuit 423a or the 2 nd current source circuit 424a is supplied to the signal line.

Since the current values supplied from the current source circuits are different, it is necessary to set the current values flowing through the 1 st to 3 rd current lines 426a to 426c to 1: 2: 4.

Here, all the transistors included in the current source circuit 420 shown in fig. 7 are of an n-channel type, but the present invention is not limited thereto. The current source circuit 420 may also use a p-channel transistor. When a p-channel transistor is used, the operation of the current source circuit 420 is the same as the above operation except that the direction of current flow is different, and the capacitance element is not connected to Vss but to Vdd, and therefore, the description thereof will be omitted.

In fig. 7, the detailed circuit configurations of the current source circuits 423b and 423C and the current source circuits 424b and 424C are not shown, but the current source circuits 423b and 423C and the current source circuits 424b and 424C are not the current source circuits having the configurations shown in fig. 23(a), and the current source circuits having the configurations shown in fig. 23(C) to (E) may be used. That is, the current source circuit used for the signal line driver circuit used for the multi-bit digital gradation display can be designed by combining a plurality of configurations.

Further, when the current source circuit uses a p-channel transistor, it is easy to use if fig. 23 and 24 are used in comparison without exchanging Vss and Vdd, that is, without changing the direction of current flow. In addition, the polarity of the transistor which operates simply as a switch is not particularly limited.

Next, a structure of the constant current circuit 414 and an operation thereof, which are different from those described above, will be described with reference to fig. 8. In the current source circuit 420 of fig. 8, whether or not a predetermined signal current is output to the signal line Si (1 ≦ i ≦ n) is controlled by information included in the digital video signal input from the 2 nd latch circuit 413.

The current source circuit 420 has transistors 180 to 188 and a capacitor 189. In the present embodiment, all of the transistors 180 to 188 are of an n-channel type.

The gate of the transistor 180 receives the 1-bit digital video signal from the 2 nd latch circuit 413. A source region and a drain region of the transistor 180, one connected to a source signal line (Si), and the other connected to one of a source region and a drain region of the transistor 183.

The 2-bit digital video signal from the 2 nd latch circuit 413 is input to the gate of the transistor 181. A source region and a drain region of the transistor 181, one is connected to a source signal line (Si), and the other is connected to one of a source region and a drain region of the transistor 184.

The gate of the transistor 182 receives the 3-bit digital video signal from the 2 nd latch circuit 413. A source region and a drain region of the transistor 182, one is connected to a source signal line (Si), and the other is connected to one of a source region and a drain region of the transistor 185.

The source and drain regions of the transistors 183 to 185, one connected to Vss, and the other connected to one of the source and drain regions of the transistors 180 to 182. The source and drain regions of transistor 186, one connected to Vss, and the other connected to one of the source and drain regions of transistor 188.

The gates of the transistor 187 and the transistor 188 input signals from the shift register 411. A source region and a drain region of the transistor 187 are connected to one of the source region and the drain region of the transistor 186, and the other is connected to one electrode of the capacitor element 189. The source and drain regions of transistor 188 are connected one to current line 190 and the other to one of the source and drain regions of transistor 186.

One electrode of the capacitor element 189 is connected to gates of the transistors 183 to 186, and the other electrode is connected to Vss. The capacitor element 189 functions to hold gate-source voltages of the transistors 183 to 186.

The current source circuit 420 shown in fig. 8 is designed in the same manner as the current source circuit 420 shown in fig. 5 except that the transistors 180, 181, 183, and 184 are added. Therefore, the operation of the current source circuit 420 shown in fig. 8 will be omitted.

The current source circuit shown in fig. 8 is a circuit in which reference constant current sources 109 whose number is smaller than the number of bits are arranged, as shown in fig. 54.

In the current source circuit 420 shown in fig. 8, the sum of drain currents of the transistors 183 to 185 flows into the signal line Si. Here, the drain currents of the transistors 183 to 185 are set to 1: 2: 4, and the magnitude of the current can be controlled in 23 to 8 steps. That is, the difference in the current values supplied from the transistors 183 to 185 is caused by setting the W/L values of the transistors 183 to 185 to 1: 2: 4 and setting the respective on currents to 1: 2: 4.

In the current source circuit 420 shown in fig. 8, the transistors 180 to 182 are selected to be turned on or off by a 3-bit digital video signal. For example, when the transistors 180 to 182 are all turned on, the current supplied to the signal line is the sum of the drain currents of the transistors 183 to 185. When only the transistor 18 is on, only the drain current of the transistor 183 is supplied to the signal line.

In this way, the gate terminals of the transistors 183 to 185 are connected to each other, whereby information of the setting operation can be shared. Here, information is shared among transistors in the same column, but the present invention is not limited to this. For example, the information of the setting operation may be shared with transistors other than the transistors in the same column. That is, in order to make the information of the setting operation the same, the gate terminal of the transistor may be connected to the transistors in another column. This reduces the number of current source circuits to be set. Therefore, the time required for the setting operation can be shortened. In addition, since the number of circuits can be reduced, the area of the wiring pattern can be reduced.

Fig. 29 shows a current source circuit 420 having a circuit configuration different from that of fig. 8. In the current source circuit 420 shown in fig. 29, switches 191 and 192 are arranged in place of the transistors 186 to 188.

The operation of the current source circuit 420 shown in fig. 29 is the same as that of the current source circuit 420 shown in fig. 27 except that when the switches 191 and 192 are turned on, a current supplied from a reference current source (not shown) connected to the current line 190 flows through the capacitance element 189, and therefore, the description thereof is omitted here.

In fig. 29, in the setting operation of the current source circuit, the transistor 182 is turned off to prevent current leakage. Alternatively, the switch 203 may be arranged in series with the transistor 182, and the switch 203 may be turned off during the setting operation and turned on at other times. The current source circuit at this time is shown by fig. 56.

Note that, although all of the transistors included in the current source circuit 420 in fig. 8, 29, and 56 are n-channel transistors, the present invention is not limited to this. The current source circuit 420 may also use a p-channel transistor. When a p-channel transistor is used, the operation of the current source circuit 420 is the same as the above operation except that the direction of current flow is different, and the capacitance element is not connected to Vss but to Vdd, and therefore, the description thereof will be omitted.

When a current source circuit is formed using a p-channel transistor and Vss and Vdd are not exchanged, that is, when the direction of current flow is not changed, it is easy to use the current source circuit by comparing fig. 23 and 24. In addition, it is possible to easily realize multi-phasing and dot sequential driving.

In the present embodiment, the configuration and operation of the signal line driver circuit when performing 3-bit digital gradation display are described. However, the present invention is not limited to 3 bits, and any number of bits can be displayed. In addition, in the present embodiment, any combination with embodiments 1 to 4 is possible.

In fig. 27, as shown in fig. 1, 1 current source circuit corresponding to each bit is arranged for each of 1 signal line. However, as shown in fig. 2, a plurality of current source circuits corresponding to the respective bits may be arranged for 1 signal line driver circuit. The diagram at this time is shown by fig. 57. The configuration of fig. 7 corresponds to the case where the configuration shown in fig. 57 is used as the configuration of fig. 27. Similarly, in fig. 54, a plurality of current source circuits share setting information. The diagram at this time is shown by fig. 58.

Next, fig. 59, 60, 61, and 62 show the detailed configuration of the circuit shown in fig. 53. In the circuit shown in fig. 53, a setting control line or a logical operator is arranged, and the timing of the setting operation of the current source circuit is controlled using the setting control line or the logical operator.

Fig. 59 is a circuit diagram showing the case where the reference constant current sources 109 having the same number and number of bits are arranged, the current source circuit shown in fig. 1 is used as the signal line driving circuit shown in fig. 53, and the configuration shown in fig. 23(a) is used as the current source circuit. In the configuration shown in fig. 59, the transistors a to C are turned off during the setting operation in order to prevent current leakage. Alternatively, a switch may be arranged in series with the transistors a to C, and the switch may be turned off during the setting operation. When the configuration of fig. 27 is made to correspond to the configuration of fig. 53, fig. 59 corresponds to fig. 55. That is, the configuration of fig. 59 corresponds to fig. 53, and the configuration of fig. 55 corresponds to fig. 27.

Fig. 60 is a circuit diagram showing the case where the reference constant current sources 109 having the same number and number of bits are arranged, the current source circuit shown in fig. 2 is used as the signal line driving circuit shown in fig. 53, and the configuration shown in fig. 23(a) is used as the current source circuit. If the structure of fig. 27 is made to correspond to the structure of fig. 53, fig. 60 corresponds to fig. 7. That is, the structure of fig. 60 corresponds to fig. 53, and the structure of fig. 7 corresponds to fig. 27.

Fig. 61 is a circuit diagram showing a case where the reference constant current sources 109 and the signal line driving circuits shown in fig. 53 are arranged in a smaller number than the number of bits, and the constant current circuits and the current source circuits shown in fig. 1 are used, while sharing information, as in the configuration shown in fig. 54, and the configuration of fig. 23(C) is used. If the configuration of fig. 27 is made to correspond to the configuration of fig. 54 and the configuration of fig. 53, fig. 61 corresponds to fig. 8.

Fig. 62 is a circuit diagram showing a case where the reference constant current sources 109 whose number is smaller than the number of bits are arranged, the signal line driving circuit shown in fig. 53 shares information as in the configuration shown in fig. 54, and the current source circuit shown in fig. 1 is used, and the current source circuit is used in the configuration shown in fig. 23 (a). When the configuration of fig. 27 is made to correspond to the configuration of fig. 54 and the configuration of fig. 53, fig. 62 corresponds to fig. 29.

In fig. 59, 60, and 62, a logical operator is disposed, but a switch or the like may be used instead of the logical operator. The logic operator may be any circuit as long as it can be used for switching control, since it switches only whether or not the setting operation of the current source circuit is performed. In fig. 60, whether or not the setting operation of the current source circuit is performed is switched by using the 4 th setting control line, and which current source circuit is set and input operation is performed by using the 1 st to 3 rd setting control lines. The setting operation of the current source circuit may be performed randomly, not sequentially from the 1 st column to the last 1 st column. In this case, a decoder circuit shown in fig. 43 or the like can be used as the shift register 411. The circuits shown in fig. 44, 45, and 46 may also be used.

(embodiment 6)

The reference constant current source 109 for supplying a current to the current source circuit may be formed integrally with the signal line driver circuit over the substrate, or may be disposed outside the substrate using an IC or the like. When formed integrally on a substrate, any one of the current source circuits shown in fig. 23 to 25, 38, 37, 40, and the like can be used. Alternatively, 1 transistor may be provided alone, and the current value may be controlled in accordance with the voltage applied to the gate. In the present embodiment, the configuration and operation of the reference constant current source 109 will be described.

Fig. 30 shows the simplest case as 1 example. That is, the gate voltage is adjusted by applying a voltage to the gate of the transistor, and 3 current lines are required. If only 1 current line is needed, the transistors 1840, 1850 and the corresponding current lines can simply be eliminated from FIG. 30. In fig. 30, the magnitude of the current is controlled from the outside via the terminal f by adjusting the gate voltage applied to the transistors 1830, 1840, and 1850. In this case, when the W/L values of the transistors 1830, 1840, and 1850 are designed to be 1: 2: 4, the conduction currents thereof are 1: 2: 4, respectively.

Next, in fig. 31(a), a case where a current is supplied from the terminal f will be described. As shown in fig. 30, when the gate voltage is applied and adjusted, the current value may vary due to temperature characteristics or the like. However, when a current is input as in fig. 31(a), the influence thereof can be suppressed.

In the case of the configuration of fig. 30 and 31(a), the voltage or current must be continuously input from the terminal f while the current line continues to flow through the current. However, when the current line does not have to flow a current, it is not necessary to input a voltage or a current from the terminal f.

Further, a switch and a capacitive element may be added as shown in fig. 31 (B). Thus, even when a current is supplied to the current line, the supply from the reference IC (the voltage or the current input from the terminal f) can be stopped, and the power consumption becomes small. In the configurations shown in fig. 30 and 31, information is shared with other current source transistors arranged in the reference constant current source. That is, the gate terminals of the transistors 1830, 1840, 1850 are connected to each other.

Therefore, fig. 32 shows a case where each current source circuit performs a setting operation. In fig. 27, a current is input from a terminal f, and timing is controlled by a signal supplied from a terminal e. In the circuit shown in fig. 27, the structures shown in fig. 23, 24, 38, 37, 40, and the like can be used. The circuit shown in fig. 32 is an example using the circuit of fig. 23 (a). Therefore, the setting operation and the input operation cannot be performed simultaneously. Therefore, in this circuit, the setting operation for the reference constant current source needs to be performed at a timing when the current line does not need to flow a current.

Fig. 33 shows an example of the reference constant current source 109 that is multi-phased. That is, the reference constant current source 109 using the structure shown in fig. 47 corresponds to this. In the case of diversification, the circuits of fig. 32, 30, and 31 may be used. However, since the current values supplied to the current lines are the same, the number of currents to be input from the outside can be reduced by performing a setting operation for each current source circuit using 1 current as shown in fig. 33.

This embodiment can be arbitrarily combined with embodiments 1 to 5.

(embodiment 7)

In the above embodiments, the case where the signal current control switch is present is mainly described. In the present embodiment, a case will be described where a current (fixed current) disproportionate to the signal current is supplied to a wiring other than the signal line when the signal current control switch is not provided. At this time, the switch 101 (signal current control switch) does not have to be provided.

Further, when there is no signal current control switch, the same is true as the case where there is a signal current switch except that there is no signal current switch. Therefore, a brief description will be given, and a description of the same parts will be omitted.

The case where the signal current switch is arranged and the case where the signal current switch is not arranged are compared, and fig. 34 corresponds to fig. 1, and fig. 35 corresponds to fig. 2. Fig. 63(a) corresponds to fig. 6 (B). In the above embodiment, the signal current control switch is controlled by a video signal, and a current is output to the signal line. In this embodiment, a current is output to a pixel current line. And outputting the video signal to the signal line.

Fig. 63(B) shows a schematic view of the pixel structure in this case. Next, the operation method of the pixel will be briefly described. First, when the switching transistor is turned on, a video signal is input to the pixel through the signal line and stored in the capacitor element. Then, the driving transistor is turned on or off according to the value of the video signal. On the other hand, the current source circuit has a capability of flowing a certain current. Therefore, when the driving transistor is turned on, a constant current flows through the light emitting element, and light is emitted. When the driving transistor is turned off, no current flows through the light-emitting element, and no light is emitted. This displays an image. Only, only 2 states of light emission and no light emission can be expressed at this time. Therefore, a time gradation method, an area gradation method, or the like is used to realize multi-gradation.

Any of the circuits shown in fig. 23, 24, 37, 38, 40, and the like may be used for the current source circuit portion. In addition, the setting operation may be performed to allow a constant current to flow through the current source circuit. When the current source circuit of the pixel is set, the current is input through the pixel current line and then the setting is performed. The setting operation of the current source circuit of the pixel can be performed at an arbitrary timing and an arbitrary number of times. The setting operation of the current source circuit arranged for the pixel can be performed regardless of the operation for displaying an image. When the charge stored in the capacitor element disposed in the current source circuit leaks, the setting operation can be performed.

Next, fig. 64 and 65 show a detailed configuration of the constant current circuit 414 shown in fig. 63 (a). Fig. 66 and 67 show a case where the setting control line and the logic operator are arranged in the configuration of fig. 64 and 65, and the timing of the setting operation of the current source circuit of the signal line driver circuit can be controlled. Here, fig. 64, 66 show circuits in the case where the current source circuit portion uses fig. 23 (a). Fig. 65, 67 show circuits in the case where the current source circuit portion uses fig. 23 (E). Although the logical operator is arranged in fig. 66 and 67, a switch or the like may be used instead.

Further, a case where the structure shown in fig. 35 is used in the current source circuit portion shown in fig. 63(a) is considered. Fig. 68 shows a detailed structure of the constant current source circuit 414 at this time. Fig. 69 shows a case where the setting control line and the logic operator are arranged in the configuration of fig. 68, and the timing of the setting operation of the current source circuit of the signal line driver circuit can be controlled. Here, fig. 68 and 69 show circuits in the case where fig. 23(a) is used for the current source circuit portion. In fig. 68, by controlling the setting control line, the setting operation can be performed for one current source, and the input operation can be performed for the other current source. Similarly, in fig. 69, by controlling the 2 nd setting control line, the setting operation can be performed for one current source, and the input operation can be performed for the other current source. By controlling the 1 st setting control line, the timing of the setting operation of the current source circuit of the signal line driver circuit can be controlled.

Thus, when there is no signal current control switch, the same as the case where there is a signal current switch, except that there is no signal current switch. Therefore, detailed description is omitted.

This embodiment can be arbitrarily combined with embodiments 1 to 6.

(embodiment 8)

An embodiment of the present invention will be described with reference to fig. 70. In fig. 70(a), a signal line driver circuit is disposed above a pixel portion, a constant current circuit is disposed below the pixel portion, a current source a is disposed in the signal line driver circuit, and a current source B is disposed in the constant current circuit. When the currents supplied from the current source A, B are IA and IB and the signal current supplied to the pixel is Idata, IA is equal to IB + Idata. When writing a signal current to a pixel, the current source A, B is set to supply a current. In this case, when IA and IB are increased, the writing speed of the signal current to the pixel can be increased.

At this time, the setting operation of the current source B is performed using the current source a. A current obtained by subtracting the current of the current source B from the current of the current source a flows in the pixel. Therefore, by performing the setting operation of the current source B using the current source a, the influence of various noises can be reduced.

In fig. 70B, a reference constant current source (hereinafter referred to as a constant current source) C, E is disposed above and below the pixel portion. The setting operation of the signal line driver circuit and the current source circuit of the constant current circuit arrangement is performed using the current source C, E. The current source D corresponds to a current source of the setting current source C, E, and supplies a reference current from the outside.

In fig. 70(B), the constant current circuit disposed below may be used as the signal line driver circuit. Thus, the signal line driver circuit can be arranged above and below. Then, the upper and lower half portions of the picture (the entire pixel portion) are controlled. Thus, 2 rows of pixels can be controlled simultaneously. Therefore, the time for setting operations (signal input operations) for the current source, the pixel current source, and the like of the signal line driver circuit can be prolonged. Therefore, the setting can be performed more accurately.

This embodiment can be arbitrarily combined with embodiments 1 to 7.

(example 1)

In this embodiment, the time gradation method is described in detail with reference to fig. 14. In general, a frame frequency is about 60Hz in a display device such as a liquid crystal display device or a light-emitting device. That is, as shown in fig. 14(a), about 60 screen scans are performed for 1 second. This makes it possible to make the human eyes feel imperceptible and flicker (flashing of the screen). In this case, a period during which 1 frame scan is performed is referred to as a 1-frame period.

In this embodiment, a time gray scale method disclosed in the publication of patent document 1 will be described as 1 example. In the time gray scale method, a 1-frame period is divided into a plurality of subframe periods. The number of divisions is usually equal to the number of gradation bits. Here, for simplicity, the division number and the gradation bit number are equal. That is, in the present embodiment, since the gray scale is 3 bits, an example of division into 3 subframe periods SF1 to SF3 is shown (fig. 14B).

Each subframe period includes an address (write) period Ta and a hold (light-emitting) period Ts. The address period is a period in which a video signal is written to a pixel, and the length is equal in each subframe period. The holding period is a period in which the light emitting element emits light or does not emit light in accordance with a video signal written by the pixel in the address period. In this case, the length ratio of the holding periods Ts1 to Ts3 is Ts1 to Ts2 to Ts3 is 4 to 2 to 1. That is, when n-bit gradation is expressed, the length ratio of the n holding periods is 2^n-1∶2^n-2∶......∶2¹∶2⁰. Then, the length of a period in which each pixel emits light in 1 frame period is determined by which holding period the light-emitting element emits light or does not emit light, thereby expressing a gray scale.

Next, a specific operation of the pixel using the time gray scale method will be described with reference to the pixel shown in fig. 16(B) in this embodiment. The pixel shown in fig. 16(B) uses a current input method.

First, the following operation is performed in the address period Ta. The 1 st scanning line 602 and the 2 nd scanning line 603 are selected, and the TFTs 606 and 607 are turned on. At this time, the current flowing through the signal line 601 is regarded as the signal current Idata. When a predetermined charge is accumulated in the capacitive element 610, the selection of the 1 st scanning line 602 and the 2 nd scanning line 603 is completed, and the TFTs 606 and 607 are turned off.

Next, the following operation is performed in the holding period Ts. The 3 rd scan line 604 is selected and the TFT609 is turned on. Since the capacitor element 610 holds the predetermined charge that has been written, the TFT608 is turned on, and a current equal to the signal current Idata flows from the signal line 605. Thereby, the light emitting element 611 emits light.

The 1-frame period is configured by performing the above operations in each subframe period. According to this method, when it is desired to increase the number of display gradations, the number of divisions in the subframe period can be increased. The order of the subframe periods is not necessarily in the order from the higher order to the lower order, and may be randomly arranged in 1 frame period, as shown in fig. 14(B) and (C). And may change its order during each frame.

Fig. 14(D) shows a subframe period SF2 of the m-th scanning line. As shown in fig. 14(D), in the pixel, immediately after the address period Ta2 ends, the period Ts2 starts.

Next, a timing of performing a setting operation in the current source circuit of the signal line driver circuit will be described.

In the above embodiment, a description has been given of a mode in which the setting operation and the input operation of the current source circuit can be performed simultaneously and a mode in which the setting operation and the input operation cannot be performed simultaneously.

In the current source circuit in which the setting operation and the input operation can be performed simultaneously, the timing for performing each operation is not particularly limited. This also applies to the case where a plurality of current source circuits are arranged in 1 column as shown in fig. 2, 54, and the like. However, in the current source circuit in which the setting operation and the input operation cannot be performed simultaneously, it is necessary to make a time for performing the setting operation. When the time gray scale method is adopted, it is necessary to perform the setting operation when the output operation is not performed. For example, in the case of a pixel having the configuration of the driving portion shown in fig. 1 and the configuration shown in fig. 16(B), it is necessary to perform the setting operation in a period of the non-address period Ta for each scanning line of the pixel portion. In the case of the pixel having the configuration of the driver portion shown in fig. 34 and the configuration shown in fig. 63(B), the setting operation of the current source circuit disposed in the driver portion must be performed while the current source circuit disposed in the pixel does not perform the setting operation.

In this case, the frequency of the shift register controlling the current source circuit may be set at a low speed. Thus, the setting operation of the current source circuit can be accurately performed in a short time.

Alternatively, the setting operation of the current source circuit may be performed at random by using a circuit such as fig. 43 as a circuit (shift register) for controlling the current source circuit. Further, circuits such as fig. 44, 45, and 46 may be used. Thus, even if the period during which the setting operation is possible is dispersed in 1 frame, the setting operation can be performed by effectively using this period. In addition, the setting operation of all the current source circuits may be performed not within 1 frame period but within several frame periods. Thus, the setting operation of the current source circuit can be accurately performed in a short time.

In the case of the pixel having the configuration of the driving unit in fig. 1 and the configuration shown in fig. 16B, the input operation can be performed in a period (address period Ta) in which the scanning line of the pixel is selected. In the case of the pixel having the configuration of the driver portion shown in fig. 1 and the configuration shown in fig. 63(B), the setting operation of the current source circuit disposed in the driver portion can be performed while the setting operation of the current source circuit disposed in the pixel is not performed.

This embodiment can be arbitrarily combined with embodiments 1 to 8.

(example 2)

In this embodiment, an example of a configuration of a pixel circuit provided in a pixel portion will be described with reference to fig. 13 and 71.

Note that the pixel having a structure including a portion to which an input current is supplied can be applied to any pixel.

The pixel in fig. 13a includes a signal line 1101, 1 st and 2 nd scan lines 1102 and 1103, a current line (power supply line) 1104, a switching TFT1105, a holding TFT1106, a driving TFT1107, a conversion driving TFT1108, a capacitor element 1109, and a light emitting element 1110. The signal line 1101 is connected to a current source circuit 1111.

The current source circuit 1111 corresponds to the current source circuit 420 provided in the signal line driver circuit 403.

In the pixel of fig. 13(a), the gate of the switching TFT1105 is connected to the 1 st scanning line 1102, the 1 st electrode is connected to the signal line 1101, and the 2 nd electrode is connected to the 1 st electrode of the driving TFT1107 and the 1 st electrode of the switching driving TFT 1108. The gate of the holding TFT1106 is connected to the 2 nd scanning line 1103, the 1 st electrode is connected to the signal line 1102, and the 2 nd electrode is connected to the gate of the driving TFT1107 and the gate of the conversion driving TFT 1108. The 2 nd electrode of the driving TFT1107 is connected to a current line (power supply line) 1104, and the 2 nd electrode of the conversion driving TFT1108 is connected to one electrode of the light-emitting element 1110. The capacitor 1109 is connected between the gate and the 2 nd electrode of the conversion driving TFT1108, and holds the voltage between the gate and the source of the conversion driving TFT 1108. The current line (power supply line) 1104 and the other electrode of the light-emitting element 1110 are each input with a predetermined potential and have a potential difference therebetween.

Note that the pixel in fig. 13(a) corresponds to a case where the circuit in fig. 38(B) is used for the pixel. However, the polarity of the transistors is reversed due to the different direction of current flow. The driving TFT1107 in fig. 13(a) corresponds to the TFT126 in fig. 38(B), the switching driving TFT1108 in fig. 13(a) corresponds to the TFT122 in fig. 38(B), and the holding TFT1106 in fig. 13(a) corresponds to the TFT124 in fig. 38 (B).

The pixel in fig. 13B includes a signal line 1151, 1 st and 2 nd scan lines 1142 and 1143, a current line (power supply line) 1144, a switching TFT1145, a holding TFT1146, a switching driving TFT1147, a driving TFT1148, a capacitor element 1149, and a light-emitting element 1140. The signal line 1151 is connected to the current source circuit 1141.

The current source circuit 1141 corresponds to the current source circuit 420 provided in the signal line driver circuit 403.

In the pixel of fig. 13(B), the gate of the switching TFT1145 is connected to the 1 st scanning line 1142, the 1 st electrode is connected to the signal line 1151, and the 2 nd electrode is connected to the 1 st electrode of the driving TFT1148 and the 1 st electrode of the switching driving TFT 1147. The gate of the holding TFT1146 is connected to the 2 nd scan line 1143, the 1 st electrode is connected to the 1 st electrode of the driving TFT1148, and the 2 nd electrode is connected to the gate of the driving TFT1148 and the gate of the conversion driving TFT 1147. The 2 nd electrode of the switching driving TFT1147 is connected to a current line (power supply line) 1144, and the 2 nd electrode of the switching driving TFT1147 is connected to one electrode of the light emitting element 1140. The capacitor element 1149 is connected between the gate and the 2 nd electrode of the switching driving TFT1147, and holds a voltage between the gate and the source of the switching driving TFT 1147. The current line (power supply line) 1144 and the other electrode of the light-emitting element 1140 are each input with a predetermined potential and have a potential difference therebetween.

Note that the pixel in fig. 13(B) corresponds to a case where the circuit in fig. 6(B) is used for the pixel. However, the polarity of the transistors is reversed due to the different direction of current flow. The TFT1147 for conversion driving in fig. 13(B) corresponds to the TFT122 in fig. 6(B), the TFT1148 for driving in fig. 13(B) corresponds to the TFT126 in fig. 6(B), and the TFT1146 for holding in fig. 13(B) corresponds to the TFT124 in fig. 6 (B).

The pixel in fig. 13(C) includes a signal line 1121, a1 st scan line 1122, a2 nd scan line 1123, a3 rd scan line 1135, a current line (power supply line) 1124, a switching TFT1125, a pixel current line 1138, an erasing TFT1126, a driving TFT1127, a capacitor element 1128, a current source TFT1129, a mirror TFT1130, a capacitor element 1131, a current input TFT1132, a holding TFT1133, and a light emitting element 1136. The pixel current line 1138 is connected to the current source circuit 1137.

In the pixel of fig. 13(C), the gate of the switching TFT1125 is connected to the 1 st scan line 1122, the 1 st electrode of the switching TFT1125 is connected to the signal line 1121, and the 2 nd electrode of the switching TFT1125 is connected to the gate of the driving TFT1127 and the 1 st electrode of the erasing TFT 1126. The gate of the erasing TFT1126 is connected to the 2 nd scanning line 1123, and the 2 nd electrode of the erasing TFT1126 is connected to the current line (power supply line) 1124. The 1 st electrode of the driving TFT1127 is connected to one electrode of the light-emitting element 1136, and the 2 nd electrode of the driving TFT1127 is connected to the 1 st electrode of the current source TFT 1129. The 2 nd electrode of the current source TFT1129 is connected to the current line 1124. One electrode of the capacitor element 1131 is connected to the gate of the current source TFT1129 and the gate of the mirror TFT1130, and the other electrode is connected to the current line (power supply line) 1124. The 1 st electrode of the mirror TFT1130 is connected to the current line 1124, and the 2 nd electrode of the mirror TFT1130 is connected to the 1 st electrode of the current input TFT 1132. The 2 nd electrode of the current input TFT1132 is connected to a current line (power supply line) 1124. The gate of the current input TFT1132 is connected to the 3 rd scan line 1135. The gate of the current holding TFT1133 is connected to the 3 rd scan line 1135, the 1 st electrode of the current holding TFT1133 is connected to the pixel current line 1138, and the 2 nd electrode of the current holding TFT1133 is connected to the gate of the current source TFT1129 and the gate of the mirror TFT 1130. The current line (power supply line) 1124 and the other electrode of the light-emitting element 1136 are each supplied with a predetermined potential and have a potential difference therebetween.

Here, the current source circuit 1137 corresponds to the current source circuit 420 disposed in the signal line driver circuit 403 (power supply line).

Note that the pixel in fig. 13(C) corresponds to the case where the circuit in fig. 23(E) is used for the pixel in fig. 63 (B). The polarity of the transistors is reversed because only the direction of current flow is different. Further, an erasing TFT1126 is added to the pixel of fig. 13 (C). The length of the lighting period can be freely controlled by the erasing TFT 1126.

The switching TFT1125 functions to control supply of a video signal to a pixel. The erasing TFT1126 discharges the electric charges held in the capacitor 1131, and the driving TFT1127 controls conduction or non-conduction according to the electric charges held in the capacitor 1131. The current source TFT1129 and the mirror TFT1130 form a current mirror circuit. The current line 1124 and the other electrode of the light-emitting element 1136 are supplied with predetermined potentials, respectively, and have a potential difference therebetween.

That is, when the switching TFT1125 is turned on, a video signal is inputted to a pixel through the signal line 1121 and stored in the capacitor 1128. The driving TFT1127 is turned on or off according to the value of the video signal. Thus, when the driving TFT1127 is turned on, the light-emitting element emits light by flowing a constant current. When the driving TFT1127 is turned off, no current flows through the light-emitting element, and no light is emitted. This displays an image.

The current source circuit in fig. 13(C) includes a current source TFT1129, a mirror TFT1130, a capacitor element 1131, a current input TFT1132, and a holding TFT 1133. The current source circuit has the capability of flowing a certain current. The current source circuit performs a setting operation by supplying a current through the pixel current line 1138. Therefore, even if the characteristics of the transistors constituting the current source circuit are varied, the magnitude of the current supplied from the current source circuit to the light emitting element is not varied. The setting operation of the current source circuit for the pixel can be performed regardless of the operation of the switching TFT1125 or the driving TFT 1127.

The pixel in fig. 71(a) corresponds to the case where the circuit in fig. 23(a) is used for the pixel in fig. 63 (B). However, the polarity of the transistors is reversed due to the different direction of current flow. The pixel in fig. 71(a) includes a current source TFT1129, a capacitor element 1131, a holding TFT1133, a pixel current line 1138(Ci), and the like. The pixel current line 1138(Ci) is connected to the current source circuit 1137. The current source circuit 1137 corresponds to the current source circuit 420 disposed in the signal line driver circuit 403.

The pixel in fig. 71(B) corresponds to the case where the circuit in fig. 24(a) is used for the pixel in fig. 63 (B). However, the polarity of the transistors is reversed due to the different direction of current flow. The pixel in fig. 71(B) includes a current source TFT1129, a capacitor element 1131, a holding TFT1133, a pixel current line 1138(Ci), and the like. The pixel current line 1138(Ci) is connected to the current source circuit 1137. The current source circuit 1137 corresponds to the current source circuit 420 disposed in the signal line driver circuit 403.

In the pixel of fig. 71(a) and the pixel of fig. 71(B), the polarity of the current source TFT1129 is different. Further, the capacitance element 1131 and the holding TFT1133 are connected differently depending on the polarity.

Thus, there are various structures of pixels. The pixels described so far can be roughly classified into 2 types. The 1 st category is a type in which a current corresponding to a video signal is input to a signal line. Fig. 13(a), 13(B), and the like correspond to these. In this case, the signal line driver circuit includes a signal current control switch as shown in fig. 1 or 2.

The other type is a type in which a video signal is input to a signal line and a fixed current which is independent of the video signal is input to a current line for a pixel, that is, a case of a pixel as shown in fig. 63 (B). This corresponds to fig. 13(C), 71(a), 71(B), and the like. In this case, the signal line driving circuit does not have a signal current control switch as shown in fig. 34 or 35.

Next, a timing chart corresponding to the type of each pixel will be described. First, a case where digital gradation and time gradation are combined will be described. The timing chart described above depends only on the type of the pixel or the configuration of the signal line driver circuit. That is, as described above, the timing may be different between a case where the setting operation and the input operation of the current source circuit of the signal line driver circuit can be performed simultaneously and a case where the setting operation and the input operation cannot be performed simultaneously.

First, a case where the type of the pixel is a type in which a current corresponding to a video signal is input to a signal line will be described. Assuming that the pixel is fig. 13(a) or fig. 13(B), the signal line driver circuit has the structure of fig. 6 (B).

Next, as a case where the setting operation and the input operation of the current source circuit of the signal line driver circuit can be performed simultaneously, a case where the circuit shown in fig. 1 is used for the constant current circuit 414 in fig. 6(B), and the circuit shown in fig. 23(C), that is, the circuit in fig. 5 is used for the current source circuit portion, will be described. The same applies to the circuits of fig. 3 and 4, in which the setting operation and the input operation can be performed simultaneously.

Fig. 72 shows a timing chart at this time. For simplicity, assume that 4-bit gray is represented, and the number of subframes is 4. First, the first subframe period SF1 starts. A scanning line (the 1 st scanning line 1102 in fig. 13a or the 1 st scanning line 1132 in fig. 13B) is selected in a row, and a current is input from a signal line (1101 in fig. 13a or 1131 in fig. 13B). The current becomes a value corresponding to the video signal. When the lighting period Ts1 ends, the next subframe period SF2 starts scanning in the same manner as SF 1. Then, the next subframe period SF3 starts, and scanning is performed in the same manner. However, since the length Ts3 of the lighting period is shorter than the length Ta3 of the address period, the light is forcibly turned off. That is, the inputted video signal is canceled. Alternatively, a current is not allowed to flow through the light emitting element. To perform erasing, the 2 nd scan line (the 2 nd scan line 1103 in fig. 13(a) or the 2 nd scan line 1133 in fig. 13 (B)) is selected one by one. Thus, the video signal can be erased to be in a non-light-emission state. Then, the next subframe SF4 starts. Here, scanning is performed as with SF3, and it is also made to be in a non-light-emitting state.

The above is a timing chart relating to an image display operation, that is, an operation of a pixel. Next, the timing of the setting operation of the current source circuit disposed in the signal line driver circuit will be described.

Here, it is assumed that the current source circuit is a circuit capable of performing the setting operation and the input operation at the same time. When the type of the pixel is a type in which a current corresponding to a video signal is input to the signal line, an input operation of the current source circuit of the signal line driver circuit (outputting a current to the pixel) is performed in an address period (Ta1, Ta2, or the like) in each sub-frame period. The setting operation of the current source circuit of the signal line driver circuit is controlled by the sampling pulse from the shift register 411.

The sampling pulse output from the shift register is output to all columns while a certain row of scanning lines (gate lines) is selected. Accordingly, as shown in fig. 72, the setting operation of the current source circuit of the signal line driver circuit is performed in synchronization with the sampling pulse output from the shift register.

Next, as shown in fig. 42, a case where the setting control line and the logical operator are arranged in the signal line driver circuit will be described. As a case where the setting operation and the input operation can be simultaneously performed for the current source circuit of the signal line driver circuit, a case where the circuit shown in fig. 1 is used for the constant current circuit 414 and fig. 23(C) is used for the current source circuit portion in fig. 42, and a case where fig. 49 is used will be described.

Timing charts at this time are shown in fig. 73, 74, and 75.

First, the image display operation, that is, the operation of the switching transistor, the driving transistor, and the like of the pixel is almost the same as the case of fig. 72, and therefore, the description thereof is omitted.

Next, the timing of the setting operation of the current source circuit disposed in the signal line driver circuit will be described. In the case of fig. 72, the setting operation of the current source circuit of the signal line driver circuit is performed in the selection period of each row of scanning lines (gate lines) in each address period.

In fig. 73, whether or not the setting operation of the current source circuit is performed can be controlled by the setting control line. Therefore, only when a certain row of scanning lines (gate lines) in a certain address period is selected, the setting operation period Tb is set and the setting operation is performed in the setting operation period Tb.

Thus, the number of times the current source circuit disposed in the signal line driver circuit performs the setting operation can be reduced. Therefore, power consumption can be reduced.

In the current source circuit 420, a capacitor element connected between the gate and the source of a certain transistor is disposed. The capacitor element is charged by a setting operation of the current source circuit. Ideally, the setting operation of the current source circuit is performed only 1 time at the time of power input. This is because the amount of charge accumulated in the capacitor does not change with the operating state, time, or the like, and does not have to be changed. Therefore, the setting operation of the current source circuit of the signal line driver circuit can be performed at any timing and any number of times.

However, in practice, various noises are input to the capacitor element, and a leakage current is generated in a transistor connected to the capacitor element. As a result, the amount of charge accumulated in the capacitor element may change with time. When the charge amount changes, a current output from the current source circuit, that is, a current input to the pixel changes. As a result, the luminance of the pixel also changes. Therefore, in order to prevent the charge stored in the capacitor element from varying, it is necessary to refresh the charge by performing the setting operation of the current source circuit at a certain cycle.

The refresh operation of the electric charge accumulated in the capacitive element can be performed several times during 1 frame. Alternatively, it may be performed 1 time during several frames.

In fig. 73, the setting operation of the current source circuit is performed 1 time each in the address periods Ta1 and Ta 2. The frequency at which the setting operation is performed can be determined appropriately according to the charge storage state of the capacitor element included in the current source circuit.

Next, fig. 74 shows a case where the timing of the setting operation of the current source circuit arranged in the signal line driver circuit is different from that in fig. 73.

In fig. 74, an address period (a period during which an input operation of the current source circuit of the signal line driver circuit is performed) and a setting operation period of the current source circuit of the signal line driver circuit are separated. That is, the setting operation of the current source circuit is not performed in the address period, that is, the input operation of the current source circuit, by the setting control line. Further, the setting operation of the current source circuit is performed during a gap period between the address period and the address period, that is, when the input operation of the current source circuit is not performed.

In this way, by performing the setting operation and the input operation of the current source circuit of the signal line driver circuit, the operation speed of each operation can be changed. That is, the frequency of the sampling pulse output from the shift register 411 can be changed. Accordingly, the operation of the shift register 411 can be delayed only when the setting operation of the current source circuit of the signal line driver circuit is performed. As a result, the setting operation of the current source circuit can be performed for a sufficiently long time, and the setting operation can be performed more accurately.

Therefore, in the case of fig. 74, a configuration may be used in which the setting operation and the input operation cannot be performed simultaneously for the current source circuit of the signal line driver circuit.

In order to perform the setting operation of the current source circuit, even if the shift register 411 is operated, the entire pixel is not affected unless the scanning line (gate line) in the pixel is selected. That is, in the address period, since the scanning line (gate line) is not selected, the entire pixel is not affected.

In the case where the shift register 411 is a circuit in which a plurality of wirings can be selected at random as shown in fig. 43, 44, 45, 46, and the like, it is not necessary to complete the setting operation of all the current source circuits in 1 section of the gap period between the 1-time address period and the address period, that is, the period in which the current source circuits do not perform the input operation. That is, it takes several frames to complete the setting operation of all the current source circuits. Alternatively, when there are a plurality of address periods and a gap period between the address periods within 1 frame period, the setting operation of the current source circuit may be performed using several periods selected from these periods. The timing chart at this time is shown in fig. 75.

Next, a case will be described where a pixel type is a type in which a video signal is input to a signal line and a fixed current independent of the video signal is input to a pixel current line. The signal line driver circuit has the structure shown in fig. 63(a), and the pixel is the pixel shown in fig. 63(B), 13(C), 71(a), 71(B), or the like. However, in the case of this pixel structure, it is necessary to perform a setting operation even for the current source circuit of the pixel. Therefore, the timing chart differs depending on whether or not the setting operation and the input operation of the current source circuit of the pixel can be performed simultaneously. First, fig. 76 shows a timing chart when the setting operation and the input operation of the current source circuit of the pixel can be performed simultaneously, that is, when the pixel is as shown in fig. 13 (C).

First, a pixel display operation, that is, an operation related to a switching transistor, a driving transistor, and the like of a pixel will be described. However, since the same is almost the same as the case of fig. 72, the description will be made briefly.

First, the first subframe period SF1 starts. A scanning line (1 st scanning line 1122 in fig. 13C) is selected one line at a time, and a video signal is input from a signal line (1121 in fig. 13C). The video signal is typically a voltage, but may also be a current. When the lighting period Ts1 ends, the next subframe period SF2 starts scanning in the same manner as SF 1. Then, the next subframe period SF3 starts, and scanning is performed in the same manner. However, since the length Ts3 of the lighting period is shorter than the length Ta3 of the address period, the light is forcibly turned off. That is, the inputted video signal is canceled. Alternatively, a current is not allowed to flow through the light emitting element. To perform erasing, the 2 nd scan line (the 2 nd scan line 1123 of fig. 13 (C)) is selected one row by one row. Thus, the video signal is erased, and the driving transistor 1127 is turned off and is in a non-light-emitting state. Then, the next subframe SF4 starts. Here, scanning is performed as in SF3, and it is also made to be in a non-light-emitting state.

Next, a setting operation of the current source circuit of the pixel will be described. In the case of fig. 13(C), the setting operation and the input operation of the current source circuit of the pixel can be performed simultaneously. Therefore, the setting operation of the current source circuit of the pixel can be performed at an arbitrary timing.

The setting operation of the current source circuit of the signal line driver circuit can be performed at any time when the setting operation can be performed simultaneously with the input operation (setting operation of the current source circuit of the pixel). When the setting operation of the current source circuit of the signal line driver circuit cannot be performed simultaneously with the input operation (setting operation of the current source circuit of the pixel), the setting operation may be performed at a time other than the period during which the input operation (setting operation of the current source circuit of the pixel) is performed.

When the setting operation of the current source circuit of the signal line driver circuit and the input operation (the setting operation of the current source circuit of the pixel, which outputs a current to the pixel) can be performed simultaneously, the constant current circuit 414 in fig. 63(a) corresponds to the case of the circuit in fig. 35, that is, the case of fig. 68. Alternatively, the constant current circuit 414 corresponding to fig. 63(a) is the case of fig. 34, and the current source circuit 420 is the case of fig. 23(C), 23(D), 23(E), and the like.

When the setting operation of the current source circuit of the signal line driver circuit and the input operation (the setting operation of the current source circuit of the pixel that outputs a current to the pixel) cannot be performed simultaneously, the constant current circuit 414 in fig. 63(a) is the circuit in fig. 34, and corresponds to the case where the current source circuit 420 is the circuit in fig. 23(a), 23(B), or the like, that is, the case in fig. 64.

Therefore, fig. 76 shows a timing chart when the setting operation and the input operation (the output of a current to a pixel, that is, the setting operation of the current source circuit of the pixel) of the current source circuit of the signal line driver circuit cannot be performed simultaneously. When the setting operation of the current source circuit of the signal line driver circuit is performed in the address period, the setting operation of the current source circuit of the pixel is performed in a gap period between the address period and the address period.

When the setting operation and the input operation (the output of a current to a pixel, that is, the setting operation of the current source circuit of the pixel) of the current source circuit of the signal line driver circuit can be performed simultaneously, the setting operation of the current source circuit of the pixel can be performed in an arbitrary period.

In the case of fig. 76, the setting operation of the current source circuit of the signal line driver circuit is performed in the selection period of each row of scanning lines (gate lines) in each address period. Next, a timing chart in the case where the setting control line or the logical operator is arranged as shown in fig. 66 or 69 will be described. In fig. 66 or 69, whether or not the setting operation of the current source circuit is performed can be controlled by the setting control line. Therefore, only when a certain row of scanning lines (gate lines) in a certain address period is selected, the setting operation period Tb is set and the setting operation is performed in the setting operation period Tb.

Therefore, fig. 77 shows a timing chart when the setting operation and the input operation (the output of a current to a pixel, that is, the setting operation of the current source circuit of the pixel) of the current source circuit of the signal line driver circuit cannot be performed simultaneously. The setting operation of the current source circuit of the signal line driver circuit is performed in the first period of the address period. In fig. 77, the process is performed during the first Ta1 and Ta 2. Therefore, the setting operation of the current source circuit of the pixel can be performed in other periods. That is, the setting operation of the current source circuit of the pixel (the input operation of the current source circuit of the signal line driver circuit) may be performed in the address period.

Further, by adopting the above method, the number of times of setting operation of the current source circuit arranged in the signal line driver circuit can be reduced. Therefore, power consumption can be reduced.

In the current source circuit 420, a capacitor element connected between the gate and the source is arranged. The capacitor element is charged by a setting operation of the current source circuit. Ideally, the setting operation of the current source circuit is performed only 1 time at the time of power input. This is because the amount of charge accumulated in the capacitor does not change with the operating state, time, or the like, and does not have to be changed. Therefore, the setting operation of the current source circuit of the signal line driver circuit can be performed at any timing and any number of times.

However, in practice, various noises are input to the capacitor element, and a leakage current is generated in a transistor connected to the capacitor element. As a result, the amount of charge accumulated in the capacitor element may change with time. When the charge amount changes, the current output from the current source circuit, that is, the current input to the pixel also changes. As a result, the luminance of the pixel also changes. Therefore, in order to prevent the charge stored in the capacitor element from varying, it is necessary to periodically perform a setting operation of the current source circuit and refresh the charge.

The refresh operation of the electric charge accumulated in the capacitive element can be performed several times during 1 frame. Alternatively, it may be performed 1 time during several frames.

In fig. 77, the setting operation of the current source circuit is performed 1 time each in the address periods Ta1 and Ta 2. The frequency at which the setting operation is performed can be determined appropriately according to the charge storage state of the capacitor element included in the current source circuit.

Next, fig. 78 shows a case where the timing of the setting operation of the current source circuit arranged in the signal line driver circuit is different from that of fig. 77.

In fig. 78, the setting control line is used to control the setting operation of the current source circuit of the signal line driver circuit not in the address period but in the gap period between the address period and the address period. Further, when the input operation of the current source circuit of the signal line driver circuit (the output of the current to the pixel, that is, the setting operation of the current source circuit of the pixel) cannot be performed simultaneously with the setting operation of the current source circuit of the signal line driver circuit, the input operation can be performed during a period in which the setting operation is not performed. When the setting operation and the input operation can be performed simultaneously, the input operation of the current source circuit of the signal line driver circuit can be performed as needed.

In this way, by performing the setting operation of the current source circuit of the signal line driver circuit in a period other than the address period, the operation in the address period and the operation speed of the setting operation can be changed. That is, the frequency of the sampling pulse output from the shift register 411 can be changed. Accordingly, the operation of the shift register 411 can be delayed only when the setting operation of the current source circuit of the signal line driver circuit is performed. As a result, the setting operation of the current source circuit can be performed for a sufficiently long time, and the setting operation can be performed more accurately.

In order to perform the setting operation of the current source circuit, even if the shift register 411 is operated, the entire pixel is not affected unless the scanning line (gate line) in the pixel is selected. That is, in the address period, since the scanning line (gate line) is not selected, the entire pixel is not affected.

In the case where the shift register 411 is a circuit in which a plurality of wirings can be selected at random as shown in fig. 43, 44, 45, 46, and the like, it is not necessary to complete the setting operation of all the current source circuits in 1 section of the gap period between the 1-time address period and the address period. That is, the setting operation of all the current source circuits can be completed within a period of several frames. Alternatively, when there are a plurality of address periods and a plurality of gap periods between the address periods within 1 frame period, the setting operation of the current source circuit may be performed using several periods selected from these periods. The timing chart at this time is shown in fig. 79.

Next, fig. 80 shows a timing chart when the type of the pixel is a type in which a video signal is input to a signal line and a fixed current independent of the video signal is input to a current line for the pixel, and the setting operation and the input operation of the current source circuit of the pixel cannot be performed simultaneously, that is, when the pixel is fig. 71(a) and 71 (B).

First, the pixel display operation, that is, the operation of the switching transistor, the driving transistor, and the like of the pixel is almost the same as the case of fig. 76, and therefore, the description will be made briefly.

First, the first subframe period SF1 starts. A scanning line (the 1 st scanning line 1122 in fig. 71a and 71B) is selected one line at a time, and a video signal is input from a signal line (1121 in fig. 71a and 71B). The video signal is typically a voltage, but may also be a current. When the lighting period Ts1 ends, the next subframe period SF2 starts scanning in the same manner as SF 1. Then, the next subframe period SF3 starts, and scanning is performed in the same manner. However, since the length Ts3 of the lighting period is shorter than the length Ta3 of the address period, the light is forcibly turned off. That is, the inputted video signal is canceled. Alternatively, a current is not allowed to flow through the light emitting element. In order to prevent the light emitting elements from flowing a current, the 2 nd scanning line (the 2 nd scanning line 1123 in fig. 13C) is set in a non-selected state line by line. Thus, the erasing TFT1127 is turned off, and the current path is cut off, so that no light is emitted. Then, the next subframe SF4 starts. Here, scanning is performed as in SF3, and it is also made to be in a non-light-emitting state.

Next, a setting operation of the current source circuit of the pixel will be described. In the case of fig. 71(a) and 71(B), the setting operation and the input operation of the current source circuit of the pixel cannot be performed simultaneously. Therefore, the setting operation of the current source circuit of the pixel can be performed when the input operation of the current source circuit of the pixel is not performed, that is, when no current flows through the light emitting element.

The setting operation of the current source circuit of the signal line driver circuit can be performed at any time when the setting operation can be performed simultaneously with the input operation (setting operation of the current source circuit of the pixel). When the setting operation of the current source circuit of the signal line driver circuit cannot be performed simultaneously with the input operation (setting operation of the current source circuit of the pixel), the setting operation may be performed at a time other than the period during which the input operation (setting operation of the current source circuit of the pixel) is performed.

When the setting operation of the current source circuit of the signal line driver circuit and the input operation (the setting operation of the current source circuit of the pixel, which outputs a current to the pixel) can be performed simultaneously, the constant current circuit 414 in fig. 63(a) corresponds to the case of the circuit in fig. 35, that is, the case of fig. 68. Alternatively, the constant current circuit 414 corresponding to fig. 63(a) is the case of fig. 34, and the current source circuit 420 is the case of fig. 23(C), 23(D), 23(E), and the like.

When the setting operation of the current source circuit of the signal line driver circuit and the input operation (the setting operation of the current source circuit of the pixel that outputs a current to the pixel) cannot be performed simultaneously, the constant current circuit 414 in fig. 63(a) is the circuit in fig. 34, and corresponds to the case where the current source circuit 420 is the circuit in fig. 23(a), 23(B), or the like, that is, the case in fig. 64.

Therefore, fig. 80 shows a timing chart when the setting operation and the input operation (the output of a current to a pixel, that is, the setting operation of the current source circuit of the pixel) of the current source circuit of the signal line driver circuit cannot be performed simultaneously. The setting operation of the current source circuit of the signal line driver circuit is performed in the address period, the setting operation of the current source circuit of the pixel is performed in the non-lighting period (non-lighting period) (Td3, Td4) in which the current source circuit of the pixel does not perform the input operation, that is, in which no current flows in the light emitting element, and the setting operation of the current source circuit of the signal line driver circuit may be performed in other periods. The non-lighting period (non-lighting period) (Td3, Td4) often overlaps with the address period.

In the case of fig. 80, the setting operation of the current source circuit of the signal line driver circuit is performed in the selection period of each row of scanning lines (gate lines) in each address period. Next, a timing chart in the case of setting a control line or a logical operator as shown in fig. 66 or 69 will be described. In fig. 66 or 69, whether or not the setting operation of the current source circuit is performed can be controlled by the setting control line. Therefore, only when a certain row of scanning lines (gate lines) in a certain address period is selected, the setting operation period Tb is set and the setting operation is performed in the setting operation period Tb.

Therefore, fig. 81 shows a timing chart when the setting operation and the input operation (the output of a current to a pixel, that is, the setting operation of the current source circuit of the pixel) of the current source circuit of the signal line driver circuit cannot be performed simultaneously. The setting operation of the current source circuit of the signal line driver circuit is performed during a period in which the setting operation of the current source circuit of the pixel is not performed. In fig. 81, the process is performed during Ta 2. The setting operation of the current source circuit of the pixel is performed in the other period. Therefore, the setting operation of the current source circuit of the signal line driver circuit can be performed while avoiding the setting operation of the current source circuit of the pixel (the input operation of the current source circuit of the signal line driver circuit).

Further, by adopting the above method, the number of times of setting operation of the current source circuit arranged in the signal line driver circuit can be reduced. Therefore, power consumption can be reduced. The setting operation of the current source circuit of the signal line driver circuit may be performed at any timing and any number of times. In order to prevent the charge accumulated in the capacitor element disposed in the current source circuit from varying, it is necessary to refresh the charge by performing a setting operation of the current source circuit at a certain cycle. Therefore, the refresh operation of the electric charge accumulated in the capacitive element can be performed several times during 1 frame. Alternatively, it may be performed 1 time during several frames.

In fig. 81, the setting operation of the current source circuit is performed only 1 time in a certain period of the address period Ta 2. The frequency at which the setting operation is performed can be determined appropriately according to the charge storage state of the capacitor element included in the current source circuit.

Next, fig. 82 shows a case where the timing of the setting operation of the current source circuit arranged in the signal line driver circuit is different from that of fig. 81.

In fig. 82, the setting control line is used to control the setting operation of the current source circuit of the signal line driver circuit not in the address period but in the address period and the address period. The input operation of the current source circuit of the signal line driver circuit (the setting operation of the current source circuit of the pixel, which outputs a current to the pixel) is performed during a non-lighting period (non-lighting period) (Td3, Td4) in which the current source circuit of the pixel does not perform the input operation, that is, in which no current flows through the light emitting element.

By adopting the above method, the setting operation and the input operation of the current source circuit of the signal line driver circuit can be performed at different times.

In this way, by performing the setting operation of the current source circuit of the signal line driver circuit in a period other than the address period, the operation in the address period and the operation speed of the setting operation can be changed. That is, the frequency of the sampling pulse output from the shift register 411 can be changed. Accordingly, the operation of the shift register 411 can be delayed only when the setting operation of the current source circuit of the signal line driver circuit is performed. As a result, the setting operation of the current source circuit can be performed for a sufficiently long time, and the setting operation can be performed more accurately.

In order to perform the setting operation of the current source circuit, even if the shift register 411 is operated, the entire pixel is not affected unless the scanning line (gate line) in the pixel is selected. That is, in the address period, since the scanning line (gate line) is not selected, the entire pixel is not affected at all.

In the case where the shift register 411 is a circuit in which a plurality of wirings can be selected at random as shown in fig. 43, 44, 45, 46, and the like, it is not necessary to complete the setting operation of all the current source circuits in 1 section of the gap period between the 1-time address period and the address period. That is, the setting operation of all the current source circuits can be completed within a period of several frames. Alternatively, when there are a plurality of address periods and a plurality of gap periods between the address periods within 1 frame period, the setting operation of the current source circuit may be performed using several periods selected from these periods. The timing chart at this time is shown in fig. 83.

Further, the setting operation of the current source circuit for the pixel may be performed only in the non-lighting period, which may be too short. In this case, as shown in fig. 84, a non-lighting period is forcibly set before each address period, and the setting operation of the current source circuit of the pixel can be performed during the non-lighting period.

Thus far, the timing chart when the digital gradation and the time gradation are combined has been described. Next, a timing chart in the case of simulating gray scales will be described. Here, a timing chart when the setting operation and the input operation of the current source circuit of the signal line driver circuit cannot be performed at the same time will be described.

First, it is assumed that the pixel is the pixel of fig. 13(a) or fig. 13 (B). The signal line driver circuit has the configuration shown in fig. 27 or 54, that is, the circuit shown in fig. 29, 7, 8, and 55. The timing chart at this time is shown in fig. 85.

A scanning line (the 1 st scanning line 1102 in fig. 13a or the 1 st scanning line 1132 in fig. 13B) is selected in a row, and a current is input from a signal line (1101 in fig. 13a or 1131 in fig. 13B). The current becomes a value corresponding to the video signal. This requires a1 frame period.

The above is a timing chart relating to an image display operation, that is, an operation of a pixel. Next, the timing of the setting operation of the current source circuit disposed in the signal line driver circuit will be described. The current source circuit described here is a circuit capable of performing a setting operation and an input operation at the same time. Therefore, this corresponds to the case where fig. 57, 58, or the like is used as the constant current circuit.

The input operation of the current source circuit of the signal line driver circuit is normally performed within 1 frame period. As shown in fig. 85, the setting operation of the current source circuit of the signal line driver circuit is performed within 1 frame period.

Next, a timing chart having a setting control line or a logical operator as shown in fig. 53, 60, 59, 61, and 62 will be described. At this time, whether or not the setting operation of the current source circuit is performed is controlled by the setting control line.

In fig. 60, the 1 st to 3 rd setting control lines control which current source circuits are set to operate and which current source circuits are input to operate. Then, the 4 th control line controls whether or not to perform the setting operation of the current source circuit.

Therefore, as shown in fig. 86, the setting operation period Tb may be provided only during the period in which the scanning line (gate line) is selected, and the setting operation may be performed during the setting operation period Tb.

In this case, in the case of fig. 61 or 60, since the setting operation and the input operation of the current source circuit disposed in the signal line driver circuit can be performed simultaneously, there is no problem in time for performing the setting operation. When the setting operation and the input operation of the current source circuit of the signal line driver circuit cannot be performed simultaneously, the setting operation may be performed by stopping the input operation of the current source circuit of the signal line driver circuit only when the scanning line is selected, that is, during the first period. This period may be made coincident with the retrace period.

In addition, it is not necessary to perform the setting operation for each line when the scanning line is selected as shown in fig. 9. In fig. 86 or 9, it is preferable that a circuit such as fig. 43 be used as a circuit (shift register) for controlling the current source circuit to randomly select the current source circuit. Circuits such as fig. 44, 45, and 46 may be used.

Alternatively, as shown in fig. 10 or 11, the input operation of the current source circuit of the signal line driver circuit (the input operation of the video signal, that is, the current output of the pixel) may be performed in one period of the 1-frame period, and the setting operation of the current source circuit of the signal line driver circuit may be performed in the remaining period. In this case, the setting operation and the input operation of the current source circuit of the signal line driver circuit may not be performed simultaneously.

In this case, when the setting operation of the current source circuit of the signal line driver circuit is performed, the setting operation may be performed for the current source circuits in a row as shown in fig. 10. Alternatively, the current source circuits may be randomly selected using circuits such as fig. 43, 44, 45, and 46, or the setting operation for all the current source circuits may not be completed within 1 frame period. That is, the setting operation for all the current source circuits may be completed within several frame periods. In this case, since the setting operation can be performed for 1 current source circuit for a long time, the setting can be performed accurately.

In addition, when the current source circuit of the signal line driver circuit is set, it is necessary to perform the setting operation without a leak current and without another current. Therefore, the transistor 182 in fig. 29, the transistor A, B, C in fig. 55, and the like need to be turned off before the setting operation of the current source circuit in the signal line driver circuit is performed. However, when the transistor 193 is arranged as shown in fig. 56, it is not necessary to consider that no leakage current flows and no other current flows.

In the present embodiment, any combination of embodiments 1 to 8 and embodiment 1 is possible.

(example 3)

In this embodiment, a method in performing color display is described.

When the light emitting element is an organic EL element, luminance varies depending on color even if the same magnitude of current flows through the light emitting element. Further, when a light emitting element ages, the degree of aging also differs depending on the color. Therefore, various methods are required to adjust the white balance.

The simplest method is to change the magnitude of the current input to the pixel according to the color.

Another method is to use a circuit as shown in fig. 20 in the pixel, the signal line driver circuit, and the reference constant current source. Also, the ratio of W/L of the 2 transistors constituting the mirror circuit is changed according to the color. Thus, the magnitude of the current changes depending on the color.

Yet another method is to change the length of the light-up period according to the color. The method is suitable for both the case of using the time gray scale method and the case of not using the time gray scale method, and can be applied in any case. Thereby, the gradation can be adjusted.

By using the above methods, or by using them in combination, the white balance can be easily adjusted.

In the present embodiment, any combination of embodiments 1 to 8 and embodiments 1 and 2 is possible.

(example 4)

In this embodiment, the appearance of a light-emitting device (semiconductor device) of the present invention will be described with reference to fig. 12. Fig. 12(a) is a bottom view of a light-emitting device formed by sealing an element substrate over which a transistor is formed with a sealing material, fig. 12(B) is a cross-sectional view taken along line a-a 'in fig. 12(a), and fig. 12(C) is a cross-sectional view taken along line B-B' in fig. 12 (a).

A sealant 4009 is provided so as to surround a pixel portion 4002, a source signal line driver circuit 4003, and gate signal line driver circuits 4004a and b, which are provided over a substrate 4001. A sealing material 4008 is provided over the pixel portion 4002, the source signal line driver circuit 4003, and the gate signal line driver circuits 4004a and b. Thus, the pixel portion 4002, the source signal line driver circuit 4003, and the gate signal line driver circuits 4004a and b are sealed with the substrate 4001, the sealing material 4009, the sealing material 4008, and the filler 4210.

Further, the pixel portion 4002, the source signal line driver circuit 4003, and the gate signal line driver circuits 4004a and b provided over the substrate 4001 include a plurality of TFTs. Fig. 12B shows a driving TFT (here, an n-channel TFT and an n-channel TFT are illustrated) 4201 included in the source signal line driver circuit 4003 and an erasing TFT4202 included in the pixel portion 4002, which are formed over the underlying film 4010.

In this embodiment, a p-channel TFT or an N-channel TFT manufactured by a known method is used for the driving TFT4201, and an N-channel TFT manufactured by a known method is used for the erasing TFT 4202.

An interlayer insulating film 4301 is formed on the driving TFT4201 and the erasing TFT4202, and a pixel electrode (anode) 4203 electrically connected to the drain of the erasing TFT4202 is formed thereon. The pixel electrode 4203 uses a transparent conductive film having a large work function. As the transparent conductive film, a compound of indium oxide and tin oxide, a compound of indium oxide and zinc oxide, tin oxide, or indium oxide can be used. Further, a mixture in which gallium is added to the transparent conductive film may be used.

An insulating film 4302 is formed on the pixel electrode 4203, and the insulating film 4302 forms an opening above the pixel electrode 4203. In the opening, a light-emitting layer 4204 is formed on the pixel electrode 4203. A well-known light-emitting material or inorganic light-emitting material can be used for the light-emitting layer 4204. Further, the light-emitting material includes a low molecular material (monomer system) and a high molecular material (polymer system), and any of them can be used.

The light-emitting layer 4204 can be formed by a known vapor deposition technique or coating technique. The light-emitting layer 4204 may have a stacked-layer structure or a single-layer structure in which a hole injection layer, a light-emitting layer, an electron transport layer, or an electron injection layer are arbitrarily combined.

A cathode 4205 formed of a conductive film having a light-shielding property (typically, a conductive film containing aluminum, copper, or silver as a main component, or a laminate film of these and another conductive film) is formed over the light-emitting layer 4204. It is preferable to exclude moisture or oxygen present at the interface between the cathode 4205 and the light-emitting layer 4204 as much as possible. Therefore, it is necessary to form the light emitting layer 4204 in nitrogen or an inert gas, and form the cathode 4205 without contact with oxygen or moisture. In this embodiment, the film formation as described above can be realized by using a film formation apparatus of a multi chamber (multi chamber) system (cluster tool) system). Further, a predetermined voltage may be applied to the cathode 4205.

As described above, the light-emitting element 4303 including the pixel electrode (anode) 4203, the light-emitting layer 4204, and the cathode 4205 is formed. Then, a protective film is formed over the insulating film to cover the light-emitting element 4303. The protective film has an effect of preventing oxygen or moisture or the like from entering the light emitting element 4303.

Reference numeral 4005a denotes a wiring connected to a power supply line, and is electrically connected to the source region of the erasing TFT 4202. The lead 4005a passes between the sealing material 4009 and the substrate 4001, and is electrically connected to an FPC wiring 4301 provided with an FPC4006 through an anisotropic conductive film 4300.

The sealing material 4008 can be made of a glass material, a metal material (typically, a stainless steel material), a ceramic material, or a plastic (including a plastic film). As the plastic, an FRP (reinforced fiberglass plastic) plate, a PVF (polyvinyl fluoride) film, a mylar (mylar) film, a polyester (polyester) film, or an acryl film may be used. Further, a sheet material having a structure in which an aluminum foil is sandwiched by a PVF film or a mylar film may also be used.

However, when the irradiation direction of light from the light-emitting layer faces the cover material side, the cover material must be transparent. In this case, a transparent material such as a glass plate, a plastic plate, a polyester (polyester) film, or an acryl film is used.

The filler 4210 may be an ultraviolet curable resin or a thermosetting resin other than an inert gas such as nitrogen or argon, and may be PVC (polyvinyl chloride), acryl, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (vinyl acetate). In the present embodiment, nitrogen is used as the filling material.

In addition, in order to place the filler 4210 in an environment of a hygroscopic substance (preferably barium oxide) or an oxygen-absorbing substance, a concave portion 4007 is provided on a side surface of the substrate 4001 of the sealant 4008, and the hygroscopic substance or the oxygen-absorbing substance 4207 is further disposed. Further, the hygroscopic substance or the oxygen-absorbing substance 4207 is held in the concave portion 4007 by the concave portion covering material 4208, and the hygroscopic substance or the oxygen-absorbing substance 4207 is prevented from scattering. The concave portion covering material 4208 has a fine grid shape, and only air and moisture pass through the concave portion covering material 4208, and a hygroscopic substance or an oxygen absorbing substance 4207 does not pass through the concave portion covering material. By providing the hygroscopic substance or the oxygen absorbing substance 4207, deterioration of the light-emitting element 4303 can be prevented.

As shown in fig. 12(C), a conductive film 4203a is formed at the same time as the pixel electrode 4203 so as to be connected to the lead 4005 a.

Further, the anisotropic conductive film 4300 has a conductive caulk 4300 a. By heat-pressing the substrate 4001 and the FPC4006, the conductive film 4203a on the substrate 4001 and the wiring 4301 for FPC on the FPC4006 are electrically connected with the conductive filler 4300 a.

In the present embodiment, the present invention can be arbitrarily combined with embodiments 1 to 8 and embodiments 1 to 3.

(example 5)

Since the light emitting device is a self-light emitting type, it is excellent in visibility in a bright place and has a wide viewing angle as compared with a liquid crystal display. Therefore, the display device can be used for display portions of various electronic apparatuses.

Electronic devices using the light-emitting device of the present invention include video cameras, digital cameras, goggle type displays (head mounted displays), navigation systems, audio playback devices (car audio, audio component systems, and the like), notebook computers, game machines, portable information terminals (mobile computers, mobile phones, portable game machines, electronic books, and the like), image reproducing devices provided with a recording medium (specifically, devices capable of reproducing an image from a recording medium such as a Digital Versatile Disc (DVD) and displaying the image), and the like. In particular, a portable information terminal, which has many opportunities to view a screen from an oblique direction, is expected to use a light-emitting device because the wide viewing angle is particularly important. Fig. 22 shows a specific example of these electronic devices.

Fig. 22(a) shows a light-emitting device, which includes a housing 2001, a support 2002, a display 2003, a speaker 2004, an image input terminal 2005, and the like. The present invention can be applied to the display portion 2003. Further, the light-emitting device shown in fig. 22(a) can be completed by the present invention. Since the light-emitting device is a self-light-emitting type, it does not require a backlight and can be used as a display portion thinner than a liquid crystal display. The light emitting device is included in all information display devices for computers, television broadcast reception, advertisement display, and the like.

Fig. 22(B) shows a digital camera, which includes a main body 2101, a display portion 2102, an image receiving portion 2103, operation keys 2104, an external interface 2105, a shutter 2106, and the like. The present invention can be applied to the display portion 2102. Further, the digital camera shown in fig. 22(B) can be completed by the present invention.

Fig. 22(C) shows a notebook computer, which includes a main body 2201, a housing 2202, a display portion 2203, a keyboard 2204, an external interface 2205, a pointing mouse 2206, and the like. The present invention can be applied to the display portion 2203. Further, the light-emitting device shown in fig. 22(C) can be completed by the present invention.

Fig. 22(D) shows a mobile computer, which includes a main body 2301, a display portion 2302, a switch 2303, operation keys 2304, an infrared interface 2305, and the like. The present invention can be applied to the display portion 2302. Further, the mobile computer shown in fig. 22(D) can be completed by the present invention.

Fig. 22E shows a portable image reproducing device having a recording medium (specifically, a DVD reproducing device), which includes a main body 2401, a housing 2402, a display portion a2403, a display portion B2404, a recording medium (DVD or the like) reading portion 2405, an operation key 2406, a speaker portion 2407, and the like. The display portion a2403 mainly displays image information, and the display portion B2404 mainly displays character information, and the present invention can be applied to the display portions A, B2403 and 2404. Further, the image reproducing apparatus having a recording medium includes a home-use game machine and the like. Further, the DVD player shown in fig. 22(E) can be completed by the present invention.

Fig. 22F shows a goggle type display (head mounted display), which includes a main body 2501, a display portion 2502, an arm portion 2503, and the like. The present invention can be applied to the display portion 2502. Further, the goggle type display shown in fig. 22(F) can be completed by the present invention.

Fig. 22(G) shows a video camera, which includes a main body 2601, a display portion 2602, a housing 2603, an external interface 2604, a remote control receiving portion 2605, an image receiving portion 2606, a battery 2607, a voice input portion 2608, operation keys 2609, an eyepiece portion 2610, and the like. The present invention can be applied to the display portion 2602. Further, the camera shown in fig. 22(G) can be completed by the present invention.

Fig. 22(H) shows a mobile phone, which includes a main body 2701, a housing 2702, a display portion 2703, an audio input portion 2704, an audio output portion 2705, operation keys 2706, an external interface 2707, an antenna 2708, and the like. The present invention can be applied to the display portion 2703. Further, the display portion 2703 can reduce the current consumption of the mobile phone by displaying white characters on a black background. In addition, the mobile phone shown in fig. 22(H) can be completed by the present invention.

Further, when the light emission luminance of the light-emitting material is increased in the future, the light including the image information to be output may be enlarged and projected by a lens or the like, and the light-emitting material may be applied to a front-projection or rear-projection type projector.

In addition, many of the electronic devices display information transmitted through an electronic communication line such as the internet or CATV (cable television), and the chances of displaying moving image information are increasing. Since the response speed of the light-emitting material is very high, the light-emitting device is ideal for animation display.

Further, since a portion of the light emitting device emitting light consumes power, it is preferable to reduce the light emitting portion as much as possible when displaying information. Therefore, in the case where the light emitting device is used for a display unit mainly containing character information such as a portable information terminal, particularly a portable telephone or an audio playback apparatus, it is preferable to drive the display unit by forming character information with a light emitting portion using a non-light emitting portion as a background.

As described above, the present invention has a very wide application range and can be applied to electronic devices in all fields. The electronic device of the present embodiment may be configured as shown in any of embodiments 1 to 6 and embodiments 1 to 6.

The present invention having the above-described structure can suppress the influence of variation in characteristics of the TFT due to a difference in a manufacturing process or a substrate used, and can supply a desired signal current to the outside.

Further, the 1 shift register of the present invention has 2 functions, one of which is to control a current source circuit, and the other of which is to control a circuit for controlling a video signal, that is, a circuit for displaying an image, for example, has a function of controlling a latch circuit, a sampling switch, a switch 101 (signal current control switch), and the like. With the above configuration, since it is not necessary to provide each circuit for controlling the current source circuit, the video signal controlling circuit, and the like, the number of circuits to be provided can be reduced, and further, the number of components can be reduced, so that the area of the circuit board can be reduced. Thus, the yield in the manufacturing process can be improved, and the cost can be reduced. In addition, if the area of the circuit board is small, the frame can be narrowed, and therefore the size of the frame can be reduced.

In addition, when a shift register having a function of randomly selecting a plurality of wirings is employed, a setting signal supplied to the current source circuit may be output at random. Therefore, the setting operation of the current source circuit may be performed not in order from the 1 st column to the last 1 st column, but at random. Thus, the period for which the setting operation of the current source circuit is performed can be freely set. Further, the influence of the leakage of the electric charge held by the capacitance element of the current source circuit can be made less conspicuous. In this way, if the setting operation of the current source circuit can be performed at random, the influence thereof can be made less conspicuous when the setting operation of the current source circuit is inappropriate.

Claims (9)

1. A signal line driver circuit comprising:

a first circuit configured to output a pulse;

a second circuit electrically connected to the first circuit; and

a current source circuit comprising a first terminal, a second terminal, and a third terminal,

wherein the content of the first and second substances,

the first terminal is electrically connected to the first circuit,

the second terminal is electrically connected to the reference current source circuit, an

The third terminal is electrically connected to a wiring.

2. A signal line driver circuit comprising:

a first circuit configured to output a pulse;

a second circuit configured to store a video signal according to the pulse supplied from the first circuit; and

a current source circuit comprising a first terminal, a second terminal, and a third terminal,

wherein the content of the first and second substances,

supplying a signal according to the pulse supplied from the first circuit to the first terminal,

the second terminal is electrically connected to a reference current source circuit,

the current source circuit converts a first current supplied from the second terminal into a voltage and converts the voltage into a second current according to a signal supplied from the first terminal, an

The second current is supplied to a wiring through the third terminal.

3. A signal line driver circuit comprising:

a first circuit configured to output a pulse;

a second circuit configured to store a video signal according to the pulse supplied from the first circuit; and

a current source circuit comprising a first terminal, a second terminal, and a third terminal,

wherein the content of the first and second substances,

supplying a pulse supplied from the first circuit to the first terminal,

the second terminal is electrically connected to a reference current source circuit,

the current source circuit converts a first current supplied from the second terminal into a voltage and converts the voltage into a second current according to a pulse supplied from the first terminal, an

The second current is supplied to a wiring through the third terminal.

4. The signal line driver circuit according to any one of claims 1 to 3, further comprising:

a switch disposed between the third terminal and the wiring.

5. The signal line driver circuit according to claim 1, further comprising:

a switch arranged between the third terminal and the wiring,

wherein the content of the first and second substances,

and controlling the switch to be switched on or off through a video signal.

6. The signal line driver circuit according to claim 2 or 3, further comprising:

a switch arranged between the third terminal and the wiring,

wherein the content of the first and second substances,

the switch is controlled to be turned on or off by the video signal stored in the second circuit.

7. The signal line driver circuit according to any one of claims 1 to 3, further comprising:

and a pixel electrically connected to the wiring.

8. The signal line driver circuit according to claim 1, wherein the current source circuit supplies a current proportional to the reference current source circuit.

9. The signal line driver circuit according to claim 2 or 3, wherein the current source circuit supplies a second current proportional to the reference current source circuit.