HK1124439B - Current detection circuit and current type switch adjustor - Google Patents

Description

Current detection circuit and current mode switching regulator

Technical Field

The present invention relates to a current mode switching regulator that uses a dc input power supply and controls an output voltage based on detected values of the output voltage and an output current, and a current detection circuit used in the current mode switching regulator.

Background

As a current mode step-down switching regulator, a circuit having a configuration shown in fig. 5 is used (for example, see patent document 1).

In this circuit, when the switch 107 is turned on, a current flows from the power supply to the coil 108, and the input voltage Vi is accumulated as electric energy (i.e., charge) in the coil 108 and also accumulated in the output capacitor 112. By turning off the switch 107, the electric energy stored in the output capacitor 112 is discharged by the electric charge.

Therefore, the current mode step-down switching regulator of fig. 5 supplies the load with a voltage averaged (integrated) by the output capacitor 112 with respect to the electric energy stored in the coil 108.

The error amplifier 101 inputs a detection voltage obtained by dividing an output voltage by the resistor 110 and the resistor 111 to the inverting input terminal, inputs a reference voltage Vref output from the reference voltage source 100 to the non-inverting input terminal, amplifies a difference between the detection voltage and the reference voltage Vref, and outputs the amplified result to the inverting input terminal of the comparator 105 as a detection amplified voltage.

The I/V circuit 121 detects a current flowing through the coil 108, generates a voltage corresponding to the current, and outputs the voltage to one input terminal of the adder 103.

The I/V circuit 122 detects a current flowing through the load, generates a voltage corresponding to the current, and outputs the voltage to the other input terminal of the adder 103.

The adder 103 adds the voltages input from the one input terminal and the other input terminal, and outputs the result of the addition as a compensation voltage to the non-inverting input terminal of the comparator 105.

That is, the compensation voltage is a voltage obtained by detecting a current flowing through each element using a detector connected in series to the load or the coil 108, converting a value proportional to a current value of the current flowing through the load or the coil 108 into a voltage value, and adding the voltage value to the voltage value by the adder 103.

The comparator 105 inputs the detection amplification voltage to the inverting input terminal, inputs the compensation voltage to the non-inverting input terminal, compares the detection amplification voltage and the compensation voltage, and outputs the comparison result as a control signal to the reset terminal R of the SR-latch 106. Therefore, as the output voltage increases, the detection amplification voltage output from the error amplifier 101 increases, and when the detection amplification voltage exceeds the compensation voltage, the comparator 105 changes the control signal from the H level to the L level. When the detection amplification voltage is lower than the compensation voltage, the comparator 105 changes the control signal from the L level to the H level.

Therefore, the SR-latch 106 receives a clock signal of a fixed period from the oscillator 104 to the set terminal, sets the switching signal to H level when set, resets the output when the control signal of H level is received, and sets the switching signal to L level. The switch 107 is turned on when the input switching signal is at the H level, and turned off when the input switching signal is at the L level.

[ patent document 1 ] Japanese patent application laid-open No. 2002-281742

As described above, the current mode step-down switching regulator generates the output voltage from the feedback information of both the output voltage and the output current, and thus controls the duty (duty) of the switching signal that controls the on/off state of the switch 107.

However, in the conventional example, the current detection circuit for detecting the current information inputted to the adder 103 has a disadvantage that the process is complicated and the reduction cannot be performed because a minute voltage is generated from a minute current and the current detection circuit is formed by bipolar or bicmos (bipolar and CMOS mixed).

Disclosure of Invention

The present invention has been made in view of such circumstances, and an object thereof is to provide a current detection circuit which is entirely formed of a cmos (complementary Metal Oxide semiconductor), and which can simplify a process and reduce a chip size as compared with a conventional example.

A current detection circuit (current sensing circuit in an embodiment) of the present invention is a current detection circuit (in an embodiment, a current mode switching regulator, a current detection circuit) that detects a current flowing through an object to be measured (coil L in an embodiment) and outputs a voltage corresponding to the current as a detection result (in an embodiment, the current mode switching regulator is a current detection circuit that generates a sense voltage corresponding to a current value of a coil current flowing through a coil, the sense voltage being slope-compensated by a voltage compensating a ramp waveform and used for voltage control), and is characterized by including a first P-channel transistor (P-channel transistor M11 in an embodiment) having a source connected to a power supply and a gate grounded and flowing a 1/N current that drives the object to be measured; a second P-channel transistor (a P-channel transistor M12 in the embodiment) having a source connected to the drain of the first P-channel transistor; a third P-channel transistor (a P-channel transistor M9 in the embodiment) connected to the drain of the transistor (a P-channel transistor M1 in the embodiment) that causes current to flow through the coil; a voltage mirror circuit (a voltage mirror circuit 20 in the present embodiment) having one terminal connected to the drain of the second P-channel transistor and the other terminal connected to the drain of the third P-channel transistor, the voltages of the terminal and the other terminal being made equal; and a first N-channel transistor (an N-channel transistor M5 in this embodiment) having a drain connected to the drain of the first P-channel transistor, a source connected to the ground through a sense resistor, and a gate to which a voltage operating in a saturation region is applied, the first N-channel transistor outputting the source voltage as the sense voltage.

In the current detection circuit of the present invention, the second P-channel transistor and the third P-channel transistor are formed with the same size.

The current detection circuit of the present invention is characterized in that, during a period in which the current of the measurement target is detected (in the present embodiment, during a period in which the P-channel transistor M1 for allowing the current to flow through the coil is turned on), a voltage for turning on the second and third P-channel transistors is applied to the gates of the second and third P-channel transistors.

The current detection circuit of the present invention is characterized in that the voltage mirror circuit includes a second N-channel transistor (an N-channel transistor M3 in the present embodiment) having a drain connected to the one terminal; a third N-channel transistor (an N-channel transistor M4 in this embodiment) having a drain connected to the source of the second N-channel transistor; a fourth N-channel transistor (an N-channel transistor M8 in the present embodiment) having a drain connected to the other terminal and a gate connected to the gate of the second N-channel transistor; a fifth N-channel transistor (an N-channel transistor M6 in the present embodiment) having a drain connected to the source of the fourth N-channel transistor and a gate connected to the gate of the third N-channel transistor, and an operational amplifier having a non-inverting input terminal connected to the one terminal, an inverting input terminal connected to the other terminal, an output terminal connected to the gates of the second and fourth N-channel transistors, and a reference voltage applied to the gates of the third and fifth N-channel transistors.

In the current detection circuit of the present invention, the gate of the first N-channel transistor is connected to the drain of the third N-channel transistor.

In the current detection circuit of the present invention, the gate of the first N-channel transistor is connected to the drain of the third N-channel transistor.

The switching regulator of the present invention is a current mode switching regulator, and is characterized by having a tilt compensation circuit for outputting a compensation ramp waveform for tilt compensation; a current detection circuit for measuring a current flowing through a coil used for voltage conversion and generating a sense voltage corresponding to the current; the adder is used for adding the voltage of the compensation ramp waveform and the sensing voltage to generate a corrected compensation sensing voltage; and an output voltage control circuit for controlling an output voltage by the corrected compensated sense voltage, wherein the sense voltage is obtained as a detection result by using any one of the current detection circuits as the current detection circuit.

With the above-described configuration, according to the present invention, since the second P-channel transistor and the third P-channel transistor are respectively inserted as switches for detection between the first P-channel transistor and the transistor for driving the coil used for voltage conversion and the terminal of the voltage mirror circuit, the voltage can be set to the same value between the drain and the source of the first P-channel transistor and the transistor for driving the coil, and the current corresponding to the transistor ratio flows through the sense resistor, so that all the transistors can be formed in a CMOS configuration, unlike the bipolar or bicmos configuration in the related art, and the process of the current mode switching regulator semiconductor device can be simplified, the chip size can be reduced, and the manufacturing cost can be reduced.

Thus, according to the present invention, by using the current sensing circuit described above, it is possible to generate a sensing voltage accurately corresponding to the current flowing through the coil, and it is possible to configure a current mode switching regulator that can output an output voltage corresponding to the load at high speed and with high accuracy at low cost.

Drawings

Fig. 1 is a conceptual diagram illustrating an example of a configuration of a current mode switching regulator using a current sensing circuit according to an embodiment of the present invention.

Fig. 2 is a waveform diagram for explaining an operation of the current mode switching regulator of fig. 1.

Fig. 3 is a waveform diagram for explaining an operation of the tilt compensation in the current mode switching regulator of fig. 1.

Fig. 4 is a conceptual diagram illustrating an example of a configuration of a current sensing circuit in the current mode switching regulator of fig. 1.

Fig. 5 is a conceptual diagram illustrating an example of a conventional current mode switching regulator.

Description of the symbols

1 semiconductor device for switching regulator

2 overvoltage protection circuit

3 error amplifier

4 tilt compensation circuit

5 Current sensing Circuit

6 PWM comparator

7 adder

8 Oscillator (OSC)

9 PWM control circuit

100 constant current source

C1, C2, C3 capacitor

M1, M9, M10, M11 and M12P channel transistors

M2, M3, M4, M5, M6, M7, M8 and M13N channel transistors

R1, R2 and Rs resistors

Detailed Description

A semiconductor device 1 for a current mode step-down switching regulator using a current detection circuit 5 according to an embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a block diagram showing an example of the configuration of the step-down switching regulator according to this embodiment. The most characteristic configuration of the invention of the present application is the current sensor circuit 5 formed of a CMOS for measuring a current flowing through the coil L or the P-channel transistor M1 with high accuracy, which is used for controlling the output voltage Vout output from the output terminal Pout, and the details thereof will be described in detail.

In fig. 1, the current mode step-down switching regulator of the present embodiment is configured by a semiconductor device 1 for a current mode step-down switching regulator, a coil L used for voltage conversion (step-down in the present embodiment), and a smoothing capacitor C2 for smoothing a voltage output from the coil L, and by turning on a P-channel MOS transistor (hereinafter, referred to as a P-channel transistor) M1, an N-channel MOS transistor (hereinafter, referred to as an N-channel transistor) M2 is turned off, and a current flows from a power supply D1 through an output terminal (CONT terminal) through a terminal Pin through the coil L, and an input voltage Vin which is a voltage of the power supply D1 is stored as electric energy (i.e., charge) in the coil L. Further, the P-channel transistor M1 is turned off, and the N-channel transistor M2 is turned on, thereby discharging the electric energy accumulated in the coil L. A capacitor C1 is connected between the output terminal of the power supply D1 and the ground point.

The source connection terminal Pin of the P-channel transistor M1 is connected to the power supply D1, i.e., through the terminal Pin source, and the source connection terminal Ps of the N-channel transistor M2 is connected to ground, i.e., through the terminal Ps. The other overvoltage protection circuit 13, the error amplifier 3, the tilt compensation circuit 4, the current sensing circuit 5, the PWM comparator 6, the adder 7, the oscillator 8, the PWM control circuit 9, and the or circuit 12 are connected to the power supply D1 through a terminal Pin and to the ground through a terminal Ps.

Therefore, the current mode step-down switching regulator adjusts the output voltage Vout output from the output terminal Pout to the load during the period in which electric energy is stored in the coil L and the period in which electric energy is discharged, and supplies the output voltage Vout averaged (integrated) by the coil L and the capacitor C2 to the load.

The drain of the P-channel transistor M1 is connected (in series) to the drain terminal CONT of the N-channel transistor M2, one end of the coil L is connected to the terminal CONT, and the other end is connected to the load (i.e., the output terminal Pout). The gate of the P-channel transistor M1 is connected to the terminal QB of the PWM control circuit 9, and the gate of the N-channel transistor M2 is connected to the terminal Q of the PWM control circuit 9.

The error amplifier 3 inputs a voltage of an output terminal which is a connection point between the capacitor C2 and the coil L, that is, a divided voltage obtained by dividing the output voltage Vout by a resistor R1 and a resistor R2 (a voltage dividing circuit connected in series) to an inverting terminal, inputs a reference voltage Vref output from the reference power supply D2 to a non-inverting terminal, amplifies a difference between the divided voltage and the reference voltage Vref, and outputs the amplified result as a detection voltage to an inverting input terminal of the PWM comparator 6. Further, a capacitor C3 for phase-controlling the change of the output voltage with respect to the connection point of the resistor R1 and the resistor R2 is inserted between the terminal FD at which the output voltage Vout is input and the connection point of the resistor R1 and the resistor R2.

Here, the target voltage, which is a target value of the voltage supplied to the load, of the output voltage Vout output from the switching regulator is set as the reference voltage Vref of the reference voltage source D2 connected to the error amplifier 3. That is, in the present embodiment, the definition of the target voltage indicates a voltage set as a control target given to the load of the output voltage. In the error amplifier 3, as described above, the reference voltage is a voltage to be compared with the divided voltage obtained by dividing the output voltage by the voltage dividing circuit, and the divided voltage is set when the output voltage matches the target voltage. Therefore, when the divided voltage obtained by dividing the output voltage by the voltage dividing circuit exceeds the reference voltage, it is considered that the output voltage exceeds the target voltage.

The slope compensation circuit 4 generates a sawtooth-shaped compensation ramp wave (a voltage waveform which linearly and sequentially changes by a slope m described later) in synchronization with the cycle T of the frequency of the clock signal oscillated by the oscillator 8, and outputs the generated compensation ramp wave to the input terminal a of the adder 7.

The current sensing circuit 5 detects a current value of the current flowing through the coil L, that is, detects a current variation corresponding to a variation in load capacity, generates a sensing voltage (corresponding to the current value flowing through the coil) S1, and outputs the sensing voltage to the input terminal b of the adder 7. The sense voltage is tilt-compensated (corrected) by the voltage of the compensation ramp wave output from the tilt compensation circuit 4.

Here, since the output voltage Vout changes in accordance with a change in the current flowing through the coil L, a sense voltage corresponding to a change in the current flowing through the coil L is obtained for the voltage value of the compensation ramp wave for tilt compensation, and as will be described later, feedback is given to the compensation ramp wave, thereby enabling highly accurate control.

That is, the period during which the P-channel transistor M1 is turned on is adjusted in accordance with the current flowing through the coil L. Therefore, the sense voltage corresponding to the current flowing through the coil L is subjected to the slope compensation by the voltage of the compensation ramp wave, and the output voltage is determined by the current (primary information) flowing through the coil L, so that the response speed of the control with respect to the load fluctuation becomes high.

As described above, the adder 7 adds the voltage value of the compensation ramp wave output from the slope compensation circuit 4 (input to the input terminal a) and the sense voltage output from the current sense circuit 5 (input to the input terminal b), thereby performing slope compensation on the sense voltage corresponding to the current flowing through the coil L by the compensation ramp wave, and outputs the result to the non-inverting input terminal of the PWM comparator 6.

The PWM comparator 6 compares the voltage value of the detection voltage output from the error amplifier 3 with the voltage value of the above-described tilt-compensated sense voltage input from the adder 7, and outputs the PWM control signal as an H-level pulse when the voltage value of the compensation ramp wave exceeds the detection voltage, as shown in fig. 2.

The oscillator 8 periodically outputs a clock signal (H-level pulse) according to a predetermined period T.

As shown in fig. 2, in synchronization with the rising edge of the clock signal, the PWM control circuit 9 applies a voltage of L level to the gate of the P-channel transistor M1 through the output terminal QB to turn on the P-channel transistor M, and applies a voltage of L level to the gate of the N-channel transistor M2 through the output terminal Q to turn off the P-channel transistor M2.

In synchronization with the rising edge of the PWM control signal (H-level pulse), the PWM control circuit 9 turns off the P-channel transistor M1 by applying an H-level voltage to the gate thereof through the output terminal QB, and turns on the N-channel transistor M2 by applying an H-level voltage to the gate thereof through the output terminal Q.

The overvoltage protection circuit 2 inputs the divided voltage to the non-inverting input terminal, inputs the reference voltage Vref to the inverting input terminal, and turns on the N-channel transistor M13 to lower the output voltage Vout for protecting the load and the semiconductor device 1 when the output voltage exceeds a predetermined voltage, that is, when the divided voltage corresponding to the output voltage exceeds the reference voltage Vref.

In the above-described tilt compensation, it is known that, in a current-mode switching regulator, when a current flowing through a coil is operated continuously at a duty factor of 50% or more, the current oscillates at a period of an integral multiple of a switching frequency, that is, sub-harmonic oscillation occurs. Here, the rising slope of the current flowing through the coil is determined by the input voltage Vin and the impedance value of the coil L, and the falling slope of the current flowing through the coil is determined by the energy consumption of the load connected to the output terminal.

Even in the same cycle, the on/off duty (duty) of the switches of the P-channel transistor M1 and the N-channel transistor M2 is greatly dispersed, and as shown in fig. 3, when the current IL flowing through the coil deviates from Δ Io, Δ Io1 < Δ Io2 in the next cycle and the starting current value gradually increases, and a stable operation is performed in the first cycle, so that sub-harmonic oscillation occurs.

On the other hand, when the off-set current is controlled to be Δ Io1 > Δ Io2, that is, the starting current Io is gradually decreased, the change gradually converges, and the operation becomes stable.

Therefore, in order to reduce the start current in the next cycle, it is necessary to perform the above-described tilt compensation so that the coil current generating sub-harmonic oscillation can be stably operated even if the coil current is continuously at a duty factor of 50% or more.

In order to perform stable operation, the slope m of the rising line of the tilt compensation is set to Δ io1 > Δ io2, and in general, in the case of a current-mode step-down switching regulator, the slope m represented by the following equation needs to be used.

m≥(m2-m1)/2＝(2Vout-Vin)/2L

Here, m2 is the gradient of decrease in the coil current, i.e., the current reduction rate, and is represented by m2 ═ Vout-Vin)/L.

Further, m1 is the gradient of the rise gradient of the coil current, i.e., the current increase rate, and is represented by m1 — Vin/L.

The tilt compensation circuit 4 outputs a compensation ramp wave for tilt compensation of the sawtooth waveform having the slope of m in synchronization with the clock signal output from the oscillator 8.

The current sensing circuit 5 according to an embodiment of the present invention will be described in detail below using fig. 4. Fig. 4 is a conceptual diagram showing an example of a circuit configuration of the current sensor circuit 5 according to the present embodiment.

The current sensing circuit 5 includes P-channel transistors M9, M10, M11, and M12, N-channel transistors M3, M4, M5, M6, M7, and M8, an operational amplifier OP, and a sense resistor Rs.

The P-channel transistor M9 has a source connected to the drain of the P-channel transistor M1 (output buffer), i.e., one end connected to the other end (connection point W) of the coil L connected to the load, and a gate connected to the output terminal QB of the PWM control circuit 9.

The P-channel transistor M10 has a source connected to a power supply line of a power supply voltage (Vin) from a power supply D1, a gate connected to the output terminal Q of the PWM control circuit 9, and a drain connected to the drain of the P-channel transistor M9 at a drain connection point Y. Here, similarly, the other transistors in each current sensing circuit 5 are supplied with the power supply voltage Vin via the power supply line connected to the power supply D1 through the terminal Pin.

P-channel transistor M11 has a source connected to a power supply line of the power supply voltage and a gate connected to output terminal QB of PWM control circuit 9.

P-channel transistor M12 has a source connected to the drain of P-channel transistor M11, i.e., to node X, and a gate connected to the output terminal QB of PWM control circuit 9.

The voltage mirror circuit 20 is configured by the N-channel transistors M3, M4, M5, M6, M7, and M8 and the operational amplifier OP, and the voltage mirror circuit 20 operates so that the voltages at the connection point X and the connection point Y are the same.

Further, since the P-channel transistor M9 and the P-channel transistor M12 have different transistor sizes (channel length and channel width), and an error occurs in the voltage between the drain and the source, a layout design of adjacent arrangement is adopted in order to obtain the same transistor size and to form the transistors with the same threshold voltage, thereby preventing the dispersion of the process.

Here, the N-channel transistor M3 has a drain connected to the connection point X and a source connected to the drain of the N-channel transistor M4. The source of the N-channel transistor M4 is grounded.

The N-channel transistor M8 has a drain connected to the connection point Y and a source connected to the drain of the N-channel transistor M6. The source of the N-channel transistor M6 is grounded.

The operational amplifier OP has a non-inverting input terminal connected to the connection point X, an inverting input terminal connected to the connection point Y, and an output terminal connected to the gates of the N-channel transistors M3 and M8.

The drain and gate of the N-channel transistor M7 are connected to a power supply voltage line via the constant current source 100, the source is grounded, and a constant current I flows from the constant current source 100.

The gates of the N-channel transistors M4 and M6 are connected to the gate and the drain of the N-channel transistor M7, and bypass the gate and drain, so that the constant current I flows through the N-channel transistors M4 and M6.

The N-channel transistor M5 has a connection point P between the drain of the P-channel transistor M11 and the source of the P-channel transistor M12, a drain connected to the connection point Z between the source of the N-channel transistor M3 and the drain of the N-channel transistor M4, and a source grounded via the sense resistor Rs. The voltage at the connection point F between the source of the N-channel transistor M5 and the sense resistor Rs is output to one input terminal of the adder 7 as the sense voltage S1. Here, the N-channel transistor M3 and the N-channel transistor M5 are darlington connected, and the gate voltages are set so that the N-channel transistors M3 and M5 operate in the saturation region.

The P-channel transistor M11 is formed to have a transistor size of 1/N of that of the P-channel transistor M1, that is, to have a current flow of 1/N of that of the P-channel transistor M1.

The constant current I flows only a minute current (for example, 1 μ a) necessary for operating the voltage mirror circuit 20 and making the connection points X and Y the same voltage. The operational amplifier OP has a general circuit structure formed of CMOS.

Therefore, the sense voltage S1 is output as a voltage value corresponding to 1/N of the current flowing through the coil L, and is output as a potential difference between the sense resistors Rs. The sense resistor Rs is set to a low resistance value (for example, several tens Ω to several hundreds Ω) as described below so as not to cause an error in the drain-source voltage of the P-channel transistor M11.

The voltage at the output terminal of the operational amplifier OP is determined by Vgs (gate-source voltage) of the N-channel transistor M3 and Vgs and VA of the N-channel transistor M5. Here, VA is a product of Rsense (resistance value of Rs) and a current value ID (drain current) flowing through the N-channel transistor. Therefore, the voltage at the output terminal of the operational amplifier OP becomes Vgs (M3) + Vgs (M5) + Rsense × ID. Therefore, the resistance Rsense is set so that Vgs (M3) + Vgs (M5) + Rsense × ID does not exceed the upper limit of the preset amplitude range of the output voltage of the operational amplifier OP.

For example, when Vgs (M3) is 0.6V, Vgs (M5) is 0.6V, ID is 1mA, and the upper limit of the amplitude range of the output voltage of the amplifier is 2.8V, Rsense is 1600 Ω.

With the above configuration, according to the current detection circuit of the present embodiment, the sense voltage S1 for correcting the minute voltage for compensating the voltage of the ramp waveform can be easily generated from the large current flowing through the coil L with the CMOS configuration. Thus, this embodiment can be easily manufactured by a normal CMOS process without using a bipolar or a bicmos as in the conventional art, and therefore can be incorporated in a logic circuit and can be miniaturized, and the manufacturing cost of a chip can be reduced as compared with the conventional example.

Next, the operation of the current mode step-down switching regulator shown in fig. 1 including the operation of the current sensing circuit 5 according to the present embodiment will be described with reference to fig. 2.

At time t1, when the oscillator 8 outputs the clock signal as a pulse signal of H level, the PWM control circuit 9 transitions the output terminal QB from H level to L level, while transitioning the output terminal Q from H level to L level.

Accordingly, the P-channel transistor M1 is turned on, the N-channel transistor M2 is turned off, and a drive current flows from the power supply D1 to the coil L, whereby electric energy is accumulated in the coil L.

At this time, the slope compensation circuit 4 starts outputting a compensation slope wave linearly changing with a slope m (rising with the slope m in the present embodiment) in synchronization with the clock signal.

The P-channel transistor M12 and the P-channel transistor M9 have gates to which a control signal at an L level is input, and are turned on.

That is, the P-channel transistor M12 and the P-channel transistor M9 operate as switches for generating the sense voltage S1 corresponding to the current flowing through the coil L while the current flows through the coil L.

Since the connection points X and Y have the same voltage, the source-drain voltages of the P-channel transistor M12 and the P-channel transistor M9 are the same, that is, the same voltage as the connection point W connecting the other end of the coil L and the drain of the P-channel transistor M9, and thus a current having a current value of 1/N flows from the connection point P to the N-channel transistor M5 with respect to the current flowing through the coil L.

Thus, the current sensing circuit 5 outputs the voltage drop between the terminals of the sense resistor Rs as the sense voltage S1. Here, when the resistance value of the sense resistor Rs is not appropriately adjusted as described above, the output voltage of the operational amplifier OP is saturated and cannot normally operate when the sense voltage S1 increases, and the gate-source voltages of the P-channel transistors M11 and M1 are different from each other, so that an accurate current value cannot be obtained.

At this time, when the voltage Vx at the connection point X decreases with respect to the voltage Vy at the connection point Y, that is, when the coil current increases, the output voltage of the operational amplifier OP decreases, the voltage Vz at the connection point Z, which is the source voltage of the N-channel transistor M3, also decreases, and the sense voltage S1, which is the source voltage of the N-channel transistor M5, decreases in accordance with the decrease in the voltage Vz. As a result, the drain current of the N-channel transistor M3 decreases, and a feedback loop in which the voltage Vx rises is formed.

That is, the operational amplifier OP inverts the polarity of the voltage output from the output terminal by the change in the source voltage of the N-channel transistor M3 to form a negative feedback loop, and performs voltage adjustment such that Vx becomes Vy.

The adder 7 adds the sense voltage S1 input from the input terminal b to the voltage value of the compensation ramp wave input at the one input terminal a, and outputs the sense voltage S1 subjected to the voltage tilt compensation by the compensation ramp wave to the inverting input terminal of the PWM comparator 6.

Thus, the PWM comparator 6 compares the detection voltage input from the error amplifier 3 with the voltage obtained by tilt-compensating the sense voltage S1 corresponding to the current flowing through the coil L with the compensation ramp wave, and can feed back the value of the current flowing through the coil L in real time to output a PWM control signal for controlling the on-time of the P-channel transistor M1.

At time t2, when detecting that the voltage of the compensation ramp linearly rising at the slope m exceeds the output voltage of the error amplifier 3, the PWM comparator 6 changes the voltage of the output PWM control signal from the L level to the H level.

Then, the PWM control circuit 9 changes the voltage of the PWM control signal input from the PWM comparator 6 from the L level to the H level, thereby changing the voltage output from the output terminal QB from the L level to the H level and changing the voltage output from the output terminal Q from the L level to the H level.

Thereby, the P-channel transistor M1 is turned off, the N-channel transistor M2 is turned on, and the electric energy accumulated in the coil L is discharged.

At this time, the gate voltages of the P-channel transistor M12 and the P-channel transistor M9 change from the L level to the H level, whereby the P-channel transistor M12 and the P-channel transistor M9 are turned off.

Here, in order to prevent the current sensing circuit 5 from malfunctioning and amplifying noise when the connection point Y is in a voltage state in which the floating state becomes unstable, the sensing voltage S1 is output, the gate of the P-channel transistor M10 is changed from the H level to the L level, and the connection point Y is set to the power supply voltage value.

Next, at time t3, the slope compensation circuit 4 sets the compensation ramp waveform to the set maximum value, and stops the output of the compensation ramp.

Thus, when the PWM comparator 6 detects that the voltage of the compensation ramp wave decreases with respect to the output voltage of the error amplifier 3, the voltage of the output PWM control signal is changed from the H level to the L level.

Next, at time t4, the oscillator 8 outputs a clock signal and starts the next cycle, and the operation from time t1 to time t4 is repeated as described above.

With the above-described configuration, the current mode switching regulator semiconductor device of the present embodiment has the same transistor size and the same threshold voltage as those of the above-described current sensing circuit having a CMOS configuration, i.e., the P-channel transistor M9, by using the P-channel transistor M12 arranged close to each other in the layout, it is possible to prevent the gate-source voltage of the P-channel transistor M11 and the P-channel transistor M1 from being shifted, to suppress the error current caused by the shift from flowing through the N-channel transistor M5, since the correct current flowing through 1/N of the coil L is detected, the sense voltage S1 corresponding to the current is supplied to the adder 7, therefore, the voltage of the compensation ramp waveform for the tilt compensation can be corrected in real time based on the information of the current flowing through the coil L, and the on period of the P-channel transistor M1 can be controlled at high speed in accordance with the current flowing through the coil L.

In the present embodiment, the current detection circuit according to the present invention is described with reference to a step-down current-mode switching regulator, but the current detection circuit according to the present invention may be used in a step-up current-mode switching regulator.

Claims (7)

1. A current detection circuit for detecting a current flowing through an object to be measured and outputting a voltage corresponding to the current as a detection result, comprising:

a first P-channel transistor having a source connected to a power supply and a gate grounded, and through which a 1/N current flows for driving a transistor to be measured;

a second P-channel transistor having a source connected to the drain of the first P-channel transistor;

a third P-channel transistor connected to the measurement target;

a voltage mirror circuit having one terminal connected to the drain of the second P-channel transistor and the other terminal connected to the drain of the third P-channel transistor, the voltages of the terminals being made the same as the voltages of the other terminals; and

a first N-channel transistor having a drain connected to the drain of the first P-channel transistor, a source connected to the ground via a sense resistor, and a gate to which a voltage operating in a saturation region is applied,

wherein 1/N is a transistor size ratio of the first P-channel transistor to a transistor for driving the measurement object,

the first N-channel transistor outputs a source voltage as a voltage of the detection result.

2. The current sensing circuit of claim 1, wherein the second and third P-channel transistors are formed with the same dimensions.

3. The current detection circuit according to claim 1, wherein a voltage for turning on the second and third P-channel transistors is applied to gates of the second and third P-channel transistors while the current of the object to be measured is detected.

4. The current detection circuit according to claim 2, wherein a voltage for turning on the second and third P-channel transistors is applied to gates of the second and third P-channel transistors while the current of the measurement target is detected.

5. The current detection circuit according to any one of claims 1 to 4,

the voltage mirror circuit has:

a second N-channel transistor having a drain connected to the one terminal,

a third N-channel transistor having a drain connected to the source of the second N-channel transistor,

a fourth N-channel transistor having a drain connected to the other terminal and a gate connected to the gate of the second N-channel transistor,

a fifth N-channel transistor having a drain connected to the source of the fourth N-channel transistor and a gate connected to the gate of the third N-channel transistor, an

An operational amplifier having a non-inverting input terminal connected to the one terminal, an inverting input terminal connected to the other terminal, and an output terminal connected to the gates of the second and fourth N-channel transistors,

a reference voltage is applied to the gates of the third and fifth N-channel transistors.

6. The current sensing circuit of claim 5, wherein a gate of the first N-channel transistor is connected to a drain of the third N-channel transistor.

7. A current mode switching regulator includes:

a tilt compensation circuit for outputting a compensation ramp waveform for tilt compensation;

a current detection circuit for measuring a current flowing through a coil used for voltage conversion and generating a sense voltage corresponding to the current;

the adder is used for adding the voltage of the compensation ramp waveform and the sensing voltage to generate a corrected compensation sensing voltage; and

an output voltage control circuit for controlling the output voltage by the corrected compensated sense voltage,

as the current detection circuit, the current detection circuit described in any one of claims 1 to 5 is used, and the sense voltage is obtained as a detection result.