HK1124173B - Shielded gate trench (sgt) mosfet units implemented with a schottky source contact - Google Patents

Abstract

The present invention discloses a semiconductor power component comprising several power crystal memory cells surrounded by grooves opened in a semiconductor substrate.At least one semiconductor memory cell further comprises a trench type source contact opened between the trenches, which passes through a source region and enters a body region, thereby electrically connecting the source region with a source metal located above an insulating layer. The bottom surface of the trench of the trench type source contact is further covered with a conductive material, acting like an integrated Schottky barrier diode in the active memory cell.An isolation structure is located at the bottom of the trench gate and is insulated from the trench gate, providing shielding effect for both the trench gate and the Schottky diode.

Description

Isolated gate trench mosfet cell implemented with schottky source contact

The present invention is a continuation of the united states patent application No. 11/056,345 filed on 11/2/2005 by the same applicant, the disclosure of which is incorporated herein by reference.

Background

1. Field of the invention

The present invention relates generally to semiconductor power devices, and more particularly to an improved and novel fabrication process and device structure for providing a schottky source contact implemented isolated gate trench (SGT) MOSFET cell for enhanced high frequency power switching (high frequency power switching), bridge (H-bridge) and synchronous rectifier (syn-rectifier) applications.

2. Background of the invention

In order to reduce the power consumption of semiconductor power devices and increase the switching speed of semiconductor power devices, it is desirable to further reduce the resistance and gate capacitance values, and the integration of a schottky diode (schottky diode) has already been implemented in semiconductor power devices, such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs). The standard MOSFET device shown in fig. 1A and 1B integrates a schottky diode to bypass a body diode (body diode), thereby improving the operation of the MOFET device. Improvements in the performance of the MOFET device improve the application of bridge (H-bridge) and synchronous rectification. The MOSFET device shown in fig. 1A has an integrated junction barrier controlled Schottky (JBS) region, which may be a Schottky array having P-N junction gates (P-N junction grids) interspersed between Schottky contacts. Upon application of a threshold reverse bias voltage, the P-N junction will pinch off the channel region underlying the Schottky contact to prevent significant bias leakage current from occurring. The shielding effect (shielding effect) caused by the dissipation layer also improves the breakdown voltage. However, considering that the series resistance increases and because the P-N junction occupies a large portion of the surface area in the integrated junction barrier control schottky (JBS) region, for practical reasons, the overall schottky contact area needs to be reduced to facilitate forward conduction, which results in an increase in the forward voltage of the via. In fig. 1B, an integrated Trench MOS Barrier Schottky (TMBS) is implemented, the integrated TMBS including an array of schottky diodes disposed between MOS trenches with charge coupling between a majority of the charge carriers in the mesa portion of the epi/drift region and the metal on the insulating sidewalls of the trenches, the charge coupling causing a redistribution of the electric field below the schottky contacts, improving breakdown voltage and reducing reverse leakage current.

Us patent No. 4,675,713 discloses a method of using a source schottky junction as a body contact of a semiconductor power device. U.S. patent No. 4,983,535 discloses a method of making a DMOS device having a source and a refractory metal schottky barrier on top of a body region. However, these devices still have the limitation of requiring the use of metals with fairly high barrier heights, and the performance of the devices does not meet the current demands for further reduction in resistance and high drive current.

Fig. 2 discloses an improved DMOS which is a co-pending application filed by the co-inventors of the present invention. The DMOS has an improved structure with a source-body trench (trench) having an anti-punch-through implant located along the trench sidewalls near the gate trench and source. An integrated Schottky diode is formed by depositing a high barrier height metal at the bottom of the source body contact trench to serve as an integrated Schottky contact. A low barrier height metal is further deposited overlying the high barrier height metal to provide ohmic contacts for the source and body regions. The DMOS device shown in fig. 2 integrates a schottky on each of the active area lossless cells to form a schottky as in the old method. However, it is disadvantageous to have a high barrier height metal to achieve an acceptable low leakage current value in the off state because of the high cost required to deposit the high barrier height metal and the low barrier height metal to meet the schottky and source-body ohmic contacts.

In addition, as shown in fig. 1A, 1B, and 2, the device structure is still limited by a relatively high gate-drain capacitance (Cgd) caused by the coupling between the trench gate and the drain disposed at the bottom of the substrate. For power transistors including MOSFETs and IGBTs, new device structures and fabrication processes have long disclosed various gate structures having an isolated gate trench (SGT) structure to reduce the speed-limited capacitance between the gate and drain of these switching power devices. The above-mentioned technologies still face the technical limitations and difficulties, and as the demand for high-frequency switching power components increases, it is more urgent to provide effective solutions to solve the technical limitations and difficulties.

Baliga in U.S. patent No. 5,998,833 discloses a DMOS cell in which a source electrode is placed under the trench gate to reduce the gate-drain capacitance, as shown in fig. 1C, and the gate of the DMOS cell is divided into two parts. The gate-drain capacitance is reduced because the capacitance in the gate-drain overlap region is eliminated.

Patent No. 6,690,062, shown in fig. 1D, discloses a MOSFET device in which the switching performance of the transistor structure is improved by providing a separate electrode in an edge region, which surrounds at least one active cell array region. Capacitance is provided between an edge gate structure and a drain region, wherein the isolation electrode at the edge region reduces the transistor gate-drain capacitance CGD.

In U.S. patent No. 6,891,223, a transistor disclosed by Krumrey et al includes a transistor cell disposed along a trench on a semiconductor substrate and having more than two electrode structures disposed in the trench. In addition, as shown in fig. 1E, a metallization structure is disposed on the substrate surface, and the trench extends into a non-active edge region of the transistor, and an electrical connection between the electrode structure and the opposing metallization structure is established in the edge region.

The transistor structure disclosed in the above patent still has a common difficulty that the source electrode located on the bottom of the trench is connected to the source voltage through the edge region of the semiconductor power device, so that the increase of the resistance of the source electrode cannot be avoided. Furthermore, additional masks are required to create such connections, thereby increasing manufacturing costs.

Therefore, there is a need in the art of power semiconductor device design and fabrication to provide a novel method and device structure for forming a power device, thereby solving the above-discussed problems and limitations.

Disclosure of Invention

It is an object of the present invention to provide a semiconductor power device having an isolated gate trench (SGT) structure with a bottom isolated electrode to more directly improve the connection to the source voltage. In particular, the present invention discloses a macro-cell layout (macro-cell layout) method, in which a trench is filled with conductive polysilicon for directly electrically connecting a bottom isolation electrode of an isolated gate trench (SGT) structure and a source metal. Therefore, in the conventional structure discussed above, the aforementioned problems and difficulties encountered in connecting the device peripheral portion to the source voltage can be solved.

It is another object of the present invention to provide a new and improved combination of an isolated gate trench (SGT) structure and an integrated schottky source contact trench structure to further improve the switching performance of the MOSFET and increase the area efficiency of the integrated schottky. A metal layer of low barrier height is formed overlying a source contact trench, thus improving source performance by the body diode as an integrated schottky contact. Meanwhile, a breakdown implantation region is formed along the trench wall to provide a breakdown prevention region (punch through prevention) at the schottky of the source contact.

It is another object of the present invention to provide an improved isolated gate trench (SGT) device structure and method for manufacturing the same to reduce the gate-source capacitance. The assembly further includes a low barrier height metal layer, such as titanium (Ti) or titanium silicide (TiSi), passing through the body region and being formed₂) The covered source contact trench functions as an integrated schottky barrier diode to improve the performance of the power MOSFET through the body diode. The disclosed assembly is particularly useful for applications in bridge circuits (H-bridges) and synchronous rectification.

Briefly, in a preferred embodiment of the invention, a trench semiconductor power device is disclosed. The semiconductor power device includes a plurality of trenches formed in a semiconductor substrate and interconnected to each other. At least one of the plurality of interconnected trenches forms an isolated gate trench (SGT) structure, and the isolated gate trench (SGT) structure includes a trench gate disposed in an upper portion of the isolated gate trench structure and a bottom isolation electrode disposed in a lower portion of the trench gate and insulated from the trench gate. At least one of the plurality of interconnected trenches constitutes a source connection trench filled with a conductive trench fill material electrically connected to the isolation electrode at the bottom of the isolation gate trench for electrically connecting the source metal on the source connection trench. The trench semiconductor power device further includes a trench source contact opening between the gate trenches and extending through the source into the body region for electrically connecting the source region to a source metal disposed on the insulating layer. The trench source contact is further covered by a low barrier height layer, such as a titanium/titanium nitride layer or titanium silicide/titanium nitride layer, to serve as an integrated schottky barrier diode in each cell of the semiconductor power device, thereby improving the device performance. The semiconductor power device further includes a breakdown prevention region doped with a body type dopant along a sidewall of the source contact trench for preventing breakdown of the semiconductor power device.

In another preferred embodiment of the present invention, an isolation structure is included at the bottom of and insulated from the trenched gate, the isolation structure extending deeper than the bottom of the source contact trench where the schottky diode is formed. The isolation structure provides a shielding effect (shielding effect) for the trench gate, thereby reducing the gate-drain capacitance Cgd and increasing the switching speed. The isolation structure further provides a shielding effect for the schottky diode to reduce leakage current, so that low barrier height materials can be used on the schottky contact to improve schottky junction resistance, and designers can try to find a pair of parameters that can be optimized without always receiving the challenge of leakage current.

Various objects and advantages of this invention will become apparent to those skilled in the art upon a reading of the following detailed description of the embodiments and a review of the various figures of the drawing.

Drawings

FIGS. 1A-1E are schematic cross-sectional views of a prior art trench MOSFET assembly;

FIG. 2 is a schematic cross-sectional view of a MOSFET device with a modified integrated Schottky diode structure;

FIG. 3A is a top view of a trench MOSFET device having an improved structure in accordance with the present invention;

FIGS. 3B-3D are schematic cross-sectional views of trench MOSFET devices having improved structures in accordance with the present invention;

FIGS. 4A-4N are schematic, sequential cross-sectional views illustrating the fabrication of the trench MOSFET device shown in FIG. 3;

FIGS. 5A-5B are schematic cross-sectional views of two other embodiments of the present invention, showing a MOSFET termination region and a tapered gate having a particular configuration;

FIGS. 6A-6B are schematic cross-sectional views of two further embodiments of a MOSFET device of the present invention having a gate-drain isolation structure to reduce the gate-drain capacitance and a Schottky barrier diode through a source contact trench covered by a low barrier height metal;

fig. 7A is a schematic cross-sectional view of a DMOS cell of the present invention showing the bottom isolated electrode of the DMOS cell connected to a voltage other than ground;

FIG. 7B is a schematic diagram of an equivalent circuit; and FIG. 7C is a top view of a device including a source metal, a gate pad, and a lower voltage gate pad.

Detailed Description

Fig. 3A to 3D are a top view and three cross-sectional views of the trench MOSFET device 100 of the present invention. As shown in fig. 3B, the trench MOSFET device 100 is supported on a substrate 105 having an epitaxial layer 110 thereon, and the trench MOSFET device 100 includes an isolated gate trench (SGT) structure. The isolated gate trench structure includes a bottom isolation electrode 130 underlying the trenched gate 150 and insulated from the trenched gate 150, and the bottom isolation electrode 130 is filled with polysilicon to isolate the trenched gate 150 from the drain deposited at the bottom of the trench. The bottom isolated gate trench structure is insulated from the drain region by a dielectric layer 113, and an insulating layer 120 separates the bottom isolated electrode 130 from the trench gate 150. The trenched gate 150 is filled with polysilicon in the trench, and a gate insulating layer 155 surrounds the trench and covers the walls of the trench. A body region 160 between the trenched gates, the body region 160 being doped with a dopant of the second conductivity type, such as a P-type dopant, and the body region 160 surrounding source regions 170, 170' doped with a dopant of the second conductivity type, such as an N + dopant. Source regions 170, 170' are formed near the upper surface of epitaxial layer 110 surrounding trench gate 150. In the present embodiment, only the source region 170 is formed, and the source region 170' is not formed.

An insulating layer 180 is also located on the top surface of the semiconductor substrate, and the MOSFET device 100 further includes source contact trenches 188 disposed on the mesa contact regions between the trenched gates 150, with the bottoms of the source contact trenches 188 extending into the body region 160. A number of more heavily doped regions 185 doped with P + type dopants are formed along the sidewalls of the contact trenches 188 to provide good ohmic contacts to the body regions 160 while also serving as punch-through prevention regions. A metal layer 198 of titanium (Ti) or titanium silicide (TiSi2) is disposed over the insulating layer 180, the metal layer 198 covering the source contact trench sidewalls and the trench bottom of the contact trench 188, the metal layer 198 being formed of titanium (Ti) or titanium silicide (TiSi2) or other low barrier height metal. The metal layer 198 is deposited into the contact trench 188 to provide the function of a source ohmic contact on the trench sidewalls and an integrated schottky-pass body diode at the bottom of the trench. To provide electrical contact to the source and gate regions (not shown), a source metal and a gate metal (not shown) are formed over the schottky barrier metal 198. Fig. 3C is a schematic cross-sectional view taken along line a-a. As shown in fig. 3A to 3D, the bottom isolation electrode 130 is electrically connected to the source metal 190 through the trench-type source connection electrode 140, and the trench-type source connection electrode 140 is electrically connected to the bottom isolation electrode 130 through the interconnected trenches extending between the MOSFET cells.

In fig. 3A, a macro-cell layout (SGT) of the device is disclosed, each active cell having a square layout that is bounded by surrounding trenches to form trenched gates 150 with bottom isolation electrodes, acting as isolated gate trenched (SGT) structures. In the region 195, two trenches have overlapping regions, and a source electrode is electrically connected to the bottom isolation electrode 130. The region 195 may extend beyond this overlap region so that the source connection electrode 140 will extend into the trench portion. In addition, the source connection electrode 140 may also be formed at a non-overlapping portion in the region 195. Other shapes of polygons, such as triangles, rectangles, hexagons, may be used in addition to the square shape shown in fig. 3A. Each macro-cell as shown in fig. 3A includes a number of active cells 115 and at least one area 125. The active cell 115 is surrounded and delimited by a trenched gate 150 in the region 125, and the trenched source connecting electrode 140 is filled with a gate fill material to electrically connect the bottom isolation electrode 130 and the source contact metal. Fig. 3C shows the boundary line of the region 125 and the active cell 115, and in addition, the bottom isolation electrode 130 in the SGT structure is connected to the source connection trench 140 by the interconnection between the bottom isolation electrode 130 (located in the active cell region 115) and the source connection trench 140 (located in the source contact trench region 125). These grooves are interconnected by means of a three-dimensional space and by means of grooves cut in the rear and front of the cross-section, as shown in fig. 3D.

As in the DMOS assembly shown in fig. 3A-3D, the isolated gate trench structure is combined with a trench contact schottky barrier in each active DMOS cell. During reverse blocking, deep trenches with source connected bottom isolation electrodes can isolate schottky contacts. This structure provides the particular advantage that lower leakage currents can be limited by using low barrier height metals such as titanium (Ti) or titanium silicide (TiSi 2). A significantly improved trade-off between forward bias Vf and leakage current is achieved. The barrier height of the metal determines the forward voltage and the leakage current. It is desirable to lower the barrier height to lower the forward voltage, however, this will cause an undesirable effect, i.e., an increase in leakage current. The improved structure disclosed in the present invention allows the use of low barrier height metals because the shielding effect (shielding effect) provided by the deep trench bottom isolation electrode limits the increase in leakage current.

Referring to fig. 3A to 3D and the above description, the present invention discloses a trench semiconductor power device. The trench semiconductor power device includes a plurality of interconnected trenches formed in a semiconductor substrate, at least one of the interconnected trenches forming an isolated gate trench (SGT), the isolated gate trench including a trench gate overlying the isolated gate trench and a bottom isolation electrode underlying the trench gate isolated from the trench gate, at least one of the interconnected trenches forming a source connection trench filled with a conductive trench fill material and electrically connected to the bottom isolation electrode of the isolated gate trench for electrical connection to a source metal on top of the source contact trench. The trench semiconductor power device further includes a trench source contact disposed between the gate trenches and extending through the source region to the body region for electrically connecting the source region to a source metal on the insulating layer. The trench source contact further extends into the body region overlying the low barrier height metal layer and acts as an integrated schottky barrier diode in each cell of the power semiconductor device, thereby improving device performance. The semiconductor power device further includes a breakdown prevention region doped with a body-type dopant along the walls of the source contact trench for preventing breakdown of the semiconductor power device.

Fig. 4A-4L are sequential schematic cross-sectional views illustrating the steps of fabricating the MOSFET device shown in fig. 3A-3D. In fig. 4A, a trench mask 208 is used as a first mask to create an oxidation-hardened mask 206, after which the trench mask 208 is removed. In fig. 4B, a trench etch process is performed to open trenches 209 in an epitaxial layer 210 on a substrate 205. The final depth of trench 209 is determined by the electrode and target oxide thickness. A gate runner trench (gateramp trench)209 'may be formed in the same manner, with the gate runner trench 209' being wider and deeper than the other trenches. In fig. 4C, sacrificial oxidation (sacrificial oxidation) is performed followed by oxide etch to remove the damaged surface on the trench walls to smooth the sidewalls, followed by gate oxidation to grow a gate oxide layer 215. The thick oxide layer 215 is grown to a thickness optimized for low Rds and high breakdown voltage components, and the gate oxide layer 215 reduces the silicon surface electric field, allowing for higher doping and lower Rds for the same breakdown rate.

In fig. 4D, a polysilicon layer 220 for forming a bottom isolation electrode is deposited into trench 209 and gate runner trench 209'. In fig. 4E, a blanket polysilicon etch back (etch back) step is performed to etch back the polysilicon layer 220 until it is lower than the top surface of the oxide layer without using a mask. Then, a conventional plasma etch (plasma etch) process is used to remove the oxide layer on the polysilicon. In fig. 4F, a second mask, polysilicon mask 222, is used to cover portions of polysilicon layer 220S, where polysilicon layer 220S is located within the designated source contact trench. Polysilicon layer 220 is then etched back to remove the upper portion of the trench, which is designated as the trench gate. The polysilicon layer 220 is etched to a target depth using a timed etch-back (timed etch-back) process, followed by removal of the polysilicon mask 222. The oxide layer on the trench sidewalls is then stripped using a wet etch process until the sidewalls on the regions not covered by the polysilicon are clean. Note that the oxide layer in the lower portion of the trench may not be over etched. In fig. 4G, a thin gate oxide layer 225 is formed to cover the upper portion of the trench walls and the upper surface of the remaining bottom polysilicon layer 220 to form the bottom isolation electrode. A thin oxide layer on the sidewalls of the trench gate provides the benefit of reducing the gate threshold voltage. Because the oxide layer is made of heavily doped polysilicon, a thicker oxide layer is grown in the gate oxidation process to cover all the exposed polysilicon regions. This thicker oxide layer around the bottom isolation electrode has the advantage of improving the breakdown voltage. In fig. 4H, a gate polysilicon layer 230 is deposited into the gate trench and etched back to form the trench gate, without the use of a mask, the polysilicon layer 230 is etched back to below the upper surface of the oxide layer, and a gate runner 230G is formed in the same manner.

In fig. 4I, a body dopant implant is performed using a body mask (not shown) to form body dopant regions 235. The body mask does not include a body region at a specific location on the termination area (termination area), resulting in the formation of a guard ring (guard ring) final structure. In fig. 4J, after removing the body mask, body diffusion is performed to form body region 235. Body drive (body drive) is used to diffuse dopants to a predetermined depth no deeper than the overlying gate electrode. Next, a fourth mask, i.e., photoresist such as source mask 237, is used to perform a source dopant implant to form source dopant regions 240. It is necessary to thin a local oxide layer prior to the source implant. In fig. 4K, after removing the photoresist layer 237, the temperature is then raised to diffuse the source region 240, and after source driving, a Low Temperature Oxide (LTO) layer 245 and a borophosphosilicate glass (BPSG) layer 250 are deposited. Thereafter, a BPSG flow process is performed.

In fig. 4L, a contact first mask (not shown) is applied and an etching process is performed through the borophosphosilicate glass layer 250 and the low temperature oxide layer 245 and then extends through the body region 235 into the epitaxial layer 210 to open the source contact trench 255. Source contact trenches 255 open on the mesa contact regions between the trenched gates 230. The contact mask (not shown) is then removed. An angle P + implant is performed to form a breakdown prevention region and an ohmic contact region 260 along the sidewalls of the source contact trench 255. In fig. 4M, a second mask (not shown) is used to open gate contact openings on some of the trenched gate runners 230G and to open source contact openings on some of the trenched source connecting electrodes 220S. In fig. 4N, after removing the second mask, a contact metal layer 265, such as a titanium (Ti) or titanium silicide (TiSi2) layer, is deposited into the contact trenches 255 and on top of the gate oxide layer. Contact metal layer 265 is a low barrier height metal that partially covers the bottom portion of source contact trench 255, providing the function as a schottky barrier diode. Therefore, high barrier height metals like platinum (Pt) are not required. The schottky barrier near the bottom of the source contact trench 255 provides the advantage of bypassing the body diode. After the titanium or titanium silicide layer 265 is deposited, a titanium nitride (TiN) selective layer may be used to protect the titanium or titanium silicide from oxidation, and then a contact metal layer may be deposited over and etched into the source metal 270 and gate metal 280 using a metal mask (not shown). A silicon nitride passivation layer 290 is then deposited over the device and a passivation layer mask (not shown) is applied to pattern the silicon nitride passivation layer 290 to cover the gate metal 280 and the gap (gap) separating the gate metal 280 and the source metal 270, wherein the source metal 270 is exposed for external connection to a particular voltage, such as a ground voltage.

Fig. 5A discloses a MOSFET device having a termination area (termination area) structure as a device operable at higher voltage levels. For a high voltage operation, the formation of the termination region requires well controlled trench layout, which is filled with source polysilicon and an oxide layer. Fig. 5A shows another embodiment of the method, wherein a deep P-doped region 199 is implanted and initially diffused to form a termination in the form of a guard ring (guard ring) or junction-termination extension (junction-termination extension). A guard ring or junction-terminal extension with a P-doped region 199 surrounds the gate 150, which is in electrical contact with the gate metal 190-G.

In fig. 5B, another trenched gate structure is disclosed, formed by a more complex process, having a tapered oxide structure in the bottom isolation electrode 130' of an isolated gate trench (SGT) deposited below the trenched gate 150. A first oxidation process is performed to a desired thickness, followed by polysilicon deposition and polysilicon etch to a desired depth, and wet etching the oxide layer at the trench sidewalls to a thinner oxide layer thickness. Thereafter, a second polysilicon deposition and etch back (etch back) is performed to a desired depth. The above process is repeated several times to provide a tapered polysilicon SGT structure 130' as shown in fig. 5B. In the penultimate polysilicon etch step, a mask is applied such that polysilicon with a flush surface remains at the center of the source contact. Thereafter, the procedure is the same as described above. Another way to form such a graded oxide layer on the gate sidewalls is to create a grade on the implant damage (implanted Damage) from a neutral gas such as oxygen. Multiple implants of the sidewall at different angles provide a gradient in implant destruction. The vertical implant has the greatest dose for maximum destruction. As the angle increases, the dose is reduced to reduce damage. Then, a single etch oxidation step is performed to produce a tapered oxidation profile along the sidewalls. The benefit of having such a tapered oxide thickness allows for the use of a better epitaxial doping profile that is easier to control to achieve the same Rds performance.

Fig. 6A and 6B respectively disclose cross-sectional schematic views of two different DMOS modules. DMOS assemblies 100 'and 100 "are similar to those shown in fig. 3A-3D, except that there is no isolated gate trench (SGT) structure in DMOS assemblies 100' and 100". Instead of the split-gate (split-gate) structure with bottom isolated electrode as shown in fig. 3A-3D, DMOS assembly 100 'has a different gate-drain isolation region 132' that underlies the trenched gate 150, forming, for example, a body-doped region. After the gate trench etch, the gate-drain isolation region 132' may be formed by a high energy implantation process accompanied by a high temperature activation. As shown in fig. 6B, the DMOS device 100 "has a gate-drain isolation structure that includes a thick oxide layer 120 ' deposited on the bottom portion of the trench gate 150, and a P-doped region 132", the P-doped region 132 "surrounding the bottom and lower portions of the sidewall of the thick oxide layer 120 ', wherein the thick oxide layer 120 ' fills the bottom portion of the trench under the trench gate 150. The P-type doped region 132 "may be formed in a similar manner as the P-type doped region 132' shown in fig. 6A, with the gate trench being extended into the P-type doped region 132" using a second gate trench etching process. The thick oxide layer 120' may be formed by a Chemical Vapor Deposition (CVD) process. A low barrier height metal layer 198 of titanium (Ti) or titanium silicide (TiSi2) covers the source contact trench 188 providing the effect of integrating as a schottky barrier diode into each cell to improve device performance.

Fig. 7A-7C disclose a specific embodiment of the present invention and its equivalent circuit with the bottom isolation electrode 130 connected to voltage, as in an isolated lower voltage gate pad 190-M of fig. 7C. When the lower voltage electrode 130 in the deep trench 109 is connected to an isolated dc potential instead of the source potential, the leakage current can be adjusted in a better controlled manner. The different structure may also allow the lower electrode 130 to be implemented as a floating electrode without having to be connected to a particular electrode structure. Lower voltage gate pad 190-M may be formed in a designated area and gate pad 190-G may also be formed in the designated area. Instead of the macro-cells formed as shown in fig. 3A and 3B, in which a trench source connection electrode is formed in each macro-cell, the trench source connection electrode 140 in fig. 7C is formed only in a designated region under the lower-voltage gate pad 190-M, thereby electrically connecting the lower-voltage gate 130 with the lower-voltage gate pad 190-M.

The above-mentioned embodiments are merely illustrative of the technical ideas and features of the present invention, and the purpose thereof is to enable those skilled in the art to understand the contents of the present invention and to implement the same, but not to limit the scope of the present invention, i.e., all equivalent changes or modifications made in the spirit of the present invention should be covered by the scope of the present invention.

Claims (58)

1. A semiconductor power device comprising a plurality of power transistor cells surrounded by a plurality of trenches formed in a semiconductor substrate, wherein:

at least one of the cells forming an active cell having an active region adjacent to a trenched gate filled with gate material and electrically connected to a gate pad and surrounding the active cell, the trenched gate further having a bottom isolation electrode filled with a low barrier height metal layer disposed below and insulated from the trenched gate;

at least one of said cells constituting a connection cell surrounded by said trench, said trench portion having the function of a connection trench filled with a low barrier height metal layer to serve as a connection electrode for electrically connecting the bottom isolation electrode to a metal disposed directly on top of said connection trench; and

at least one active cell further includes a trench source contact opening between adjacent trenches, the trench source contact passing through a source region into a body region to electrically connect the source region with source metal disposed on top of an insulating layer, the trench bottom surface of the trench source contact being covered by a low barrier height metal layer, having the role of an integrated schottky barrier diode in the active cell.

2. The semiconductor power device of claim 1 wherein said low barrier height metal layer comprises a low barrier height material, said low barrier height metal layer overlying a trench bottom surface of said source contact trench.

3. The semiconductor power device of claim 1 wherein said low barrier height metal layer comprises a titanium/titanium nitride or titanium silicide/titanium nitride material, said low barrier height metal layer overlying a trench bottom surface of said source contact trench.

4. The semiconductor power device of claim 1 further comprising a breakdown prevention region doped with a body dopant, said breakdown prevention region located below said source region and along trench walls of said source contact trench.

5. The semiconductor power device of claim 1, further comprising an insulating protection layer on the semiconductor power device, the insulating protection layer having openings above the connecting trenches for electrically connecting to metal disposed directly on top of the connecting trenches.

6. The semiconductor power device of claim 5, further comprising at least one gate pad opening through the insulating protective layer to electrically connect the gate pad to the trenched gate via a trenched gate runner.

7. The semiconductor power device of claim 6, wherein said gate pad opening is disposed directly above said trenched gate runner.

8. The semiconductor power device of claim 6, wherein the trenched gate runner further comprises an isolated gate trench structure at a bottom of the trenched gate runner, the trenched gate runner having a width and depth greater than other isolated gate trenches.

9. The semiconductor power device of claim 1, wherein the trench gate is surrounded by an insulating layer covering an upper portion of a trench sidewall of the trench gate, the insulating layer having a thickness less than an insulating layer located at a lower portion of the trench sidewall for insulating the bottom isolation electrode.

10. The semiconductor power device of claim 1 wherein each of said cells further comprises a body region between said trenches and surrounding said cell, said body region in said active cell surrounding a source region adjacent said trenched gate.

11. The semiconductor power device of claim 1 wherein said bottom isolation electrode has an oxide layer thereon, said oxide layer insulating said bottom isolation electrode from said trenched gate, said oxide layer being disposed in said trench by an aging etch step to a predetermined depth.

12. The semiconductor power device of claim 1 wherein the bottom isolation electrode filled with gate material has a stepped taper toward the trench bottom with a liner layer surrounding said gate material, said liner layer having a corresponding stepped increase in thickness.

13. The semiconductor power device of claim 1 wherein the bottom isolation electrode filled with gate material has a stepped taper toward the bottom of the trench and a liner layer surrounding the gate material, the liner layer having a corresponding gradually increasing thickness.

14. The semiconductor power device of claim 1, further comprising a termination region comprising a deep P-doped region to form a termination in the form of a guard ring or junction-termination extension.

15. The semiconductor power device of claim 14, wherein said deep P-doped region is deeper than said trenched gate runner.

16. The semiconductor power device of claim 1 wherein said bottom isolation electrode is connected to a voltage which acts as an isolation lower voltage gate pad.

17. The semiconductor power device of claim 1, wherein said bottom isolation electrode is connected to a source.

18. The semiconductor power device of claim 1, wherein said bottom isolation electrode corresponds to a floating electrode.

19. The semiconductor power device of claim 1 wherein said trenched connecting electrode is located in a designated area on said semiconductor power device for connecting said trenched connecting electrode to an isolated contact pad proximate said designated area.

20. A semiconductor power device comprising a plurality of power transistor cells surrounded by a continuously extending trench, said trench opening in a semiconductor substrate, wherein:

at least one of the cells forming an active cell having a source region adjacent a trenched gate, the trenched gate being located in the extended trench and the trenched gate surrounding the cell, the active cell being electrically connected to a gate pad, the trenched gate further comprising a bottom isolated gate filled with a gate material located below and insulated from the trenched gate, the trenched gate filled with the gate material having a tapered shape towards the bottom of the trench and having a liner surrounding the gate material, the liner having a corresponding gradually increasing thickness; and

at least one active cell includes a trench source contact opened between trenches through a source region into a body region to electrically connect the source region with a source metal on an insulating layer, the trench source contact having a trench bottom surface covered with a low barrier height metal layer corresponding to the role of an integrated schottky barrier diode in the active cell.

21. The semiconductor power device of claim 20 wherein at least one of said cells forms a connection cell surrounded by a trench and having a portion corresponding to the connection trench filled with said gate material, thereby electrically connecting said bottom isolation electrode to a metal located above said connection trench.

22. The semiconductor power device of claim 20 wherein an insulating layer is disposed over said bottom isolation electrode, insulating said bottom isolation electrode from said trenched gate, and said insulating layer is located in said trench at a predetermined depth controlled by an etch time step.

23. The semiconductor power device of claim 20 wherein the bottom isolation electrode is filled with gate material having a stepped taper shape toward the bottom of the trench and a liner layer surrounding the gate material, the liner having a corresponding stepped increase in thickness.

24. The semiconductor power device of claim 20 wherein said power transistor cells further comprise trench mosfet cells.

25. The semiconductor power device of claim 20 wherein a trenched source contact is located in a designated area on the semiconductor power device for connecting the trenched source contact to an isolation contact pad proximate the designated area.

26. A semiconductor power assembly comprising a plurality of power transistor cells surrounded by a continuously extending trench, said trench being disposed in a semiconductor substrate, wherein:

at least one of the cells constitutes an active cell having a source region adjacent to a trenched gate, the trenched gate being located in an extended trench, the trenched gate surrounding the cell, the active cell being electrically connected to a gate pad;

a gate-drain isolation region formed as a body doped region located under the trench gate; and

at least one of the active cells includes a trench source contact in a middle portion of the active cell, the trench source contact passing through a source region and extending into a body region of the active cell to electrically connect the source region with a source metal over an insulating layer, a trench bottom surface of the trench source contact further covered with a low barrier height metal layer corresponding to a role of an integrated schottky barrier diode in the active cell.

27. The semiconductor power device of claim 26 wherein said low barrier height metal layer comprises a low barrier height material, said low barrier height metal layer overlying a trench bottom surface of said source contact trench.

28. The semiconductor power device of claim 26 wherein said low barrier height metal layer comprises a titanium/titanium nitride or titanium silicide/titanium nitride material, said low barrier height metal layer overlying said trench bottom surface of said source contact trench.

29. The semiconductor power device of claim 26 further comprising a breakdown preventing region doped with a body dopant located below the source region and along trench walls of the source contact trench.

30. The semiconductor power device of claim 26 wherein said power transistor cells further comprise trench mosfet cells.

31. A semiconductor power assembly comprising a plurality of power transistor cells surrounded by a continuously extending trench, said trench being disposed in a semiconductor substrate, wherein:

at least one of the cells forming an active cell having a source region adjacent a trenched gate, the trenched gate being in the extended trench and the trenched gate surrounding the cell, the active cell being electrically connected to a gate pad;

a thick oxide layer disposed on the bottom portion of the trench gate, a body doped region surrounding the bottom and a lower portion of the sidewall of the thick oxide layer, the thick oxide layer filling the bottom portion of the trench under the trench gate; and

at least one active cell includes a trench source contact in a middle portion of the active cell, the trench source contact passing through a source region and extending into a body region of the active cell to electrically connect the source region with a source metal over an insulating layer, a trench bottom surface of the trench source contact further covered with a low barrier height metal layer, corresponding to a role of an integrated schottky barrier diode in the active cell.

32. The semiconductor power device of claim 31 wherein said low barrier height metal layer comprises a low barrier height material, said low barrier height metal layer overlying a trench bottom surface of said source contact trench.

33. The semiconductor power device of claim 31 wherein said low barrier height metal layer comprises a titanium/titanium nitride or titanium silicide/titanium nitride material, said low barrier height metal layer overlying a trench bottom surface of said source contact trench.

34. The semiconductor power device of claim 31 further comprising a breakdown prevention region doped with a body dopant located below the source region and along trench walls of the source contact trench.

35. The semiconductor power device of claim 31, wherein said power transistor cell further comprises a trench Metal Oxide Semiconductor Field Effect Transistor (MOSFET) cell.

36. The semiconductor power device of claim 31, wherein said semiconductor power device has a reduced gate-drain capacitance Cgd, which depends on the thickness of the oxide layer under the trenched gate.

37. A method of manufacturing a semiconductor power module, comprising the steps of:

opening a trench in a substrate so as to surround a plurality of power transistor cells, the trench being filled with a gate material;

applying a time-sensitive etch to etch back the gate material over the selected portion of the trench, and then covering the bottom of the gate material in the selected portion of the trench with an isolation layer to form a bottom isolation electrode while maintaining direct electrical connection between the gate material in the remaining portion of the trench and the bottom of the isolation electrode;

filling selected portions of the trench with the gate material, thereby forming a trenched gate; and

forming an insulating layer to cover the upper surface of the semiconductor power device, opening a plurality of source contact trenches extending to the body region between the trench gates, and depositing a conductive material on the bottom surface of the source contact trenches to act as an integrated schottky barrier diode in the semiconductor power device.

38. The method of fabricating a semiconductor power device of claim 37, further comprising controlling the time-dependent etch to remove gate material from an upper half of the selected portion of the trench to control a depth of the trenched gate of the semiconductor power device.

39. A semiconductor power assembly, comprising:

a plurality of insulated trench gates surrounded by source regions, the source regions doped with a dopant of a first conductivity type and located on an upper surface of the body region, the body region doped with a dopant of a second conductivity type, which is opposite to the first conductivity type; and

a trench source contact is opened between the trench gates, the trench source contact penetrates the source region into the body region to electrically connect the source region with the source metal over an insulating layer, and the trench bottom surface of the trench source contact is further covered with a low barrier height metal to serve as an integrated Schottky barrier diode in the active cell.

40. The semiconductor power device of claim 39 wherein said low barrier height metal comprises a titanium/titanium nitride or titanium silicide/titanium nitride material.

41. The semiconductor power device of claim 39, further comprising an isolation structure located under the trenched gate.

42. The semiconductor power device of claim 41, wherein said isolation structure is a bottom isolation electrode underlying and insulated from said trenched gate.

43. The semiconductor power device of claim 42, wherein said bottom isolation electrode is connected to a source voltage.

44. The semiconductor power device of claim 42, wherein said bottom isolation electrode is connected to a bottom gate pad.

45. The semiconductor power device of claim 42 wherein said bottom isolated electrode is floating.

46. The semiconductor power device of claim 41, wherein said isolation structure comprises a body doped region at the bottom of said trenched gate and insulated from said trenched gate.

47. The semiconductor power device of claim 41, wherein the isolation structure comprises a thick oxide layer disposed at a bottom portion below the trench gate, and a body doped region surrounding a bottom portion and a lower portion of the sidewall, and the sidewall surrounds the thick oxide layer, filling the bottom portion in the trench below the trench gate.

48. The semiconductor power device of claim 39 wherein said isolation structure extends to a depth that is deeper than said trenched bottom surface of said trenched source contact.

49. A semiconductor power assembly, comprising:

a plurality of insulated trench gates surrounded by source regions, the source regions doped with a dopant of a first conductivity type and located on an upper surface of a body region doped with a dopant of a second conductivity type, opposite to the first conductivity type;

a trench source contact opened between the trench gates, the trench source contact passing through the source region into the body region to electrically connect the source region with the source metal over an insulating layer, the trench bottom surface of the trench source contact further covered with a low barrier height metal layer to serve as an integrated schottky barrier diode in the active cell; and

and the isolation structure is positioned at the bottom of the trench type grid and is insulated from the trench type grid.

50. The semiconductor power device of claim 49, wherein said conductive material is a low barrier height metal.

51. The semiconductor power device of claim 49 wherein said low barrier height metal comprises Ti/TiN or TiSix/TiN.

52. The semiconductor power device of claim 49 wherein said isolation structure extends to a depth that is deeper than said trenched bottom surface of said trenched source contact.

53. The semiconductor power device of claim 49 wherein said isolation electrode is a bottom isolation electrode underlying and insulated from said trenched gate.

54. The semiconductor power device of claim 53, wherein said bottom isolation electrode is connected to a source voltage.

55. The semiconductor power device of claim 53, wherein said bottom isolation electrode is connected to a bottom gate pad.

56. The semiconductor power device of claim 53 wherein said bottom isolated electrode is floating.

57. The semiconductor power device of claim 49, wherein said isolation structure comprises a body doped region at the bottom of said trenched gate and insulated from said trenched gate.

58. The semiconductor power device of claim 49, wherein the isolation structure comprises a thick oxide layer disposed at a bottom portion under the trench gate, and a body doped region surrounding a bottom and a lower portion of the sidewall, and the sidewall surrounds the thick oxide layer, which fills the bottom portion in the trench under the trench gate.