HK1123657B - Method and system for data processing - Google Patents

Description

Data processing method and system

Technical Field

The present invention relates to digital media processing, and more particularly, to a method and system for embedding watermarks in a multimedia system-on-chip (system-on-chip).

Background

Watermarking is a technique used to protect data media from unauthorized use or illegal copying, for example, using copyrighted material. Watermarks for digital media can be divided into two categories: visible or invisible. A visible watermark is typically added to a digital image to indicate its ownership and to deter unauthorized use of the image. For example, the watermark may include the owner's identity and/or copyright symbol and date. This type of watermark can be considered a spatial watermark, in which data is spatially embedded in an image, and the watermark signal is different from the original image data. Due to the ability to filter, cull, and/or prune data, the spatial domain watermark may not be robust against attacks.

The degree of alteration of the image by the invisible watermark is not perceptible. This can be achieved by making small changes to a minimum number of significant bits of the original data, and the unknown watermark can be treated as a secret to the end-user.

Watermarking can embed data in the frequency domain, making it more robust against attacks. This technique is similar to spread spectrum coding in communications. Wherein the watermark signal may be modulated with pseudo-noise to spread the data to be embedded in most frequencies before adding it to the original data. Factors such as low signal amplitude, large bandwidth of the original data (e.g., picture or video), and lack of watermark messages may indicate spread spectrum encoding as a logical choice, since the watermark is not visible.

In the protection of multimedia data, it is also important to detect whether a watermark is present, in addition to embedding the watermark in the digital multimedia data. The multimedia player may include watermark sensing electronics for avoiding the use of unauthorized or pirated media.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some features of the present invention as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

A method and/or system for embedding a watermark in a multimedia-on-chip (system-on-chip), substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

According to one aspect of the invention, there is provided a method of processing data, comprising:

in a system-on-chip, decrypting the encrypted and marked watermark signal using a secure processor integrated in the system-on-chip; and

in the system-on-chip, a watermark is embedded into the multimedia signal using the decrypted watermark data.

Preferably, the encrypted and marked watermark signal comprises: an embedding key, a message to be embedded, and parameters defining the embedding.

Preferably, the embedding key is used for embedding of the watermark.

Preferably, the method further comprises receiving the encrypted and marked watermark signal from an external memory by a host CPU located in the system on chip.

Preferably, the method further comprises receiving the encrypted and marked watermark signal from a secure server.

Preferably, the method comprises verifying a signature of the decrypted watermark signal using a public key in the system on chip.

Preferably, the public key is stored in the system on chip.

Preferably, the verification uses a random number generated by a secure processor located in the system-on-chip.

Preferably, the method further comprises storing the verified watermark signal onto a non-volatile memory in the system on chip.

Preferably, the method further comprises encrypting the verified watermark signal again before causing the verified watermark signal to be stored in a non-volatile memory externally connected to the system on chip.

Preferably, the method further comprises re-marking the re-encrypted watermark signal.

Preferably, the method further comprises retrieving the re-encrypted watermark signal from the external non-volatile memory.

Preferably, the method further comprises decrypting the retrieved encrypted watermark signal again in the system on chip.

Preferably, the method further comprises re-verifying the re-decrypted watermark signal in the system on chip.

According to an aspect of the invention, there is provided a system for signal processing, comprising:

in a system-on-chip, one or more circuits including a secure processor for decrypting an encrypted and marked watermark signal; and

the one or more circuits embed, in the system-on-chip, a watermark into a multimedia signal using the decrypted watermark data.

Preferably, the encrypted and marked watermark signal comprises: an embedding key, a message to be embedded, and parameters defining the embedding.

Preferably, the embedding key is used for embedding of the watermark.

Preferably, the one or more circuits receive the encrypted and marked watermark signal from an external memory through a host CPU located in the system on chip.

Preferably, the one or more circuits receive the encrypted and marked watermark signal from a secure server.

Preferably, the one or more circuits verify a signature of the decrypted watermark signal in the system-on-chip using a public key.

Preferably, the public key is stored in the system on chip.

Preferably, the one or more circuits perform the verification using a random number generated by a secure processor located in the system-on-chip.

Preferably, the one or more circuits store the verified watermark signal onto a non-volatile memory in the system-on-chip.

Preferably, the one or more circuits are configured to encrypt the verified watermark signal again before causing the verified watermark signal to be stored in a non-volatile memory external to the system-on-chip.

Preferably, the one or more circuits re-mark the re-encrypted watermark signal.

Preferably, the one or more circuits retrieve the re-encrypted watermark signal from the external non-volatile memory.

Preferably, the one or more circuits are operable to decrypt the retrieved encrypted watermark signal again in the system on chip.

Preferably, the one or more circuits re-verify the re-decrypted watermark signal in the system-on-chip.

Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully described with reference to the following description and drawings.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a schematic diagram of an exemplary application of system-on-chip digital watermarking according to an embodiment of the present invention;

FIG. 2 is a block diagram of an exemplary system on a watermark chip, according to an embodiment of the invention;

FIG. 3 is a block diagram of an exemplary watermarking system using a secure processor, according to an embodiment of the present invention;

FIG. 4A is a block diagram of an exemplary external flash watermark and algorithm information storage, according to an embodiment of the present invention;

FIG. 4B is a block diagram of an exemplary random number store according to an embodiment of the present invention;

FIG. 5 is a block diagram of an exemplary server-side encrypted message generation in accordance with an embodiment of the present invention;

fig. 6 is a flow diagram of exemplary steps occurring at the server side in a watermark generation process, according to an embodiment of the invention;

FIG. 7 is a flowchart of exemplary steps occurring on the system-on-chip side in a watermark generation process, according to an embodiment of the present invention;

fig. 8 is a flow chart of exemplary steps occurring on the system-on-chip side in a watermark embedding process according to an embodiment of the present invention.

Detailed Description

Aspects of the present invention relate to a method and system for embedding a watermark in a multimedia system-on-a-chip. Typical steps of the present invention include: the encrypted and marked watermark signal is decrypted using a secure processor integrated in the system-on-chip and the watermark is embedded in the multimedia signal using the decrypted watermark signal. The watermark signal may comprise an embedding key, a message to be embedded and embedding parameters. The encrypted and marked watermark signal may be received from an external memory by a host CPU in the system-on-chip or the secure server. The decrypted watermark signal may be verified using the signature, the public key and the locally generated random number word. The verified watermark signal may be stored on a non-volatile memory in the system-on-chip, or may be re-encrypted and re-marked before being stored on a non-volatile memory external to the system-on-chip. The watermark signal may be retrieved from an external non-volatile memory and decrypted again and verified again in the system-on-chip.

Fig. 1 is a schematic diagram of a typical application of system-on-chip digital watermarking according to an embodiment of the present invention. Referring to fig. 1, a watermarking application 100 is shown comprising a cable input 101, a television set 109 and a set-top box 103, the set-top box 103 comprising a watermarking system-on-a-chip (SoC)105 and a memory 107. For example, cable input 101 may transmit multimedia signals including: audio, video, data, and/or voice. The set top box 103 may comprise suitable logic, circuitry and/or code that may be enabled to receive a multimedia input signal and generate an output signal that may be displayed on the television 109. The memory 107 may comprise suitable logic, circuitry, and/or code that may enable storage of multimedia data received from the cable input 101 that may have been processed by the watermarking SoC 105. Although a cable input 101 is shown, the present invention is not so limited. Thus, other media inputs (e.g., a satellite feed) may also be provided as inputs to set top box 103.

The watermark SoC 105 may comprise suitable logic, circuitry, and/or code that may be enabled to receive multimedia data (e.g., from the cable input 101) and to generate and embed a digital watermark in the data. For example, the digital watermark may include encrypted data associated with the multimedia data source and/or recording privileges associated with the set-top box 103. Encrypted messages in the data can only be detected by suitable watermark detection circuitry.

In operation, multimedia data may be transmitted to the set top box 103 via the cable input 101. For example, in instances where it is desirable to protect multimedia data from illicit copying and use, the watermark SoC 105 may generate a watermark using the copyright material and embed the watermark in the multimedia data prior to storing the multimedia data in memory 107 and/or transmitting to the television 109.

The embedded watermark may be viewed as a function, which includes: raw media (content) dataEmbedded keyParameter set for controlling embedded program/algorithmAnd messages to be embedded in video and/or audioCan transmit message dataAs a sequence of bits. Parameter setA so-called watermark embedding factor between other parameters may be included, i.e. controlling the amount of degradation (degradation) of the original media data that will be affected by the watermark. The output of the watermark embedding function comprises watermark dataThus, the watermark embedding function may be in the following format:

to ensure secure execution of watermark embedding, in watermark SoC 105Andwill be protected.

Fig. 2 is a block diagram of an exemplary embodiment of a system on a watermark chip according to an embodiment of the present invention. Referring to fig. 2, a watermark SoC execution 200 is shown, comprising a watermark SoC 201, a DRAM211, and a flash memory 219. The watermark SoC 201 may include a Watermark Embedding Function (WEFM)203, a secure processor 213, a memory bus 215, and a host CPU 217. WEFM 203 may include watermark embedding module 205, message generation module 207, and watermark generation module 209. The host CPU 217 may comprise suitable logic, circuitry, and/or code that may enable capturing information required by the security processor 213 during the watermarking process. For example, the host CPU may include a MIPS processor and may be connected to DRAM211 via memory bus 215 and may also be connected to flash memory 219. The memory bus 215 may comprise suitable logic, circuitry, and/or code that may enable transfer of data between the host CPU 217, the DRAM211, and other components of the watermark SoC 201 that may require access to data stored in the DRAM 211.

The DRAM211 may comprise suitable logic, circuitry, and/or code that may enable storage of digital data for access by the main CPU 217 via the memory bus 215. For example, DRAM211 may be used to store processed data generated by main CPU 217 and/or secure processor 213. The DRAM211 may also be used to store information (e.g., configuration information) to be used to control the operation of at least one module in the watermark SoC 201. The flash memory may comprise suitable logic, circuitry, and/or code that may enable storage of digital data that may be accessed by the main CPU 217. The data stored in DRAM211 or flash 219 may include encryptionThe encrypted message may comprise a messageAnd parameters(see fig. 1) and may be used by the security processor 213 in the watermark process.

The secure processor 213 may comprise suitable logic, circuitry, and/or code that may enable generation of output data by the WEFM 203 to construct or embed a watermark, such as the watermark 111 shown in fig. 1. According to an aspect of the present invention, the secure processor 213 that is on-chip integrated on the watermark SoC 201 is not vulnerable to attacks that may be made on an external processor or host CPU (e.g., host CPU 217) through hardware operations. This substantially improves the safety performance.

The message generation module 207 may comprise suitable logic, circuitry and/or code that may enable generation of a message for watermark generationThe encrypted message may be received from the input signal or retrieved by the host CPU 217 from the DRAM211 or the flash memory 219. The watermark generation module 209 may comprise suitable logic, circuitry, and/or code that may enable generation of a watermark M based on input received from the security processor 213 and the message generation module 207_W。

In operation, the main CPU 217 may retrieve encrypted and tagged messages, which may be stored on DRAM211 or in flash memory 219, and transfer the encrypted tagged messages into the secure processor 213. The security processor 213 decrypts the message M 'and verifies the signature before extracting the message M', which will be sent to the message generation module 207. The secure processor 213 may generate the watermark signal M in the generation_WSecret key used by the watermark generation module 209 in the processAnd parametersGroup ofSecret keyCan be used to implement watermark generation process, and parameter setMay be used to determine algorithms that may be used in the watermark generation module 209. The message generation module 209 may generate a message from the received message M' generated by the security processor 213Or from raw media dataGenerating a message from the extracted message dataAnd will send the messageTo the watermark generation module 209. The watermark generation module 209 may use the input signal M'),Anda watermark signal is generated. Can watermark signal M_WSum parameter setTo the watermark embedding module 205. The watermark embedding module 205 may embed the watermark signal M_WApplication to sets of usage parametersOf the original media dataWhich can generate an output signalThe signalWith watermark M embedded in the data_W。

The secure processor 213 may securely generate and transmit the keyMessage M' andwatermark signal M_WSum parameter setSuch a set of CPUs 217 or any other processor may be used to directly access these parameters at any time. The secure generation and transmission of these parameters in the watermark generation process may be a requirement of the watermark robustness rules.

Fig. 3 is a block diagram of an exemplary watermarking system using a secure processor, according to an embodiment of the present invention. Referring to fig. 3, there is shown a watermarking system 300 comprising a media processing unit 301 and a security processor 307. Also shown are an encrypted input signal 325, a key 323 unique to each chip, a public key 333, and a signature 335. The encrypted input signal 325 may include a keyAnd a message M' to be decrypted (see fig. 2), and a set of parametersThe secure processor may include registers 309, on-chip non-volatile memory (NVM)313, Random Number Generation (RNG) engine 315, NVM1319 and NVM2321, decryption engine 327, gate 329, and signature verification module 331. The media processing unit may comprise a watermark generation and embedding module 311.

The on-chip NVM313 may comprise suitable logic, circuitry, and/or code that may enable storing data. The stored data may include a chip ID317, which may be used to identify the individual chip that may be used in the watermarking process, so that the watermark data generated by the chip may be used to identify the source of the data. The chip ID317 may also be stored in the NVM1319 so as to be included in the watermark data generated and embedded by the media processing unit 301. The data stored in the on-chip NVM313 may also include a key 323 unique to each chip, which may be used by the decryption engine 327 to generate an appropriate signature 335.

The RNG engine 315 may comprise suitable logic, circuitry, and/or code that may enable generation of a random number. The random number can be used to provide more security because the unique combination of the random number and the chip ID317 can only be used once. The registers 309 may comprise suitable logic, circuitry, and/or code that may enable storage of data. The stored data may include the chip ID317 and a random number generated by the RNG engine 315. The on-chip NVM313, NVM1319, and NVM2321 may comprise suitable logic, circuitry, and/or code that may enable storage of data. The data stored on the NVM1319 may include watermark keys and algorithm information that may be used by the media processing unit 301. The data stored on the NVM 1321 may include a random number generated by the RNG engine 315, which may be accessed by the signature verification module 331.

The media processing unit 301 may access data stored on the NVM1319 to determine the watermark generation and embedding module 311 parameters that are to be used for processing and data to be embedded. These parameters may include, for example, algorithms, watermark keys, watermarks M_WAnd a chip ID. The watermark generation and embedding module 311 may apply the watermark M_WEmbedding into original media data303 to generate an output signal305。

The secure processor 307 may securely generate and transmit keysMessage M' andwatermark signal M_WSum parameter setSo that the main CPU or any other processor may not be able to directly access these parameters at any time. The secure generation and transmission of parameters included in the watermarking process may be a requirement as the watermark robustness rules.

Fig. 4A is a block diagram of an exemplary external flash watermark and algorithm information storage, according to an embodiment of the invention. Referring to fig. 4A, an external storage system 400 is shown, which includes an authentication module 401, a decryption module 403, a flash memory 405, a marking module 407, and an encryption module 409. Also shown are chip key 411, authentication key 413, and signing key 415. In examples where no non-volatile memory is available, the external flash memory system 400 may be used in place of the NVM1319 shown in fig. 3 and may be used to store watermark key and algorithm information needed by the watermark generation and embedding module 311 (see fig. 3).

The authentication module 401, the decryption module 403, the marking module 407, and the encryption module 409 may be provided in the secure processor 307 (see fig. 3), and the flash memory 405 may be externally connected to the secure processor 307 but provided in the SoC (see fig. 2). Flash memory 405 may be substantially similar to flash memory 219 shown in fig. 2.

The marking module 407 may comprise suitable logic, circuitry, and/or code that may be enabled to receive input from the gate 329 (see fig. 3), which may comprise decrypted data generated by the decryption engine 327. The tagging module 407 may also receive as input a tagging key 415, which tagging key 415 may be included in or tagged with data to be transmitted to the encryption module 409 to indicate that the data request from the flash memory 405 is from a secure source, i.e., the secure processor 307 (see fig. 3). The encryption module 409 may comprise suitable logic, circuitry, and/or code that may enable encryption of data to be stored in the flash memory 405. The encryption module 409 may receive as inputs the signal generated by the tagging module 407 and a chip key 411, which may be substantially similar to the unique key 323 for each chip shown in fig. 3.

The decryption module 403 may comprise suitable logic, circuitry, and/or code that may enable decryption of encrypted data stored on the flash memory 405 and generate an output signal that may be communicated to the verification module 401. Decryption module 403 may receive as input encrypted data stored in flash memory 405 and chip key 411. The authentication module 401 may comprise suitable logic, circuitry, and/or code that may enable comparing an input received from the decryption module 403 with the authentication key 413 to determine whether data may be transferred to the media processing unit 301 (see fig. 3).

In operation, in instances where non-volatile memory in the secure processor 307 (see FIG. 3) is not available, the external flash memory system 400 may be used to securely store encrypted data in the external flash memory 405. The input signal generated by gate 329 (see fig. 3) may be received by a marking module 407. The marker key 415 may be embedded in the data received from the input signal. The encryption module 409 may insert the chip key 411 and encrypt data for storage on the external flash memory 405. In this manner, the data will be stored in the off-board memory and still maintain the security of the secure processor 307 (see FIG. 3).

The decryption module may decrypt encrypted data stored in the flash memory 405 if the appropriate chip key 411 is also received as input. The decrypted data may then be communicated to the verification module 401. In the example where the decrypted data is authenticated by the authentication key 413, the data may be transmitted to the media processing unit 304 (see fig. 3).

Fig. 4B is an exemplary block diagram of random number storage according to an embodiment of the present invention. Referring to FIG. 4B, an external random number flash memory system 420 is shown that includes a signing module 421, a flash memory 423, an authentication module 425, a signing key 427, and an authentication key 429. The marking module 421, the verification module 425, the marking key 427, and the verification key 429 may be inscribed within the secure processor 307 (see fig. 3), and the flash memory 423 may be circumscribed to the secure processor 307, but would be disposed in the watermark SoC 201 (see fig. 2). The tagging module 421, authentication module 425, flash memory 423, tagging key 427, and authentication key 429 may be substantially similar to the tagging module 407, authentication module 425, flash memory 405, tagging key 415, and authentication key 413 shown in fig. 4A. Flash memory 423 may be used to store random numbers generated by RNG engine 315 (see FIG. 3). The flash memory 423 may also store the chip ID to the register 309 (see fig. 3).

In operation, signals generated by the RNG engine 315 may be received by the tagging module 421. The signing module may receive as input a signing key 427. This data includes random numbers generated by RNG engine 315 and signatures derived from signing key 427 and may be stored in flash memory 423. Data stored in flash memory 423 may be transferred to authentication module 425. If the data transmitted from the verification module is verified by the verification key 429, the data may be transmitted to the signature verification module 331 (see fig. 3).

Fig. 5 is a block diagram of an exemplary server-side encrypted message generation in accordance with an embodiment of the present invention. Referring to fig. 5, there is shown an encrypted message generator 500 comprising a secure server 503 and a register 501. The secure server 503 may include a secure database 505, a watermarking information module 507, an encryption and signing module 509, a public key 511, and an encryption key 513. The register 501 may be substantially similar to the register 309 (see FIG. 3) and may be used to store the chip ID317 (see FIG. 3) and the random number generated by the RNG engine 315 (see FIG. 3).

The secure database 505 may comprise suitable logic, circuitry, and/or code that may enable storing data but may not enableAllowing readable access from outside the secure server 503. The data stored in the secure database 505 may include a plurality of encryption keys (e.g., encryption key 513) defined for chip IDs corresponding to a plurality of watermarks SoC (e.g., watermark SoC 201 shown in fig. 2). Watermark information module 507 may include an embedded keyMessage M' and parameter set(see FIG. 1). Message M' may also include chip ID317, chip ID317 being stored in register 501 and read by secure server 503. The encryption and tagging module 509 may comprise suitable logic, circuitry, and/or code that may enable encrypting data and providing a signature for the encrypted data. The encryption and marking module 509 may encrypt the encryption key 513, the personal key 511, and the watermark information (including the embedding key)Message M' and parameter set) Receives as input and generates output (including encrypted and signed watermark key)Message M' and parameter set)。

In operation, the chip ID (such as chip ID317 shown in FIG. 3) may be used to retrieve the encryption key 513 from the secure database 505. The encryption and marking module 509 may encrypt and mark the watermark information from the watermark information module 507, including the embedding key, using the encryption key 513 and the personal key 511Message M' and parameter setThe output generated by the encryption and marking module 509 may be transmitted to a remote host over a network or stored externally for use by a water-marking SoC, such as the watermarking SoC 201 shown in fig. 2.

Fig. 6 is a flow diagram of exemplary steps occurring at the server side in a watermark generation process, according to an embodiment of the present invention. Referring to FIG. 6, in step 603 following the start step 601, the security server 503 may retrieve the random number and chip ID317 generated by the RNG engine 315. In step 605, the chip ID317 may be used to retrieve the corresponding encryption key 513. In step 607, watermark information may be generated, which may include chip ID 317. In step 609, the random number from RNG engine 315 may be marked with the personal key 511 with the watermark information, which is then encrypted by encryption and marking module 509 using encryption key 513. In step 611, the output of the encryption and tagging module 509 to the SoC 201 includes the encrypted and tagged embedded keyMessage M' and parameter set

Fig. 7 is a flow diagram of exemplary steps occurring on the system-on-chip side in a watermark generation process, according to an embodiment of the invention. Referring to FIG. 7, in step 703, which follows the start step 701, the chip ID317 may be read from the on-chip NVM313 and stored in the register 309. In step 705, the random number generated by the RNG engine 315 may be stored in a register 309. In step 707, in the example of an on-chip writable non-volatile memory (e.g., NVM2321), a random number may be stored in NVM2321, followed by ending step 713. In the case where there is no on-chip writable non-volatile memory, the random number may be marked with a marking key 427 and stored in an external memory (e.g., flash memory 423), followed by ending step 713.

Fig. 8 is a flow chart of exemplary steps occurring on the system-on-chip side in a watermark embedding process according to an embodiment of the present invention. Referring to fig. 8, in step 803 following the start step 801, a decryption engine 327 may encrypt the input signal 325 using a key 323 unique to each chip. In step 805, if there is a writable internal non-volatile memory (e.g., NVM2321), the random number generated by RNG engine 315 may be read from NVM 2321. In step 815, the signature verification module 331 may verify the signature 335 using the public key and the random number generated by the RNG engine 315. If, in step 805, no writable internal non-volatile memory exists, signature verification module 331 may read and use the random number stored in flash memory 423 to verify signature 335 using public key 333. In step 811, if the signature 335 passes verification, the process will proceed to step 815, and if verification fails, the process will stop at step 813. In step 817, the decrypted embedded key may be encryptedMessage M' and parameter setStored to the NVM1319 and transferred to the watermark generation and embedding module 311. In step 819, the watermark generation and embedding module 311 may generate a watermark M_WAnd embed it into the original media data303 to generate an output signal305 and then end step 821 is performed.

In an embodiment of the invention the secure processor 307 integrated in the system-on-chip 201 may decrypt the encrypted and marked watermark signal and use the decrypted watermark signal MW to decrypt the encrypted and marked watermark signalEmbedding a watermark in a multimedia signal, the watermark signal may comprise an embedding key to be embeddedMessage M' and embedded parameter setThe encrypted and marked watermark signal may be received from the external memory 219 by the host CPU 217 located in the system-on-chip 201 and the secure server 503. The decrypted watermark signal may be verified using the signature 335, the public key 333 and a locally generated random number. The verified watermark signal may be stored in the non-volatile memory 319 in the system-on-chip 201 or encrypted and re-marked again before being stored on the non-volatile memory 405 external to the system-on-chip 201. The watermark signal may be retrieved from the external non-volatile memory 405 and encrypted and verified again in the system-on-chip 201.

Yet another embodiment of the present invention may provide a machine-readable storage, having stored thereon, a computer program comprising at least one code section for exchanging information with a network, the at least one code section being executable by a machine for causing the machine to perform the above-described method.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

Embodiments of the present invention may be implemented as a board level product (board level product), such as a single chip, an Application Specific Integrated Circuit (ASIC), or as separate components integrated with other portions of the system on a single chip with varying degrees of integration. The degree of integration of the system depends primarily on speed and cost considerations. Modern processors are so diverse that processors currently found on the market can be employed. Additionally, if the processor is available as an ASIC core or logic module, the processors currently found on the market may be part of an ASIC device with firmware for various functions.

The present invention may also be implemented by a computer program product, comprising all the features enabling the implementation of the methods of the invention, when loaded in a computer system. The computer program in this document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to other languages, codes or symbols; b) reproduced in a different format.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (10)

1. A method of processing data, the method comprising:

in a system-on-chip, decrypting the encrypted and marked watermark signal using a secure processor integrated in the system-on-chip;

in a system-on-chip, verifying a signature of the decrypted watermark signal using a public key or a random number generated by a secure processor,

in the system on chip, the verified watermark signal is re-encrypted and re-marked;

storing the re-marked watermark signal to a nonvolatile memory externally connected to the system on chip;

retrieving the watermark signal from the external non-volatile memory;

in the system-on-chip, decrypting and re-verifying the retrieved watermark signal again; and

in the system-on-chip, a watermark is embedded into the multimedia signal using the decrypted watermark data.

2. The method of claim 1, wherein the encrypted and marked watermark signal comprises: an embedding key, a message to be embedded, and parameters defining the embedding.

3. The method of claim 2, wherein the embedding key is used for embedding of the watermark.

4. The method of claim 1, further comprising receiving the encrypted and marked watermark signal from an external memory by a host CPU located in the system on chip.

5. The method of claim 1, further comprising receiving the encrypted and marked watermark signal from a secure server.

6. A system for signal processing, the system comprising:

in a system-on-chip, one or more circuits including a secure processor for decrypting an encrypted and marked watermark signal; and

the one or more circuits verify a signature of the decrypted watermark signal in the system-on-chip using a public key or a random number generated by a secure processor,

in the system on chip, the verified watermark signal is re-encrypted and re-marked;

storing the re-marked watermark signal to a nonvolatile memory externally connected to the system on chip;

retrieving the watermark signal from the external non-volatile memory;

in the system-on-chip, the retrieved watermark signal is decrypted again and verified again and the watermark is embedded into the multimedia signal using the decrypted watermark data.

7. The system of claim 6, wherein the encrypted and marked watermark signal comprises: an embedding key, a message to be embedded, and parameters defining the embedding.

8. The method of claim 7, wherein the embedding key is used for embedding of the watermark.

9. The system according to claim 6, wherein said one or more circuits receive said encrypted and marked watermark signal from an external memory through a host CPU located in said system on a chip.

10. The system according to claim 6, wherein said one or more circuits receive said encrypted and marked watermark signal from a secure server.