HK1122679B - Pcr correction circuit - Google Patents

Description

Program clock reference correction circuit

Technical Field

The present invention relates to bit rate conversion processing of an MPEG2-TS signal in a digital transmission system, and more particularly to a bit rate conversion processing method for correcting jitter (ジ) of PCR (program clock reference) reference time information generated at the time of buffering_ツタ).

Background

Currently, as a digital transmission system, an MPEG2-TS system (ISO/IEC13818-1) is used, whereby a plurality of encoded images, audio, data information, and the like can be multiplexed in one transport stream (hereinafter referred to as a TS signal) and transmitted.

That is, for example, as shown in fig. 7, a TS packet is composed of a header portion, an adaptation field portion, a payload portion (data information portion), and has a fixed length of 188 bytes. The header is 4 bytes, and includes packet identifier information called a sync byte (0x47h) and a 13-bit pid (packet indication), an adaptation field flag indicating whether or not an adaptation field section is included, and the like. Since the length of the adaptation field section is variable, the adaptation field section is an area including an adaptation field length indicating the byte length, a PCR flag indicating whether or not PCR information described below is included, reference time information synchronized with a system clock (27MHz) owned by the encoder, and the like. The Reference time information is called PCR (Program Clock Reference), and there are 1 PCR for each 1 Program, that is, the Reference time information for synchronizing the system Clock between the encoder that generates the Program and the decoder that reproduces the Program.

The payload section of the TS packet is called PSI (Program specific information) and includes Program information multiplexed in the TS signal and table information indicating the contents of each Program. The structure of the multiplexed Program is described in PAT (Program Association Table, i.e., Program auxiliary Table). The content of each Program is described in a PMT (Program Map Table), and is described in the PID identifier information. Specifically, the PAT describes the correspondence between each program and the PMT, and the PMT describes the PID of the packet constituting the program.

Further, conventionally, in order to provide a PCR correction circuit which can be realized by a relatively easy control method, while reducing the number of components and the circuit scale in comparison with a PLL control method in which a PCR correction circuit is used by externally connecting a VCO oscillator and a smoothing circuit, a correction circuit in which a time difference between a PCR input timing before bit rate conversion and an output PCR timing after bit rate conversion is calculated and a value obtained by adding the time difference and an input PCR value is used as a corrected PCR value to replace the PCR value after bit rate conversion is known from patent document 1 below.

[ patent document 1 ]: japanese patent laid-open publication No. 2005-318029

As described above, since 1 PCR is used as reference time information of 1 program in the TS signal, a system clock (27MHz) synchronized with an encoder is reproduced in a PLL circuit having 1 VCXO (voltage controlled quartz oscillator) and an STC counter for 1 program in general in the conventional PCR correction circuit, and PCR correction is performed based on the STC counter. However, the PLL circuit must be controlled with high accuracy, and therefore, there are problems that the circuit becomes complicated and the scale becomes large.

In addition, when PCR correction of a TS signal in which a plurality of programs are multiplexed is performed, a PLL circuit (VCXO, STC counter) shared by the multiplexed programs is required, and there is a problem that the circuit scale is enormous. In this case, it is necessary to analyze the PSI information to extract PCR information of each program from a TS signal in which a plurality of programs are multiplexed. First, there is a problem that a circuit of this type is complicated and large-sized because a process for detecting a PAT packet, detecting a PMT packet by referring to the content thereof, detecting a packet having a PID identifier including PCR information by referring to the detected PMT packet, and extracting the PCR information from the packet requires the number of multiplexed programs.

Further, according to the above patent document 1, the number of components and the circuit scale are reduced in comparison with the PLL control system in which the PCR correction circuit employs the VCO oscillator and the smoothing circuit connected externally, in addition, in order to obtain a PCR correction circuit which can be realized by a relatively easy control method, although a configuration is known in which a time difference between PCR input timing before bit rate conversion and output PCR timing after bit rate conversion is calculated, and a value obtained by adding the time difference to an input PCR value is used as a corrected PCR value to replace a PCR value after bit rate conversion, the following is not disclosed with respect to a plurality of multiplexed programs, that is, it is possible to provide a PCR correction circuit which can reduce the number of components and the circuit scale without having a PLL circuit (VCXO, STC counter) for PCR correction shared by the number of multiplexed programs and can be realized by a relatively easy control method.

Disclosure of Invention

The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to provide a PCR correction circuit that can reduce the number of components and the circuit scale without having to provide a PLL (phase locked loop) circuit (VCXO, STC counter) for PCR correction that shares the number of multiplexed programs, and can be realized by a relatively easy control method.

According to the present invention, in order to achieve the above object, there is provided a program clock reference correcting circuit for correcting jitter of reference time information of a program clock reference generated when a TS signal in which a plurality of programs are multiplexed is converted into a different bit rate via a memory, the circuit including: a quartz oscillator as a reference clock for reference correction of a program clock; a reference counter unit for program clock reference correction that generates a reference count value for program clock reference correction in synchronization with the reference clock; a reference count value adding unit that adds the reference count value to the TS signal before bit rate conversion; a rate conversion unit that temporarily stores the TS signal to which the reference count value is added in a buffer memory, and converts the TS signal into an output bit rate to output the TS signal; a program clock reference correction count value calculation unit that extracts an input time reference count value when the TS signal to which the reference count value is added is input to the rate conversion unit from the reference count values added to the output TS signal from the rate conversion unit, acquires an output time reference count value when the TS signal is output from the rate conversion unit by the program clock reference correction reference counter unit, and calculates a difference between the input time reference count value and the output time reference count value to obtain a program clock reference correction count value; and a program clock reference replacing unit which detects a program clock reference count value included in the output TS signal from the rate converting unit and replaces the detected program clock reference count value with the calculated program clock reference correction count value as a new program clock reference count value, wherein the reference count value adding unit performs bit width expansion on the TS signal before bit rate conversion and adds the reference count value to the expanded bit region; the rate conversion unit stores the TS packets, to which the reference count value is added, in a buffer memory by performing bit width expansion; the program clock reference correction count value calculation unit obtains the input time reference count value by extracting the reference count value added to an extended bit width region of the TS signal when the TS signal stored in the buffer memory is read from the rate conversion unit; and a program clock reference detection circuit for detecting a program clock reference count value included in the rate-converted TS signal of the program clock reference substitution unit, the program clock reference detection circuit extracting the program clock reference count value from an adaptation field of the following TS packet out of all the TS packets: reference is made to an adaptation field flag within the header information of the TS packet indicating the presence of an adaptation field, and reference is made to an adaptation field length flag within the adaptation field of the TS packet indicating that the adaptation field is of finite length, and reference is made to a program clock reference flag within the adaptation field of the TS packet indicating that there is a description of a program clock reference count value within the adaptation field.

According to the present invention, it is possible to configure a PCR correction circuit without having a PLL circuit (VCXO, STC counter) for PCR correction for multiplexing the number of programs, reduce the number of components and the circuit scale thereof, provide a PCR correction circuit which can be realized by a relatively easy control method, and achieve excellent effects.

Drawings

Fig. 1 is a block diagram showing the structure of a PCR correction circuit according to an embodiment of the present invention.

Fig. 2 is a diagram showing an example of the structure of the PCR correction reference count value in the embodiment of the present invention.

Fig. 3 is a diagram showing an example of the structure of a TS packet to which a reference count value is added in the above-described embodiment of the present invention.

Fig. 4 is a diagram showing another configuration example of a TS packet to which a reference count value is added in the above-described embodiment of the present invention.

Fig. 5 is a diagram showing an example of the configuration of the PCR information detection circuit in the embodiment of the present invention described above.

Fig. 6 is a diagram for explaining temporal jitter of the PCR generated in the rate conversion unit in the above-described embodiment of the present invention.

Fig. 7 is a diagram for explaining an overview of a TS packet of the related art.

Fig. 8 is a diagram showing a configuration example of a high-precision PCR correction circuit in the present invention.

Fig. 9 is a diagram showing an example of the configuration of the system clock frequency difference detection unit in the present invention.

Fig. 10 is an explanatory diagram showing the timings of the input TS signal c and the count value of the STC counter 9 in the present invention.

Fig. 11 is a diagram showing an example of the structure of the frequency deviation correction value in the present invention.

Fig. 12 is a diagram showing an example of the structure of a TS packet to which a reference count value and a frequency offset value are added in the present invention.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings.

First, a PCR correction circuit according to an embodiment of the present invention will be described in detail with reference to fig. 1. The present embodiment includes a quartz oscillator 1 for a system clock, a PCR correction reference counter unit 2, a reference count value adding unit 3, a rate conversion unit 4, a PCR correction count value calculation unit 5, and a PCR substitution unit 6.

In the above-described configuration, the quartz oscillator 1 for the system clock is a 27MHz fixed quartz oscillator independent of the encoder corresponding to the program contained in the input TS signal c. The PCR correction reference counter section 2 is a counter synchronized with the system clock a from the system clock quartz oscillator 1, generates a reference count value b used for PCR correction, and outputs the reference count value b to the reference count value adding section 3 and the PCR correction count value calculating section 5.

On the other hand, the input TS signal c in which a plurality of programs are multiplexed is generated in the reference count value adding section 3, and the TS signal d in which the reference count value b is added is output to the rate converting section 4. The reference count value b is added to the entire packet of the input TS signal c. The rate conversion unit 4 temporarily stores the TS signal d to which the reference count value b is added in a buffer memory, reads a bit rate different from the input bit rate (rate conversion), generates a rate-converted TS signal e, and outputs the TS signal e to the PCR correction counter value calculation unit 5 and the PCR substitution unit 6.

In the PCR correction counter value calculating section 5, the reference count value b added to the reference count value adding section 3 is extracted from the TS signal e after rate conversion output from the rate converting section 4 as an input time reference count value when the TS signal d before rate conversion is input to the rate converting section 4, the reference count value b from the PCR correction reference counter section 2 is extracted as an output time reference count value when the TS signal e after rate conversion is output from the rate converting section 4, and a difference count value between the input time reference count value and the output time reference count value is calculated as a PCR correction count value f and input to the PCR replacing section 6. The PCR correction count value f is calculated for the entire packet of the TS signal e after rate conversion output from the rate conversion unit 4. The PCR substitution unit 6 detects PCR count information included in the rate-converted TS signal e, adds the detected PCR count information to the PCR correction count value f to obtain a new PCR count value after PCR correction, and substitutes the detected PCR count information to output the rate-converted output TS signal after PCR correction.

Further, the reference counter unit 2 for PCR calibration will be described in detail. In addition, the PCR information in the MPEG2-TS signal used in the present invention includes: a 300-bit count value of 9 bits called PROGRAM _ Clock _ Reference _ Extension (hereinafter referred to as PCR _ Ext), synchronized with a 27MHz system Clock owned by an encoder generating a PROGRAM; and a count value synchronized with 90kHz that is divided by 1/300 the above-mentioned 27MHz system Clock of 33 bits called PROGRAM _ Clock _ Reference _ Base (hereinafter referred to as PCR Base). In the present invention, the PCR correction count value f and the calculation circuit for adding the corrected PCR count value f are simplified in the same manner as the counter of the reference counter section 2 for PCR correction. However, since the present counter is a device for correcting the time jitter generated when buffering is performed in the rate conversion unit 4, it is not necessary to adopt a counter configuration having the same number of bits as the PCR information based on the MPEG 2-TS.

FIG. 2 is an example of the reference count value b for PCR correction of the present invention, which shows the case including the lower reference count value [8-0] 9bit corresponding to the PCR _ Ext and the upper reference count value [15-9] 7bit corresponding to the PCR _ Base. In this case, it is assumed that the time jitter generated when buffering is performed in the rate conversion unit 4 is 1.4ms or less at maximum. (1.4ms < 2^7bit x 1/90kHz)

In addition, although the system clock (27MHz) for operating the PCR correction reference counter unit 2 is ± 30ppm in the MPEG2-TS standard to obtain high accuracy, the PLL circuit for reproducing the system clock as in the conventional method has a disadvantage that the processing becomes complicated and the circuit scale increases. In addition, although there is a possibility that a plurality of PLL circuits are provided correspondingly to TS signals in which a plurality of programs are multiplexed, the number of programs that can be PCR-corrected is limited due to problems such as a circuit installation space.

Thus, the PCR correction circuit of the present embodiment has an independent system clock (quartz oscillator) with a precision equal to or higher than that of the encoder. In view of the fact that the correction time of the PCR value described above can be reduced and the PCR jitter value (± 500ns) conforming to the MPEG2-TS specification can be corrected, even if it is not necessary to reproduce the existing system clock using the PLL circuit, the frequency deviation (ズレ) between the system clock of the present PCR correction circuit and the system clock of the encoder that generates the program can be said to hardly cause a malfunction for the program reproduction on the decoder side. Even if there is a deviation of about 1 to 2 clocks, the PCR jitter is about 75ns or less, and is a very small value for the MPEG2-TS standard. In turn, the circuit structure can be simplified, and the circuit scale can be greatly reduced. That is, the present invention has been made based on the new knowledge of the above-mentioned inventors and the like.

Next, the reference count value adding unit 3 will be described in detail. Fig. 3 shows an example of the structure of a TS packet, and in the reference count value adding section 3, an 8-bit extended bit region is provided for 8 bits of the bit width of the input TS signal c, and the 16-bit reference count value b including the upper/lower reference count value (as described above in fig. 2) is added to the extended bit region corresponding to the timing of the next 2 bytes of the sync byte (0x47h) divided every 8 bits. In the present embodiment, by adding the reference count value b before the position (the 7 th byte in the sync header) where the PCR information is added, the calculation of the PCR correction count value can be completed at the timing before the calculation of the newly corrected PCR count value and the replacement timing of the PCR value as described below, and therefore, there is no need to manage the timing of the signal processing. The TS signal d to which the reference count value b thus obtained is added is input to the rate conversion unit 4 in an expanded 16-bit width and stored in the buffer memory.

Although this process is performed only for TS packets containing the original PCR information, the entire TS packets of the input TS signal c are also performed to simplify the circuit. The region other than the 2 bytes to which the reference count value b is added in the extended bit region may be used for other purposes than PCR correction, but if not used, it does not matter if any dummy data is added. However, in the present embodiment, although the extended width is 8 bits, since only 2 bytes are used, the memory area of the buffer memory of the rate conversion unit 4 is wasted.

In contrast, fig. 4 is an embodiment of the case where the buffer memory is expanded in width by 4 bits because the used bit width of the buffer memory is reduced. In this way, by dividing and multiplexing the data with a smaller bit width, the usable area of the buffer memory to be used can be reduced.

Here, returning again to fig. 1, the rate conversion unit 4 temporarily stores the TS signal d to which the reference count value b is added according to the expanded bit width in the buffer memory, and then reads (rate-converts) the TS signal d at a bit rate different from the input bit rate to generate a rate-converted TS signal e. In this case, dummy packets called NULL packets are inserted in order to match different rates.

Fig. 6 shows the streams of an input TS signal c and a rate-converted TS signal e. In the input TS signal c, the TSPs 2 and 7 are TS packets containing the PCRs 1 and 2 as PCR information. The time positions of the original PCRs 1 and 2 are shifted from the Δ PCR1 and Δ PCR2 times, respectively, by adding NULL packets to the rate-converted TS signal e during rate conversion. The Δ PCR1 and Δ PCR2 are time jitters (delay times) at the time of rate conversion. Therefore, in the PCR correction circuit of the present invention, corrected PCR values PCR1 'and PCR 2' can be obtained by calculating Δ PCR1 and Δ PCR2 and adding the correction values to the original PCR1 and PCR 2. The relational expression is as follows.

PCR1’＝PCR1+ΔPCR1

PCR2’＝PCR2+ΔPCR2

Next, the PCR corrected count value calculation section 5 will be described in detail. When outputting the rate-converted TS signal e from the rate converter 4, the reference count value b at the time of writing into the buffer memory added to the bit extension portion is extracted to obtain an input time reference count value. At the same time, the reference count value b is extracted from the PCR correction reference counter unit 2 that outputs the TS signal e after rate conversion, and an output time reference count value is obtained. By calculating the difference between the input time reference count value and the output time reference count value thus obtained, the PCR correction count value f can be obtained. The PCR correction count value f is a temporal jitter (delay time) generated when the rate conversion unit 4 buffers the PCR correction count value f, that is, the values of Δ PCR1 and Δ PCR2 described above. Although this processing is performed only for TS packets containing PCR count information, the processing may be performed for the entire TS signal e after rate conversion for the sake of circuit simplification.

The PCR substitution unit 6 will be described in detail below. That is, the PCR substitution unit 6 extracts only the TS signal from which the bit extension portion is removed from the bit-extended rate-converted TS signal e. PCR count information contained in the extracted TS signal is detected.

Fig. 5 shows an example of a PCR count information detection circuit according to an embodiment of the present invention. In the present embodiment, the present invention includes: an adaptation field flag detecting section 101, an adaptation field length detecting section 102, a PCR flag detecting section 103, and a PCR count value detecting section 104.

In the above configuration, the TS signal o extracted from the bit-extended rate-converted TS signal e is input to the adaptation field flag detecting section 101, the adaptation field length detecting section 102, the PCR flag detecting section 103, and the PCR count value detecting section 104. Then, the adaptation field flag detecting section 101 extracts the adaptation field flag from the header information portion in the entire packet of the rate-converted TS signal o, and outputs the adaptation field detection flag p only when the adaptation field flag indicates the presence of the adaptation field. The adaptation field length detection unit 102 extracts adaptation field length information from the adaptation field portion in the entire packet of the TS signal o, and outputs an adaptation field length detection flag q only when the adaptation field has a finite length.

The PCR detection flag detection unit 103 extracts a PCR flag from the adaptation field in the entire packet of the TS signal o, and outputs the PCR detection flag r only when the PCR flag indicates the presence of the PCR count value. The PCR count value detection unit 104 extracts a PCR count value from only TS packets to which all the detected adaptation field detection flag p, adaptation field length detection flag q, and PCR detection flag r have been output.

As described above, the PCR correction circuit of the present invention can significantly reduce the number of components, the circuit scale, and the control, compared to the conventional method of reproducing the system clock by the PLL circuit. In addition, according to the present invention, since jitter (delay time) of PCR information generated at the time of buffering at the time of rate conversion can be calculated for the entire packet including PCR information, there is no limitation on the number of programs (number of PCRs) that can be PCR-corrected. Further, the circuit for detecting PCR count information necessary for PCR correction does not have to analyze PSI information to detect PCR values for each program as in the prior art, and simply can be realized by merely determining whether PCR information is included, and therefore, it is needless to say that the circuit can be further simplified and the circuit scale can be reduced.

Next, with reference to fig. 8, an embodiment of a PCR correction circuit that can perform PCR correction with higher accuracy and implement the present invention is described with respect to the PCR correction circuit described in fig. 1. In fig. 8, the system clock frequency difference calculation units 7-1 to 7-n have n circuits for the number of programs multiplexed in the input TS signal c, and calculate the frequency difference between the system clock of the encoder corresponding to each multiplexed program and the system clock a from the system clock quartz oscillator 1 only for the packet including the PCR count value among the input TS signal c, and output the frequency difference correction values t-1 to t-n.

At this time, if the packet does not include the PCR count value, the frequency offset correction value is set to 0 (no correction is performed). The reference count value adding unit 3 adds the reference count value b for PCR correction from the PCR correction reference counter unit 2 and the frequency deviation correction values t-1 to t-n from the system clock frequency difference calculating units 7-1 to 7-n to a region having an expanded bit width, and inputs the result to the rate converting unit 4. The PCR corrected count value deviation adding unit 11 extracts the frequency deviation correction values t-1 to t-n added to the extended region of the bit width of the TS signal e after rate conversion for the PCR corrected count value f obtained from the difference between the input time reference count value and the output time reference count value from the PCR corrected count value calculating unit 5, and performs correction processing using the extracted values, thereby obtaining a PCR corrected count value f' with relatively high accuracy.

Next, the system clock frequency difference calculation units 7-1 to 7-n will be described in detail with reference to fig. 9.

The system clock frequency difference calculation unit includes n circuits, which are the same as the number of programs multiplexed in the input TS signal c. The PCR detection unit 8 detects only the PCR count value u corresponding to the specific encoder in the program included in the input TS signal c, and outputs the PCR detection flag v. The STC counter 9 is a counter synchronized with the system clock a from the system clock quartz oscillator 1, and has the same configuration (42bit) as the PCR count value u. When the PCR detection mark v from the PCR detection unit 8 is detected, the counter loads the PCR count value u input at the same time as an initial value, and counts up until the next PCR count value u is detected.

The frequency deviation correction value calculation unit 10 calculates a difference in frequency between the system clock of the specific encoder and the system clock a from the system clock quartz oscillator 1 based on the PCR count value u input together with the PCR detection mark v and the count value w from the STC counter 9, and outputs a frequency correction deviation correction value t.

The method of calculating the frequency correction deviation correction value t will be described with reference to fig. 10. Fig. 10 shows a time series of the input TS signal c and the count value of the STC counter 9. When the PCR1 as the PCR count value u is detected from the input TS signal c, the value is loaded as the initial value of the STC counter 9. The STC counter 9 continues counting until a PCR2, which is the next PCR count value u, is detected from the loaded values. At this time, when the count value of the STC counter 9 at the time of detecting the PCR2 is taken as PCR2a, the difference Δ PCR2a between this value and PCR2 can be found by the following equation.

ΔPCR2a＝PCR2-PCR2a

This value is the frequency difference of the system clock of the predetermined encoder with respect to the system clock a used in the PCR correction circuit of the present invention, which is generated from the start of PCR1 until reaching PCR 2. In addition, the time (Δ PCR1-2) from the start of this PCR1 until reaching PCR2 can be obtained by the following formula.

ΔPCR1-2＝PCR2a-PCR1

The Δ PCR2a and Δ PCR1-2 were used as the frequency deviation correction value t.

Next, a structural example of the frequency correction deviation correction value t will be explained. FIG. 11 is an example of the frequency correction offset correction value t of the present invention, showing a case where Δ PCR1-2 is composed of a lower count value [8-0] 9bit corresponding to the PCR _ Ext and an upper count value [22-9] 14bit corresponding to the PCR _ Base. On the other hand, Δ PCR2a is only the count [8-0] of 9 bits corresponding to PCR _ Ext, of which the lower 8 bits are employed as difference information and the most significant bit is a bit of (±) for indicating the sign of the correction value. At this time, the arrival interval of packets including the calculable PCR correction value is within 100ms of the maximum value of the MPEG2-TS standard, and the system clock of the encoder is within + -30 ppm of the maximum value of the same standard.

(100ms＜2^14bit×1/90kHz，100ms＜2^5bit×1/(27MHz×±30ppm))

Next, the reference count value adding unit 3 will be described in detail. Fig. 12 shows a TS packet to which the frequency correction deviation correction value t is newly added after the reference count value b added to the 8-bit extension area, among the TS packets to which the reference count values are added described in the above-described fig. 3.

Next, the PCR correction count value deviation adding section 11 will be described in detail. A PCR correction count value, which is difference information between an input time reference count value and an output time reference count value obtained from the rate-converted TS signal e from the PCR correction count value calculation section 5, is input. At the same time, the frequency correction deviation correction value t (Δ PCR2a, Δ PCR1-2) added after the reference count value b of the bit extension portion is also extracted, and the input PCR correction count value f is subjected to correction processing using this value. The correction method is given by the following formula.

PCR corrected count value f ═ PCR corrected count value f × α

(α＝1+ΔPCR2a/ΔPCR1-2)

Here, the sign of α is defined so as to correspond to the sign bit that is the most significant bit of Δ PCR2 a. Thus, a new PCR corrected count value f' can be obtained. The PCR corrected count value f' thus obtained is a value corrected by the count value of the reference system clock from 1 crystal oscillator (the difference between the counts from input to output in the buffer memory), and is a PCR corrected count value with higher accuracy because the frequency difference between the system clock of the crystal oscillator as the reference and the system clock of the original multiplexed encoder is corrected.

Further, in the present embodiment, although the calculation of the frequency deviation correction value t is performed every time the PCR count value arrives, in an actual system, since it is difficult to consider that the frequency difference between the system clock of the quartz oscillator and the system clock of the encoder always occurs largely, it is possible to take an average value of 50 times, for example, and add and transmit 1 time every 50 times. In addition, the PCR correction circuit may adopt a configuration in which, after the correction operation is started, the frequency correction deviation correction value t is used to obtain a new PCR correction count value f' only in the case where the time length of the transmission interrupted state exceeds a predetermined time. Although the present invention is applied to both Δ PCR2a and Δ PCR1-2 in a packet, a system clock frequency difference detector may calculate α (═ 1+ Δ PCR2a and Δ PCR1-2) in advance and apply the result as a frequency correction deviation correction value t. In the PCR replacement section 6, similarly to the PCR correction circuit described in fig. 1 of the present invention, a new high-precision PCR correction count value f' is replaced with a corrected PCR count value for the rate-converted TS signal e instead of the PCR correction count value f.

As described above, the circuit configuration of the PCR correction circuit configuration illustrated in fig. 1 of the present invention, in which the PCR correction count value f' is calculated in fig. 8, is an effective method in a system that requires a PCR correction process with higher accuracy.

Claims (4)

1. A program clock reference correcting circuit for correcting jitter of reference time information of a program clock reference generated when a TS signal in which a plurality of programs are multiplexed is converted into a different bit rate by a memory, the circuit comprising:

a quartz oscillator as a reference clock for reference correction of a program clock;

a reference counter unit for program clock reference correction that generates a reference count value for program clock reference correction in synchronization with the reference clock;

a reference count value adding unit that adds the reference count value to the TS signal before bit rate conversion;

a rate conversion unit that temporarily stores the TS signal to which the reference count value is added in a buffer memory, and converts the TS signal into an output bit rate to output the TS signal;

a program clock reference correction count value calculation unit that extracts an input time reference count value when the TS signal to which the reference count value is added is input to the rate conversion unit from the reference count values added to the output TS signal from the rate conversion unit, acquires an output time reference count value when the TS signal is output from the rate conversion unit by the program clock reference correction reference counter unit, and calculates a difference between the input time reference count value and the output time reference count value to obtain a program clock reference correction count value; and

a program clock reference replacing section for detecting a program clock reference count value included in the output TS signal from the rate converting section, and adding the calculated program clock reference correction count value to the detected program clock reference count value to replace the detected program clock reference count value with a new program clock reference count value,

the reference count value adding unit performs bit width expansion on the TS signal before the bit rate conversion and adds the reference count value to the expanded bit region;

the rate conversion unit stores the TS packets, to which the reference count value is added, in a buffer memory by performing bit width expansion;

the program clock reference correction count value calculation unit obtains the input time reference count value by extracting the reference count value added to an extended bit width region of the TS signal when the TS signal stored in the buffer memory is read from the rate conversion unit; and the number of the first and second electrodes,

a program clock reference detection circuit for detecting a program clock reference count value contained in the rate-converted TS signal of the program clock reference substitution unit, the program clock reference detection circuit extracting the program clock reference count value from adaptation fields of the following TS packets among all the TS packets: reference is made to an adaptation field flag within the header information of the TS packet indicating the presence of an adaptation field, and reference is made to an adaptation field length flag within the adaptation field of the TS packet indicating that the adaptation field is of finite length, and reference is made to a program clock reference flag within the adaptation field of the TS packet indicating that there is a description of a program clock reference count value within the adaptation field.

2. The program clock reference correction circuit of claim 1,

and correcting the new program clock reference count value by a frequency deviation value, the new program clock reference count value being a value to which the program clock reference correction count value is added, the program clock reference correction count value being calculated from the difference between the input time reference count value and the output time reference count value, the frequency deviation value being a value that detects a frequency deviation value between a system clock of an encoder that is independent for each of the plurality of programs and included in the output TS signal from the rate conversion section and a reference clock from the quartz oscillator, respectively.

3. The program clock reference correction circuit of claim 2, wherein:

continuing to use the new program clock reference count value in a case where a time length of a transmission interruption state is shorter than a predetermined time after the program clock reference correction circuit starts a correction operation.

4. The program clock reference correction circuit of claim 3, wherein:

in the case where the time length of the transmission interruption state is longer than the predetermined time, the new program clock reference count value is corrected with the frequency offset value.