HK1122425B - Bit-deskewing io method and system - Google Patents

Description

Bit deskew IO method and system

Technical Field

The present invention relates to the field of data transmission in computers and other digital systems.

Background

As computers and other digital systems become more complex and powerful, methods and hardware to enhance the transfer of data between system components or elements typically continue to evolve. The data to be transmitted includes signals representing data, commands, or any other signals. A system component or element may comprise hardware blocks of different functionality on a single Integrated Circuit (IC) or on different integrated circuits. The different integrated circuits may or may not be on the same Printed Circuit Board (PCB). System components typically include input/output (I/O) interfaces specifically designed to receive data from and transmit data to other system components. In general, existing I/O interfaces can be classified as serial "links" and parallel "links". Regardless of the type of I/O interface, the transferred data must be synchronized between the system components for proper operation. Synchronization includes accounting for or compensating for a number of phenomena potentially causing errors, including signal jitter and signal skew. The phenomena include differences between component clocks and physical properties of the data path that cause noise and affect the integrity of the transmitted signal. Current methods for manipulating serial I/O interfaces and parallel I/O interfaces address these data synchronization issues, but have limitations.

A typical serial link embeds clock information into a data stream and uses a clock recovery scheme in the receiver to extract the clock information. Such a scheme is also referred to as per-line closed-loop timing. Ensuring the transition density requires encoding the data, typically using 8B/10B codes. The disadvantage of this approach is increased bandwidth overhead and increased complexity, which compromises performance and increases cost.

A typical parallel link sends a clock signal or strobe (strobe) while sending a set of N data signals (e.g., N may be 8 in a double data rate dynamic random access memory (DDR DRAM)). Depending on the data rate and the level of sophistication required, one of the following "source synchronous timing" methods is used: if the strobe is shifted by half a bit time relative to the data sent by the transmitter, the receiver simply samples the data directly with the strobe; or if the sampling pulse is aligned with the edge of the data transmitted by the transmitter, the receiver delays the strobe by the same fixed amount over the entire set of data to sample the data eye at the nominal center.

Each of the two parallel linking methods described above requires very tight trace impedance and trace length matching of the entire set of data and strobe to achieve high data rates. To alleviate this, each bit receiver may delay the strobe by a different amount to center its own clock on its own data. Sometimes this is called per bit deskew. A disadvantage of this parallel scheme is that the strobe (which is typically sent across the entire board and distributed to the entire set of data) is noisy, thus reducing the timing budget of the system. In addition, the receiver simply uses or delays the strobe, which adds jitter without filtering the jitter. In some embodiments, one strobe is sent for each data bit rather than a group of data bits, which increases pin count and cost.

Drawings

FIG. 1 is a block diagram of a portion of a system including a receiver interface, according to one embodiment.

FIG. 2 is a flow diagram of a method performed by the circuit of FIG. 1 according to one embodiment.

Detailed Description

Embodiments of bit deskew IO methods and systems are described herein. A method and system for bit de-skew is described. In one embodiment, a system component receives a forward strobe signal and a plurality of data bit signals from a transmit component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock to improve sampling accuracy. The receive component also includes at least one data bit clock recovery circuit that is configurable to align the data bit sampling clock to improve sampling accuracy and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe clock during system operation.

The data rate achieved by the embodiments is similar to a serial link using per-line closed loop timing, but without the complexity and coding bandwidth overhead typically associated. In one embodiment, these advantages are provided in an interface that includes improved performance over existing source synchronous parallel links, but does not include the complexity and overhead associated with current serial links (e.g., due to encoding a clock into a serial data stream).

FIG. 1 is a block diagram of a portion of a system 100 according to one embodiment. The system 100 includes a transmitter 104 and a receiver interface 102. The system 100 may be any computer system or subsystem thereof, a digital system, a component or combination of components that transfer data between components. The components may be blocks of circuitry on an integrated circuit, different integrated circuits on the same printed circuit board, or components that communicate over a network. In various embodiments, the components communicate at high speed and high data rate. For example, system 100 may be a computer system having a graphics processing or video processing unit in communication with Double Data Rate (DDR) DRAM, although embodiments are not so limited.

Relevant portions of transmitter 104 are shown, including latches or flip-flops 106(0) -106(N-1) and associated output buffers. In one embodiment, transmitter 104 transmits a strobe signal or forward clock (labeled DQS) associated with data bits DQ (0) -DQ (N-1). The data bits and forward strobe are transmitted over the transmission medium 107. In different embodiments, the transmission medium 107 may be one or more cables, PCB traces, or any other known transmission medium. The data bits DQ are transmitted according to communications that occur between the transmitter 104 and a receiving component that includes the receiver interface 102. In contrast, as shown, the forward strobe DQS is continuously transmitted as a toggle logic value (101010 …). The transmitter 104 also includes a transmit phase locked loop (TxPLL)108, which is a well known circuit. For example, PLLs are used as control mechanisms in most frequency synthesizers. TxPLL108 operates in a known manner.

Receiver interface 102 includes a receive pll (rxpll)110 that operates in a known manner. TxPLL108 and RxPLL110 both receive a reference clock signal Ref Clk 109. The output of TxPLL108 provides a clock signal for latch 106. The output of the RxPLL110 is input to a clock phase delay circuit 120 for each data bit DQ and for the forward strobe signal DQs, which is described in more detail below.

The forward strobe signal DQS is received by the clock recovery circuit 112(S) of the receiver interface 102. Receiver interface 102 also includes a separate clock recovery circuit 113 for each of the data bits DQ (clock recovery circuit 113(0) for DQ (0), clock recovery circuit 113(1) for DQ (1), etc.).

To help ensure that the received signal, including the strobe and data signals, is correctly sampled by the receiver interface 102, the sampling clock signals are aligned to optimally sample the received signal. For example, in one embodiment, the sampling clock signals are aligned to sample near the center of the valid window (also referred to as the data eye) of received data. This maximizes the setup and hold time and reduces the likelihood of sampling errors. The forward strobe signal and the data bits DQ are transmitted in an edge-aligned manner. The function of the clock recovery circuits 112 and 113 in the receiver interface 102 is to adjust the phase of the received RxPLL110 output signal so that the sampling point is close to the center of the data eye. In another embodiment, the phase of the received RxPLL110 output signal may be adjusted or aligned based on other criteria to improve sampling accuracy suitable for the design of the system embodiment.

Referring to the clock recovery circuit 112(S), the forward strobe DQS is received by the phase detector 114. Phase detector 114 is a known circuit, such as a comparator, that compares the phase of the received signal with the phase of the sampling clock signal and determines whether the received signal is early or late with respect to the sampling clock signal. As explained further below, the sampling clock signal is the output of the RxPLL110, after which its phase relationship with the received signal is adjusted by the clock phase delay circuit 120 to be aligned with the center of the forward strobe DQS. The output of phase detector 114 is an early/late indication for each clock cycle. The early/late indication is input to divider 116. The divider 116 may be adjusted to cause the number of detected early/late indications to be reduced at a certain rate. The output of divider 116 is the adjusted number of early/late indications received by phase counter 118. The number of early/late indications is adjusted because it may not be desirable to react to each early or late indication by adjusting the phase of the RxPLL110 output. For example, adjusting the phase of the RxPLL110 output in response to each early/late indication may result in clock jitter. Thus, the early/late indication is divided by a number, e.g., 32, such that the phase of the RxPLL110 output is shifted once every 32 indications.

The output of the phase counter 118 is the signal DQSPC which is input to a clock phase delay circuit 120, the clock phase delay circuit 120 adjusting the delay of the RxPLL110 output to center the RxPLL110 output on DQS. In one embodiment, clock phase delay circuit 120 is a phase interpolator, but embodiments are not so limited. The clock phase delay circuit 120 outputs a recovered forward clock signal DQSrclk that is fed back to the phase detector circuit 114. In the current embodiment, DQSrclk will be adjusted until it is centered in the received DQS signal to maximize the setup/hold time window. Thus, when the clock recovery circuit 112(S) is enabled or activated, DQSrclk is compared to the received DQS signal for constant adjustment.

According to one embodiment, clock recovery circuit 112(S) operates in an initial "training" phase to train circuit 112(S) for an appropriate amount of delay required to center the recovered forward clock signal DQSrclk in the data eye of DQS (the received strobe signal). This amount of delay is represented by the DQSPC signal. Once the clock recovery circuit 112(S) is trained and the DQSPC signal is obtained, the clock recovery circuit 112(S) is disabled by the DQS freeze signal input to the divider circuit 116. The DQS freeze signal has the effect of keeping the DQSPC signal at a stable value.

The receiver interface 102 also includes, for each of the data bits DQ, data bit clock recovery circuitry 113(0), 113(1), and so on, through 113 (N-1). In one embodiment, data bit clock recovery circuit 113 is disabled by the common DQ freeze signal during the training phase of clock recovery circuit 112 (S). After the clock recovery circuit 112(S) is trained and disabled, the clock recovery circuit 113 is enabled during the data clock recovery circuit training phase. During the data clock recovery circuit training phase, each of the data clock recovery circuits 113 operates to detect a phase difference between the output of the RxPLL110 and the data eye of the respective received data signal. In one embodiment, the phase adjustments determined during the training phase of clock recovery circuit 112(S), which are represented by the DQSPC signal, are added to the phase adjustments determined by each clock recovery circuit 113.

The reference clock recovery circuit 133(0), the data signal DQ (0) is received by the phase detector circuit 114. The output of the phase detector circuit 114 is received by an adjustable divider circuit 116 as explained with reference to the clock recovery circuit 112 (S). The output of divider circuit 116 is received by phase counter 118, and phase counter 118 outputs signal DQPC (0) to adder 122. Adder 122 also receives the DQSPC signals from strobe clock recovery circuit 112(S) and adds the received signals to produce an input to phase delay circuit 120. The DQPC signal is an intermediate clock offset that is added to the DQSPC clock offset to produce a data clock offset signal that is input to clock phase delay circuit 120. The input from adder 122 to clock phase delay circuit 120 indicates the amount by which the output of RxPLL110 should be delayed. The output of the clock phase delay circuit 120 is the recovered clock signal for the data bit DQ (0), or DQrclk (0).

Each data clock recovery circuit 113 goes through a similar training phase to obtain a DQPC signal and a DQrclk signal. The training phases for different clock recovery circuits 113 may occur simultaneously or at different times. When all of the data clock recovery circuits 113 are trained, they are disabled by the DQ freeze signal. Disabling the data clock recovery circuits 113 prevents the DQPC signals of the respective circuits 113 from changing.

In normal system operation, the strobe clock recovery circuit 112(S) is again enabled and free running while the components comprising the receiver interface 102 are running. Thus, circuit 112(S) will adjust DQSPC as needed to keep DQSrclk in the center of the received forward strobe (DQS). On the other hand, the data clock recovery circuit remains disabled during normal system operation. However, because each data clock recovery circuit receives DQSPC, the phase adjustment or offset of the signal clocking each data bit (from DQ (0) to DQ (N-1)) will be adjusted to track any DQSPC changes. The data thus "tracks" the forward strobe. That is, since the respective sampling clocks of the data and the forward strobe move together, the data and the forward strobe also move together. This is valid because the relationship of each data signal to the forward strobe (or the relationship between each data signal and the respective sampling clock of the forward strobe) is established during the training phase and does not change much if each encounters similar environmental changes.

FIG. 2 is a flow diagram illustrating a bit deskewing method 200, which may be performed by the system of FIG. 1, in accordance with one embodiment. At 202, the system initializes. As part of the initialization process, the forward strobe clock recovery circuit is enabled and the data clock recovery circuit is disabled, as shown at 204. At 206, the forward strobe clock recovery circuit is allowed to operate to determine DQSPC. As previously described, DQSPC is determined when the value of DQSPC is appropriate to cause the clock phase delay circuit to place the forward strobe sampling clock DQSrclk in the center of the received forward strobe data eye. In one embodiment, the forward strobe sampling clock DQSrclk is the delayed output of the transmit PLL, RxPLL, which receives the reference clock. In one embodiment, the forward strobe clock recovery circuit operates for a predetermined amount of time (e.g., one millisecond) determined to be sufficient to determine DQSPC. In another embodiment, additional circuitry (not shown) determines when to determine DQSPC.

When DQSPC is asserted, the forward strobe clock recovery circuit is disabled and the data clock recovery circuit is enabled, as shown at 208. At 210, the data clock recovery circuit is run to determine the individual DQPCs. As previously described with reference to fig. 1, DQSPC is added to each DQPC phase counter output during this data clock recovery training phase.

When DQPC is asserted, the forward strobe clock recovery circuit is again enabled and the data clock recovery circuit is disabled, as shown at 212. Normal system operation then proceeds at 214.

In various embodiments, a clock recovery event during normal operation may cause one or more clock recovery circuits to complete another training phase during system operation. For example, in one embodiment, if one or more of the DQPC values has not changed for a predetermined number of clock cycles (e.g., one thousand cycles), the training process beginning at 208 will be repeated. In another embodiment, a system component containing the receiver interface 102 experiences an idle period or power saving period during which the system component does not "useful" work. In such embodiments, the idle period is also a clock recovery event. One example of such a component is a Double Data Rate Dynamic Random Access Memory (DDRDRAM), for DDR DRAMs, a refresh cycle may be used as a clock recovery event.

In various embodiments, control of the circuitry is performed by a higher-level system protocol. A certain behavior (behavior) of the circuit may be specified for a particular component so that a user of the component may adjust the behavior of the circuit by the protocol. Examples of the specified behavior are values for the divider circuit, a predetermined amount of time for performing clock recovery circuit training, and which events (if any) are clock recovery events.

Embodiments of deskew IO methods and systems disclosed herein include a system comprising: at least one component configurable to transmit a plurality of data bits and a forward strobe associated with the plurality of data bits; at least one component configurable to receive a plurality of signals. In one embodiment, the at least one configurable means for receiving comprises: a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock to improve sampling accuracy; and at least one data bit clock recovery circuit configurable to align a data bit sampling clock to improve sampling accuracy and to receive a signal from the forward strobe clock recovery circuit during operation of the at least one configurable means for receiving that causes the data bit sampling clock to track the forward strobe sampling clock.

In one embodiment, the signal received from the forward strobe clock recovery circuit includes a forward strobe clock offset, and wherein the forward strobe clock offset is combined with the intermediate data bit clock offset to produce the data bit clock offset.

In one embodiment, during a training phase, the data bit sampling clocks are aligned by generating data bit clock offsets, the at least one data bit clock recovery circuit is active during the training phase, and wherein the data bit clock offsets comprise intermediate data bit clock offsets combined with the signal from the forward strobe clock recovery circuit, wherein the signal comprises forward strobe clock offsets.

In one embodiment, the at least one data bit clock recovery circuit is inactive during operation of the at least one configurable means for receiving, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

In one embodiment, during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and during a data bit training phase, the at least one data bit clock recovery circuit aligns the data bit sampling clock, the forward strobe clock recovery circuit is inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

In one embodiment, the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of a plurality of data bits.

In one embodiment, wherein the at least one data bit clock recovery circuit includes a phase detector that receives the respective data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

In one embodiment, the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

In one embodiment, the early/late indication is divided by a predetermined number before being received by the phase counter.

In one embodiment, the at least one data bit clock recovery circuit further comprises an adder that adds an intermediate data bit clock offset to a signal received from the forward strobe clock recovery circuit, wherein the signal comprises the forward strobe clock offset.

In one embodiment, the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives the output of the adder and generates a recovered data clock signal.

Embodiments also include a computer-readable medium having instructions stored thereon, which when executed in a system, cause the system to implement a method of data transmission, the method comprising: training a forward strobe clock recovery circuit to determine a forward strobe sampling clock offset for improving sampling accuracy; and training at least one data bit clock recovery circuit to determine a data bit sampling clock offset for improved sampling accuracy, wherein the data bit sampling clock offset comprises the forward strobe sampling clock offset and an intermediate data bit sampling clock offset.

In one embodiment, the method implemented by the system further comprises: enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit while training the forward strobe clock recovery circuit.

In one embodiment, the method implemented by the system further comprises: disabling the forward strobe clock recovery circuit and enabling the data clock recovery circuit while training the data clock recovery circuit.

In one embodiment, the method implemented by the system further comprises: enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit during system operation such that the data bit sampling clock offset tracks the forward strobe sampling clock offset.

In one embodiment, the method implemented by the system further comprises: detecting at least one clock recovery event during operation of the system; and repetitively training at least one data bit clock recovery circuit.

In one embodiment, the at least one clock recovery event comprises: a predetermined amount of time has elapsed since a last training of the at least one data clock recovery circuit; an idle state of a system component including the at least one data clock recovery circuit; and a low power state of a system component including the at least one data clock recovery circuit.

Embodiments also include a method of transmitting data in a system, the method comprising: training a forward strobe clock recovery circuit to determine a forward strobe clock offset for improving sampling accuracy; training at least one data bit clock recovery circuit to determine a data bit sampling clock offset for improved sampling accuracy, wherein the data bit sampling clock offset comprises the forward strobe sampling clock offset and an intermediate data bit sampling clock offset.

One embodiment includes: enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit while training the forward strobe clock recovery circuit.

One embodiment includes: disabling the forward strobe clock recovery circuit and enabling the data clock recovery circuit while training the data clock recovery circuit.

One embodiment includes enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit during system operation such that the data bit sampling clock offset tracks the forward strobe sampling clock offset.

One embodiment includes: detecting at least one clock recovery event during operation of the system; and repetitively training at least one data bit clock recovery circuit.

In one embodiment, the at least one clock recovery event comprises: a predetermined amount of time has elapsed since a last training of the at least one data clock recovery circuit; an idle state of a system component including the at least one data clock recovery circuit; and a low power state of the at least one data clock recovery circuit.

Embodiments also include an apparatus for transmitting data, comprising: a strobe signal transmitter for transmitting a strobe signal over a transmission medium; and at least one data transmitter for transmitting at least one data signal over a transmission medium, wherein the receiver strobe sampling clocks are aligned to sample the strobe signal, and wherein at least one receiver data sampling clock is aligned to track the aligned receiver strobe sampling clock.

In one embodiment, the strobe signal is sent continuously over the transmission medium.

In one embodiment, the strobe signal, which is transmitted continuously, transitions between a logic high value and a logic low value.

Embodiments also include a method of transmitting data, comprising: transmitting a strobe signal on a transmission medium; and transmitting at least one data signal over a transmission medium, wherein a strobe sampling clock that samples the transmitted strobe signal is adjusted by an adjustment value that aligns the strobe sampling clock, and wherein the adjustment value is further used to align at least one data sampling clock that samples the at least one data signal.

In one embodiment, transmitting the strobe signal comprises continuously transmitting the strobe signal over the transmission medium.

In one embodiment, continuously transmitting the strobe signal includes transitioning the continuously transmitted strobe signal between a logic high value and a logic low value.

Embodiments also include a receiver for receiving data, comprising: a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock; and at least one data bit clock recovery circuit configurable to align a data bit sampling clock and receive a signal from the forward strobe clock recovery circuit, the at least one data bit recovery circuit configuring the data bit sampling clock to track the forward strobe sampling clock during operation.

In one embodiment, the signal received from the forward strobe clock recovery circuit includes a forward strobe clock offset, and wherein the forward strobe clock offset is combined with an intermediate data bit clock offset to produce a data bit clock offset.

In one embodiment, during a training phase, the data bit sampling clocks are aligned by generating data bit clock offsets, the at least one data bit clock recovery circuit is active during the training phase, and wherein the data bit clock offsets comprise intermediate data bit clock offsets combined with the signal from the forward strobe clock recovery circuit, wherein the signal comprises forward strobe clock offsets.

In one embodiment, the at least one data bit clock recovery circuit is inactive during operation of the at least one configurable means for receiving, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

In one embodiment, during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and during a data bit training phase, the at least one data bit clock recovery circuit aligns the data bit sampling clock, the forward strobe clock recovery circuit is inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

In one embodiment, the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of the plurality of data bits.

In one embodiment, the at least one data bit clock recovery circuit includes a phase detector that receives the respective data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

In one embodiment, the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

In one embodiment, the early/late indication is divided by a predetermined number before being received by the phase counter.

In one embodiment, the at least one data bit clock recovery circuit further comprises an adder that adds the intermediate data bit clock offset to the signal received from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

In one embodiment, the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives the output of the adder and generates the recovered data clock signal.

Embodiments also include a method for receiving data, comprising: in response to receiving the forward strobe, the strobe clock recovery circuit aligns the forward strobe sampling clock; and aligning a data bit sampling clock to track the forward strobe sampling clock during operation.

In one embodiment, the signal received from the forward strobe clock recovery circuit includes a forward strobe clock offset, and wherein the forward strobe clock offset is combined with an intermediate data bit clock offset to produce a data bit clock offset.

In one embodiment, during a training phase, the data bit sampling clocks are aligned by generating data bit clock offsets, the at least one data bit clock recovery circuit is active during the training phase, and wherein the data bit clock offsets comprise intermediate data bit clock offsets combined with the signal from the forward strobe clock recovery circuit, wherein the signal comprises forward strobe clock offsets.

In one embodiment, the at least one data bit clock recovery circuit is inactive during operation of the at least one configurable means for receiving, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

In one embodiment, during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and during a data bit training phase, the at least one data bit clock recovery circuit aligns the data bit sampling clock, the forward strobe clock recovery circuit is inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

In one embodiment, the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of the plurality of data bits.

In one embodiment, the at least one data bit clock recovery circuit includes a phase detector that receives the respective data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

In one embodiment, the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

In one embodiment, the early/late indication is divided by a predetermined number before being received by the phase counter.

In one embodiment, the at least one data bit clock recovery circuit further comprises an adder that adds the intermediate data bit clock offset to the signal received from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

In one embodiment, the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives the output of the adder and generates the recovered data clock signal.

Aspects of the invention described above may be implemented as functionality programmed into any of a variety of circuits, including but not limited to programmable devices (PLDs), such as Field Programmable Gate Arrays (FPGAs), Programmable Array Logic (PAL) devices, electrically programmable logic and memory devices and standard cell based devices, as well as Application Specific Integrated Circuits (ASICs) and fully custom integrated circuits. Some other possibilities for implementing aspects of the invention include: a microcontroller with memory, such as Electrically Erasable Programmable Read Only Memory (EEPROM), an embedded microprocessor, firmware, software, etc. Furthermore, aspects of the invention may be implemented in microprocessors having software-based circuit emulation, discrete logic (sequential and combinatorial), custom devices, fuzzy (neural) logic, quantum devices, and hybrids of any of the above device types. Of course, the underlying device technology may be provided in a variety of component types, such as Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technologies like Complementary Metal Oxide Semiconductor (CMOS), bipolar technologies like Emitter Coupled Logic (ECL), polymer technologies (e.g., silicon conjugated polymer and metal conjugated polymer metal structures), digital-analog hybrid technologies, and so forth.

Throughout the specification and claims, the words "comprise", "comprising" and the like are to be construed in an inclusive sense as opposed to an exclusive or exhaustive sense, unless the context clearly requires otherwise. That is, what is meant is "including but not limited to". Words using the singular or plural number also include the plural or singular number, respectively. Additionally, the words "herein," "hereinafter," "above," "below," and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. When the word "or" is used in a list of two or more items, that word covers all of the following interpretations of the word: any one of the items in the list, all of the items in the list, and any combination of the items in the list.

The above description of illustrated embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. The teachings of the invention provided herein may be applied to other systems than those including graphics processing or video processing or DDR DRAM as described above. The various operations described may be implemented in a wide variety of architectures and may be distributed in ways other than those described. Additionally, although many configurations are described herein, none are intended to be limiting or exclusive.

In further embodiments, some or all of the hardware or software capabilities described herein may reside in a printer, a camera, a television, a handheld device, a mobile phone, or some other device. The components and acts of the different embodiments described above can be combined to provide further embodiments. These and other changes can be made to the invention in light of the above detailed description.

In general, in the following claims, the terms used should not be construed to limit the video processing methods and systems to the specific embodiments disclosed in the specification and the claims, but should be construed to include any processing system that operates in accordance with the claims to provide video processing. Accordingly, the method and system are not limited by the disclosure, but rather the scope of the method and system for bit de-skew is to be determined entirely by the claims.

While certain aspects of the methods and apparatus for video processing are presented below in certain claim forms, the inventors contemplate the various aspects of the methods and apparatus in any number of claim forms. For example, while only one aspect of the methods and apparatus may be described as embodied in a computer-readable medium, other aspects may likewise be embodied in a computer-readable medium. Accordingly, the inventors reserve the right to add additional claims after filing the application to pursue such additional claim forms for other aspects of the method and apparatus for bit de-skew.

Claims (34)

1. A system for transmitting data, comprising:

at least one component configurable to transmit a plurality of data bits and a forward strobe associated with the plurality of data bits;

at least one component configurable to receive the plurality of data bits and a forward strobe, wherein the at least one component configurable to receive comprises:

forward strobe clock recovery circuit configurable for aligning forward strobe samples

A clock to improve sampling accuracy; and

at least one data bit clock recovery circuit configurable to align a data bit sampling clock to improve sampling accuracy and to receive a signal from the forward strobe clock recovery circuit during operation of the at least one configurable means for receiving that causes the data bit sampling clock to track the forward strobe sampling clock;

wherein: during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and

the at least one data bit clock recovery circuit aligns the data bit sampling clock during a data bit training phase, the forward strobe clock recovery circuit being inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

2. The system of claim 1, wherein the signal received from the forward strobe clock recovery circuit comprises a forward strobe clock offset, and wherein the forward strobe clock offset is combined with an intermediate data bit clock offset to produce a data bit clock offset.

3. The system of claim 1, wherein during a training phase, the data bit sampling clocks are aligned by generating a data bit clock offset, the at least one data bit clock recovery circuit being active during the training phase, and wherein the data bit clock offset comprises an intermediate data bit clock offset combined with the signal from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

4. The system of claim 3, wherein the at least one data bit clock recovery circuit is inactive during operation of the at least one component configurable for receiving, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

5. The system of claim 1, wherein the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of the plurality of data bits.

6. The system of claim 5, wherein the at least one data bit clock recovery circuit includes a phase detector that receives the corresponding data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

7. The system of claim 6, wherein the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

8. The system of claim 7, wherein the early/late indication is divided by a predetermined number before being received by the phase counter.

9. The system of claim 7, wherein the at least one data bit clock recovery circuit further comprises an adder that adds the intermediate data bit clock offset to the signal received from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

10. The system of claim 9, wherein the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives an output of the adder and generates the recovered data clock signal.

11. A method of transmitting data in a system, the method comprising:

training a forward strobe clock recovery circuit to determine a forward strobe clock offset for improving sampling accuracy;

training at least one data bit clock recovery circuit to determine a data bit sampling clock offset for improved sampling accuracy, wherein the data bit sampling clock offset comprises the forward strobe sampling clock offset and an intermediate data bit sampling clock offset, further comprising: enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit while training the forward strobe clock recovery circuit.

12. The method of claim 11, further comprising: disabling the forward strobe clock recovery circuit and enabling the data clock recovery circuit while training the data clock recovery circuit.

13. The method of claim 11, further comprising: enabling the forward strobe clock recovery circuit and disabling the data clock recovery circuit during system operation such that the data bit sampling clock offset tracks the forward strobe sampling clock offset.

14. The method of claim 11, further comprising:

detecting at least one clock recovery event during operation of the system; and

the training of the at least one data bit clock recovery circuit is repeated.

15. The method of claim 14, wherein the at least one clock recovery event comprises:

a predetermined amount of time has elapsed since a last training of the at least one data clock recovery circuit;

an idle state of a system component including the at least one data clock recovery circuit; and

a low power state of the at least one data clock recovery circuit.

16. A receiver for receiving data, comprising:

a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock; and

at least one data bit clock recovery circuit configurable to align a data bit sampling clock and to receive a signal from the forward strobe clock recovery circuit, the at least one data bit recovery circuit configuring the data bit sampling clock to track the forward strobe sampling clock during operation, wherein in a training phase the data bit sampling clock is aligned by generating a data bit clock offset, the at least one data bit clock recovery circuit being active in the training phase, and wherein the data bit clock offset comprises an intermediate data bit clock offset combined with the signal from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset; and

wherein during operation of the at least one data bit clock recovery circuit configured to align a data bit sampling clock and receive signals from the forward strobe clock recovery circuit, the at least one data bit clock recovery circuit is inactive, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

17. The receiver of claim 16, wherein the signal received from the forward strobe clock recovery circuit includes a forward strobe clock offset, and wherein the forward strobe clock offset is combined with an intermediate data bit clock offset to produce a data bit clock offset.

18. The receiver of claim 16, wherein:

during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and

the at least one data bit clock recovery circuit aligns the data bit sampling clock during a data bit training phase, the forward strobe clock recovery circuit being inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

19. The receiver of claim 16, wherein the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of a plurality of data bits received by the receiver.

20. The receiver of claim 19, wherein the at least one data bit clock recovery circuit includes a phase detector that receives the corresponding data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

21. The receiver of claim 20, wherein the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

22. The receiver of claim 21, wherein the early/late indication is divided by a predetermined number before being received by the phase counter.

23. The receiver of claim 21, wherein the at least one data bit clock recovery circuit further comprises an adder that adds the intermediate data bit clock offset to the signal received from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

24. The receiver of claim 23, wherein the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives an output of the adder and generates the recovered data clock signal.

25. A method for receiving data, comprising:

in response to receiving the forward strobe, the forward strobe clock recovery circuit aligns the forward strobe sampling clock; and

at least one data bit clock recovery circuit aligns a data bit sampling clock to track the forward strobe sampling clock during operation;

wherein: during a forward strobe training phase, the forward strobe clock recovery circuit aligns the forward strobe sampling clock, including generating a forward strobe clock offset; and

the at least one data bit clock recovery circuit aligns the data bit sampling clock during a data bit training phase, the forward strobe clock recovery circuit being inactive during the data bit training phase, wherein the signal received from the forward strobe clock is the forward strobe offset, which is combined with an intermediate data clock offset to produce a data bit clock offset.

26. The method of claim 25, wherein the signal received from the forward strobe clock recovery circuit includes a forward strobe clock offset, and wherein the forward strobe clock offset is combined with an intermediate data bit clock offset to produce a data bit clock offset.

27. The method of claim 25, wherein during a training phase, the data bit sampling clocks are aligned by generating a data bit clock offset, the at least one data bit clock recovery circuit being active during the training phase, and wherein the data bit clock offset comprises an intermediate data bit clock offset combined with a signal from the forward strobe clock recovery circuit, wherein the signal comprises a forward strobe clock offset.

28. The method of claim 27, wherein during operation of the method the at least one data bit clock recovery circuit is inactive, the intermediate data bit clock offset is fixed, and the data bit clock offset varies with the forward strobe clock offset.

29. The method of claim 25, wherein the at least one data bit clock recovery circuit comprises a data bit clock recovery circuit for each of the received plurality of data bits.

30. The method of claim 29, wherein the at least one data bit clock recovery circuit includes a phase detector that receives the corresponding data bit and the recovered data clock signal and outputs an early/late indication representative of the phase difference.

31. The method of claim 30, wherein the at least one data bit clock recovery circuit further comprises a phase counter that receives the early/late indication and outputs an intermediate data bit clock offset.

32. The method of claim 31, wherein the early/late indication is divided by a predetermined number before being received by the phase counter.

33. The method of claim 31, wherein said at least one data bit clock recovery circuit further comprises an adder that adds said intermediate data bit clock offset to a signal received from said forward strobe clock recovery circuit, wherein said signal comprises a forward strobe clock offset.

34. The method of claim 33, wherein the at least one data bit clock recovery circuit further comprises a clock phase delay circuit that receives an output of the adder and generates the recovered data clock signal.