HK1121731B - Thin package for a micro component - Google Patents

Description

Thin package for micro components

Technical Field

The present disclosure relates to packaging of micro components.

Background

Proper packaging of optoelectronic and other micro-components is important to ensure the integrity of the signals to and from the micro-components and often determines the overall cost of the assembly.

U.S. patent No.6,818,464, assigned to the assignee of the present application, discloses techniques for making packages that may be used to house, for example, optoelectronic devices. As disclosed in that patent, the opto-electronic component may be mounted to a substrate. A semiconductor cap (cap) may be attached to the substrate to hermetically seal the optoelectronic component. Feed-through metallization through the cap may be used to provide electrical connections from the exterior of the cap to the optoelectronic components housed inside the package.

Typically, the thickness of the semiconductor wafer used for the cap in such a package may be on the order of at least several hundred microns (e.g., 300-700 μm). However, for some applications, thinner caps may be required. Unfortunately, thin caps are more difficult to handle and may result in lower yields.

Disclosure of Invention

Techniques are disclosed for making relatively thin packages for housing one or more micro components. For example, the package may be fabricated in a wafer-level batch process.

According to one aspect, a method of fabricating a package for a micro component may include bonding a first wafer to a second wafer so that the micro component is located in an area defined by the first and second wafers, and then thinning the first wafer from its backside.

In some embodiments, the package can include feed-through metallization that couples the micro component to electrical contacts on the exterior surface of the package. Thus, according to another aspect, a method is disclosed for fabricating a package for a micro component located in an area defined by first and second wafers bonded together. The first wafer includes feed-through metallization that at least partially fills micro-vias from a front side of the first wafer, and the feed-through metallization forms part of one or more electrical paths to or from the micro component. The method may include thinning the first wafer from its backside.

The disclosed techniques can provide a relatively thin micro component package that can be fabricated such that the likelihood of damaging the package during wafer processing is reduced.

Other features and advantages will become apparent from the following detailed description, the accompanying drawings, and the claims.

Drawings

Fig. 1 shows a cross-sectional view of a micro component package according to an embodiment of the invention.

FIG. 2 shows a side view of a semiconductor wafer with cavities and micro-vias for a cap structure of a package.

Fig. 2A and 2B are top views of respective semiconductor wafers showing examples of possible locations of micro-vias for feed-through metallization.

Fig. 3 and 4 show side views of the wafer of fig. 2 after further processing.

Fig. 5 shows a semiconductor wafer with a cap structure bonded to a second wafer, where a micro component is machined or mounted thereon.

FIG. 6 shows the wafer of FIG. 5 after thinning the backside of the wafer with the cap structure.

Fig. 7 and 8 show packages with alternative cap structures for larger micro-components.

Fig. 9-13 illustrate another process for fabricating a package for a micro component in which a backside wafer thinning technique exposes previously deposited feed-through metallization.

Fig. 14-23 illustrate another process for fabricating a package for micro components mounted on or integrated with the same wafer, in which feed-through metallization is provided and which includes backside wafer thinning techniques.

Fig. 24 shows a package that includes inlet/outlet fluidic channels from a micro component.

Fig. 25 illustrates a package that includes multiple micro components housed in different enclosed areas of the package.

Fig. 26 is a side view of a package including a capacitive element.

Fig. 27A is a side view of a package including an inductive element.

Fig. 27B is a top view of the package of fig. 27A.

Fig. 28 is a side view of a package including a pressure sensing membrane in an SOI layer.

Detailed Description

As shown in fig. 1, the package 20 includes a cap 22 and a substrate (or base) 24. The cap 22 may comprise, for example, a semiconductor material such as silicon. The substrate 24 may also comprise a semiconductor material such as silicon or a glass material. The micro component 26 is mounted to or integrated with the base 24, and the base 24 may be bonded to the cap 22, for example, by a sealing ring 28. The micro component 26 may be hermetically sealed within the package.

As used in this disclosure, the phrase "micro component" includes integrated circuit devices, electronic devices, optical devices, electromagnetic devices, chemical devices, micromechanical devices, optoelectronic devices, microelectromechanical systems (MEMS) devices, micro-opto-electromechanical systems (MOEMS) devices, or other such devices containing elements of micro, micron, and sub-micron dimensions.

Conductive lines 30 may extend along the surface of the base 26 from the micro component 26 to conductive bumps 32, the conductive bumps 32 electrically connected to feed-through metallization 34 extending through micro-vias in the cap 22. At the outer surface of the cap 22, the feed-through metallization serves as surface mount pads 35, which in turn may be electrically coupled to solder bumps 36. The solder bumps 36 may be connected to, for example, a printed circuit board (not shown). Using the techniques described in this disclosure, the final thickness of the cap 22 may be made as small as 200 μm or less for some embodiments.

Multiple packages may be fabricated simultaneously in a wafer-level batch process. For example, a plurality of cap structures (which may be referred to as "cap-wafers") may be fabricated on a first wafer. The cap-wafer may then be bonded to a second wafer (which may be referred to as a "device wafer") on which the micro components are mounted. The device wafer may be used as a substrate to form a base of a package.

As explained in more detail below, the cap-wafer may have an initial thickness of, for example, about several hundred microns (e.g., 300-700 μm). The wafer may have a diameter of, for example, four inches. Larger diameter wafers (e.g., 6 inches) may also be suitable for some embodiments. After the cap-wafer is bonded to the device-wafer, mechanical grinding or other processes may be used to thin the backside of the cap-wafer so that the resulting cap has a desired thickness, which may be as small as 200 μm or less. The wafer may then be provided with solder bumps, reflowed, and diced to form individual packages that house the micro components.

One process that may be used to fabricate multiple cap structures on a wafer employs a double-sided etching technique. As shown in fig. 2, a double-sided etching technique may be used to form a large cavity 38 on the backside 40 of the cap-wafer. The cavities serve as boundaries between adjacent cap structures.

During the double-sided etching process, micro-vias 44 for feed-through metallization may be etched from the front side 42 of the cap-wafer. Preferably, the micro-vias are formed near the edges of the cavity 38, for example as shown in fig. 2A. In some embodiments, every other chip may be rotated 90 °, for example as shown in fig. 2B. The cavities 38 and micro-vias 44 may be formed using a variety of etching techniques depending on the material of the cap-wafer.

The wafer suitable for forming the cap 22 may have, for example, a multilayer structure comprising a layer substantially resistant to etching sandwiched between first and second semiconductor layers. The first and second semiconductor layers may include, for example, silicon, and the etch-resistant layer may include, for example, silicon nitride, silicon oxynitride, or silicon dioxide. One suitable etching technique utilizes a KOH wet etch. Further details of examples of multilayer structures and etching techniques are disclosed in the aforementioned U.S. patent No.6,818,464. The entire contents of which are incorporated herein by reference. Other wafer structures and other etching techniques may also be used. For example, although FIG. 2 shows the sidewalls of the cavity 38 as being sloped, other etching techniques may result in substantially vertical sidewalls.

As can be seen from the example of fig. 2, after the cavities 38 and micro-vias 44 are formed, the cap wafer may still have a total thickness on the order of several hundred microns (e.g., 300-700 μm). Such a thickness facilitates subsequent processing and handling of the cap-wafer and reduces the likelihood of damage that may occur if the wafer is thin.

After the cavities 38 and micro-vias 44 are formed, the micro-vias may be hermetically sealed, for example, using an electroplated feed-through metallization technique (see fig. 3 and 4). The feed-through metallization may also comprise a diffusion barrier and the sealing material may comprise, for example, a non-noble metal. Further details of such feed-through metallization techniques are disclosed in the aforementioned U.S. patent No.6,818,464.

Conductive bumps 32 are disposed on the front side of the cap-wafer in electrical contact with the feed-through metallization.

The cap-wafer may then be bonded to a device-wafer that serves as a substrate on which the micro components are mounted (see fig. 5). The cap-wafer and the device-wafer are aligned such that the conductive bumps 32 contact conductive lines 30 extending from the micro-component 26 along the surface of the substrate 24 and such that the micro-component conforms within the region 46 between the wafers. As discussed above, the sealing ring 28 may provide a seal such that the micro component 26 is hermetically seated in the area 46.

After the cap-wafer and the device-wafer are bonded, as shown, for example, in FIG. 5, the backside of the cap-wafer is thinned to a desired thickness, as shown, for example, in FIG. 6. A variety of techniques may be used for the thinning process, including mechanical grinding or polishing techniques. Thinning of the cap-wafer after it is bonded to the device-wafer, rather than being performed in advance, may reduce the likelihood of damage occurring during subsequent processing of the thin cap-wafer.

The amount of thinning will vary depending on the particular application. However, the degree of thinning can be quite large, and in some embodiments can be on the order of 50 μm to several hundred microns. Thus, the final thickness of the cap-wafer may be in the range of about 30-70% of the initial wafer thickness for some embodiments. The cap-wafer may be thinned to a final thickness as small as 200 μm or less. Preferably, the wafer should not be thinned to a height of less than about 10 μm above the backside pads 35. Otherwise, there is a risk of damaging the pad 35.

After thinning the backside of the cap-wafer, a screen printing or other process may be performed to provide solder bumps 36 on the backside pads 35 (see fig. 1).

The wafer may then be diced to form individual packages, each housing one or more micro components.

The foregoing techniques may provide a relatively thin micro component package that includes hermetically sealed feed-through electrical connections coupling the micro component to electrical contacts on an exterior surface of the package.

In various embodiments, the height of the cavity 46 in which the micro component is disposed may be as small as the height of the sealing ring 28, which may be, for example, about 5-50 μm. In those cases where the height of the micro component is greater than that height or greater than the height of the sealing ring 28, additional cavities 50 may be provided in the front-side surface of the cap-wafer, as shown, for example, in fig. 7 and 8. The cavity 50 provides additional space so that thicker micro-components can fit in the area 46. As discussed in connection with the embodiment of fig. 1, the backside of the cap-wafer of fig. 7 and 8 may be thinned to a desired thickness after the cap-wafer is bonded to the device-wafer.

In the foregoing embodiments, the through vias 44 extending from the front side 42 to the back side 40 of the wafer may be formed in the cap structure 22 prior to providing the feed-through metallization (see, e.g., fig. 2 and 4). In other embodiments, the micro-vias for the feed-through metallization need not extend completely through the wafer before the feed-through metallization is provided. Fig. 9-13 illustrate an example of one such technique in which micro-vias are formed that extend only partially through the wafer, and feed-through metallization is provided in the micro-vias. In a subsequent back side wafer thinning process, the feed-through metallization is exposed so that electrical contacts to the feed-through metallization can be provided.

As shown in fig. 9, micro-vias (e.g., V-grooves) 44 are etched into the front-side surface of the semiconductor wafer providing the cap structure 22. The depth of the micro-vias 44 may be as small as about 200 μm or less. The interior surface of the micro-vias may be oxidized to provide isolation between the feed-through metallization (fig. 10) and the semiconductor material of the cap structure 22. As shown in fig. 10, a seal ring 28 and a conductive protrusion 32 are also provided on the front face of the cap 22. The cap-wafer may then be bonded to the device-wafer, as shown in FIG. 11. As can be seen in fig. 11, at this stage of the fabrication process, the feed-through metallization 34 is still not exposed at the backside 40 of the cap-wafer. Next, as shown in fig. 12, a grinding or polishing process is performed on the backside 40 of the cap-wafer until the feed-through metallization 34 is exposed. Subsequently, a photosensitive polymer 50, such as benzocyclobutene (BCB) or polyimide (polyimide), is deposited on the back side 40 of the wafer (fig. 13). Openings are made in the polymer 50 and conductive contact pads and solder 52 are deposited so that the package can be connected to, for example, a printed circuit board (not shown).

In the foregoing example approach, the micro component is mounted in or integrated with a wafer that is bonded to another wafer having a cap structure (including feed-through metallization). In other embodiments, the micro component may be mounted on or integrated with the same wafer in which the feed-through metallization is provided. The wafer is then bonded to another semiconductor or glass wafer that serves as a package lid. This technique is illustrated in fig. 14-23 and allows for a backside wafer thinning technique for post-processing of the device wafer.

As shown in fig. 14, shallow redistribution grooves 102 with sloped sidewalls may be etched in a first semiconductor wafer 100, which may include, for example, an etch-resistant layer (e.g., a buried oxide layer) 106 sandwiched between a relatively thin (e.g., 10 μm) semiconductor layer 104 and a relatively thick (e.g., 400-. As will become apparent from the discussion below, the shallow grooves 102 may facilitate redistribution of electrical connections from the micro components to contacts on the back side of the wafer.

In a particular embodiment, the first wafer 100 may have a diameter of, for example, 6 inches. The semiconductor layers 104, 108 may comprise, for example, silicon. The thickness of the buried oxide layer may have a thickness of, for example, about 1000 nanometers (nm), and the depth of the redistribution grooves 102 may be about 2-3 μm. In other embodiments different dimensions may be appropriate. A dry etch may be used to form redistribution grooves 102.

As shown in fig. 15, micro-vias 110 are formed in respective distal ends of the redistribution grooves 102, for example, by a dry etching technique. The micro-vias may be etched until the surface of the etch-resistant layer 106 is exposed. Next, as shown in fig. 16, a timed Buffered Hydrogen Fluoride (BHF) etch may be performed to expand the depth of the micro-via portion into the buried oxide layer 106. In a specific embodiment, the micro-vias 110 are etched approximately half way through the oxide layer 106. The front and back sides of wafer 100 are then covered with an oxide layer 116 (see fig. 17A), which may have a thickness of, for example, about half the thickness of buried oxide layer 106. The oxide layer 116 may be formed using a thermal oxidation process. Assuming, for example, that layers 104 and 108 are silicon and etch stop layer 106 is silicon oxide, then thermally grown oxide layer 116 will cover the surfaces of silicon layers 104 and 108.

As shown in fig. 17A, micro components 114 may be mounted on the wafer area between the micro-vias 110. The relatively deep micro-vias may be small and far away from the micro-feature so as not to interfere with the lithography step. Fig. 17B shows a top view of the wafer after the micro component 114 is mounted.

As shown in fig. 18, a conductive line, such as an electroplated gold line 118, is provided from the micro component 114 to the bottom of the micro-via 110. Preferably, the thickness of the metal 118 is less than the depth of the redistribution grooves. The bottom of the micro-vias 110 as well as the lower portion of the sidewalls should be completely covered with metal. Further processing of the micro component may also be performed at this stage. For example, if the micro component is a MEMS device, the sacrificial layer may be etched away.

As shown in fig. 19, a semiconductor or glass cap wafer 120 is bonded to the first wafer 100 so that the micro component 114 is seated within the area defined by the two wafers 100, 120. A variety of bonding techniques may be used such as anodic bonding, frit reflow, thermocompression bonding, or solder reflow. If a metal seal is used to bond the wafers, the gold wires 118 may need to be passivated.

After bonding the wafers, a grinding or other thinning process may be performed relative to the backside of the device wafer 100. The remaining thickness of the back side silicon layer 108 may be as small as about 50-100 μm. Preferably, the remaining silicon layer 108 should be thinner than the final height of the electrical bump (see fig. 23).

To expose the metal 118 in the micro-vias 110, a dry etch technique with a photoresist mask may be used to etch cavities 122 with sloped sidewalls in the backside of the silicon layer 108 (fig. 21). During the dry etch, buried oxide layer 106 may serve as an etch stop. Next, as shown in fig. 22, the metallization 118 at the bottom of the micro-vias 110 may be exposed, for example, using BHF to partially etch through the thin buried oxide layer 106 and any plating base (e.g., titanium) that may be used during the gold plating process. As shown in fig. 22, the BHF etch stops when the feed-through metallization is exposed, and a thin layer of buried oxide 106 remains on the back side of the wafer 100. The remaining oxide 106 provides isolation between the semiconductor material 104 and electrical connections (124, 126) that are subsequently provided on the backside of the wafer 100 in contact with the feed-through metallization (see fig. 23). In a specific embodiment, the thickness of the remaining oxide layer 106 is approximately half the original thickness of the buried oxide layer.

As shown in fig. 23, the backside metallization 124 may be provided, for example, by using a gold titanium (TiAu) plating base and a copper (Cu) plating. The solder bumps 126 or other electrical contacts may be provided, for example, by a solder screening and reflow process. The solder bumps 126 may be connected to, for example, a printed circuit board (not shown). The wafer may then be diced to form individual packages, each housing one or more micro components and each package being relatively thin.

In the embodiment of fig. 14-23, the post-processing steps, including back-side thinning of the device wafer, may be performed by an entity other than the entity that fabricated the micro components and either integrated them with the device wafer or mounted them on the device wafer. In other cases, the same entity may perform the pre-processing and post-processing steps.

In some embodiments, the micro component may comprise a MEMS-based system for fluid analysis. In such a case, the MEMS device may comprise, for example, a micro pump or a chemical sensor. Additional grooves may be provided in the above-described package to serve as inlet and outlet channels for the fluid.

Fig. 24 illustrates one such inlet/outlet channel 130, which may be formed simultaneously with the redistribution grooves 102 (fig. 14). Multiple inlet/outlet channels may be provided for micro component 114 and may be routed to the edge of the package. For example, in particular embodiments, a pair of inlet/outlet channels may be disposed on the same side of the package, with the inlet channels disposed on one side of the redistribution grooves and the outlet channels disposed on the other side of the redistribution grooves. The width of the inlet/outlet channels 130 may be different from the width of the redistribution grooves.

The package may contain more than one micro component, for example as shown in fig. 25. Further, one portion of the package may include a micro component 114A and an inlet/outlet channel 130 for fluid analysis, while another portion of the package may include a micro component 114B hermetically sealed within the package. Various electrical interconnects may be provided to and from the micro components. For example, electrical connections may be provided from the micro component 114B to the SMD bumps 126. Additionally, electrical interconnects 132 may be provided to electrically connect the micro components 114A, 114B. The feed-through metallization 118 provides a portion of the electrical path from the micro component to the contacts on the back side of the package.

Other features may be present in some embodiments. For example, capacitors or inductors may be integrated into the package, and in particular, they may be integrated into the cap-wafer. Fig. 26 shows an example of an integrated capacitor structure that includes metallization on either side of the SOI layer (i.e., silicon layer 104 on oxide layer 106)Surfaces 140, 142. Metallization 140 may be formed on the front side of device wafer 100 simultaneously with feed-through metallization 118. Metallization 142 may be disposed on the back side of wafer 100 at the same time as back side metallization 124. Thus, the capacitive element can be formed without an additional process step. In some embodiments, due to the very thin SOI layer, it may be as small as 100 μm²A capacitor having a large capacitance (e.g., 1-10 nanofarads) is formed over the area of (a).

Fig. 27A and 27B show examples of inductive micro-coils integrated into a package. Metallization 150 in the form of coils may be provided on the front side of the device wafer 100, for example, and routed through micro-vias toward the back side. Metallization 152 on the back side of wafer 100 is routed through a second micro-via extending through oxide layer 106 and providing an electrical connection to front side metallization 150. Front side metallization for the coil may be provided simultaneously with the feed-through metallization 118. Similarly, the back side metallization 152 may be provided simultaneously with the metallization 124. Thus, the inductive element can be formed without additional process steps. The cap wafer 120 may include additional headroom 154 above the micro-coil 150 to help reduce magnetic losses in the coil.

Fig. 28 shows an example of a thin film 160 formed in the device layer of the SOI wafer. The membrane 160 may for example be used as part of a pressure sensor or for detecting pressure changes inside the package by small deflections of the membrane. The small pressure variations can be converted into electrical signals using known techniques, which can be used as an indicator of possible leaks in the package and as an alarm for possible failure of the micro component due to the leak.

The micro component is located in an area defined by first and second wafers (e.g., a cap wafer and a lid wafer). Although the figures show the micro component mounted on one of the wafers, in some embodiments the micro component may be integrated within one of the wafers.

Other implementations are within the scope of the following claims.

Claims (44)

1. A method of making a package for a micro component, the method comprising:

bonding a first chip to a second chip such that a micro component is located in an area defined by a front side of the first chip and the second chip, and the micro component is disposed on the second chip, wherein the first chip comprises feed-through metallization that at least partially fills micro-vias from the front side of the first chip, and wherein the feed-through metallization forms part of one or more conductive paths to or from the micro component when the first and second chips are bonded together;

providing a cavity in the back side of the first chip opposite the micro-via in the front side of the first chip, wherein the position of the cavity corresponds to the position of the micro-via;

providing a conductive contact within the cavity on the back side of the first chip, which is electrically coupled to the feed-through metallization; and

the first chip is subsequently thinned from its backside.

2. The method of claim 1, wherein the thinning comprises thinning the first chip to a thickness of 200 μ ι η or less.

3. The method of claim 1, wherein the thinning comprises thinning the first chip to a thickness of 100 μ ι η or less.

4. The method of claim 1, comprising thinning the first chip to a thickness of less than 50% of its original thickness.

5. The method of claim 1, wherein thinning the back side of the first chip comprises using a mechanical process.

6. The method of claim 4, wherein thinning the back side of the first die comprises grinding the back side of the first die.

7. The method of claim 1, wherein the micro component is mounted on or integrated with the second chip.

8. The method of claim 7, comprising providing a cavity in the front side of the first chip to provide space for the micro component.

9. The method of claim 1, wherein the micro component is mounted to or integrated with the first chip.

10. The method of claim 9, comprising providing a cavity in the front side of the second chip to provide space for the micro component.

11. The method of claim 1, comprising forming a cavity and providing a conductive contact prior to thinning the back side of the first chip.

12. The method of claim 1, wherein thinning the back side of the first chip exposes the feed-through metallization, the method comprising providing electrical contacts at the back side of the first chip to contact the exposed feed-through metallization.

13. The method of claim 1, comprising:

removing material from the backside of the first chip after the thinning to expose the feed-through metallization; and

electrical contacts are provided at the back side of the first chip to contact the exposed feed-through metallization.

14. The method of claim 13, wherein removing material from the backside of the first chip comprises partially etching away the buried oxide layer or other isolation etch stop layer to expose the feed-through metallization.

15. The method of claim 1, wherein the first chip comprises a semiconductor material and the second chip comprises glass or a semiconductor material.

16. The method of claim 1, comprising:

forming a micro-via in a front side of a first chip; and

providing feed-through metallization in the micro-vias, wherein the feed-through metallization forms part of one or more electrical paths to or from the micro-component when the first and second chips are bonded together, and

wherein said thinning of the first chip is performed after providing feed-through metallization in the micro-vias.

17. The method of claim 1, comprising:

forming a shallow recess in the front side of the first chip adjacent to the area for the micro component before bonding the first and second chips together; and is

A respective one of the micro-vias is formed in each shallow groove toward the end further away from the area for the micro-feature.

18. The method of claim 1, wherein the method is part of a chip-scale batch process.

19. The method of claim 1, wherein at least one of the chips is an SOI chip.

20. The method of claim 1, wherein at least one of the chips comprises a semiconductor layer on the isolation layer.

21. A method of fabricating a package for a micro component located in an area defined by first and second chips bonded together and disposed on a front side of the first chip, wherein the first chip includes feed-through metallization that at least partially fills micro-vias from the front side of the first chip, and wherein the feed-through metallization forms part of one or more electrical paths to or from the micro component, the method comprising thinning the first chip from its back side;

providing a cavity in the back side of the first chip opposite the feed-through metallization, wherein the position of the cavity corresponds to the position of the micro-via; and

providing a conductive contact within the cavity on the back side of the first chip, which is electrically coupled to the feed-through metallization,

wherein the forming of the cavity and the providing of the conductive contact are performed after thinning the backside of the first chip.

22. The method of claim 21, wherein the thinning comprises thinning the first chip to a thickness of 200 μ ι η or less.

23. The method of claim 21, said thinning comprising thinning the first chip to a thickness of 100 μ ι η or less.

24. The method of claim 21, comprising thinning the first chip to a thickness of less than 50% of its original thickness.

25. The method of claim 21, wherein thinning the back side of the first chip comprises using a mechanical process.

26. The method of claim 25, wherein thinning the back side of the first die comprises grinding the back side of the first die.

27. The method of claim 21, wherein thinning the back side of the first chip exposes the feed-through metallization, the method comprising providing electrical contacts at the back side of the first chip to contact the exposed feed-through metallization.

28. The method of claim 21, comprising:

etching from the backside of the first chip after the thinning to expose the feed-through metallization; and

electrical contacts are provided at the back side of the first chip to contact the exposed feed-through metallization.

29. A package comprising a first micro component located in a region defined by a semiconductor structure and a lid structure bonded to the semiconductor structure, wherein the semiconductor structure has a thickness of about 200 μ ι η or less and comprises feed-through metallization in a micro-via extending from a front side of the semiconductor structure to a back side of the semiconductor structure, and a cavity in the back side of the semiconductor structure, wherein a location of the cavity corresponds to a location of the micro-via and comprises an electrically conductive contact disposed in the cavity electrically coupled with the feed-through metallization, and wherein the feed-through metallization forms part of one or more electrically conductive paths to or from the micro component.

30. The package of claim 29, wherein the semiconductor structure has a thickness of about 100 μm or less.

31. The package of claim 29, wherein the micro component is mounted on or integrated in the front side of the semiconductor structure.

32. The package of claim 29, wherein the micro component is mounted on or integrated in the lid structure.

33. The package of claim 29, wherein the micro component is an electronic device.

34. The package of claim 29, wherein the micro component is a photovoltaic device.

35. The package of claim 29 wherein the micro component is a micro-electromechanical systems device.

36. The package of claim 29, wherein the micro component is a micro-opto-electro-mechanical system device.

37. The package of claim 29 comprising a shallow recess in the front side of the semiconductor structure, wherein the shallow recess is at least partially filled with a conductive material to provide a conductive path connecting the micro component to the feed-through metallization in the micro-via.

38. The package of claim 29, comprising inlet and outlet channels from the micro component to the package periphery, wherein the inlet and outlet channels allow fluid to be provided to or from the micro component.

39. The package of claim 29, comprising a second micro component located in a region between the semiconductor structure and the lid structure, wherein the semiconductor structure comprises additional feed-through metallization in a micro-via extending from a front side of the semiconductor structure to a back side of the semiconductor structure, wherein the additional feed-through metallization forms part of one or more conductive paths to or from the second micro component, and wherein first and second micro components are electrically coupled by a contact at the back side of the semiconductor structure.

40. The package of claim 39, wherein a first micro component is hermetically sealed in a first region of the package, and wherein the package comprises inlet and outlet channels from a second micro component to a periphery of the package, wherein the inlet and outlet channels allow fluid to be provided to or from the second micro component.

41. The package of claim 40 wherein the second micro component is a MEMS device for fluid analysis.

42. The package of claim 29 wherein the semiconductor structure comprises a silicon-on-insulator structure and the feed-through metallization extends through the silicon-on-insulator structure, and

wherein the package includes a capacitive component comprising a portion of the silicon-on-insulator structure having metallization on its front and back side surfaces.

43. The package of claim 29 wherein the semiconductor structure comprises a silicon-on-insulator structure and the feed-through metallization extends through the silicon-on-insulator structure, and

wherein the package includes an inductive component comprising a micro-coil on front and back side surfaces of the semiconductor structure, wherein the micro-coil is electrically coupled to metallization on opposite sides of the semiconductor structure through feed-through metallization.

44. The package of claim 29 wherein the semiconductor structure comprises a silicon-on-insulator structure and the feed-through metallization extends through the silicon-on-insulator structure, and

wherein a portion of the silicon-on-insulator structure functions as a membrane to detect changes in pressure.