HK1121601B - A method and system for wire communication - Google Patents

Description

Method and system for wired communication

Technical Field

The present invention relates to high-speed wired communication, and more particularly, to a method and system for a non-symmetric physical layer (PHY) in a long-distance (extended reach) ethernet local area network.

Background

As the number of devices connected to data networks increases and the demand for high speed data transmission rates increases, the need for new technologies for high speed data transmission over existing cable infrastructure increases. In this regard, various techniques exist, including techniques that have transmission rates in excess of gigabits per second over existing cables. For example, the IEEE 802.3 standard defines the Media Access Control (MAC) interface and physical layer (PHY) for ethernet connections that transmit at 10Mbps, 100Mbps, 1Gbps, and 10Gbps data rates over 100 meters long twisted pair copper cable. For every 10-fold increase in data rate, more complex signal processing methods are required to maintain the range of a 100 meter long standard cable. However, connections that are more than 100 meters long may require the placement of ethernet switches, hubs, and/or repeaters with fiber optics or at the midpoint of the connection to make all cables less than 100 meters in length.

Additional research has included developing standards for 10Gbps ethernet transmission over twisted pair cable (10 GBASE-T). The emerging 10GBASE-T physical layer specification aims to achieve 10Gbps data rates over existing twisted pair wires at distances up to 182 feet and over new cables up to 330 meters. To achieve 10Gbps full duplex transmission over a 4-pair twisted-pair copper cable requires elaborate digital signal processing techniques to eliminate or reduce frequency-dependent signal attenuation, signal reflection, near-end and far-end crosstalk between the 4 wire pairs, and external signals coupled into the 4 wire pairs from adjacent transmission links or other external noise sources. While new cable standard specifications are being developed to reduce susceptibility to external electromagnetic interference, existing systems may become expensive due to the various signal processing methods used to reduce the above-described effects. Even with these techniques, the current need for longer travel distances remains unmet.

It may be the case that the data rate in one direction is more demanding than the data rate in the opposite direction, as is the case, for example, with the transmission of interactive video from a central office to a consumer. In this case, the data rate for transmitting the video data in one direction is much greater than the data rate for transmitting the interactive command in the opposite direction. The current IEEE 802.3 ethernet standard only defines symmetric links that can support the same data rate in both directions. As a result, receivers with low data rates may support higher computational complexity than those needed to receive low data rates.

The limitations and disadvantages of the latter will become apparent to one of skill in the art, through comparison of a system having certain features of the present invention with a conventional, general method, as described in the remainder of the specification in conjunction with the embodiments of the present drawings.

Disclosure of Invention

A system/method for a non-symmetric physical layer in a long-range ethernet local area network, as shown in and/or described in at least one of the figures, as set forth more completely in the claims.

One aspect of the present invention provides a method for wired communication, the method comprising:

reducing a communication rate of an asymmetric multiple data rate physical layer from a higher communication rate to a lower communication rate;

applying signal processing operations supported by the asymmetric multiple data rate physical layer in relation to the higher communication rate to the lower communication rate.

Preferably, the asymmetric multiple data rate physical layer is an asymmetric ethernet multiple data rate physical layer.

Preferably, the method further comprises allocating the reduced communication rate on at least one of: the uplink portion and the downlink portion of the lower communication rate.

Preferably, the method further comprises aggregating the lower-rate upstream portion by evenly distributing the upstream portion over each twisted pair used in the copper cable.

Preferably, the method further comprises aggregating the lower rate downlink portion by evenly distributing the downlink portion over each twisted pair used in the copper cable.

Preferably, the method further comprises aggregating the lower-rate upstream portion by non-uniformly distributing the upstream portion over each twisted pair used in the copper cable

Preferably, the method further comprises aggregating the lower communication rate downstream portion by non-uniformly distributing the downstream portion over each twisted pair used in the copper cable.

Preferably, the method further comprises reducing the communication rate from a higher symbol rate to a lower symbol rate.

Preferably, the signal processing operation associated with the higher communication rate comprises at least one of an ECHO (ECHO) cancellation operation, a NEXT cancellation operation, and a FEXT cancellation.

Preferably, the signal processing operation associated with the higher communication rate comprises an equalization operation.

Preferably, the method further comprises communicating at said lower communication rate with a cable having a higher insertion loss than a cable associated with said higher communication rate.

According to another aspect of the invention, there is provided a machine readable storage, having stored thereon, a computer program having at least one code section for performing wired communications, the at least one code section being executable by a machine for causing the machine to perform the steps of:

reducing a communication rate of an asymmetric multiple data rate physical layer from a higher communication rate to a lower communication rate;

applying signal processing operations supported by the asymmetric multiple data rate physical layer in relation to the higher communication rate to the lower communication rate.

Preferably, the asymmetric multiple data rate physical layer is an asymmetric ethernet multiple data rate physical layer.

Preferably, the machine-readable storage further comprises code for allocating the reduced communication rate on at least one of: the uplink portion and the downlink portion of the lower communication rate.

Preferably, the machine-readable storage further comprises code for aggregating the lower-rate upstream portion by evenly distributing the upstream portion over each twisted pair used in the copper cable.

Preferably, the machine-readable storage further comprises code for aggregating downstream portions of the lower communication rate by evenly distributing the downstream portions over each twisted pair used in a copper cable.

Preferably, the machine-readable storage further comprises code for aggregating the upstream portion of the lower communication rate by non-uniformly distributing the upstream portion over each twisted pair used in the copper cable.

Preferably, the machine-readable storage further comprises code for aggregating downstream portions of the lower communication rate by non-uniformly distributing the downstream portions over each twisted pair used in a copper cable.

Preferably, the machine-readable storage further comprises code for reducing the communication rate from a higher symbol rate to a lower symbol rate.

Preferably, the signal processing operations associated with the higher communication rate include at least one of ECHO cancellation operations, NEXT cancellation operations, FEXT cancellation.

Preferably, the signal processing operation associated with the higher communication rate comprises an equalization operation.

According to another aspect of the present invention, the present invention also proposes a system for wired communication, the system comprising:

a circuit to reduce a communication rate of an asymmetric multiple data rate physical layer from a higher communication rate to a lower communication rate;

applying signal processing operations supported by the asymmetric multiple data rate physical layer associated with the higher communication rate to the lower communication rate circuitry.

Preferably, the asymmetric multiple data rate physical layer is an asymmetric ethernet multiple data rate physical layer.

Preferably, the system further comprises circuitry for allocating the reduced communication rate at least one of: the uplink portion and the downlink portion of the lower communication rate.

Preferably, the system further comprises circuitry for aggregating the lower-rate upstream portion by evenly distributing the upstream portion over each twisted pair used in the copper cable.

Preferably, the system further comprises circuitry for aggregating the lower rate downstream portion by evenly distributing the downstream portion over each twisted pair used in the copper cable.

Preferably, the system further comprises circuitry for aggregating the lower-rate upstream portion by non-uniformly distributing the upstream portion over each twisted pair used in the copper cable.

Preferably, the system further comprises circuitry for aggregating the lower rate downstream portion by non-uniformly distributing the downstream portion over each twisted pair used in the copper cable.

Preferably, the system further comprises circuitry to reduce the communication rate from a higher symbol rate to a lower symbol rate.

Preferably, the signal processing operations associated with the higher communication rate include at least one of ECHO cancellation operations, NEXT cancellation operations, FEXT cancellation.

Preferably, the signal processing operation associated with the higher communication rate comprises an equalization operation.

Preferably, the system further comprises circuitry for communicating at the lower communication rate with a cable having a higher insertion loss than the cable associated with the higher communication rate.

These and other advantages, aspects, and novel features of the invention, as described in the specification, will be more fully understood from the following description and drawings.

Drawings

FIG. 1 is a block diagram of a local area network configuration of a multi-subscriber unit (MTU) incorporating one embodiment of the present invention;

FIG. 2 is a block diagram of a long-range LAN configuration for multiple subscriber units with asymmetric data transmission, according to one embodiment of the present invention;

FIG. 3 is a schematic diagram of an Ethernet system incorporating an embodiment of the present invention for twisted pair copper cabling between an uplink party and a downlink party for extended range, long range asymmetric data transmission;

FIG. 4 is a block diagram of an Ethernet transceiver including an asymmetric multiple data rate physical layer in accordance with one embodiment of the present invention;

FIG. 5 is a schematic illustration of ECHO, NEXT, FEXT channel conditions in an Ethernet network in accordance with one embodiment of the present invention;

fig. 6A is a schematic diagram of gigabit signal processing operations for received signals in an ethernet system for asymmetric data transmission in accordance with one embodiment of the present invention;

FIG. 6B is a schematic diagram of separate equalization and decoded signal processing operations according to one embodiment of the present invention;

FIG. 6C is a schematic diagram of joint equalization and decoded signal processing operations according to one embodiment of the present invention;

FIG. 7 is a schematic diagram of a multiple data rate Ethernet system using gigabit signal processing resources for asymmetric data transmission in 4-wire pair extended mode in accordance with one embodiment of the present invention;

fig. 8 is a schematic diagram of an echo canceller in an uplink asymmetric multiple data rate physical layer with a downlink data rate of 10Mbps and an uplink data rate of 2Mbps in conjunction with one embodiment of the present invention;

FIG. 9 is a schematic diagram of a multiple data rate Ethernet system using gigabit signal processing resources for asymmetric data transmission in 2-wire pair extended mode in accordance with one embodiment of the present invention;

fig. 10 is a flowchart of the steps for reducing communication rates to implement a long range ethernet system using an asymmetric multiple data rate physical layer, in accordance with one embodiment of the present invention.

Detailed Description

The present invention relates to a method and system for an asymmetric physical layer in a long-range ethernet local area network. The invention comprises the following steps: in the case of Customer Premises Equipment (CPE) located in a multi-subscriber unit, the communication rate provided by the asymmetric ethernet multiple data rate physical layer in the ethernet transceiver is reduced, thereby extending the standard distance of transmission over twisted pair. The upstream and downstream data rates may be aggregated on average or non-average per twisted pair of wires in a copper cable. When operating at a higher communication rate, the asymmetric ethernet multiple data rate physical layer may support signal processing operations, such as echo cancellation and/or equalization, which are applied to the reduced communication rate to extend the range. The aim of reducing the communication rate can be achieved by reducing the symbol rate provided by the asymmetric Ethernet multi-data rate physical layer. Reducing the communication rate also makes it possible to use cables with a greater insertion loss than for standard connection distances.

When used and deployed in the broadband access market and in new residential and enterprise applications, such as providing Central Office (CO) services to Customer Premise Equipment (CPE) located in a multi-subscriber unit (MTU), the cost of implementing new ethernet application physical layer equipment beyond the long-range working range of standard distances is greatly reduced.

Fig. 1 is a block diagram of a local area network configuration for a multi-subscriber unit incorporating one embodiment of the present invention. Referring to fig. 1, this figure illustrates a local area network configuration within an MTU 100, the MTU 100 including an entry point switch (entry point switch)102, a point-to-point (PP) bridge 104, a plurality of mid-span switches/repeaters 106a, ·, 106b, and 106c, and a plurality of CPEs 108.

The ingress point switch 102 may comprise suitable logic, circuitry, and/or code that may enable data communication between a Central Office (CO) and a plurality of CPEs 108 in a local area network within the MTU 100. In this regard, the entry point switch 102 may communicate with the central office through an internet service provider using a broadband access link or connection such as a Gigabit Passive Optical Network (GPON) or an Ethernet Passive Optical Network (EPON). PP bridge 104 may comprise suitable logic, circuitry, and/or code that may enable communication between ingress point switch 102 and a plurality of midspan switches/repeaters 106 a. Each midspan switch/repeater 106a, 106b, and 106c comprises suitable logic, circuitry, and/or code that may enable communication between PP bridge 104 and a plurality of CPEs 108. Each CPE 108 may comprise suitable logic, circuitry, and/or code that may enable customer equipment, such as computers, associated with the CPE 108 to communicate with the central office via a local area network configured in the MTU 100. In this regard, the CPE 108 may provide the customer with a port to plug into its equipment for communicating with the service provider and/or provide the service provider with the ability to monitor connections with the customer premises.

In the embodiment shown in fig. 1, midspan switch/repeater 106a may be connected to multiple CPEs 108. Each CPE 108 connected to the midspan switch/repeater 106a includes a unit switch 110 comprising suitable logic, circuitry, and/or code that enables communication between a user or customer device, such as a computer 112, and the midspan switch/repeater 106 a. In addition to the lan configuration depicted in fig. 1, additional lan configurations may be used in MTU 100.

The ingress point switch 102, the PP bridge 104, the plurality of mid-span switches/repeaters 106a, 106b, and 106c, and the plurality of CPEs 108 may be communicatively connected by 4-wire twisted pair cables. In this regard, in standard ethernet applications, the distance between the ingress point switch 102 and one of the mid-span switches/repeaters 106a,.., 106b and 106c may generally extend to about 100 meters. Also, the distance between CPE 108 and one midspan switch/repeater 106a, 106b and 106c may typically extend to about 100 meters. Extending the range and distance of twisted pair cables for ethernet applications allows local area network configurations in MTU 100 to enable connection of ingress point switch 102 to CPE 108 without the need for a mid-span switch/repeater. This approach may reduce the cost of implementing local area network configuration in the MTU 100.

In some cases, more data is transmitted from the central office to the CPEs within MTU 100 (referred to as the downstream data transmission direction) than is transmitted from a CPE to the central office (referred to as the upstream data transmission direction), or more data is transmitted from one CPE to another CPE. For example, a service at a central office, such as video-on-demand or Internet Protocol Television (IPTV), may result in an asymmetric data pattern or transmission in a local area network, such as the local area network in the MTU 100. In this regard, CPEs 108 of MTU 100 may receive high data rate transmissions from ingress point switch 102, while ingress point switch 102 may receive low data rate transmissions from CPEs 108. In this case, to reduce the overall cost and/or power consumption in the local area network configuration in the MTU 100, a simpler ingress point switch 102 may be used, use fewer signal processing operations, and/or operate at a lower speed.

The simplicity of the design of an entry point switch for asymmetric data transmission, such as entry point switch 102 for example, results in a lower complexity at the transmitter end than at the receiving end of the transceiver for data communication over twisted pair copper cable. In this regard, a simpler transmitter portion may handle high data rate transmissions, while a more complex receiver portion may handle lower data rate transmissions. Because high data rates can be handled without increasing the complexity of the transceiver, transceivers for asymmetric data transmission applications can reduce integrated circuit area and reduce power consumption as compared to those for symmetric data transmission.

The simple design of the transceivers for the ingress point switches allows a large number of ports to be integrated into one integrated circuit, allowing for higher port densities, and further reducing the cost and/or operation of the local area network in the MTU 100. Standard ethernet local area networks are typically used for symmetric data transmission and may not benefit from asymmetric data transmission in many MTU and enterprise local area network configurations.

In addition, asymmetric data transmission may also use different Forward Error Correction (FEC) methods in the uplink direction than in the downlink direction. In general, an FEC encoder is much simpler to implement than a corresponding FEC decoder. Most of the complexity of using a stronger coding method can be implemented in the decoder of the CPE transceiver when the stronger coding method is used in the downlink direction to allow for a higher and/or more reliable downlink data rate. The entry point switch transceiver, including the encoder of the encoding method, can still be implemented relatively simply. This also allows a large number of ports to be integrated into a single transceiver integrated circuit within the ingress point switch, increasing the higher port density and further reducing the cost of the local area network.

Figure 2 is a block diagram of a long-range local area network configuration of a multi-subscriber unit for asymmetric data transmission according to one embodiment of the present invention. Referring to fig. 2, there is shown a local area network configuration in MTU 200, including an ingress point switch 202, a point-to-point (PP) bridge 204, a plurality of PP bridges 206 a.

Ingress point switch 202 may comprise suitable logic, circuitry, and/or code that may enable asymmetric data transfer between the CO and the plurality of CPEs 208 within the local area network of MTU 200. For example, downstream data transmission in the direction from ingress point switch 202 to CPE 208 has a higher data rate than upstream data transmission in the direction from CPE 208 to ingress point switch 202. Moreover, the entry point switch 202 may regulate multiple data rate operations to extend the range or distance over which communications are made over the 4-wire twisted pair copper cable. The entry point switch 202 may also communicate with the central office through an ISP using a broadband access link or connection such as a Gigabit Passive Optical Network (GPON) or an Ethernet Passive Optical Network (EPON).

PP bridge 204 may comprise suitable logic, circuitry, and/or code that may enable non-aligned data communication between entry point switch 102 and a plurality of PP bridges 206 a. Each PP bridge 206a, 206b, 206c, and 206d may comprise suitable logic and/or code that may enable asymmetric data communications between PP bridge 204 and a plurality of CPEs 208. Each CPE 208 may comprise suitable logic, circuitry, and/or code that may enable customer equipment, such as computers, connected to the CPE 208 to asymmetrically communicate data with a central office via a local area network configured within the MTU 200. In this regard, the CPE 208 may provide a port for customers to plug into their equipment, communicate with the service provider, and/or may also provide the service provider with the ability to monitor connections with clients.

In the embodiment illustrated with reference to fig. 2, PP bridge 206a may be communicatively coupled to a plurality of CPEs 108. CPE 108, connected to PP bridge 206a, each includes a cell switch 210, which may comprise suitable logic, circuitry, and/or code that may enable asymmetric communication between a user or customer device, such as computer 212, and PP bridge 206 ad. In this regard, the downstream data rate to the CPE 208 is higher than the upstream data rate to the PP bridge.

Ingress point switch 202, PP bridge 204, plurality of PP bridges 206a,... 206b, 206c, and 206d, and plurality of CPEs 208 may be communicatively coupled by 4-wire twisted pair cables. In this regard, the distance between PP-bridge 204 and one of the CPEs 208 used in asymmetric ethernet applications may be extended beyond 100 meters, allowing ingress point switch 202 to connect to CPE 208 without the need for a mid-span switch/repeater.

Fig. 3 is a schematic diagram of an ethernet system over a twisted pair copper cable link between an uplink party and a downlink party for long range asymmetric data transmission incorporating one embodiment of the present invention. Referring to fig. 3, a system 300 is shown that includes an uplink party 302 and a downlink party 304. The uplink 302 and downlink 304 parties communicate via a cable 312. For example, the cable 312 may be a 4-pair unshielded twisted pair copper cable (UTP). Certain performance and/or specifications have been standardized with respect to UTP copper cables. For example, a category 3 cable may provide the performance required for 10Mbps ethernet transmission over twisted pair (10 BASE-T). In another example, category 5 cable may provide the performance required for 1000Mbps or 1Gbps ethernet transmission (1000BASE-T) over twisted pair. In most instances, lower category cables generally have higher insertion loss than higher category cables.

The uplink party 302 may include a computer system 306a, a Media Access Control (MAC) controller 308a, a transceiver 304 a. The downlink party 304 may include a computer system 306b, a MAC controller 308b, and a transceiver 304 b. However, the present invention is not limited in this regard.

The transceiver 310a may comprise suitable logic, circuitry, and/or code that may enable asymmetric ethernet communications, such as sending and receiving data between the uplink party 302 and the downlink party 304. In this regard, the transceiver 310a may enable high data rate transmission to the downlink party 304 while also enabling low data rate reception from the downlink party 304. Similarly, the transceiver 310b may comprise suitable logic, circuitry, and/or code that may enable asymmetric Ethernet communications between the downstream party 304 and the upstream party 302. In this regard, the transceiver 310b may transmit data to the uplink party 302 at a low data rate while also receiving data from the uplink party 302 at a high data rate.

Data transmitted and/or received by transceivers 310a and 310b may be formatted in accordance with known OSI protocol standards. The OSI model divides operation and functionality into 7 different hierarchical layers. In general, each layer in the OSI model may provide services to an adjacent higher intermediate layer. For example, a first layer, i.e., a physical layer, may provide services to a second layer, and the second layer may provide services to a third layer. In this regard, the transceiver 310a may implement physical layer operations for asymmetric data communications with the downlink party 304. In addition, the transceiver 310a may implement physical layer operations for asymmetric data communications with the uplink party 302.

Transceivers 310a and 310b may implement asymmetric multiple data rate communications. In this regard, the data rate in the upstream direction and/or the data rate in the downstream direction may be < 10Mbps, 100Mbps, 1000Mbps (i.e., 1Gbps), and/or 10 Gbps. Transceivers 310a and 310b may support standard-based asymmetric data rates and/or non-standard asymmetric data rates. The transceivers 310a and 310b may use multi-level signaling (multi-level signaling) in their operation. In this regard, the transceivers 310a and 310b may represent the various symbols transmitted with Pulse Amplitude Modulation (PAM) having different levels. For example, in 1000Mbps ethernet applications, PAM5 transmission scheme may be used per twisted pair cable, where PAM5 represents a PAM with 5 levels { -2, -1, 0, 1, 2 }.

In the embodiment of the invention shown in FIG. 3, computer systems 306a and 306b represent the third and higher layers. MAC controllers 308a and 308b may represent second and higher layers and transceivers 310a and 310b may represent first layer or physical layer operability and functionality. In this regard, the computer systems 306a and 306b may comprise suitable logic, circuitry, and/or code that may enable the 5 highest functional level of operations and functions for data packets to be transmitted over the cable 312. Because each layer in the OSI model provides services to its neighboring higher level intermediate layers, MAC controllers 308a and 308b can provide the necessary services to computer systems 306a and 310b to ensure that data packets are properly formatted and transmitted to transceivers 310a and 310 b. At the time of transfer, each layer adds its own header to data transferred from a higher intermediate layer thereon. However, during reception, compatible devices with similar OSI protocol stacks remove headers when messages pass from lower layers to higher layers.

Transceivers 310a and 310b may be configured to handle all physical layer requirements including, but not limited to: data grouping, data transfer, and serialization/deserialization (SERDES) in the case where this operation is needed. The data packets received by the transceivers 310a and 310b from the MAC controllers 308a and 308b, respectively, may include data and header information for the 6 functional layers described above. The transceivers 310a and 310b may encode data packets to be transmitted over the cable 312 and/or decode data packets received from the cable 312.

The MAC controller 308a may comprise suitable logic, circuitry, and/or code that may enable handling of the operability and functionality of the data link layer, i.e., the second layer, in the uplink party 302. Similarly, the MAC controller 308b may comprise suitable logic, circuitry, and/or code that may enable handling of the operability and functionality of the data link layer, i.e., the second layer, in the downlink side 304. MAC controllers 308a and 308b may implement an ethernet protocol, such as a protocol based on the IEEE 802.3 standard. However, the present invention is not limited in this regard.

The MAC controller 308a may communicate with the transceiver 310a through an interface 314a and may also communicate with the computer system 306a through a bus control interface 316 a. MAC controller 308b may communicate with transceiver 310b through interface 314a and may also communicate with computer system 306b through bus control interface 316 b. The interfaces 314a and 314b correspond to ethernet interfaces including protocol and/or link management control signals. The interfaces 314a and 314b may be multiple data rate interfaces. Bus controller interfaces 316a and 316b may correspond to PCI or PCI-X interfaces. However, the present invention is not limited in this regard.

Fig. 4 is a block diagram of an ethernet transceiver including an asymmetric multiple data rate physical layer in accordance with one embodiment of the present invention. Referring to fig. 4, a linker 400 is shown, which includes a transceiver 402, a MAC controller 404, a computer system 406, an interface 408, and a bus control interface 410.

The transceiver 402 may be an integrated device that includes an asymmetric multiple data rate PHY module 412, multiple transmitters 414a, 414c, 414e, and 414g, multiple receivers 414b, 414d, 414f, and 414h, a memory 416, and a memory interface 418. The operation of transceiver 402 is largely similar to transceivers 310a and 310b already described in fig. 3. For example, when transceiver 402 is used for the uplink side, transceiver 402 can transmit at a high data rate and receive at a low data rate. In another example, when transceiver 402 is used in a downlink party, transceiver 402 can transmit at a low data rate and receive at a high data rate. In this regard, the transceiver 402 may provide first layer or physical layer operations and/or functions to enable asymmetric data transmission.

Similarly, the operation of MAC controller 404, computer system 406, interface 408, and bus controller 410 is the same or substantially similar to MAC controllers 308a and 308b, computer systems 306a and 306b, interfaces 314a and 314b, and bus control interfaces 316a and 316b, respectively, illustrated in fig. 3. In this regard, MAC controller 404, computer system 406, interface 408, and bus controller 410 may enable transmission of different data rates and/or reception of different data rates in either the uplink side or the downlink side. The MAC controller 404 may comprise a multiple data rate interface 404a comprising suitable logic, circuitry, and/or code that may enable communication with the transceiver 402 via the interface 408 at multiple data rates.

The asymmetric multiple data rate physical layer module 412 in the transceiver 402 may comprise suitable logic, circuitry, and/or code that may enable physical layer operations and functions required for asymmetric data transmission. The asymmetric multiple data rate physical layer module 402 may communicate with the MAC controller 404 through an interface 408. According to an aspect of the invention, interface 408 uses multiple serial data channels to receive data from and/or transmit data to asymmetric multiple data rate physical layer module 412 for higher operating speeds, such as Gbps or 10 Gbps. The asymmetric multiple data rate physical layer module 412 may operate in one or more communication modes, each of which implements a different communication protocol. These communication protocols include, but are not limited to, IEEE 802.3, 10GBASE-T, and other similar protocols and/or non-standard communication protocols capable of asymmetric data communication. The asymmetric multiple data rate physical layer module 412 may be configured to operate in a particular mode of operation at initialization or during operation. The asymmetric multiple data rate physical layer module 412 may also be configured to operate in an extended range mode.

In some cases, transceiver 402 may use an auto-negotiation scheme to indicate or communicate with the remote linking party that the transceiver is operating in an extended range mode. The remote linking party then configures itself into the appropriate extended range mode. Through auto-negotiation, a network link may be configured as an extended range from one end of the link, ensuring interoperability between an extended range-enabled ethernet transceiver and legacy devices. In some cases, the link may be pre-configured and the transceiver fixed in extended range mode.

The asymmetric multiple data rate physical layer module 412 may be coupled to the memory 416 via a memory interface 418. The memory interface 418 is implemented as a serial interface or bus. The memory 416 may comprise suitable logic, circuitry, and/or code that may enable storage or programming of information, including parameters and/or code that enable operation of the asymmetric multiple data rate physical layer module 412. The parameters may include configuration data, including operational code such as software and/or firmware, but the information is not limited thereto. Moreover, the parameters may also include adaptive filters and/or module coefficients used by the asymmetric multiple data rate physical layer module 412.

The transmitters 414a, 414c, 414e, 414g may comprise suitable logic, circuitry, and/or code that may enable data to be transmitted from a transmitting party to a remote party via the cable 312 shown in FIG. 3. In this regard, when the transmitting link is an uplink link, the transmitters 414a, 414c, 414e, 414g may operate at a higher data rate than the data rate received from the downlink link. Similarly, when the transmitting party is the downlink party, the transmitters 414a, 414c, 414e, 414g may operate at a lower data rate than the data rate received from the uplink party.

The receivers 414b, 414d, 414f, 414h may comprise suitable logic, circuitry, and/or code that may enable the receiving party to receive data from the remote party via the cable 312. In this regard, when the receiving link is an uplink link, the receivers 414b, 414d, 414f, 414h may operate at a lower data rate than the data rate sent to the downlink link. Similarly, when the receiving link is the downlink, the receivers 414b, 414d, 414f, 414h may operate at a higher data rate than the data rate sent to the downlink.

Each of the 4 pairs of transmitters and receivers within transceiver 402 may correspond to one of the 4 wires in cable 312. For example, the transmitter 414a and receiver 414b can be used for asymmetric data communication with a remote link partner over a first pair of wires in the cable 312. Similarly, transmitter 414g and receiver 414h can be used for asymmetric data communication with the remote link partner over pair 4 in cable 312. In this regard, at least one of the 4 pairs of transmit/receiver pairs may be used to provide a suitable communication rate. For example, the above disclosed scheme may be used for fewer or more pairs.

Figure 5 is a schematic diagram of ECHO, NEXT, FEXT channel conditions in an ethernet network according to one embodiment of the present invention. Referring to fig. 5, an asymmetric ethernet system 500 is shown that may include an uplink party 501a and a downlink party 501 b. The uplink 501a and downlink 501b parties can communicate data asymmetrically over 4 twisted pair cables 510 in full duplex operation. Each twisted pair of the 4 twisted pair cable 510 may support a fraction of the data traffic rate needed to provide the total upstream and downstream data traffic. In this regard, each of the 4 twisted pairs may support a fraction of equal or average or unequal or non-average data communication rates in the total upstream and downstream data communications.

The uplink side 501a may include 4 mixers 506. Each mixer 506 in the uplink party 501a is communicatively coupled to one of the transmitter 502a, the receiver 504a, and the 4 twisted pair cable 510. Similarly, the downlink party 501b may include 4 mixers 506. Each mixer 506 in the downlinker 501b is communicatively coupled to one of the transmitter 502b, the receiver 504b and the 4 twisted pair cable 510. A portion of the uplink party 501a and the downlink party 501b shown in fig. 5 correspond to a portion of the physical layer operations supported by the uplink party 501a and the downlink party 501b, respectively.

Each mixer 506 in the uplink party 501a or the downlink party 501b may be communicatively coupled to a transformer 508 or may itself include a transformer 508. The mixer 506 may comprise suitable logic, circuitry, and/or code that may enable separating data transmitted and received over the twisted pair cable 510. The transmitters 502a and 502b may comprise suitable logic, circuitry, and/or code that may enable generating signals that may be transmitted via the mixer 506 and the twisted pair cable 510 to a link partner at the other end of the link. In this regard, transmitter 502a may operate at a higher data rate than transmitter 502 b. The receiver 304 may comprise suitable logic, circuitry, and/or code that may enable processing of signals received from a link partner on the other end of the link via the twisted pair cable 510 and the mixer 506. In this regard, receiver 504a may operate at a lower data rate than receiver 504 b.

During operation, several conditions occur on each twisted pair of twisted pair cable 510. For example, intersymbol interference (ISI) may occur due to frequency dependent cable attenuation. As shown in fig. 5, an ECHO component is received on twisted pair cable 510 due to an ECHO generated by transmitter 502a in uplink party 510a on the same twisted pair cable 510. The twisted pair cable 510 also receives a near end crosstalk (NEXT) component from the local transmitter 502a, which local transmitter 502a corresponds to 3 adjacent twisted pairs 510 in the uplink party 501 a. Further, far end crosstalk (FEXT) components are also received in twisted pair cable 510, originating from transmitter 501b located in the downstream party 501b at the other end of the link. Similar other situations may occur in the downlink party 501b, for example.

Fig. 6A is a schematic diagram of gigabit signal processing operations for received signals in an ethernet system for asymmetric data transmission in accordance with one embodiment of the present invention. Referring to fig. 6A, a signal processing system 600 is shown that provides a portion of the signal processing functions performed by physical layer operations within an ethernet transceiver that supports asymmetric multiple data rate operations. For example, the signal processing system 600 may be implemented in the asymmetric multiple data rate physical layer module 412 and/or in the receivers 414b, 414d, 414f, 414h in fig. 4. Signal processing system 600 may include an analog-to-digital converter (a/D)602, an adaptive Feed Forward Equalizer (FFE)604, a 3NEXT canceller 606, a summer 608, an ECHO canceller 610, and an equalizer/trellis decoder (trellis decoder) 612.

The a/D602 may comprise suitable logic, circuitry, and/or code that may be operable to convert analog signals received over the twisted pair cable into digital signals. The output of A/D602 is transmitted to FFE 604. FFE 604 may comprise suitable logic, circuitry, and/or code that may enable cancellation of preamble ISI, minimization of channel phase, and whitening of noise in the channel (whiten). The 3NEXT canceller 606 may comprise suitable logic, circuitry, and/or code that may be enabled to cancel at least a portion of the received NEXT components in a twisted-pair cable from local transmitters corresponding to 3 adjacent twisted-pair cables. ECHO canceller 610 may comprise suitable logic, circuitry, and/or code that may enable cancellation of at least a portion of ECHO components received on a twisted pair cable from a local transmitter on the same twisted pair cable.

Summer 608 may comprise suitable logic, circuitry, and/or code and may be adapted to sum the outputs of FFE 604, 3NEXT canceller 606, and/or ECHO canceller to produce a backward (postcursor) channel impulse response z_n，1. The equalizer/trellis decoder 612 may comprise suitable logic, circuitry, and/or code that may enableThe ISI resulting from the backward impulse response is equalized and the trellis code is decoded. The equalizer/trellis decoder 612 may receive the backward channel impulse response z corresponding to the other twisted pair cable_n，2、z_n，3And z_n，4As an input. The equalizer/trellis decoder 612 may generate detected bits (detecdbits) corresponding to the received analog signal.

Fig. 6B is a schematic diagram of separate equalization and decoded signal processing operations according to one embodiment of the invention. Referring to fig. 6B, the equalizer/trellis decoder 612 depicted in fig. 6A is shown implemented to perform separate equalization and trellis decoding operations. The equalizer/trellis decoder 612 includes 4 Decision Feedback Equalizers (DFE)620 and one trellis code modulation decoder (TCM) 622. The DFE 620 may comprise suitable logic, circuitry, and/or code that may enable cancellation of post-ISI for each twisted pair. The TCM decoder 622 may comprise suitable logic, circuitry, and/or code that may enable a Viterbi algorithm to be run on a code trellis to decode trellis-encoded symbols. For example, the TCM decoder 622 may be implemented with a parallel decision feedback decoding architecture. The method of separate equalization and trellis decoding may provide low implementation complexity and higher data rates, e.g., data rates up to Gbps may be easily implemented.

Fig. 6C is a schematic diagram of joint equalization and decoded signal processing operations according to one embodiment of the present invention. Referring to fig. 6C, there is shown an equalizer/trellis decoder 612 as depicted in fig. 6A, in which the equalization and trellis decoding operations are jointly implemented. The equalizer/trellis decoder 612 may include a decision feedback pre-filtering (DFP) module 650 and a look-ahead parallel decision feedback decoder (LA-PDFD) 652. The DFP module 650 may include 4 DFPs 654, one for each twisted pair cable. The DFP654 may comprise suitable logic, circuitry, and/or code that may enable reducing the backward channel memory. The LA-PDFP 652 may comprise suitable logic, circuitry, and/or code that may enable branch metric values (branchmetrics) to be calculated in a look ahead manner. Training and adaptation of the channel coefficients may be used to improve the performance of the equalizer/trellis decoder 612.

Fig. 7 is a schematic diagram of a multiple data rate ethernet system utilizing gigabit signal processing resources for asymmetric data transmission in 4-wire pair extended mode according to one embodiment of the present invention. Referring to fig. 7, an asymmetric multiple data rate ethernet system 700 is shown including an uplink party 701a and a downlink party 701 b. For example, the uplink party 701a may correspond to the ingress point switch 202 in fig. 2, while the downlink party 701b corresponds to, for example, CPE 20. The asymmetric multiple data rate ethernet system 700 may support various asymmetric data rates or modes of operation on 4-pair twisted-pair cable, including, for example, providing 1Gbps or 10Gbps data rates. In the embodiment with reference to fig. 7, the asymmetric multiple data rate ethernet system 700 may operate in an extended range mode, for example, providing a data rate of 10Mbps in the downstream direction and a data rate of 2Mbps in the upstream direction. In this regard, extended range operation may be achieved by using lower communication data rates of 2Mbps and 10Mbps, that is, data rates below 1Gbps or 10Gbps achieved by signal processing operations in the uplink party 701a or the downlink party 701 b.

As described in connection with fig. 5, the uplink side 701a includes 4 mixers 506. The invention is not limited thereto, however, and may support the implementation of various mixer circuits. Each mixer 506 in the uplink side 701a may be communicatively coupled to a transmitter 502a, a receiver 504a, and one of the 4 twisted pair cables also depicted in fig. 5. Also connected to each mixer 506 in the uplink side 701a are an echo canceller 702a and a subtractor 704 a. The uplink side 701a may further include a demultiplexer (demux)706a, an aligner (aligner)708a, and a multiplexer (mux)710 a.

Similarly, the downlink side 701b includes 4 mixers 506. Each mixer 506 in the downlink party 701b is communicatively coupled to a transmitter 502b, a receiver 504b, and one of the 4 twisted-pair cables 510, also depicted in fig. 5. Also connected to each mixer 506 in the downlink side 701b are an echo canceller 702b and a subtractor 704 b. The downlinker 701b also includes a demultiplexer (demux)706b, a calibrator 708b, and a multiplexer (mux)710 b. The uplink party and 701a and the downlink party 701b shown in fig. 7 may correspond to partial operations of physical layers supported by the uplink party 701a and the downlink party 701b, respectively.

The demultiplexer 706a may comprise suitable logic, circuitry and/or code that may be operable to separate a 10Mbps downstream signal into 4 2.5Mbps signals for transmission over 4 twisted pair cables. Similarly, the demultiplexer 706b may comprise suitable logic, circuitry and/or code that may be operable to separate 2Mbps upstream signals into 4 500kbps signals for transmission over 4 twisted-pair cables. The calibrator 708a may comprise suitable logic, circuitry, and/or code that may enable calibration of 500kbps signals received by the uplink party 701a from each of the 4 twisted pairs. Similarly, the calibrator 708b may comprise suitable logic, circuitry, and/or code that may be operable to calibrate 2.5Mbps of signals received by the downlinker 701b from each of the 4 twisted pairs. Multiplexer 710a may comprise suitable logic, circuitry, and/or code that may be enabled to combine the calibrated 500kbps signals received from calibrator 708a to generate a received 2Mbps uplink signal. Similarly, multiplexer 710b may comprise suitable logic, circuitry, and/or code that may be operable to combine the calibrated 2.5Mbps signals from calibrator 708a to generate a received 10Mbps downstream signal.

The ECHO cancellers 702a and 702b may comprise suitable logic, circuitry, and/or code that may be enabled to at least partially cancel ECHO components of corresponding signals received by the receivers 504a and 504b, respectively, that may be connected to the same twisted pair. The subtractors 704a and 704b may comprise suitable logic, circuitry and/or code that may enable cancellation of an ECHO component of a received signal.

In operation, the uplink side 701a can divide the signal of 10Mbps to be transmitted into 4 signals of 2.5Mbps through the demultiplexer 706 a. Each signal to be transmitted is processed by transmitter 502a before being passed to the corresponding twisted pair by mixer 506. The 4 transmitted signals may be received by the downlink party 701b, where each signal is processed by the receiver 504b and then echo cancelled by the corresponding echo canceller 702b and subtractor 704 b. The 4 received 2.5Mbps signals are calibrated in calibrator 708b and then combined into a 10Mbps received downstream signal in multiplexer 710 b.

Similarly, the downlink side 701b can divide the signal of 2Mbps to be transmitted into 4 signals of 500kbps through the demultiplexer 706 b. Each signal to be transmitted is processed by transmitter 502b before being passed to the corresponding twisted pair by mixer 506. The 4 transmitted signals may be received by the uplink party 701a, where each signal is processed by the receiver 504a before performing echo cancellation by the corresponding echo canceller 702a and subtractor 704 a. The 4 received 500kbps signals are aligned in aligner 708a and then combined into a 2Mbps received downstream signal in multiplexer 710 a.

The uplink party 701a and the downlink party 701b may communicate in full duplex over 4 twisted pair cables 510, providing a total 2Mbps uplink data rate and a total 10Mbps downlink data rate. Reducing the communication rate from 100Mbps or higher to 2Mbps and 10Mbps while operating with higher communication rate physical layer signal processing, the range can be extended, i.e., the standard length of twisted pair cable 510 is extended. In this regard, asymmetric multiple data rate operation of the uplink 701a and downlink 701b may support gigabit physical layer operation, using multi-level signaling to transmit multiple bits per clock cycle. PAM-5 may be used to transmit 2 bits per symbol, reducing the symbol rate to transmit over each twisted pair. In this regard, multi-level signaling may be applied to data rates of 100Mbps, 10Mbps, or less than 10Mbps, that is, using lower data rates to allow operation at reduced symbol rates. For example, a 25Mbps data rate may be achieved at a symbol rate of 12.5Msps on a single twisted pair of wires. A reduced symbol rate allows transmission over a longer cable range. For example, signal processing operations available to the gigabit physical layer can support 2, 3, 4, or 5 levels of signaling without increasing complexity.

Reducing the communication rate may also allow for the use of cables with higher insertion losses while maintaining the same standard length. For example, for gigabit operation, category 5 cables may be used. Reducing the communication rate in one direction to 100Mbps allows for a higher insertion loss cable than a category 5 cable while maintaining the requirement of 100 meters under the IEEE 802.3 standard. The insertion loss of twisted pair cables increases as the square root of the frequency increases. The insertion loss in dB is proportional to the length of the cable. Applying gigabit signal processing operations at a data rate of 100Mbps may increase the length range of the cable. NEXT cancellation operations may also improve the SNR of each received signal and may be applied at data rates of 100Mbps and 10Mbps to achieve the same improvement in SNR and may further extend the cable length range at those reduced communication rates.

The asymmetric multiple data rate ethernet system 700 is not limited to achieving lower communication rates in either direction by evenly distributing the data rate over each twisted pair used. In further embodiments of the present invention, the asymmetric multiple data rate ethernet system 700 may achieve lower communication rates by unevenly distributing the data rate over the 4 twisted pairs used. For example, to achieve a downlink data rate of 10Mbps, the first twisted pair may support a data rate of 1Mbps, the second twisted pair may support a data rate of 2Mbps, the third twisted pair may support a data rate of 3Mbps, and the fourth twisted pair may support a data rate of 4Mbps, thus achieving a total data rate of 10 Mbps. A similar approach may also be used to unevenly distribute the data rate over the 4 twisted pairs used to produce the total upstream data rate. In this regard, components within the uplink party 701a and/or the downlink party 701b may be adapted to handle low communication rates that are not uniformly distributed.

Fig. 8 is a schematic diagram of an echo canceller in an uplink asymmetric multiple data rate physical layer with a downlink data rate of 10Mbps and an uplink data rate of 2Mbps in accordance with an embodiment of the present invention. Referring to fig. 8, an echo canceller 806 in a portion of an asymmetric multiple data rate transceiver in an uplink side of an operational mode supporting a 10Mbps downlink data rate and a 2Mbps uplink data rate is shown. For example, the echo canceller 806 may employ an echo canceller structure with N taps (taps) using N/5 multipliers. In this regard, the echo canceller 806 may use a plurality of registers 810, a plurality of multipliers 814, a plurality of delay taps 812, a plurality of summers 816, an output register 818, and a switch 820.

Echo canceller 806 may use a transmit clock based F_TXTo generate an output signal that is delivered to adder 808 via switch 820, where the output signal is based on receive clock F_RX＝F_TXAnd/5. The digital downstream signal may be converted to an analog downstream signal by a digital-to-analog converter (DAC)802 for transmission over a twisted-pair copper cable 822. The analog upstream signal may be received by an analog-to-digital converter 804, which converts it to a digital upstream signal to the upstream party. The digital uplink signal and the output signal generated by ECHO canceller 806 are summed in summer 808 to reduce the ECHO component of the received digital uplink signal.

Fig. 9 is a schematic diagram of a multiple data rate ethernet system using gigabit signal processing resources for asymmetric data transmission in 2-wire pair extended mode according to one embodiment of the present invention. Referring to fig. 9, an asymmetric multiple data rate ethernet system 900 is shown, including an uplink party 901a and a downlink party 901 b. For example, the asymmetric ethernet system 900 may support asymmetric data transmission up to 1Gbps or up to 10 Gbps. The asymmetric multiple data rate ethernet system 900 may also support other modes of operation, such as a lower asymmetric transmission data rate over two twisted pair cables. In this regard, the asymmetric multiple data rate ethernet system 900 may support lower communication rates, such as a 10Mbps downlink data rate and a 2Mbps uplink data rate, while using signal processing operations available in the asymmetric multiple data rate physical layer for handling higher communication rates, such as 1Gbps or 10 Gbps.

The uplink 901a and downlink 901b parties may communicate over 2 twisted pair cables 510 in a full duplex manner at a downlink data rate of 5Mbps on each twisted pair, providing a total downlink data rate of 10Mbps, and communicate at an uplink data rate of 1Mbps on each twisted pair, providing a total uplink data rate of 2 Mbps. The uplink side 901a may provide 2 mixers 506 and corresponding echo cancellers 902a and subtractors 904 a. The uplink side 901a may also use the demultiplexer 906a, the calibrator 908a, and the multiplexer 910a to transmit and receive data at a reduced asymmetric communication rate. Likewise, the downlink side 901b may provide 2 mixers 506 and corresponding echo cancellers 902b and subtractors 904 b. The downlink side 901b may also use the demultiplexer 906b, the calibrator 908b, and the multiplexer 910b to transmit and receive data at a reduced asymmetric communication rate. The remaining twisted pairs are not used in the asymmetric ethernet system 900.

The asymmetric multiple data rate ethernet system 900 is not limited to achieving lower data rates by evenly distributing the data rates among the twisted pair lines used. In further embodiments of the present invention, an asymmetric multiple data rate ethernet system may achieve lower data rates by unevenly distributing the upstream and downstream data rates over each twisted pair. For example, the first twisted pair may support a downlink data rate of 4Mbps, while the second twisted pair may support a downlink data rate of 6Mbps to achieve a total downlink data rate of 10 Mbps. Similarly, the first twisted pair may support an uplink data rate of 800kbps, while the second twisted pair may support an uplink data rate of 1.2Mbps, for a total uplink data rate of 2 Mbps. In this regard, various components within the uplink party 901a and/or the downlink party 901b may be adapted to handle asymmetric data rate communications at unevenly distributed lower communication rates.

Fig. 10 is a flowchart of steps for reducing communication rates to achieve range extension in an ethernet system using an asymmetric multiple data rate physical layer, in accordance with one embodiment of the present invention. Referring to fig. 10, a flow chart 1000 is shown. After start step 1002, in step 1004, the asymmetric gigabit ethernet transceiver is enabled. Gigabit ethernet transceivers may use asymmetric multiple data rate physical layers to reduce communication rates from, for example, 1Gbps to lower communication rates. For example, the lower communication rate may be a downlink data rate of 10Mbps and an uplink data rate of 2Mbps, but is not limited thereto. The asymmetric multiple data rate physical layer may also reduce the symbol rate of the asymmetric gigabit ethernet transceiver. In reducing the communication rate or symbol rate, the asymmetric multiple data rate physical layer applies gigabit signal processing operations to the reduced communication rate or symbol rate.

In step 1006, an extended range mode is enabled in the asymmetric gigabit ethernet transceiver in which the asymmetric multiple data rate physical layer reduces the communication rate and/or symbol rate in at least one direction. At step 1008, at least a portion of the asymmetric gigabit signal processing operations available within the asymmetric multiple data rate physical layer are used in the extended range mode to enable use of longer cables or use of cables with higher insertion loss at standard lengths. After step 1008, process flow advances to end step 1010.

Various embodiments of the present invention may be used to extend the range of an asymmetric multiple data rate physical layer in an ethernet transceiver, for example, less than 10Mbps, 100Mbps, and 1000 Mbps. The same approach can be used to extend the range of any arbitrary data rate. The application of the extended asymmetric multiple data rate physical layer comprises the following steps: backhaul, multi-subscriber unit (MTU) FTTX + LAN, VDSL replacement, and/or extending point-to-point connections with switches, hubs, and/or repeaters to general networks over distances of 100 meters. Further, for example, the asymmetric multiple data rate physical layers within the ethernet transceivers at both ends of the asymmetric ethernet link may have different speeds, error correction coding, equalization complexity, crosstalk cancellation complexity, and/or linear coding.

The asymmetric ethernet transceiver supports extended range through its asymmetric physical layer operation, which may facilitate the elimination of a switch that is purely used as a network extender, thus saving cost. In addition, a single pair operation may be used to replace DSL equipment with cheaper ethernet equipment. In accordance with various embodiments of the present invention, various features within the extended range may be built into an asymmetric gigabit physical layer structure with minimal expense. This allows an extended range of applications to enjoy the advantage of low cost using large capacity components.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. The method is implemented in a computer system using a processor and a memory unit.

The present invention can also be implemented by a computer program product, which comprises all the features enabling the implementation of the methods of the invention and which, when loaded in a computer system, is able to carry out these methods. The computer program in this document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to other languages, codes or symbols; b) reproduced in a different format.

While the invention has been described with reference to several embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (6)

1. A method for wired communication, the method comprising:

reducing a communication rate of an asymmetric multiple data rate physical layer from a higher communication rate to a lower communication rate;

applying signal processing operations supported by the asymmetric multiple data rate physical layer in relation to the higher communication rate to the lower communication rate; the asymmetric multiple data rate physical layer is an asymmetric Ethernet multiple data rate physical layer;

the asymmetric Ethernet system with the asymmetric Ethernet multi-data-rate physical layer comprises an uplink party and a downlink party, wherein the uplink party and the downlink party carry out asymmetric data communication through 4 twisted-pair cables in a full-duplex operation mode; each twisted pair of the 4 twisted pair cables may support a fraction of the data traffic rate required to provide total upstream and downstream data traffic;

the uplink side includes 4 mixers, each mixer in the uplink side communicatively coupled to a transmitter, a receiver, and one of the 4 twisted pair cables; the downstream party includes 4 mixers, each mixer in the downstream party communicatively coupled to a transmitter, a receiver, and one of the 4 twisted pair cables;

the transmitter is used for generating signals and transmitting the signals to a link partner at the other end of the link through the mixer and the twisted pair cable; the receiver is used to process signals received from the link partner at the other end of the link through the twisted pair cable and the hybrid.

2. The method of claim 1, further comprising allocating the reduced communication rate at least one of: the uplink portion and the downlink portion of the lower communication rate.

3. The method of claim 2 further comprising aggregating the lower-rate upstream portion by evenly distributing the upstream portion over each twisted pair used in a copper cable.

4. The method of claim 2, further comprising aggregating the lower communication rate downlink portion by evenly distributing the downlink portion over each twisted pair used in a copper cable.

5. A system for wired communication, the system comprising:

a circuit to reduce a communication rate of an asymmetric multiple data rate physical layer from a higher communication rate to a lower communication rate;

applying signal processing operations supported by the asymmetric multiple data rate physical layer associated with the higher communication rate to the lower communication rate circuitry; the asymmetric multiple data rate physical layer is an asymmetric Ethernet multiple data rate physical layer;

the asymmetric Ethernet system with the asymmetric Ethernet multi-data-rate physical layer comprises an uplink party and a downlink party, wherein the uplink party and the downlink party carry out asymmetric data communication through 4 twisted-pair cables in a full-duplex operation mode; each twisted pair of the 4 twisted pair cables may support a fraction of the data traffic rate required to provide total upstream and downstream data traffic;

the uplink side includes 4 mixers, each mixer in the uplink side communicatively coupled to a transmitter, a receiver, and one of the 4 twisted pair cables; the downstream party includes 4 mixers, each mixer in the downstream party communicatively coupled to a transmitter, a receiver, and one of the 4 twisted pair cables;

the transmitter is used for generating signals and transmitting the signals to a link partner at the other end of the link through the mixer and the twisted pair cable; the receiver is used to process signals received from the link partner at the other end of the link through the twisted pair cable and the hybrid.

6. The system of claim 5, further comprising circuitry to allocate the reduced communication rate at least one of: the uplink portion and the downlink portion of the lower communication rate.