HK1121281B - Active matrix type display device and driving method thereof - Google Patents

Description

Active matrix display device and driving method

Technical Field

The present invention relates to an active matrix display device and a driving method of the type in which 1 signal line is shared by 2 adjacent pixels.

Background

In recent years, active matrix display devices using Thin Film Transistors (TFTs) as switching elements have been developed.

The active matrix display device includes a scanning line driving circuit (hereinafter, referred to as a gate driver) that generates scanning signals for sequentially scanning a plurality of pixels provided in a matrix for each row. The operating frequency of the gate driver is lower than that of a signal line driver circuit (hereinafter referred to as a source driver) that supplies a video signal to each of the pixels. Thus, even if the TFT and the gate driver are simultaneously formed in the same process for forming the TFT corresponding to each pixel, the gate driver can satisfy the standard.

In addition, each pixel in the active matrix type display device includes a pixel electrode connected to the TFT described above, and a common electrode to which a common voltage Vcom is applied. In an active matrix display device, in order to prevent deterioration of the liquid crystal performance caused by long-term application of an electric field in one direction, inversion driving is generally performed in which the polarity of a video signal Vsig from a source driver is inverted for each frame, line, or dot with respect to a common electrode Vcom.

However, in the mounting of an active matrix display device, the gate driver, the source driver, and the like are provided around a display panel (display screen) in which a plurality of pixels are arranged. Scanning lines (hereinafter, referred to as gate lines) and signal lines (hereinafter, referred to as source lines) in the display screen, and wirings for electrically connecting the gate lines and the source lines surround the outside of the display screen and connect the scanning lines and the signal lines. In this case, from the viewpoint of downsizing of an information apparatus incorporating the active matrix display device, it is strongly desired to reduce the winding area of the wirings, that is, the area (narrow edge) other than the display panel.

Accordingly, since the occupied area of the source line can be reduced particularly in response to a request for narrowing the vertical edge of the display panel, a pixel connection line in which the source line is halved is considered (for example, fig. 5 of JP 2004-185006 a).

Fig. 10 is a schematic diagram of an example of a pixel connection line in a display screen, which is considered as one method for realizing such a narrow edge. Wherein 1 epipolar line is common to 2 adjacent pixels 100. In this case, the TFTs 102 of the 2 pixels 100 are connected to respectively different gate lines. For example, in fig. 10, the TFT102 of the pixel 100 of red (R) at the upper left is connected to the gate line G1 and the source line S1, and the TFT102 of the pixel 100 of green (G) at the right neighbor thereof is connected to the gate line G2 and the source line S1.

Fig. 11 is a diagram showing a sequence of writing the video signal Vsig to each pixel 100 for such a pixel connection. The pixel connection described above is such that writing of the video signal Vsig to each pixel 100 is performed in the order of the gate lines, as shown in fig. 11.

In the pixel line for halving the source line as described above, a portion having an active line and a portion having no source line exist between pixels, and the parasitic capacitance between pixels is larger than that of the active line in the portion having no source line. Fig. 12 is a diagram showing an equivalent circuit at this time. Voltage leakage occurs between pixels having the inter-pixel parasitic capacitance 104, and thus the potential of the pixel 100 written first fluctuates due to the influence of the potential of the pixel 100 written later. This potential variation causes display unevenness in the pixels. As shown in fig. 11, since the pixel writing order is fixed, display unevenness due to the occurrence of the leakage always occurs at the same portion.

Fig. 13 is a diagram showing an example of this display unevenness. For ease of understanding, the figure shows only the pixel 100 of G. Here, the scanning order of the gate lines is G1 → G2 → G3 … → G8. In fig. 13, the same applies to the potential fluctuation of the pixel 100 written first in the pixels 100 of the other black color (details will be described later).

This pixel potential variation will be described in more detail below. Fig. 14 is a diagram of the structure of each pixel in the case where the display panel is a tft lcd. Each pixel 100 is configured in such a manner that: a liquid crystal (not shown) is sandwiched between a pixel electrode connected to a source line via a TFT102 connected to a gate line, and a common electrode (not shown) to which a common voltage Vcom is applied. In addition, a corresponding display is realized by holding electric charges in the liquid crystal capacitor Clc throughout the entire field scanning period (frame scanning period in the case of the non-interlace method). In order to take countermeasures against current leakage of the TFT via the liquid crystal capacitance Clc, an auxiliary capacitance Cs is provided in parallel with the liquid crystal capacitance Clc.

Fig. 15A is a diagram showing a scan timing chart of the gate lines G1 to G4 of the gate driver of fig. 14. Fig. 15B is a diagram showing pixel potential waveforms of, for example, a green pixel F (hereinafter, referred to as a pixel before G) connected to the source line S3 in fig. 12 that is written first, and a red pixel L (hereinafter, referred to as a pixel after R) connected to the source line S2 in fig. 12 that is written later, in the case of performing horizontal line inversion driving in which the polarity of the common voltage Vcom is inverted for each horizontal period.

The following description will be made in the case of a liquid crystal display device of a normal white mode in which the larger the voltage of a pixel, the lower the transmittance (becomes dark). Fig. 15B shows a case where the amplitude of the common voltage Vcom is 5.0V, the writing voltage (video signal Vsig) of the pixel F before G is 2.0V (halftone) with respect to the common voltage Vcom, and the writing voltage (video signal Vsig) of the pixel L after R is 4.0V (black, dark) with respect to the common voltage Vcom. The influence of the introduced voltage (field penetration voltage) Δ V generated when the TFT102 is turned on and off can be eliminated by adjusting the common voltage Vcom (by shifting the Vcom amount downward by the Δ V amount), and therefore is not described in the waveform of fig. 15B (the same applies to other pixel potential waveforms described below).

As shown in fig. 15A, in each field, 2 gate lines are selected for 1 horizontal period, and the selected 2 gate lines are sequentially scanned for each horizontal period. In addition, as shown in fig. 15B, the TFT102 connected to the selected gate line is turned on, and the video signal Vsig supplied from the source line is written in the corresponding pixel 100. Then, the writing timing of the pixel F before G is W in fig. 15B_GThe writing timing of the pixel L after R is W_R. The pixel potential written at these writing timings is maintained until the next field writing.

Fig. 15B shows a pixel potential waveform in an ideal state in the case where the inter-pixel parasitic capacitance 104 is 0. However, as described above, the inter-pixel parasitic capacitance 104 exists in a portion where the source line is not present. Fig. 16A is a diagram of a pixel potential waveform under the same voltage condition as fig. 15B in consideration of the inter-pixel parasitic capacitance 104. Fig. 16B is a diagram showing pixel potential waveforms in a case where the amplitude of the common voltage Vcom is 5.0V, the writing voltage of the pixel F before G is 2.0V with respect to the common voltage Vcom, and the writing voltage of the pixel L after R is 1.0V (white, bright) with respect to the common voltage Vcom, taking into consideration the inter-pixel parasitic capacitance 104.

That is, as shown in fig. 16A and 16B, in the pixel F before G, the pixel potential written by the selection of the gate line G1 is shifted in a direction away from the common voltage Vcom by Vc (direction of darkening) at the time of writing in the pixel L after R by the selection of the gate line G2. The value of Vc is expressed as follows:

Vc＝(Vsig(Fn-1)+Vsig(Fn))×Cpp/(Cs+Clc+Cpp)×α…(1)

in the formula (1), Vsig (Fn) is a write voltage of the pixel L after R in the current field, and Vsig (Fn-1) is a write voltage of the pixel L after R in the previous field. Then, in the case of fig. 16A, Vsig (Fn-1) + Vsig (Fn) ═ 8.0V. In the case of fig. 16B, Vsig (Fn-1) + Vsig (Fn) ═ 2.0V. Cpp is a capacitance value of the inter-pixel parasitic capacitance 104, Cs is a capacitance value of the auxiliary capacitance Cs, Clc is a capacitance value of the liquid crystal capacitance Clc, and α is a proportionality coefficient and is a value determined by a plate structure or the like.

As described above, the larger Vsig (Fn-1) + Vsig (Fn) is, the larger the value Vc of the potential variation becomes, and is independent of the amplitude of Vcom.

As described above, the case of horizontal line inversion driving in which the polarity of the common voltage Vcom differs between pixels adjacent in the direction of the source line, that is, for example, in fig. 11, the case of horizontal line inversion driving in which the polarity of the common voltage Vcom differs between a pixel connected to the gate line G1 or G2 and a pixel connected to the gate line G3 or G4 is described.

However, there is also a driving method of dot inversion driving in which the polarity of the common voltage Vcom is different between pixels adjacent in the source line direction and pixels adjacent in the gate line direction with respect to the polarity inversion of the common voltage Vcom. For example, the polarity of the common voltage Vcom is different between the pixel connected to the gate line G2 or the gate line G3 and the pixel connected to the gate line G1 or the gate line G3.

In the case of dot inversion driving, the dot inversion driving is as shown in fig. 17A and 17B. Here, fig. 17A is a diagram showing pixel potential waveforms in a case where the amplitude of the common voltage Vcom is 5.0V, the writing voltage of the pixel F before G is 2.0V (middle tone) with respect to the common voltage Vcom, and the writing voltage of the pixel L after R is 4.0V (black) with respect to the common voltage Vcom, in consideration of the inter-pixel parasitic capacitance 104, fig. 17B is a diagram showing pixel potential waveforms in a case where the amplitude of the common voltage Vcom is 5.0V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage Vcom, and the writing voltage of the pixel after R is 1.0V (white) with respect to the common voltage Vcom, in consideration of the inter-pixel parasitic capacitance 104.

That is, as shown in fig. 17A and 17B, similarly in the case of dot inversion driving, the pixel potential written by selection of the gate line G1 in the pixel F before G is shifted by Vc in writing of the pixel L after R by selection of the gate line G2, as in the case of horizontal line inversion driving.

Also in this case, as Vsig (Fn-1) + Vsig (Fn) increases, the value Vc of the potential variation increases, independently of the amplitude of Vcom, which is the same as that in the case of the horizontal line inversion driving.

However, in the case of horizontal line inversion driving, the potential is varied so that the potential difference with the common voltage Vcom increases, whereas in the case of dot inversion driving, the potential is varied so that the potential difference with the common voltage Vcom decreases.

In the normal white mode in which white display is performed when no voltage is applied and black display is performed when a voltage is applied, the pixels before G are darker than the actual display when the horizontal line is inverted by the above-described fluctuation in the Vc amount. In addition, in the case of dot inversion driving, the display is brighter than actual display. In contrast, since a normal voltage is written to the pixel potential of the pixel after G, if a display such as a G grid (raster) is formed, light and dark green is displayed every 1 pixel in the vertical direction regardless of inversion driving.

The same fluctuation in Vc amount occurs in the pixels before R and the pixels before B.

The above case is not limited to the case where the pixels 100 are arranged in stripes, and the same applies to the case where the pixels are arranged in triangles.

The method disclosed in JP 2004-185006 a cannot cope with the problem of display unevenness due to potential variation occurring in the pixels written first, which is caused by the inter-pixel parasitic capacitance 104.

Disclosure of Invention

The present invention has been made in view of the above-mentioned problems occurring in the prior art, and an object of the present invention is to reduce display unevenness in the case where there is parasitic capacitance between pixels.

An active matrix display device according to a preferred embodiment of the present invention, wherein:

the 1st pixel and the 2 nd pixel are adjacently arranged in a predetermined direction;

a 3 rd pixel which is adjacent to the 1st pixel with a 1st signal line interposed therebetween in a direction opposite to the 2 nd pixel;

a 4 th pixel which is adjacent to the 2 nd pixel with a 2 nd signal line interposed therebetween in a direction opposite to the 1st pixel;

the 1st pixel and the 3 rd pixel share the 1st signal line;

the 2 nd pixel and the 4 th pixel share the 2 nd signal line;

the 1st pixel and the 4 th pixel are connected to a 1st scanning line;

the 2 nd pixel and the 3 rd pixel are connected to the 2 nd scan line;

the active matrix display device includes:

and a scanning line driving circuit which selects only the 2 nd scanning line in the 2 nd period after simultaneously selecting the 1st scanning line and the 2 nd scanning line in the 1st period.

An active matrix type display device according to a preferred embodiment of the present invention, wherein,

the 1st pixel and the 2 nd pixel are adjacently arranged in a predetermined direction;

a 3 rd pixel which is adjacent to the 1st pixel with a 1st signal line interposed therebetween in a direction opposite to the 1st pixel;

a 4 th pixel which is adjacent to the 2 nd pixel with a 2 nd signal line interposed therebetween in a direction opposite to the 2 nd pixel;

the 1st pixel and the 3 rd pixel share the 1st signal line;

the 2 nd pixel and the 4 th pixel share the 2 nd signal line;

the 1st pixel and the 4 th pixel are connected to a 1st scanning line;

the 2 nd pixel and the 3 rd pixel are connected to the 2 nd scan line;

the active matrix display device includes:

and a correction circuit for outputting a signal in which a potential variation amount due to a parasitic capacitance between the 1st pixel and the 2 nd pixel is corrected for the 1st pixel or the 2 nd pixel.

An active matrix display device according to a preferred embodiment of the present invention, wherein:

1 signal line is provided for every 2 pixels with respect to the direction in which the scanning lines extend;

2 pixels adjacent to each other in a direction in which the scanning lines extend, the 2 pixels sandwiching the signal lines, sharing the signal lines, and being connected to different scanning lines via switching elements;

the active matrix display device includes:

a scanning line driving circuit for sequentially selecting a plurality of the scanning lines; and

a signal line driving circuit for outputting a signal corresponding to information to be displayed to the plurality of signal lines;

the scanning line driving circuit can switch:

a normal mode in which 2 scanning lines corresponding to the 2 pixels adjacent in the direction in which the scanning lines extend across the signal lines are sequentially selected in 1 horizontal period, and

and a 2-time writing mode in which only 1 scanning line of the 2 simultaneously selected scanning lines is selected after the 2 simultaneously selected scanning lines.

An active matrix display device according to a preferred embodiment of the present invention, wherein:

1 signal line is provided for every 2 pixels with respect to a predetermined direction;

2 pixels adjacent to each other in the predetermined direction with the signal line interposed therebetween, the 2 pixels sharing the signal line and being connected to different scanning lines via switching elements;

the active matrix display device includes:

a scanning line driving circuit for sequentially selecting a plurality of the scanning lines;

a signal line driving circuit for outputting a signal corresponding to information to be displayed to the plurality of signal lines; and

and a correction circuit for outputting a signal in which a potential variation amount due to inter-pixel parasitic capacitance is corrected for 1 pixel out of 2 pixels connected to different signal lines and provided adjacent to each other in the predetermined direction to the scanning line drive circuit.

A driving method of an active matrix display device according to a preferred embodiment of the present invention is a driving method of driving a display panel including a plurality of pixels and a plurality of switching elements, wherein a plurality of signal lines and a plurality of scanning lines are provided in a matrix, 1 signal line is shared by 2 adjacent pixels among the plurality of pixels, and the plurality of switching elements are provided for each pixel to control the pixel in accordance with a selection state of the signal line and the scanning line corresponding to each pixel, the driving method including: selecting 2 scanning lines corresponding to 2 pixels connected to different signal lines and adjacently disposed, simultaneously when the plurality of scanning lines are sequentially selected and signals corresponding to information to be displayed are output to the plurality of signal lines; and selecting only 1 of the simultaneously selected scan lines.

By the invention, even under the condition of having parasitic capacitance between pixels, uneven display can be reduced.

Drawings

Fig. 1A is a schematic configuration diagram showing an overall configuration of a matrix display device according to embodiment 1 of the present invention;

FIG. 1B is a schematic diagram of a pixel connection of an LCD panel;

FIG. 2 is a block diagram of a driving circuit;

fig. 3A is a diagram showing a structure of a gate driving module;

FIG. 3B is a diagram showing a timing diagram for non-inverted offset of the gate 2 write mode in the gate driver module;

FIG. 3C is a diagram showing a timing diagram of a top-bottom inversion shift of the gate 2 write mode in the gate driver module;

FIG. 4A is a diagram showing a scan timing chart at the time of non-inversion shift of the gate 2 write mode;

fig. 4B is a diagram showing a pixel potential waveform in the case where the amplitude of the common voltage at the time of horizontal line inversion driving is 5.0V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage, the writing voltage of the pixel after R is 4.0V with respect to the common voltage, and the writing voltage of the pixel before B is 2.0V with respect to the common voltage;

fig. 4C is a diagram showing a pixel potential waveform in the case where the amplitude of the common voltage when horizontal line inversion driving is performed is 5V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage, the writing voltage of the pixel after R is 1.0V with respect to the common voltage, and the writing voltage of the pixel before B is 2.0V with respect to the common voltage;

fig. 5 is a diagram showing a circuit configuration of a γ circuit block of a matrix display device according to embodiment 2 of the invention;

fig. 6A is a graph showing a γ curve of a normal mode and a data shift mode when POL of the γ circuit block is L;

fig. 6B is a graph showing a γ curve of the normal mode and the data shift mode when POL of the γ circuit block is H;

FIG. 6C is a graph showing the relationship between the output voltage and the amplitude adjustment signal in the data shift mode;

FIG. 6D is a graph showing an offset amount;

FIG. 7A is a diagram showing a timing chart at the time of non-inversion offset;

FIG. 7B is a diagram showing a timing chart at the time of the vertical reverse shift;

FIG. 8A is a diagram showing a scan timing chart at the time of non-inversion shift of the data shift pattern;

fig. 8B is a diagram showing pixel potential waveforms in the case where the amplitude of the common voltage is 5.0V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage, and the writing voltage of the pixel after R is 4.0V with respect to the common voltage when horizontal line inversion driving is performed;

FIG. 9A is a diagram showing a scan timing chart at the time of non-inversion shift of the data shift pattern;

fig. 9B is a diagram showing pixel potential waveforms in the case where the amplitude of the common voltage is 5.0V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage, and the writing voltage of the pixel after R is 4.0V with respect to the common voltage when horizontal line inversion driving is performed;

fig. 10 is a schematic view showing pixel connection lines of a display panel in which source lines in a conventional matrix display device are halved;

fig. 11 is a diagram showing a procedure of writing video signals to the respective pixels in the pixel line of fig. 10;

fig. 12 is a diagram showing an equivalent circuit of the display panel of fig. 10;

fig. 13 is a view showing an example of display unevenness of the display panel of fig. 10;

fig. 14 is a diagram showing a structure of each pixel in the case where the display panel is a TFLCD panel;

FIG. 15A is a view showing a scan timing chart;

fig. 15B is a diagram showing a pixel potential waveform of horizontal line inversion driving in the case where there is no inter-pixel parasitic capacitance;

fig. 16A is a diagram showing a pixel potential waveform of horizontal line inversion driving in consideration of parasitic capacitance between pixels, and shows a case where the amplitude of the common voltage is 5.0V, the writing voltage of the pixel before G is 2.0V with respect to the common voltage, and the writing voltage of the pixel after R is 4.0V with respect to the common voltage;

fig. 16B is a diagram showing a pixel potential waveform of horizontal line inversion driving in consideration of parasitic capacitance between pixels, and is a diagram showing a pixel potential waveform in a case where an amplitude of a common voltage is 5.0V, a writing voltage of a pixel before G is 2.0V with respect to the common voltage, and a writing voltage of a pixel after R is 1.0V with respect to the common voltage;

fig. 17A is a diagram showing a pixel potential waveform of dot inversion driving in consideration of parasitic capacitance between pixels, and is a diagram showing a pixel potential waveform in a case where an amplitude of a common voltage is 5.0V, a writing voltage of a pixel before G is 2.0V with respect to the common voltage, and a writing voltage of a pixel after R is 4.0V with respect to the common voltage;

fig. 17B is a diagram showing a pixel potential waveform of dot inversion driving in consideration of parasitic capacitance between pixels, and is a diagram showing a pixel potential waveform in a case where an amplitude of a common voltage is 5.0V, a writing voltage of a pixel before G is 2.0V with respect to the common voltage, and a writing voltage of a pixel after R is 1.0V with respect to the common voltage.

Detailed Description

Preferred embodiments of the present invention will be described below with reference to the accompanying drawings.

(embodiment 1)

Fig. 1A is a schematic diagram showing an overall structure of an active matrix display device according to embodiment 1 of the present invention, and fig. 1B is a schematic diagram showing a pixel connection line of the LCD panel in fig. 1A;

that is, as shown in fig. 1A, the active matrix display device of the present embodiment includes a panel 10 in which a plurality of pixel LCDs are provided, a drive circuit 12 for driving and controlling each pixel of the LCD panel 10, and a Vcom circuit 14 for applying a common voltage Vcom to the LCD panel 10.

As shown in fig. 1B, the LCD panel 10 includes a plurality of pixels arranged in a matrix. The source lines S1 to S480 and the gate lines X1 to X480 intersect each other. Each pixel is connected to one of the source lines and one of the gate lines via a TFT18 serving as a switching element. Here, each pixel is provided so that 2 pixels 16 adjacent to each other share 1 source line. In this case, the respective TFTs 18 corresponding to the 2 pixels 16 are connected to mutually different gate lines. For example, in fig. 1B, the TFT18 of the pixel 16 of the upper left R is connected to the gate line X1 and the source line S1, and the TFT18 of the pixel 16 of the right adjacent G is connected to the gate line X2 and the source line S1. Here, the case where the pixels 16 are arranged in a triangular array is given.

The plurality of source lines S1 to S480 and the plurality of gate lines X1 to X480 in the LCD panel 10 are electrically connected to the driver circuit 12 through a wiring 20 that bypasses a substrate 20 (not shown) of the LCD panel 10.

Fig. 2 is a block configuration diagram of the driving circuit 12 of fig. 1A. As shown in the figure, the driving circuit 12 includes a gate driving module 22, a source driving module 24, a level shift (level shift) circuit 26, a timing generator (hereinafter abbreviated to "TG") section logic circuit 28, a gradation (hereinafter abbreviated to "γ") circuit module 30, a charge pump/adjustment module 32, an analog module 34, and others.

Here, the gate driving module 22 sequentially selects the plurality of gate lines X1 to X480 of the LCD panel 10, and the source driving module 24 outputs the video signal Vsig corresponding to information to be displayed to the plurality of signal lines S1 to S480 of the LCD panel 10.

The level shift circuit 26 shifts the level of a signal supplied from the outside to a predetermined level. The TG unit logic circuit 28 generates necessary timing signals and control signals based on the signal shifted to a predetermined level by the level shift circuit 26 and an externally supplied signal, and supplies the timing signals and the control signals to each unit in the drive circuit 12.

The γ circuit block 30 performs γ correction so that the video signal Vsig output from the source drive block 24 has good gradation characteristics.

The charge pump/regulation block 32 is used to generate various voltages of necessary logic levels from an external power source, and the analog block 34 further generates various voltages from the voltages formed by the charge pump/regulation block 32. The Vcom circuit 14 generates the common voltage Vcom based on the voltage VVCOM generated by the analog block 34. Since other modules are not directly related to the present invention, the description thereof will be omitted.

Fig. 3A is a diagram showing the structure of the gate driver module 22 in fig. 2. In addition, for simplification of description and illustration, an example in which 8 gate lines are used will be described here. In this case, the gate driving module 22 is composed of 3 bit counters 36, 9 and gates, 2 or gates, 3 not gates, and 1 not gate.

That is, in the 3-bit counter 36, a gate clock and an up/down (hereinafter, abbreviated as U/D) signal are supplied from the TG section logic circuit 28. The U/D signal is "1" in the case of non-inversion offset which is normal display, and is "0" in the case of inversion offset in the case of display in which the up and down are inverted. In the non-inversion offset and the vertical inversion offset, the scanning direction of the gate line is reversed vertically, and as a result, the pixel written first and the pixel written later are reversed, and accordingly, the switching operation is required.

The Q1 output of the 3-bit counter 36 is provided through an or gate to an and gate for the even-numbered gate lines X2, X4, X6, X8. The output signal of the and gate, which performs a logical operation of the U/D signal and a double gate (hereinafter referred to as GDOUBLE) signal supplied from the TG unit logic circuit 28, is supplied to the or gate. Here, the GDOUBLE signal is "0" in the normal mode in the normal display state, and is "1" in the gate 2-time writing mode in which the display unevenness reduction driving (hereinafter, referred to as gate 2-time writing driving) of the present embodiment is performed. The Q1 output of the 3-bit counter 36 is further supplied to odd-numbered gate lines X1, X3, X5, and X7 through an and gate. An output signal of an or gate that performs a logical operation of the U/D signal and a signal obtained by inverting the GDOUBLE signal by the not gate is supplied to the not gate. The outputs of the nand gates are supplied to and gates for odd-numbered gate lines X1, X3, X5, and X7.

The Q2 output of the 3-bit counter 36 is supplied to and gates for the gate lines X3, X4, X7, and X8, and is supplied to and gates for the gate lines X1, X2, X5, and X6 via not gates.

Further, the Q3 output of the 3-bit counter 36 is supplied to and gates for the gate lines X5, X6, X7, and X8, and is supplied to and gates for the gate lines X1, X2, X3, and X4 via not gates.

Fig. 3B is a timing chart showing a non-inversion shift of the gate 2 write pattern of the gate driver block 22 having such a configuration. Fig. 3C is a diagram showing a timing chart at the time of the above-described vertical inversion offset.

In the non-inversion shift, as shown in fig. 3B, H signals are sequentially output to the odd-numbered gate lines X1, X3, X5, and X7 for a period corresponding to 1 cycle of the gate clock, and to the even-numbered gate lines X2, X4, X6, and X8 for a period corresponding to 2 cycles of the gate clock. That is, in timing: gate line X1, X2 in selected state → gate line X2 in selected state → gate line X3, X4 in selected state → gate line X4 in selected state → gate line X5, X6 in selected state → gate line X6 in selected state → gate line X7, and X8 in selected state → gate line X8 in selected state.

In the case of the vertical inversion shift, as shown in fig. 3C, the H signals are sequentially output in reverse direction for the even-numbered gate lines X2, X4, X6, and X8 for 1 cycle of the gate clock and for the odd-numbered gate lines X1, X3, X5, and X7 for 2 cycles (minute) of the gate clock. That is, in timing: gate line X8, X7 in selected state → gate line X7 in selected state → gate line X6, X5 in selected state → gate line X5 in selected state → gate line X4, X3 in selected state → gate line X3 in selected state → gate line X2, and X1 in selected state → gate line X1 in selected state.

Fig. 4A is a diagram showing a scanning timing chart at the time of non-inversion shift of the gate 2 write pattern according to the present embodiment corresponding to fig. 15A.

Fig. 4B and 4C are diagrams showing pixel potential waveforms of a pixel Fg of fig. 1B to which writing is performed first, for example, green connected to S3 (hereinafter referred to as a "pixel before G"), and a pixel Lr of fig. 1B to which writing is performed later, for example, red connected to S2 (hereinafter referred to as a "pixel after R"), in the case of performing horizontal line inversion driving in which the polarity of the common voltage Vcom is inverted for each horizontal period.

In this case, as will be described later, the pixel potential waveform has a relationship with, for example, a blue pixel Fb (hereinafter referred to as a "pixel before B") connected to the same S2 as the red pixel Lr in fig. 1B to be selected in advance.

At this time, since the gate lines are selected as described above, in each field, 2 gate lines corresponding to 2 pixels which are connected to different signal lines and arranged adjacent to each other are simultaneously selected for 1 horizontal period, and then only 1 gate line X corresponding to a pixel to be selected later among the 2 pixels is selected.

Fig. 4B is a diagram of pixel potential waveforms in the case where the horizontal line inversion drive is performed in which the polarity of the common voltage Vcom is inverted for each horizontal period, the amplitude of the common voltage Vcom is 5.0V, the write voltage (video signal Vsig) of the pixel Fg before G is 2.0V (middle tone) with respect to the common voltage Vcom, the write voltage (video voltage Vsig) of the pixel Lr after R is 4.0V (black) with respect to the common voltage Vcom, the write voltage (video signal Vsig) of the pixel Fb before B is 2.0V (middle tone) with respect to the common voltage Vcom, fig. 4C is a diagram of pixel potential waveforms in the case where the amplitude of the common voltage Vcom is 5.0V, the write voltage (video signal Vsig) of the pixel Fg before G is 2.0V with respect to the common voltage Vcom, the write voltage (video voltage Vsig) of the pixel Lr after R is 1.0V (white) with respect to the common voltage Vcom, and the write voltage (video signal Vsig) of the pixel Fb before B is 2.0V (middle tone) with respect to the common voltage Vcom Graph of potential waveform.

In this embodiment, by performing the scanning of the gate lines as shown in fig. 4A, as shown in fig. 4B and 4C, the pixel Fb before B and the pixel Lr after R share 1 source line S2 (signal line), and thus, while the gate line X1 and the gate line X2 are simultaneously selected, the writing potential of the pixel Fb before B is also applied to the pixel Lr after R, and writing is also performed in the pixel Lr after R, and the potential is the same as that of the pixel Fb before B. When only the subsequent gate line X2 is selected, the writing voltage of the pixel Lr after R is output to the source line, and the pixel potential before B is written to the pixel Lr after R.

Thus, in the present embodiment, the generation of Vc represented by the formula (1) can be suppressed.

However, in the present embodiment as well, since the inter-pixel parasitic capacitance Cpp exists, in the pixel Fg before G, when only the gate line X2 is selected for the pixel potential written by the selection of the gate line X1 and the voltage writing to the pixel Lr after R is performed in the pixel Lr after R, the pixel potential shifts to a direction away from the common voltage Vcom (a direction of darkening). The value of the newly generated potential variation Vc is expressed by the following formula:

Vc＝(Vsig(X2)-Vsig(X1))×Cpp/(Cs+Clc+Cpp)×α…(2)

in the expression (2), Vsig (X2) indicates a writing voltage of the pixel Lr after R when only the gate line X2 is selected, and Vsig (X1) indicates a writing voltage of the pixel Fb before B when the gate lines X1 and X2 are simultaneously selected. Otherwise, the formula (1) is the same as the above.

That is, in this embodiment, the pixel potential of the field is not influenced by the potential of the pixel Fb of the adjacent pixel connected to the same signal line. However, it is known that the absolute value of the potential fluctuation Vc due to the inter-pixel capacitance Cpp can be made small as compared with the past, for example, in the case of fig. 4B, in which Vsig (X2) -Vsig (X1) is 4.0 to 2.0V, and in the case of fig. 4C, in which Vsig (X2) -Vsig (X1) is 1.0 to 2.0V. Thus, in the present embodiment, display unevenness is reduced as compared with the past.

(in the past, corresponding to fig. 15A, fig. 15B, 8.0V, 2.0V., respectively).

In general, when the pixel voltage with respect to the common voltage Vcom varies in a range of 1.0V (white) to 4.0V (black),

(1) of formula (II)

Vsig (Fn-1) + Vsig (Fn) is in the range of 2.0V-8.0V;

(2) of formula (II)

Vsig (X2) -Vsig (X1) is in the range of-3.0V to 3.0V.

As described above, according to the present embodiment, since the absolute value of Vc is small, the potential variation Vc due to the inter-pixel parasitic capacitance Cpp can be made smaller than in the past, and the display unevenness can be reduced.

In addition, in the case where the potential difference between the adjacent pixels connected to the same signal line is large, for example, in the case where the writing voltage of the pixel Fg before G is 4.0V (black) with respect to the common voltage Vcom, the writing voltage of the pixel Lr after R is 1.0V (white) with respect to the common voltage Vcom, and the writing voltage of the pixel Fb before B is 4.0V (black) with respect to the common voltage Vcom, the potential variation Vc may be larger than that in the conventional example.

(Vsig(X2)-Vsig(X1)＝1.0-4.0＝-3.0V

Vsig(Fn-1)+Vsig(Fn)＝1.0+1.0＝2.0V)

However, in this case, the affected pixel Fg before G is at a sufficiently saturated black level, and the potential variation Vc is not recognized at all on the display, so that no problem occurs. In addition, the pixel Lr after R affected by the influence is at white level, and the pixel Fb before B is at black level, and in this case, the screen is displayed as a bright R grid screen, and the potential variation before G is more difficult to be recognized in the display. Thus, although the absolute value of the potential variation Vc is large in this embodiment as compared with the conventional example, this case does not cause a disadvantage in practical use.

In the case of the vertical inversion shift, since only the scanning direction is reversed, similarly, the potential variation Vc due to the inter-pixel parasitic capacitance Cpp can be made smaller than that of the conventional example, and the display unevenness can be reduced.

Further, the GDOUBLE signal may be used to switch between the normal mode of the past mode and the gate 2 write mode of the present embodiment, as needed.

In this case, the above-described special display screen can be applied.

The above description is the case of the horizontal line inversion driving, but also in the case of the pseudo dot inversion (dot inversion driving in a triangular arrangement corresponding to the dot inversion driving in a stripe arrangement), the potential variation Vc due to the inter-pixel parasitic capacitance Cpp can be made smaller than in the past, and the display unevenness can be reduced.

The same applies to the case of stripe arrangement as well as to the case of delta arrangement of the pixels 16.

However, in the case where the pixels 16 are arranged in a triangular shape, display unevenness (for example, vertical stripes corresponding to fig. 13) has a meandering shape, and thus there is an effect that discomfort can be visually suppressed as compared with display unevenness in the vertical stripes generated in accordance with the stripe arrangement.

(embodiment 2)

The following describes example 2 of the present invention.

In this embodiment, the potential variation Vc due to the inter-pixel parasitic capacitance Cpp is added to the previously written pixel potential, and writing is performed, whereby the potential variation Vc due to the inter-pixel parasitic capacitance Cpp is cancelled, and display unevenness is eliminated.

Here, a case will be described in which the γ circuit block 30 using the drive circuit 12 corrects the potential variation. In addition, a case of a still picture in which unevenness is likely to be conspicuous will be described.

As shown in fig. 2, the drive circuit 12 has a γ circuit block 30. Fig. 5 is a diagram showing a circuit configuration of the γ circuit block 30. As shown in the figure, the γ circuit block 30 includes a γ curve resistor 38 and a tap switch (hereinafter referred to as "TAPSW") 40. The gamma curve resistor 38 is tapped so as to take out a potential corresponding to the gamma curve, and a voltage value corresponding to the gradation of the pixel data is supplied to the source driver block 24 via the TAPSW 40. The source drive block 24 is configured by a digital/analog conversion circuit (hereinafter referred to as DAC)42 and a source output amplifier 44, and a voltage value corresponding to the gradation of the pixel data is converted into an analog signal by the DAC42, passed through the source output amplifier 44, and output as a write voltage (video signal Vsig) to the corresponding source line in the LCD panel 10. Further, the amplitude adjustment signals VRH1, VRH2, VRL1, and VRL2, which are input to the γ circuit module 30, are supplied from the TG unit logic circuit 28 by switching the polarity of POL (the opposite polarity of the common voltage Vcom).

Fig. 6A is a graph showing a γ curve of the γ circuit module 30 when POL is L, that is, when the common voltage Vcom is H. Fig. 6B is a graph of a γ curve of the γ circuit module 30 when POL is H, that is, the common voltage Vcom is L. In these drawings, the "uncorrected" γ curve is a γ curve of a normal mode in which the correction of the potential variation Vc of the present embodiment is not performed. In contrast, in the present embodiment, the mode (hereinafter referred to as the data offset mode) for correcting the potential variation Vc can select a γ curve indicated as "having correction". The "corrected" gamma curve is a curve obtained by shifting a "uncorrected" gamma curve by a predetermined value in a direction of simple lighting (in the case of fig. 6A, in a direction of increasing output voltage, and in the case of fig. 6B, in a direction of decreasing output voltage) without changing the slope and the amplitude.

The constant value is a value that can appropriately correct potential variation Vc occurring in a gradation (halftone) where unevenness is easily noticeable, and is a value corresponding to Vc when Vsig (Fn-1) is Vsig (Fn) — Vsig (Fn).

Fig. 6C is a diagram showing the relationship between the output voltage in the data shift mode and the amplitude adjustment signals VRH1, VRH2, VRL1, and VRL2, and fig. 6D is a diagram showing the shift amount. Fig. 7A is a diagram showing a timing chart in the non-inversion offset, and fig. 7B is a diagram showing a timing chart in the up-down inversion offset.

When such a "corrected" γ curve is created, the voltage on the upper side and the voltage on the lower side of the DAC42 can be made to be voltages offset by a certain value, and therefore, the "corrected" γ curve can be created very easily.

As shown in fig. 6C and fig. 7A, 7B, in the present embodiment, as in the past, 2 gate lines are sequentially selected during one horizontal period, and a write voltage (video signal Vsig) corresponding to the selected gate line is output. At this time, in the γ circuit block 30, the writing voltage corresponding to one of the gate lines adopts a "no correction" γ curve, and the writing voltage corresponding to the other gate line adopts a "correction" γ curve. The γ circuit block 30 determines the timing of switching the gate line based on the G1STH signal, which is a signal provided from the TG section logic 28 and has a first half H and a second half L for one horizontal period.

The TG unit logic 28 inputs the data offset signal DSHIFT to the circuit block 30. As shown in fig. 6D, the offset is set according to LSB2 bits of the data offset signal DSHIFT. The reason for this is that the driving circuit 12 can be applied to a plurality of LCD panels 10, and the offset amount is selected by the connected driving circuit 12. In addition, by MSB1 bit of the data offset signal DSHIFT, the write voltage corresponding to which gate line of the front and rear is set to adopt a "corrected" γ curve. In the present embodiment 2, it is assumed that a "corrected" γ curve is used for the previous write voltage.

Further, as described above, the voltage written first undergoes potential variation so that the potential difference with the common voltage Vcom increases in the case of the horizontal line inversion driving, and undergoes potential variation so that the potential difference with the common voltage Vcom decreases in the case of the dot inversion driving. Thus, it is preferable that a γ curve corresponding to horizontal line inversion driving and a γ curve corresponding to (pseudo) dot inversion driving be stored in advance for the "corrected" γ curve, and the γ curve be selected and set according to the driving method.

Fig. 8A is a diagram showing a scan timing chart at the time of non-inversion shift of the data shift pattern of the present embodiment corresponding to fig. 15A. In this case, as in fig. 15A, in each field, 2 gate lines are sequentially selected in one horizontal period, and the selected 2 gate lines are sequentially scanned in the horizontal period.

Fig. 8B is a diagram showing a pixel potential waveform in the case where the amplitude of the common voltage Vcom is 5.0V in the horizontal line inversion driving, the writing voltage (video signal Vsig) of the pixel Fg before G is 2.0V (middle tone) with respect to the common voltage Vcom, and the writing voltage (video signal Vsig) of the pixel Lr after R is 4.0V (black) with respect to the common voltage Vcom.

In this case, a "corrected" gamma curve is used for the previously written voltage by MSB1 bit of the data offset signal DSHIFT.

Then, since POL is H, that is, Vcom is L, the group 1 pixel Fg before G adopts a "corrected" γ curve in which VRH2 is VRH2S and VRL2 is VRL2S, and the write voltage (video signal Vsig) of the pixel Fg before G is not 2.0V but 2.0V-Vc with respect to the common voltage Vcom. Further, for the pixel Lr after R, a "uncorrected" γ curve in which VRH2 is VRH2N and VRL2 is VRL2N is used, and the write voltage (video signal Vsig) of the pixel Lr after R is 4.0V with respect to the common voltage Vcom. In writing to the pixel Lr after R, the potential of the pixel Fg before G fluctuates by the amount of Vc due to the inter-pixel parasitic capacitance Cpp, and becomes (2.0V-Vc) + Vc. As a result, a desired pixel potential of 2.0V is formed with respect to the common voltage Vcom.

In field 2, since POL is L, that is, Vcom is H, a "corrected" γ curve in which VRH1 is VRH1S and VRL1 is VRL1S is adopted for the pixel Fg before G, and the writing voltage (video signal Vsig) of the pixel Fg before G is 2.0V-Vc, instead of 2.0V, with respect to the common voltage Vcom. Further, for the pixel Lr after R, a "uncorrected" γ curve in which VRH1 is VRH1N and VRL1 is VRL1N is used, and the write voltage (video signal Vsig) of the pixel Lr after R is 4.0V with respect to the common voltage Vcom. In writing to the pixel Lr after R, the potential of the pixel Fg before G varies by the amount of Vc due to the inter-pixel parasitic capacitance Vpp, and becomes (2.0V-Vc) + Vc. As a result, a desired pixel potential of 2.0V is formed with respect to the common voltage Vcom.

In this way, by correcting the potential variation Vc due to the inter-pixel parasitic capacitance Cpp by writing the potential variation Vc to the pixel potential written earlier, the potential variation Vc due to the inter-pixel parasitic capacitance Cpp is cancelled, and display unevenness can be eliminated. Further, the γ circuit block 30 using the driving circuit 12 can provide a simple and practical effect.

(modified example of embodiment 2)

In embodiment 2, the potential variation Vc due to the inter-pixel parasitic capacitance Cpp is canceled out by additionally writing the potential variation Vc due to the inter-pixel parasitic capacitance Cpp to the previously written pixel potential, but unevenness can be eliminated as shown in fig. 9A and 9B.

Fig. 9A is a diagram showing a scanning timing chart at the time of non-inversion offset in the data offset mode, similarly to fig. 8A, and fig. 9B is a diagram showing pixel potential waveforms in the case where the amplitude of the common voltage Vcom is 5.0V, the write voltage (video signal Vsig) of the pixel Fg before G is 2.0V (halftone) with respect to the common voltage Vcom, and the write voltage (video signal Vsig) of the pixel Lr after R is 4.0V (black) with respect to the common voltage Vcom, in the case where horizontal line inversion driving is performed.

As shown in fig. 9B, in the modification example of embodiment 2, the potential corresponding to the potential variation Vc 'occurring in the pixel written first is additionally written to the pixel potential written later, and both the pixel written first and the pixel written later are shifted by Vc' from the target potential, whereby at least display unevenness can be eliminated. (in this case, the potential variation Vc 'occurring in the pixel potential written first differs from the potential variation Vc occurring in embodiment 2 by the amount of potential to be added to the pixel potential written later, specifically, the offset voltage Vc' is 1/(1- (Cpp/Cs + Clc + Cpp). times.alpha.). times.Vc. ).

In this case, although the entire screen is shifted by the potential variation Vc 'due to the inter-pixel capacitance Cpp, the potential variation Vc' is originally a small voltage 2 bits smaller than the writing voltage Vsig, and therefore, even when the voltage of the entire screen is shifted, there is no practical problem in use.

Also in this case, by switching the γ circuit block 30 included in the driver circuit 12, a simple and practical effect can be obtained without adding another circuit. In the present modified example, the MSB1 bit of the data offset signal DSHFIT is set to use a "corrected" gamma curve for the subsequent write voltage.

In this way, if the correction level is corrected in accordance with the gray scale (halftone) of a portion where the unevenness is easily noticeable, the display unevenness can be improved while simplifying the circuit.

In addition, since the correction amount can be easily switched (as shown in fig. 6D), it is possible to flexibly cope with liquid crystals having different parasitic capacitances between pixels.

Further, since the direction of correction can be simply switched in accordance with the up-down inversion mode (as shown in fig. 6A, 6B, 6C, 6D, 7A, and 7B), it is possible to flexibly cope with various driving methods including the above-described polarity inversion mode.

In this way, the gamma circuit block 30 solves the problem of display unevenness due to potential variation occurring in pixels written first due to parasitic capacitance between pixels, and thus, it is not necessary to mount a new circuit which is not required, and good display without unevenness can be realized with a small space and at low cost.

The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments, and it is obvious that various modifications and applications can be made within the scope of the gist of the present invention.

For example, the method of gate 2 writing in embodiment 1 and the method of data shift in embodiment 2 are not related to each other.

Although the gamma circuit block is used to correct the potential variation in embodiment 2, it is obvious that the correction may be performed by another circuit provided separately for the correction.

In the above-described embodiment 2, the correction voltage is formed so as to be shifted by a constant value regardless of the gradation, but a correction amount corresponding to expression (1) may be calculated in accordance with the gradation to form an appropriate correction voltage. Also in this case, if the γ circuit block 30 is adopted, the selection manner of TAPSW40 of the γ curve resistance is switched corresponding to the gradation, it can be simply realized.

In addition, for example, in order to correspond to an animation of Vsig (Fn-1) ≠ Vsig (Fn), it can be realized if a circuit including a field memory is employed.

Although the description has been made above for the normally white liquid crystal, the present invention is similarly applicable to the case of the normally black liquid crystal whose transmittance is improved (brightened) by a large voltage applied to the pixel, since the direction of brightness is merely reversed.

The switching element is not limited to the TFT, and may be a diode or the like.

Further, the pixels of the matrix display device are not limited to liquid crystal, and if they are capacitive elements, parasitic capacitance between pixels occurs, so that display unevenness can be reduced similarly by the present invention.

Claims (3)

1. An active matrix type display device, wherein:

1 signal line is provided for every 2 pixels with respect to the direction in which the scanning lines extend;

2 pixels adjacent to each other in a direction in which the scanning lines extend, the 2 pixels sandwiching the signal lines, sharing the signal lines, and being connected to different scanning lines via switching elements;

the active matrix display device includes:

a scanning line driving circuit for sequentially selecting a plurality of the scanning lines; and

a signal line driving circuit for outputting a signal corresponding to information to be displayed to the plurality of signal lines;

the scan line driving circuit can be switched

A normal mode in which 2 scanning lines corresponding to the 2 pixels adjacent in the direction in which the scanning lines extend across the signal lines are sequentially selected in 1 horizontal period, and

and a 2-time writing mode in which only 1 scanning line of the 2 simultaneously selected scanning lines is selected after the 2 simultaneously selected scanning lines.

2. The active matrix type display device according to claim 1, wherein:

the plurality of pixels are arranged in a triangular shape.

3. The active matrix type display device according to claim 1, wherein:

the scanning line driving circuit simultaneously selects the 2 scanning lines and then selects the 1 scanning line in 1 horizontal period.