HK1120943B - Method and system for optimizing transmit power of a power amplifier using a battery voltage (vbat) monitor - Google Patents

Description

Method and system for controlling a circuit in a transmitter

Technical Field

The present invention relates to control of circuits in a communication device, and more particularly to using battery voltage (V)_bat) A method and system for a monitor (monitor) to optimize the transmit power of a power amplifier.

Background

Power amplification circuits in wireless systems are typically large signal devices. In a Wireless Local Area Network (WLAN) system, for example, a Power Amplifier (PA) circuit transmits an output signal at an average power between 10dBm and 20dBm, a peak power of about 20 to 30 dBm. In such WLAN systems, various types of modulation schemes may be used, for example from Binary Phase Shift Keying (BPSK) to 512-level (level) quadrature amplitude modulation (512-QAM), and thus the output power varies greatly, so that the ratio of peak power to average power is also large, for example 10dBm to 20 dBm.

The power output of the power amplifier is affected by the battery level. In the case where the power amplifier is designed to operate at a specific voltage, the performance of the power amplifier will be degraded when the battery voltage is higher or lower than the specific voltage. In other words, when the battery voltage that powers the transmitter (including the power amplifier) changes, the performance of the power amplifier will also change. Operation of the power amplifier at different bias levels can adversely affect linearity, output power, Adjacent Channel Power Ratio (ACPR), and Error Vector Magnitude (EVM).

The limitations on power amplifier circuit performance are further exacerbated when the power amplifier is integrated with other RF transmitter circuits, such as digital-to-analog converters (DACs), low-pass filters (LPFs), mixers, and RF programmable gain amplifiers (RFPGAs), in an Integrated Circuit (IC). However, as there is an urgent need to integrate more functions in a single IC, the increasing number of semiconductor devices, which follows, will push the development of semiconductor manufacturing techniques towards reducing the size of the semiconductor devices, and these particular semiconductor manufacturing techniques will impose more limitations on the performance of the integrated power amplifier circuit. For example, using a 65nm cmos process would limit the range of input power (for which the PA provides linear output power amplification). The requirement for AM-AM and or AM-PM distortion levels specified in WLAN standards (e.g., IEEE 802.11) will preclude output signals transmitted at high output power using power amplifiers fabricated using, for example, 65nm CMOS processes.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

The invention relates to the utilization of the battery voltage (V)_bat) A method and system for a monitor to optimize transmit power of a power amplifier.

According to an aspect of the present invention, there is provided a method of controlling a circuit in a transmitter, including:

the gain of at least one gain stage of a plurality of gain stages of a transmit channel is adjusted based on a control signal, wherein the control signal includes supply voltage indication information.

Preferably, the method further comprises receiving a supply voltage signal detected from a power supply for powering the transmit channel.

Preferably, the power supply voltage signal is generated by a power management unit.

Preferably, the supply voltage signal is detected directly from the power supply.

Preferably, the control signal is generated based on the detected supply voltage signal.

Preferably, the method further comprises comparing the supply voltage with a reference voltage.

Preferably, the method further comprises generating the control signal based on the comparison.

Preferably, a plurality of values of the control signal corresponding to a plurality of values of the supply voltage are stored in a look-up table.

Preferably, the method further comprises determining a control signal indicative of the supply voltage from the look-up table.

Preferably, the gain adjustment is based on one or more of transmit power, voltage standing wave ratio and modulation type.

According to another aspect of the invention, there is provided a system for controlling circuitry in a transmitter, comprising:

one or more circuits in the chip that adjust a gain of at least one gain stage of a plurality of gain stages of a transmit channel based on a control signal, wherein the control signal includes supply voltage indication information.

Preferably, the one or more circuits receive a supply voltage signal detected from a power supply for powering the transmit channel.

Preferably, the one or more circuits receive a supply voltage signal generated by a power management unit.

Preferably, the one or more circuits detect the supply voltage signal directly on the power supply.

Preferably, the one or more circuits generate the control signal based on the detected supply voltage signal.

Preferably, the one or more circuits compare the supply voltage to a reference voltage.

Preferably, the one or more circuits generate the control signal based on the comparison.

Preferably, the one or more circuits store a plurality of values of the control signal corresponding to a plurality of values of the supply voltage in a look-up table.

Preferably, the one or more circuits determine a control signal indicative of the supply voltage from the look-up table.

Preferably, the one or more circuits adjust the gain based on one or more of transmit power, voltage standing wave ratio, and modulation type.

According to an aspect of the present invention, there is provided a computer readable memory having stored therein a computer program comprising at least one code section for controlling circuitry in a transmitter, said at least one code section, when executed by a computer, causing the computer to perform the steps of:

the gain of at least one gain stage of a plurality of gain stages of a transmit channel is adjusted based on a control signal, wherein the control signal includes supply voltage indication information.

Preferably, the at least one code segment comprises code for receiving a supply voltage signal, wherein the supply voltage is detected from a power supply for powering the transmit channel.

Preferably, the at least one code segment comprises code for receiving a supply voltage signal generated by a power management unit.

Preferably, said at least one code segment comprises code for detecting said supply voltage signal directly on said power supply.

Preferably, said at least one code segment comprises code for generating said control signal based on said detected supply voltage signal.

Preferably, the at least one code segment comprises code for comparing the supply voltage with a reference voltage.

Preferably, said at least one code segment comprises code for generating said control signal based on said comparison.

Preferably, said at least one code segment comprises code for storing a plurality of values of said control signal corresponding to a plurality of values of said supply voltage in a look-up table.

Preferably, the at least one code segment comprises code for determining a control signal indicative of the supply voltage from the look-up table.

Preferably, the at least one code segment comprises code for adjusting the gain based on one or more of transmit power, voltage standing wave ratio and modulation type.

Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully described with reference to the following description and drawings.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1A is a schematic diagram of an exemplary mobile terminal that may be used in embodiments of the present invention;

FIG. 1B is a schematic diagram of exemplary I and Q transmit channels in accordance with embodiments of the present invention;

FIG. 2 is an exemplary V according to an embodiment of the present invention_batA schematic view of a monitor;

FIG. 3 isV according to an embodiment of the present invention_batA flow chart of monitor processing steps.

Detailed Description

The invention relates to the utilization of the battery voltage (V)_bat) A method and system for a monitor to optimize transmit power of a power amplifier. The scheme of the invention comprises the following steps: the gain of one or more gain stages in the transmit channel is adjusted based on a control signal that is a function of a battery voltage signal derived from a battery voltage used to power the transmit channel. The battery voltage signal may be received from a power management unit or obtained directly from the battery. The battery voltage signal may be compared to a reference signal and a control signal may be generated based on the comparison. The value of the control signal may be determined over a range of battery voltages and stored in a look-up table.

Fig. 1A is a schematic diagram of an exemplary mobile terminal that may be used in embodiments of the present invention. As shown in fig. 1A, mobile terminal 150 includes an RF receiver 153a, an RF transmitter 153b, a T/R switch 152, a digital baseband processor 159, a processor 155, a Power Management Unit (PMU)161, and a memory 157. The antenna 151 may be connected to a T/R switch 152. When the T/R switch 152 is placed in "R" or receive, the antenna 151 is connected to the RF receiver 153a, and when the T/R switch 152 is placed in "T" or transmit, the antenna 151 is connected to the RF transmitter 153 b.

The RF receiver 153a may comprise suitable logic, circuitry and or code that may be enabled to process a received RF signal. The RF receiver 153a is capable of receiving RF signals of various frequency bands used by various wireless communication systems, such as bluetooth, WLAN, GSM and/or CDMA systems.

The digital baseband processor 159 may comprise suitable logic, circuitry, and/or code that may enable processing of baseband frequency signals. In this regard, the digital baseband processor 159 may process signals received from the RF receiver 153a and/or process signals to be transmitted to the RF transmitter 153b (for transmission out over a wireless transmission medium). Based on information in the processed signal, the digital baseband processor 159 may also provide control signals and/or feedback information to the RF receiver 153a and the RF transmitter 153 b. Digital baseband processor 159 may communicate information and/or data in the processed signal to processor 155 and/or memory 157. In addition, the digital baseband processor 129 may receive information from the processor 155 and/or the memory 157, process it, and send it to the RF transmitter 153b for transmission out over a wireless transmission medium.

The RF transmitter 153b may comprise suitable logic, circuitry, and/or code that may enable processing of an RF signal to be transmitted. The RF transmitter 153b is capable of transmitting RF signals in various frequency bands used by various wireless communication systems, such as bluetooth, WLAN, GSM, and/or CDMA systems.

The processor 155 may comprise suitable logic, circuitry, and/or code that may enable control and/or data processing operations for the mobile terminal 150. The processor 155 may be used to control at least a portion of the RF receiver 153a, the RF transmitter 153b, the digital baseband processor 159, and/or the memory 157. In this regard, the processor 125 may generate at least one signal for controlling the internal operations of the mobile terminal 150.

The memory 157 may comprise suitable logic, circuitry, and/or code that may enable storage of data and/or other information for use by the mobile terminal 150. For example, the memory 157 may be used to store processed data generated by the digital baseband processor 159 and/or the processor 155. Memory 157 may also be used to store information, such as configuration information, that may be used to control the operation of at least one module in mobile terminal 150. For example, the memory 157 may include the necessary information for configuring the RF receiver 153a to be able to receive RF signals of an appropriate frequency band.

The Power Management Unit (PMU)161 may comprise suitable logic, circuitry, and/or code that may be operable to manage power requirements of various components within the mobile terminal 150. The PMU 161 may generate a battery voltage signal V_bat。

FIG. 1B is a schematic diagram of exemplary I and Q transmit channels in accordance with embodiments of the present invention. AS shown in fig. 1B, the transmit channel 100 includes digital-to-analog converters (DACs) 105 and 107, low pass filters 109 and 111, Active Stages (AS) 113, 115, 123, an in-phase up-conversion mixer 117 and a quadrature up-conversion mixer 119, an adder 120, a Power Amplification Driver (PAD)125, a Power Amplifier (PA)127, a transmit/receive (T/R) switch 129, and an antenna 133. The in-phase channel includes the DAC 105, LPF109, AS 113, and in-phase up-conversion mixer 117. The quadrature channel includes DAC 107, LPF111, AS 115, and quadrature up-conversion mixer 119. The transmitter 100 shown in FIG. 1B is one embodiment of the RF transmitter 153B of FIG. 1A.

The DAC 105 may comprise suitable logic, circuitry, and or code that may be operable to convert a digital signal to an analog output. The DAC 105 is arranged to receive an input signal, i.e. an in-phase digital intermediate frequency signal 101. The input signal may comprise one or more bits used to represent a digital value. The input digital signal may be a baseband signal that may be mapped to constellation points based on the modulation type. The mapped constellation points may be represented by analog signal amplitudes. The number of bits or characters represented by the analog signal amplitude may be determined based on the modulation type. The DAC 105 is capable of generating an analog output signal that is passed to the input of the low pass filter 109. DAC 107 is substantially identical to DAC 105. The DAC 107 is capable of receiving the input signal 103 from the baseband processor 135 and accordingly generating an analog signal that is passed to the input of the low pass filter 111.

The LPF109 may comprise suitable logic, circuitry, and/or code that may be operable to select a cutoff frequency, wherein the LPF109 may attenuate the amplitude of input signal components (components) having frequencies above the cutoff frequency; while the amplitude of the input signal components having frequencies below the cut-off frequency is "passed" or not attenuated, or, although attenuated, to a lesser extent than the attenuation of the input signal components having frequencies above the cut-off frequency. In various embodiments of the present invention, the LPF109 may be a passive filter, such as constructed using resistive, capacitive, and/or inductive elements; or may be an active filter, such as implemented using an operational amplifier. The LPF111 is substantially identical to the LPF 109. The LPF111 is capable of receiving the analog input signal from the DAC 107 and accordingly generating a low pass filtered signal that is passed to the input of the active stage 115.

The AS 113 comprises suitable logic, circuitry, and or code that may enable attenuation of an input signal to generate an attenuated output signal. The amount of attenuation produced by the AS 113, e.g., measured in dB, may be determined based on an input control signal, which may be generated by the processor 155 (AS shown in fig. 1A). The AS 113 can receive the output signal generated by the LPF 109. The AS 113 is capable of generating an amplified (amplified gain) or attenuated output signal and delivering it to the in-phase up-conversion mixer 117. AS 115 is substantially identical to AS 113. An input of AS 115 may be connected to an output of low pass filter 111 and an output of AS 115 is connected to an input of mixer 119.

The in-phase up-conversion mixer 117 may comprise suitable logic, circuitry, and/or code that may be enabled to generate an RF signal by modulating an input signal. The in-phase up-conversion mixer 117 may modulate the input signal with an input local oscillator signal LO 117. The modulated signal is an RF signal. The transmitter in-phase up-conversion mixer 117 may generate an RF signal having a carrier frequency that approximates the frequency of the local oscillator signal LO 117. The in-phase up-conversion mixer 117 is capable of receiving the output signal generated by the active stage 113 and generating an output signal that is passed to the active stage 123. The quadrature upconversion mixer 119 is substantially identical to the in-phase upconversion mixer 117. The input of the quadrature upconversion mixer 119 is connected to the output of the AS 115.

The adder 120 may comprise suitable logic, circuitry, and/or code that may be adapted to receive an analog input signal and generate an output signal that is the sum of the signals entering the adder. The adder 120 is capable of receiving the output signals generated by the in-phase up-conversion mixer 117 and the quadrature up-conversion mixer 119 to generate a signal 121.

The AS 123 comprises suitable logic, circuitry, and or code that enables attenuation of an input signal to generate an attenuated output signal. The amount of attenuation produced by the AS 123, e.g., measured in dB, may be determined based on an input control signal, which may be generated by the processor 155 (AS shown in FIG. 1A). AS 123 can receive the output signal generated by adder 120. The AS 113 can generate and transmit an increased or decreased output signal to the PAD 125.

The PAD 125 comprises suitable logic, circuitry, and or code that may be enabled to receive an analog input signal and generate an output signal that may be used to drive a power amplifier. The PAD 125 may receive an input control signal, which may be generated by the processor 155. The received control signal may be used to set the amount of gain or attenuation of PAD 125. The PAD 125 is capable of receiving the output signal generated by the AS 123. PAD 125 is capable of generating an output signal and transmitting to PA 127.

PA 127 comprises suitable logic, circuitry, and or code that may be enabled to amplify an input signal to generate a transmit signal having sufficient signal power (e.g., measured in dBm) to be transmitted out over a wireless communication medium. PA 127 may receive an input control signal, which may be generated by processor 155. The received control signal may be used to set the amount of gain or attenuation of PA 127.

A transmit/receive (T/R) switch 129 may comprise suitable logic, circuitry, and/or code that may be adapted to switch the antenna 133 between the transmit path 100 and an RF receiver. The antenna 133 includes appropriate circuitry for transmitting or receiving RF signals.

The baseband processor 135 comprises suitable logic, circuitry, and or code that may enable processing of binary data contained in an input baseband signal. Baseband processor 135 is substantially the same as digital baseband processor 159 shown in fig. 1A. The baseband processor 135 may perform processing tasks corresponding to one or more layers of an applicable Protocol Reference Model (PRM). For example, the baseband processor 135 may perform Physical (PHY) layer processing, layer 1(L1) processing, Medium Access Control (MAC) layer processing, Logical Link Control (LLC) layer processing, layer 2(L2) processing, and/or high-layer protocol processing based on input binary data. The processing tasks performed by baseband processor 135 may be referred to as processing in the digital domain. The baseband processor 135 may also generate control signals based on the processing of input binary data.

During operation, the baseband processor 135 may generate data comprising a bit sequence for transmission out over a wireless communication medium. The baseband processor 135 may generate control signals for configuring the RF transmit channel 100 to transmit data using a particular modulation type. Based on the particular modulation type, the baseband processor may send a portion of the data (an in-phase baseband (IBB) signal) to DAC 105 and another portion of the data (a quadrature baseband (QBB) signal) to DAC 107. DAC 105 may receive a bit sequence and generate an analog signal comprising a sequence of symbols. The number of bits represented by a single character may be determined based on the particular modulation type. The DAC 107 may also generate analog signals.

The analog signals generated by DAC 105 and DAC 107 may contain unwanted frequency components. The LPFs 109 and 111 may attenuate the signal amplitude of these unwanted frequency components in the signals generated by the DACs 105 and 107, respectively. The baseband processor 135 may configure the in-phase up-conversion mixer 117 to select the appropriate local oscillator LO117 signal frequency to modulate the filtered signal from the LPF 109. The modulated signal output from the in-phase up-conversion mixer 117 comprises an I-component RF signal. The baseband processor 135 may also configure the quadrature upconversion mixer 119 to generate a Q-component RF signal based on the filtered signal from the LPF 111. The I and Q component RF signals may be added by an adder 120 at the output of the in-phase up-conversion mixer 117 and the quadrature up-conversion mixer 119 to generate a quadrature composite (combined) RF signal.

The AS 123 may amplify the orthogonal composite RF signal, wherein the amplification provided by the AS 123 may be set based on a control signal generated by the baseband processor 135. PAD 125 may perform a second stage of amplification on the signal generated by AS 123, while PA 127 performs a third stage of amplification on the signal generated by PAD 125. When T/R switch 129 is set to "T" or transmit mode, the amplified signal from PA 127 may be transmitted through transmit antenna 133 into a wireless communication medium.

FIG. 2 is an exemplary V according to an embodiment of the present invention_batSchematic view of the monitor. As shown in FIG. 2, V_batMonitor 200 includes V_batA level detection center (core)209, voltage dividing resistors 203 and 205, a memory 215, and a processor 213. V_batThe level detection center 209 may comprise suitable logic, circuitry and/or code that may be enabled to receive a reference input signal V_ref207 and sense input signal V_sense219 and the latter is compared with the former. V_batThe output signal of the level detection center 209 is two inputs V_ref207 and V_sense219, relative amplitude. Reference voltage V_ref207 is a constant reference voltage that is not affected by temperature.

The voltage dividing resistors 203 and 205 can divide the supply voltage V of the battery_bat201 to a voltage level suitable for the processing operation of the circuit. In one embodiment of the invention, V may be paired by an integrated power management unit_bat201, monitoring is performed. In another embodiment of the invention, a separate V may be used_bat201 monitor circuit. The processor 213 may comprise suitable logic, circuitry, and/or code that may enable control of the transmit channel 100. Processor 213 is substantially the same as processor 155 shown in FIG. 1A and is capable of receiving V_batThe level detection center 209 generates an output signal 211. The processor 213 may receive other gain control inputs in addition to these. Other gain control inputs may include transmit power, Voltage Standing Wave Ratio (VSWR) conditions, and modulation type. For example, if a high order modulation type 64-QAM is used, the maximum transmit power may be slightly less to meet EVM requirements due to linearity requirements compared to simple modulation types such as Binary Phase Shift Keying (BPSK). At baseband there will be a number of variables fed to the transmit control loop processor 213 from which the actual transmit power is then determined. Memory 215 is substantially the same as memory 157 shown in FIG. 1A.

During operation, a voltage indicative of the battery voltage is provided from PMU 161 (as described in connection with FIG. 1A), or directly from the battery or other power sourceV_bat201, a voltage reduction process may be performed by voltage dividing resistors 203 and 205. Voltage V after voltage reduction_sense219 is transmitted to V_batAn input terminal of the level detection center 209 and a reference voltage V_ref207 for comparison. The output signal 211 is a voltage V_sense219 and a reference voltage V_ref207 compare the functions of the values.

Except for V_batThe output voltage 211 of the level detection center 209, the processor 213 may receive a plurality of input signals that may be used to control the transmit channel 100. The overall gain of the transmit channel 100 is the sum of the gains of the various gain stages, such as the active stages 113, 115, and 123, the PAD 123, and the PA 125 described in conjunction with fig. 1B. These gain stages can be designed to meet performance requirements at a particular voltage. Voltage V of the battery_batAn exemplary range for 201 may be 2.4-5.5 volts. If the gain stage can be designed or programmed for the lower voltage portion in the range of 2.4-5.5 volts, then when V is_bat201 above the design voltage, the output power may be greater than V_bat201 is at a level above the design voltage but below the lowest value that the power may reach. If the gain stage is programmable for the higher voltage portion, which may be in the range of 2.4-5.5 volts, then when V is_bat201 to the lower voltage portion of the range, such as when the battery is running low, the output power of the transmit channel 100 may force the gain stages to operate in a non-linear mode, which may cause ACPR and EVM to drop below desired levels. Therefore, the voltage V of the battery is required_bat201 monitors and adjusts the amount of gain of the gain stage accordingly.

In one embodiment of the invention, the gain stage may be designed to operate at the low end of the battery supply voltage range. When the battery voltage V_bat201 is higher than the design voltage (e.g. the battery is just charged), V_batV may be sensed by monitor 200_bat201 is high voltage and transmits a corresponding output signal 211 to the processor 213. The processor 213 generates a gain control signal 217 to increase the output power capacity of the gain stage due to the higher supply voltage present, resulting in an increase in the output power capacity of the gain stage, to improve transmissionThe amount of gain of one or more gain stages in the channel 100. For a given V_batThe required amount of gain may be calibrated and stored in a look-up table 201. The processor 213 may increase the amount of gain of one or more gain stages in the transmit channel 100 to maintain various performance metrics as needed, such as Adjacent Channel Power Ratio (ACPR), Error Vector Magnitude (EVM), linearity, and output power.

FIG. 3 is a V according to an embodiment of the invention_batA flow chart of monitor processing steps. Fig. 3 shows a flow chart 300. After start step 301, a voltage value V is received from a PMU, battery, or other power source in step 303_bat201. In step 305, a voltage V_bat201 down to a manageable voltage level. In step 307, V_batThe level detection center 209 applies the voltage V_bat201 and a reference voltage V_ref207 for comparison. In step 309, V_batThe output signal 201 of the level detection center 209 is transmitted to the processor 213. In step 311, the processor 213 determines the gain control signal 217 according to the look-up table. In step 313, a gain control signal is transmitted to the gain stage to apply the appropriate gain in the transmit channel 100. Process flow then ends at step 315.

In one embodiment of the present invention, the use of V is described_batA method and system for a monitor to optimize the transmit power of a power amplifier 127 includes adjusting the gain of the power amplifier gain stage in the transmit path 100 based on a control signal 217. The control signal 217 may be a function of the battery voltage signal 201, the signal 201 being derived from the voltage of the battery powering the transmit channel. The battery voltage signal 201 may be received from a power management unit or obtained directly from the battery. The battery voltage signal 201 may fall and the result of the comparison of the battery voltage signal 201 to the reference voltage 207 may be used by the processor 213 to generate the gain control signal 217. The value of the control signal may be determined over a range of battery voltages and stored in a look-up table.

Some embodiments of the present invention may include a computer readable memory having stored thereon a computer program having at least one code section for transmitting information in a network, the at least one code section, when executed by a computer, causing the computer to perform one or more of the steps described above.

The present invention can be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein. The method is implemented in a computer system using a processor and a memory unit.

Embodiments of the present invention may be implemented as a board level product (board level product), such as a single chip, an Application Specific Integrated Circuit (ASIC), or as separate components integrated with other portions of the system on a single chip with varying degrees of integration. The degree of integration of the system depends primarily on speed and cost considerations. Modern processors are so diverse that processors currently found on the market can be employed. Alternatively, if the processor is available as an ASIC core or logic module, the processor currently found on the market may be part of an ASIC device with firmware for various functions.

The present invention can also be implemented by a computer program product, which comprises all the features enabling the implementation of the methods of the invention and which, when loaded in a computer system, is able to carry out these methods. The computer program in the present document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following a) conversion to another language, code or notation; b) reproduced in different formats to implement specific functions.

While the invention has been described with reference to several embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (8)

1. A method of controlling a circuit in a transmitter, comprising:

comparing the supply voltage signal with a reference voltage and determining a control signal from a look-up table based on the comparison, the reference voltage being a constant reference voltage that is not affected by temperature; wherein for a given supply voltage signal, the required amount of gain is calibrated and stored in the look-up table;

adjusting a gain of at least one gain stage of a plurality of gain stages of a transmit channel based on the control signal, wherein the control signal includes supply voltage indication information.

2. The method of claim 1, comprising receiving the supply voltage signal detected from a power supply used to power a transmit channel.

3. The method of claim 2, wherein the supply voltage signal is generated by a power management unit.

4. The method of claim 2, wherein the supply voltage signal is detected directly from the power supply.

5. A system for controlling circuitry in a transmitter, comprising:

one or more circuits in the chip that compare the supply voltage signal to a reference voltage and determine a control signal from a look-up table based on the comparison, wherein for a given supply voltage signal, a desired amount of gain is calibrated and stored in the look-up table; and adjusting a gain of at least one gain stage of a plurality of gain stages of a transmit channel based on the control signal, wherein the control signal comprises supply voltage indication information; the reference voltage is a constant reference voltage that is not affected by temperature.

6. The system according to claim 5, wherein said one or more circuits receive said power supply voltage signal detected from a power supply for powering a transmit channel.

7. The system of claim 6, wherein the one or more circuits receive the supply voltage signal generated by a power management unit.

8. The system of claim 6, wherein the one or more circuits detect the supply voltage signal directly on the power supply.