HK1120870B - A conductive lithographic polymer and method of making devices using same - Google Patents

Description

Conductive lithographic polymer and method of making a device using the same

Background

Embodiments of the present invention relate to conductive lithographic polymers and methods of making interconnects and conductive features for devices comprising the conductive lithographic polymers.

An integrated circuit is an interconnected ensemble of devices formed within a semiconductor material and within a dielectric material overlying a semiconductor surface. Devices that may be formed within a semiconductor include transistors, bipolar transistors, diodes, and diffusion resistors, to name a few. Devices that may be formed within the dielectric include thin film resistors and capacitors. Silicon or silicon-containing materials are commonly used as substrates for these devices.

Typically, 100 integrated circuit chips (IC chips) are built on a single 8-inch diameter silicon wafer. The devices are interconnected by conductive vias (also called metallization layers) formed within the dielectric. Typically two or more layers of conductive vias are used as interconnects, with successive layers separated by dielectric layers. In current practice, a metallization layer (typically made of copper) is formed on a dielectric layer to create a conductive path. Examples of processing methods for forming metallization layers include Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), and electrochemical deposition. Electrochemical deposition of copper has been found to be the most cost effective way to deposit copper metallization layers. In addition to being economically viable, such deposition techniques provide substantially uniform thickness copper films that are mechanically and electrically suitable for interconnect structures.

An example of electrochemical deposition is described herein (FIGS. 1A-1E). First, an electroless copper plated layer 102 is formed on an insulating layer 104 of a substrate 106, which may include conductive features or devices 108 (FIG. 1A) thereon. The insulating layer 104 includes a via or via 110 to enable connection with the conductive feature 108. The insulating layer 104 is generally interposed between conductive patterns formed on a plurality of layers in order to ensure electrical insulation between the conductive patterns.

Next, a photoresist layer 112 is patterned on the electroless copper plating layer 102, as shown in fig. 1B. Next, an electrolytic copper plating layer 114 is formed on the exposed electroless copper plating layer 102, as shown in fig. 1C. The electroless copper plated layer 102 serves as a feed (electrical feed) or seed layer for the electrolytic plating layer 114.

Next, as shown in fig. 1D, the photoresist layer 112 is removed. The exposed electroless copper layer 102 is then removed with a copper etchant, as shown in FIG. 1E. An alkaline etching solution is generally used as the etching solution. For the foregoing reason, the conductive pattern 116 in which the electrolytic copper plated layer 114 is laminated on the electroless copper plated layer 102 may be formed on the insulating layer 104. To form a multi-layer device, the process is typically repeated iteratively.

Current practice requires a longer time for the fabrication of devices such as printed circuit boards due to the time consumed in film lamination to complete the patterning of the conductive layer. Multiple uses of the photoresist layer are required, as well as multiple uses of the electroless and electrolytic coatings, and removal in each step. In addition, various control systems are required for the chemical solution to maintain line stability, for example, in the electroless plating process, to accurately and carefully control the amount to be deposited and control the thickness of the electroless plating layer. The fabrication process of the device is therefore time consuming and expensive.

Brief Description of Drawings

Embodiments of the invention are illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like references indicate similar elements. The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. It should be noted that references to "an" embodiment of the invention in this specification are not necessarily to the same embodiment, but to at least one. In the drawings:

FIGS. 1A-1E illustrate an example of a prior art method of electrochemically forming conductive paths for a device;

FIGS. 2A-2E illustrate an exemplary method of forming a conductive via according to an embodiment of the present invention; and

FIGS. 3A-3D illustrate another exemplary method of forming a conductive via according to an embodiment of the present invention;

Detailed Description

Exemplary embodiments are described below with reference to specific configurations and techniques. Those skilled in the art will appreciate that various changes and modifications can be made within the scope of the appended claims. In addition, well-known elements, devices, components, circuits, process steps and the like are not set forth in detail.

Exemplary embodiments of the present invention relate to conductive lithographic polymers and methods of making devices (e.g., printed circuit boards) having interconnects and conductive features comprising the conductive lithographic polymers. Conductive lines and conductive vias are used throughout the fabrication process of the device. For example, devices are formed on a substrate and interconnected to each other through insulating layers and conductive vias or metallization layers. As discussed above, electrochemical methods are well known and widely used for making such conductive paths. Conventional methods typically require multiple etching and lithographic steps in making the conductive paths of the semiconductor device. The existing practice requires long production time and high cost for device fabrication.

Exemplary embodiments of the present invention disclose a conductive lithographic polymer that can be used to make conductive paths, metallization layers, or other conductive features for semiconductor devices. The conductive lithographic polymer used herein can be a synthetic material, including intrinsically conductive polymers and polymers with optical properties. The conductive lithographic polymer can also be a material comprising a lithographic polymer and a conductive polymer comprising a physical mixture of a non-conductive polymer and a conductive material such as a metal or carbon powder. The conductive lithographic polymer can also be a material comprising a lithographic polymer and a conductive polymer comprising a physical mixture of the conductive polymer and another conductive material, such as a metal or carbon powder added to the polymer to enhance the conductivity of the conductive polymer. Conductive lithographic polymers can be used as photoresist materials due to their optical properties. Standard lithographic methods can be used to pattern the conductive lithographic polymer. Due to its conductive properties, lines, traces or vias formed with conductive lithographic polymers can be used as conductive lines or vias or metallization layers. The conductive lithographic polymer can thus replace the aforementioned conventional photoresist layer plus electroless plating or can replace the aforementioned conventional photoresist layer, electroless plating, and electrolytic plating. The conductive lithographic polymer can also be used to form other conductive lines and/or metallization layers that are currently formed with metals such as copper.

In one embodiment, the conductive lithographic polymer is a mixture comprising (1) from about 50% to about 60% (weight percent) of a mixture of an epoxy acrylate, a thermal curing agent, and a conductive polymer; (2) from about 20% to about 30% by weight of a lithographically-active component; (3) from about 10% to about 15% (weight percent) of a photoactive material; and (iv) from about 3% to about 5% (weight percent) of an additive to increase the conductivity of the conductive lithographic polymer or to function as an additional functional conductivity for the conductive lithographic polymer.

The ratio of epoxy acrylate, thermal curing agent, and conductive polymer can vary depending on the desired level of conductivity of the conductive lithographic polymer and the conductivity of the conductive polymer used in the mixture.

In one embodiment, the epoxy acrylate is a mixture of an acid functional monomer and a non-acid functional monomer. The epoxy acrylate may be selected from the group consisting of acrylic acid, methacrylic acid, maleic acid, fumaric acid, citraconic acid, 2-acrylamido-2-methylpropanesulfonic acid, 2-hydroxyethyl acrylate phosphate (2-hydroxyethoxylyl phosphate), 2-hydroxypropyl acrylate phosphate, 2-hydroxy-alpha-acryloylphosphate, methyl acrylate, 2-ethylhexyl acrylate, n-butyl acrylate, n-hexyl acrylate, methyl methacrylate, hydroxyethyl acrylate, butyl methacrylate, octyl acrylate, 2-ethoxyethyl methacrylate, and tert-butyl acrylate.

In one embodiment, the thermal curing agent is selected from the group consisting of imidazole, imidazole derivatives, 2-methylimidazole, 2-ethylimidazole, 2-ethyl-4-methylimidazole, 2-phenylimidazole, 4-phenylimidazole, 1-cyanoethyl-2-phenylimidazole, 1- (2-cyanoethyl) -2-ethyl-4-methylimidazole, guanamine, acetoguanamine, benzoguanamine, amines, dicyandiamide, benzyldimethylamine, 4- (dimethylamino) -N, N-dimethylbenzylamine, 4-methoxy-N, N-dimethylbenzylamine, 4-methyl-N, N-dimethylbenzylamine, melamine, phenol-formaldehyde resins, phenol-formaldehyde novolacs, and cresol novolacs.

In one embodiment, the electrically conductive polymer is intrinsically or naturally electrically conductive. In one embodiment, the electrically conductive polymer is selected from the group consisting of polyaniline, polypyrrole, polythiophene, polyphenylenevinylene, polydialkylfluorene, polyaniline derivatives, polypyrrole derivatives, polythiophene derivatives, and nanocomposite polymers. The conductive material may also be I (AsF)₅) Polyacetylene or polysulfide nitride containing a dopant.

In one embodiment, the lithographically-active component is a monomer, dimer, or short-chain oligomer containing ethylenic unsaturation. The lithographic active ingredient may be selected from styrene maleic anhydride copolymers and similar anhydride-containing copolymers, wherein each of the styrene maleic anhydride copolymers and similar anhydride-containing copolymers is partially esterified with a hydroxy-functional (meth) acrylate. In one embodiment, the hydroxy-functional (meth) acrylate is selected from the group consisting of hydroxyethyl acrylate, acrylic acid, methacrylic acid, maleic acid, fumaric acid, and citraconic acid functional monomers.

In one embodiment, the photoactive material is selected from the group consisting of 9-phenylacridine, N-phenylglycine, aromatic ketones, 4 '-bis (N, N-diethylamino) benzophenone, and 4-methoxy-4' -dimethylaminobenzophenone. The aromatic ketone can be benzophenone, 4' -bis (N, N-dimethylamino) benzophenone.

Surfactants may also be included in the additive. In one embodiment, the additive is selected from the group consisting of color formers, surfactants, catalysts, fillers, plasticizers, and metal powders. The additive may be a component that enhances the conductivity of the polymer. Materials that can be used as additives also include conductive agents, metals, metal powders, and nanosized metal powders. The conductive material may be copper, gold, titanium, chromium, aluminum, iron, nickel, cobalt, zinc, copper zinc, nickel-iron, cobalt-iron, silver, graphite, or carbon black powder, etc.

The mixture for preparing the conductive lithographic polymer comprises a solvent. The solvent may be selected from various types of suitable organic solvents, including hydrocarbon solvents or alcohols. The organic solvent may also be selected from the group consisting of ketones, methyl ethyl ketone, cyclohexanone, aromatic hydrocarbons, toluene, xylene, tetramethylbenzene, glycol ethers, diethylene glycol monoethyl ether, dipropylene glycol diethyl ether, esters, ethyl acetate, butyl cellosolve acetate, carbitol acetate, aliphatic hydrocarbons, octane, decane, white spirit, naphtha and solvent naphtha.

The conductive photolithographic polymer has a conductivity comparable to that of a conductive metal such as copper, iron, nickel, cobalt, zinc, copper zinc, nickel-iron, or cobalt-iron. By varying the concentration of the additive or metal powder, the conductivity of the conductive photolithographic polymer can be made comparable to the conductivity of these conductive metals. In one embodiment, the conductive photolithographic polymer has a conductivity of about 1X 10^-10About 1X 10⁶Siemens per centimeter. Typically, the level of conductivity of copper is about 1 × 10⁶The conductivity level of the semiconductor material is about 1 x 10 per cm of siemens^-8Siemens per centimeter to about 1X 10²Siemens per centimeter.

Films, patterns or lines formed with the conductive lithographic polymer can be obtained with lithographic techniques currently used in device fabrication. Standard lithographic techniques can be used to make films, lines, or patterns of conductive lithographic polymers on various substrates. After fabrication, films, lines, or patterns of these conductive lithographic polymers can form conductive features or metallization for various semiconductor or electronic devices. The conductive lithographic polymer can be formed on a substrate from an ink, solution or dry film by a deposition, printing or lamination process. The conductive lithographic polymer can be used in the fabrication of electronic devices, microelectronic devices, microprocessors, chip sets, electrical controllers, printed circuit boards, electrical devices, optical couplers, optoelectronic components, display components, liquid crystal displays, flat panel displays, and the like, all of which can use the conductive lithographic polymer in the circuitry of such devices.

In one embodiment, an electronic device, such as a printed circuit board, is formed with a conductive lithographic polymer as described above. It should be noted that the foregoing exemplary mixtures of conductive lithographic polymers are not the only components that can be used to make the conductive lithographic polymers used in electronic devices. The fabrication of electronic devices that may benefit from the conductive photolithographic polymers will be described with reference to fig. 2A-2D.

First, an insulating layer 250 having an opening 240 as a via or a through hole is formed on both surfaces (top and bottom surfaces) of a core substrate 200 (fig. 2A). The substrate 200 may be any desired substrate such as an organic material, a ceramic, a glass, or a semiconductor material (e.g., silicon, a silicon-containing material, silicon on an insulating material, a silicon germanium material). The substrate 200 may include microelectronic structures such as transistors or integrated circuits (not shown) formed thereon or therein.

The substrate 200 also includes a conductive feature 202. The conductive features 202 may be formed on the top, side, and bottom surfaces of the substrate 200. The conductive features 202 may be one or more conductive contacts or metallization layers of a device (not shown) such as a transistor or integrated circuit (not shown) that has been formed in the substrate 200 using methods well known in the art. The conductive contacts may be made of copper, titanium, aluminum, chromium, or other suitable conductive material.

The insulating layer 250 is a conventional dielectric or insulating material commonly used in semiconductor devices. The insulating layer 250 is formed on the substrate 200 using conventional methods well known in the art. Vias or through holes 240 are created through the insulating layer 250 so that electrical contact can be established for the conductive features 202. The insulating layer 250 may be formed on both the top and bottom surfaces of the substrate 200 depending on the application and device.

Next, a conductive photolithographic film 230 is formed on the surface of the insulating layer 250 (fig. 2A). In one embodiment, the conductive photolithographic film 230 is formed on both the top and bottom surfaces of the insulating layer 250. In one embodiment, the conductive photolithographic film 230 is formed from an ink solution in which the conductive photolithographic material is printed or laid down on the surface of the insulating layer 250. The printed conductive photolithographic material is then allowed to dry or cure to form the conductive photolithographic film 230. Alternatively, the conductive photolithographic film 230 may be formed by laminating a dry film onto the surface of the insulating layer 250. Pressure and temperature may be applied to cause the conductive photolithographic film 230 to flow into the vias or through holes 240 to contact the conductive features 202.

The conductive photolithographic film 230 is then masked with a mask 241 in the desired circuit pattern of the film 230 in a manner similar to masking a photoresist film as is well known in the art (fig. 2B). The conductive photolithographic film 230 is then exposed, for example, to about 50-150mJ/cm²As is often done in exposing a photoresist film. The exposed conductive photolithographic film 230 is then developed to produce the desired conductive photolithographic film pattern. Upon development of the film 230, the unmasked portions 230 of the conductive lithographic film are removed, leaving masked portions 232 of the conductive lithographic film, as shown in fig. 2C. The developer may be a conventional developer well known in the art for developing photoresist films, such as a 0.7-1.0% solution of sodium.

The conductive photolithographic film 232 may have a thickness similar to that of a typical electroless plating film used in conventional processes for forming conductive vias as previously described. In one embodiment, the conductive photolithographic film 232 has a thickness between about 0.5 μm to about 10 μm.

The circuitry of the conductive photolithographic film 232 is designed or configured such that all of the circuitry is connected to an outer electrode (not shown) that is electrolytically plated with copper. The connection lines are etched after electrolytic copper plating.

Next, an electrolytic plating film 234 is formed on the conductive photolithographic film 232 by a method well known in the art (fig. 2D). For example, the electrolytic plating film 234 may be formed by immersing the substrate 200 in a plating solution and flowing an electric current through the conductive photolithographic film 232. The electrolytic plating film 234 will be formed on the conductive photolithographic film 232. The thickness of the electrolytic plating film 234 may be about 5 to 30 μm. The electrolytic plating film 234 is typically an electrolytic copper plating film. In one embodiment, a solution comprising about 180g/L sulfuric acid and about 80g/L copper sulfate is used in the electrolytic plating process to form electrolytic plating film 234. The electrolytic plating film 234 and the conductive photolithographic film 232 together form a conductive pattern or circuit pattern 236 of the semiconductor device. In the embodiment where the conductive photolithographic film 232 is formed on both the top and bottom surfaces of the substrate 200, the electrolytic plating film 234 may also be formed on both the top and bottom surfaces of the substrate 200, as shown in fig. 2D. After the electrolytic plating, the wiring connected to the external pole used for the electrolytic plating is etched away by a conventional method.

The process shown in fig. 2A-2D may be repeated as many times as desired to form additional conductive pattern layers of a multi-layer semiconductor device. For example, another insulating layer 247 may be formed atop the substrate 200 and over the conductive pattern 236, as shown in fig. 2E. Vias/vias 249 are created through the insulating layer to establish connections with the conductive patterns 236 or other conductive features on the substrate 200. The process of forming the conductive photolithographic film and the foregoing electrolytic film may then be repeated as well to produce additional desired circuit patterns.

In one embodiment, the conductive features 202 shown above may also be made from a conductive lithographic polymer. In this embodiment, a conductive lithographic polymer (such as those previously described) is formed, deposited, or laminated (in ink or dry film form) onto the substrate 200 to form a conductive lithographic polymer film. The conductive lithographic polymer film is then masked, exposed, and developed in a similar manner as previously described to form the desired circuit pattern for the conductive features 202. After patterning the conductive lithographic film, conductive elements 202 are then formed on the substrate 250. In embodiments where the conductive lithographic polymer is laid down as a film, pressure and temperature may be applied to cause the conductive lithographic polymer film to flow into crevices, openings, trenches, or vias (not shown) on the substrate 200.

In the above embodiments, a conductive lithographic polymer is used instead of the electroless copper plating process and the photoresist process as used in the conventional method of forming a conductive pattern. In some other embodiments, conductive lithographic polymers are used to replace electroless copper plating, photoresist, and electrolytic copper plating as used in conventional methods of forming conductive patterns. Such an embodiment is illustrated in fig. 3A-3C. In these embodiments, a conductive lithographic polymer film is first formed on the substrate surface. The conductive lithographic polymer film is then masked, exposed and developed to form a conductive pattern. The conductive lithographic polymer film should be formed thick enough and have sufficient conductivity so that electrolytic plating is not necessary.

In fig. 3A, an insulating layer 350 having an opening 340 as a via or via is formed on a surface (as shown herein, each of the top and bottom surfaces) of the core substrate 300. The substrate 300 may be any desired substrate such as an organic material, a ceramic, a glass, or a semiconductor material (e.g., silicon, a silicon-containing material, silicon on an insulating material, a silicon germanium material). Substrate 300 may include microelectronic structures such as transistors or integrated circuits (not shown) formed thereon or therein. The substrate 300 also includes conductive features 302. The conductive features 302 may be formed on the top, side, and bottom surfaces of the substrate 300. The conductive features 302 may be conductive contacts or metallization layers for devices (not shown) that have been formed in the substrate 300, such as transistors or integrated circuits, using methods well known in the art. The conductive contacts may be made of copper, titanium, aluminum, chromium, or other suitable conductive material.

Next, a conductive photolithographic film 330 is formed on the surface of the insulating layer 350. In one embodiment, the conductive photolithographic film 330 is formed on both the top and bottom surfaces of the insulating layer 350. In one embodiment, the conductive photolithographic film 330 is formed from an ink solution in which a conductive photolithographic material is printed or laid down on the surface of the insulating layer 350. The printed conductive photolithographic material is then allowed to dry or cure to form the conductive photolithographic film 330. Alternatively, the conductive photolithographic film 330 may be formed by laminating a dry film onto the surface of the insulating layer 350. Pressure and temperature may be applied to cause the conductive photolithographic film 330 to flow into the vias or through-holes 340 to contact the conductive features 302. After being formed on the insulating layer, the conductive photolithographic material may fill in the openings, vias, trenches, or crevices, as shown in fig. 3A-3C.

The conductive photolithographic film 330 is then masked with a mask 362 in the desired circuit pattern of the film 330 using methods well known in the art similar to masking photoresist films (fig. 3B). The conductive photolithographic film 330 is then exposed, for example, to about 50-150mJ/cm²As is often done in exposing a photoresist film. The exposed conductive photolithographic film 330 is then developed to produce the desired conductive photolithographic film pattern. Upon development of the film 330, the unmasked portions 330 of the conductive lithographic film are removed, leaving masked portions 332 of the conductive lithographic film, as shown in fig. 3C. The developer may be a conventional developer well known in the art for developing photoresist films, such as a 0.7-1.0% solution of sodium.

The conductive photolithographic film 332 may have a thickness similar to the thickness of a typical electroless plating film plus a typical electroplating film used in conventional processes for forming conductive vias as previously described. In one embodiment, the conductive photolithographic film 332 has a thickness between about 10 μm to about 100 μm.

The process shown in fig. 3A-3C may be repeated as many times as desired to form additional conductive pattern layers of a multi-layer semiconductor device. For example, as shown in fig. 3D, another insulating layer 347 may be formed atop the substrate 300 and on the conductive pattern 332. Vias/vias 349 are created through the insulating layer 347 to establish connections with the conductive patterns 332 or other conductive features on the substrate 300. The process of forming the conductive photolithographic film can then be repeated as well to produce additional desired circuit patterns.

In one embodiment, the conductive features 302 shown above may also be made from a conductive lithographic polymer. In this embodiment, a conductive lithographic polymer (such as those previously described) is formed, deposited, or laminated (in ink or dry film form) onto the substrate 300 to form a conductive lithographic polymer film. The conductive lithographic polymer film is then masked, exposed, and developed in a similar manner as previously described to form the desired circuit pattern for the conductive features 302. After patterning of the conductive lithographic film, conductive elements 302 are then formed on the substrate 300. In embodiments where the conductive lithographic polymer is laid down as a film, pressure and temperature may be applied to cause the conductive lithographic polymer film to flow into crevices, openings, trenches, or vias (not shown) on the substrate 300.

Embodiments of the present invention may be used to shorten the longer semiconductor device fabrication process time due to electroless and electrolytic plating processes. In addition, the embodiments can reduce the materials (e.g., photoresist materials and electroless plating materials) used in fabrication intermediate steps typically used in coating and etching processes.

While the invention has been described with reference to several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described. The method and apparatus of the present invention can be adapted and varied within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

The foregoing discloses exemplary embodiments, and modifications and variations may be made to the disclosed embodiments without departing from the spirit and scope of the invention as defined by the following claims.

Claims (19)

1. A method of fabricating a device, the method comprising:

depositing a conductive photolithographic polymer film on the surface of the dielectric layer on the substrate; and

patterning a conductive photolithographic polymer film with a lithographic process to create a circuit pattern, the lithographic process comprising masking, exposing and developing the conductive photolithographic polymer film to remove unmasked portions of the conductive photolithographic polymer film;

forming a conductive film on the circuit pattern using an electrolytic plating process, wherein the circuit pattern includes masked portions of the conductive photolithographic polymer film.

2. The method of claim 1, further comprising:

the dielectric layer having one or more vias formed thereon prior to deposition of the conductive photolithographic polymer film, wherein the dielectric layer insulates the substrate from the conductive photolithographic polymer film and the conductive photolithographic polymer film is formed on the dielectric layer.

3. The method of claim 2, wherein the substrate further comprises one or more features comprising conductive elements formed therein, and the vias enable electrical interconnection of the conductive elements.

4. The method of claim 3, further comprising:

interconnecting the conductive photolithographic polymer film with the conductive element.

5. The method of claim 3, further comprising:

depositing a second conductive photolithographic polymer film on the other side of the substrate; and

the second conductive photolithographic polymer film is patterned with a lithographic process to create a second circuit pattern.

6. The method of claim 5, further comprising:

a second dielectric layer having one or more vias formed on the other side of the substrate prior to deposition of a second conductive photolithographic polymer film, wherein the second dielectric layer insulates the other side of the substrate from the second conductive photolithographic polymer film, and the second conductive photolithographic polymer film is formed on the second dielectric layer.

7. The method of claim 6, wherein the vias of the second dielectric layer enable electrical interconnection of the conductive elements.

8. The method of claim 7, further comprising:

interconnecting the second conductive photolithographic polymer film with the conductive element.

9. The method of claim 8, further comprising:

forming an additional conductive film on the circuit pattern of the second photolithographic polymer film using an electrolytic plating process; and

the further conductive film is interconnected with the conductive element by a via.

10. An electronic device, the device comprising:

a substrate;

a dielectric layer formed on the substrate;

a conductive photolithographic polymer film formed on the dielectric layer, wherein the conductive photolithographic polymer film is patterned in a circuit pattern using a lithographic process; and

a conductive film formed on the circuit pattern using an electrolytic plating process.

11. The electronic device of claim 10, wherein the substrate comprises one or more components having conductive elements therein, and the dielectric layer has vias therethrough, the vias enabling electrical interconnection of the conductive elements, and the conductive photolithographic polymer film is electrically interconnected with the conductive elements through the vias.

12. The electronic device of claim 11, wherein the conductive film is interconnected to the conductive element by a via.

13. The electronic device of claim 10, wherein the conductive lithographic polymer film comprises an intrinsically conductive polymer.

14. The electronic device of claim 10, wherein the substrate comprises a printed circuit board.

15. The electronic device of claim 10, wherein the conductive photolithographic polymer film comprises a metal.

16. The electronic device of claim 10, wherein the conductive photolithographic polymer film comprises a metal powder.

17. The electronic device of claim 10, wherein the conductive photolithographic polymer film comprises a nanosized metal powder.

18. The electronic device of claim 10, wherein the conductive photolithographic polymer film comprises graphite.

19. The electronic device of claim 10, wherein the conductive photolithographic polymer film comprises carbon black powder.