HK1120671B - Method and system for signal processing in receiver - Google Patents

Description

Method and system for processing signals in a receiver

Technical Field

The present invention relates to processing of received wireless signals, and more particularly, to a method and system for low complexity conjugate gradient based equalization in a wireless system.

Background

In most existing wireless communication systems, nodes in the network system can be arranged to operate based on a single transmit or a single receive antenna. However, for many existing wireless systems, the use of multiple transmit and/or receive antennas may result in an overall improvement in system performance. These multiple antenna configurations, such as known smart antenna techniques, may be used to reduce the negative effects of multipath and/or signal interference on signal reception. Existing systems and/or systems now being deployed, such as Code Division Multiple Access (CDMA) based systems, Time Division Multiple Access (TDMA) based systems, Wireless Local Area Network (WLAN) systems, and Orthogonal Frequency Division Multiplexing (OFDM) based systems, such as ieee802.11a/g, may benefit from multiple transmit and/or receive antenna based configurations. It should be appreciated that smart antenna technology is increasingly being used in connection with the deployment of base station infrastructure and mobile subscriber units in cellular systems to meet the increasing performance demands placed on these systems. These needs stem in part from an ongoing transition from pure voice services to next generation wireless multimedia services that provide integrated voice, video, and data transmission.

The use of multiple transmit and/or receive antennas introduces diversity gain and suppresses interference generated during signal reception. Such diversity gain improves system performance by increasing the received signal-to-noise ratio, providing greater robustness to signal interference, and/or allowing greater frequency reuse for higher capacity. In a communication system employing a multi-antenna receiver, a set of M receive antennas may be used to nullify the effects of M-1 interferers. Thus, N signals may be transmitted simultaneously in the same bandwidth using N transmit antennas, and then the transmitted signals are separated into N separate signals via a set of N antennas configured on the receiver side.

This type of system is known as a multiple-input multiple-output (MIMO) system. One attractive aspect of multi-antenna systems, particularly MIMO, is that by using these transmission configurations, a significant increase in system capacity can be obtained. For a fixed total transmit power, the performance provided by the MIMO configuration may increase proportionally with increasing signal-to-noise ratio. For example, in the case of a fading multipath channel, the MIMO configuration increases system row performance by: for every 3-db increase in signal-to-noise ratio, the system performance increases by nearly M additional bits/period.

However, widespread deployment of multiple antenna systems in wireless communications, particularly wireless handset devices, is limited by the increased cost due to increased size, complexity, and power consumption. It is assumed that separate signal chains for each transmit and receive antenna is a direct factor in the cost increase in multi-antenna systems. Each RF chain typically includes a Low Noise Amplifier (LNA), a filter, a down-converter, and an analog-to-digital (a/D) converter. In some existing signal-antenna wireless receivers, a single necessary RF chain may account for over 30% of the total cost of the receiver. Thus, it is apparent that as the number of transmit and receive antennas increases, the complexity, power consumption, and overall cost of the system also increases.

In addition, multipath transmission in a bandwidth-limited time-dispersive channel may cause intersymbol interference (ISI), which is considered to be the most significant hindrance in increasing a data transmission rate with a desired accuracy. ISI may occur when a transmitted pulse is erased so that pulses corresponding to different symbols will not be discernable or separated. Meanwhile, due to inter-carrier interference (ICI) caused by the imperfection of the multiple access scheme, data obtained from an intended user may be interfered by other transmitters. For a reliable data transmission system, it is desirable to reduce ISI and ICI effects.

Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.

Disclosure of Invention

A system and/or method for low complexity conjugate gradient based equalization in a wireless system, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.

According to an aspect of the present invention, there is provided a method for processing a signal in a receiver, the method comprising:

updating a plurality of filtering branches (filter taps) for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector based on initialization values related to the at least one channel response vector and the at least one correlation vector; and

filtering at least a portion of the received signal clusters using at least a portion of the updated plurality of filtering branches.

Preferably, the method further comprises repeating the updating whenever a certain signal-to-noise ratio (SNR) for the received signal constellation is reached.

Preferably, the method further comprises updating the initialization value over a plurality of iterations.

Preferably, the method further comprises repeating the updating as long as a certain number of iterations is reached.

Preferably, the method further comprises generating a plurality of chip rate synchronously sampled signals using the plurality of received signal clusters.

Preferably, the method further comprises generating the plurality of chip rate synchronously sampled signals using a chip clock signal.

Preferably, the method further comprises generating the at least one correlation vector using the plurality of chip rate synchronously sampled signals.

Preferably, the at least one correlation vector comprises a complex conjugate of a plurality of chip-synchronously sampled signals, wherein the plurality of chip-synchronously sampled signals are based on the plurality of received signal clusters.

Preferably, the method further comprises updating the at least one channel response vector and the at least one correlation vector based on a minimum mean square error algorithm (MMSE).

Preferably, the method further comprises generating at least one estimate of the plurality of clusters of received signals based on the filtering.

According to an aspect of the invention, there is provided a system for processing a signal in a receiver, the system comprising:

at least one processor configured to update a plurality of filtering branches for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector based on initialization values related to the at least one channel response vector and the at least one correlation vector; and

the at least one processor filters at least a portion of the received signal clusters using at least a portion of the updated plurality of filtering branches.

Preferably, the at least one processor repeats the updating to achieve a particular signal-to-noise ratio (SNR) for the received signal constellation.

Preferably, the at least one processor updates the initialization value over a plurality of iterations.

Preferably, the at least one processor repeats the updating as long as a certain number of iterations is reached.

Preferably, the at least one processor generates a plurality of chip rate synchronously sampled signals using the plurality of received signal clusters.

Preferably, the at least one processor generates the plurality of chip rate synchronously sampled signals using a chip clock signal.

Preferably, the at least one processor generates the at least one correlation vector using the plurality of chip rate synchronously sampled signals.

Preferably, the at least one correlation vector comprises a complex conjugate of a plurality of chip-synchronously sampled signals, wherein the plurality of chip-synchronously sampled signals are based on the plurality of received signal clusters.

Preferably, the at least one processor updates the at least one channel response vector and the at least one correlation vector based on a minimum mean square error algorithm (MMSE).

Preferably, the at least one processor generates at least one estimate of the plurality of clusters of received signals based on the filtering.

According to one aspect of the present invention there is provided a machine readable storage, having stored thereon, a computer program comprising at least one code section for processing a signal in a receiver, the at least one code section being executable by a machine for causing the machine to perform the steps of:

updating a plurality of filtering branches for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector based on initialization values related to the at least one channel response vector and the at least one correlation vector; and

filtering at least a portion of the received signal clusters using at least a portion of the updated plurality of filtering branches.

Preferably, the machine-readable storage further comprises code to repeat the updating as long as a signal-to-noise ratio (SNR) for the received signal cluster is reached.

Preferably, the machine-readable memory further comprises code for updating the initialization value over a plurality of iterations.

Preferably, the machine-readable memory further comprises code to repeat the updating whenever a certain number of iterations is reached.

Preferably, the machine-readable storage further comprises code for generating a plurality of chip rate synchronously sampled signals using the plurality of received signal clusters.

Preferably, the machine-readable memory further comprises code for generating the plurality of chip rate synchronously sampled signals using a chip clock signal.

Preferably, the machine-readable memory further comprises code for generating the at least one correlation vector using the plurality of chip rate synchronously sampled signals.

Preferably, the at least one correlation vector comprises a complex conjugate of a plurality of chip-synchronously sampled signals, wherein the plurality of chip-synchronously sampled signals are based on the plurality of received signal clusters.

Preferably, the machine-readable memory further comprises code for updating the at least one channel response vector and the at least one correlation vector based on a minimum mean square error algorithm (MMSE).

Preferably, the machine-readable storage further comprises code for generating at least one estimate of the plurality of clusters of received signals based on the filtering.

Various advantages, aspects and novel features of the invention, as well as details of an illustrated embodiment thereof, will be more fully described with reference to the following description and drawings.

Drawings

The invention will be further described with reference to the accompanying drawings and examples, in which:

FIG. 1 is a representative block diagram of a Spatial Multiplexing (SM) multiple-input multiple-output (MIMO) antenna system using a conjugate gradient branch optimizer (taps optimizer) in accordance with an embodiment of the present invention;

FIG. 2 is a block diagram of a Radio Frequency (RF) processing module used in accordance with an aspect of the present invention;

fig. 3 is a block diagram of a receiver front end of a two transmit-two receive MIMO antenna system using conjugate gradient optimization according to an embodiment of the present invention;

fig. 4 is a block diagram of a receiver front end of a multiple transmit-multiple receive MIMO antenna system using conjugate gradient optimization in accordance with an embodiment of the present invention;

fig. 5 is an exemplary flowchart of method steps for processing a signal in a receiver, in accordance with an embodiment of the present invention.

Detailed Description

The invention relates to a method and a system for low complexity conjugate gradient based equalization in a wireless system, comprising updating a plurality of filtering branches of an equalization filter for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector. The updating of the equalization filter branches may be based on initialization values related to the channel response vector and correlation vector. At least a portion of the received signal clusters may be filtered using at least a portion of the updated plurality of filtering branches. A signal cluster may be defined as a plurality of signals sampled and synchronized with the receiver chip rate clock (or a fraction of a chip rate period). Each sample constitutes an estimate of the received signal transmitted on a different path (channel). The updating is repeated as long as a certain signal-to-noise ratio for the received signal cluster is reached. The initialization value may be updated during a plurality of iterations, and the updating may be repeated as long as the plurality of iterations reaches a specified number. Using the plurality of received signal clusters and/or chip clock signals, a plurality of chip rate synchronously sampled signals may be generated. The correlation vector is generated using a plurality of chip rate synchronously sampled signals, and the correlation vector comprises a complex conjugate of the plurality of chip rate synchronously sampled signals. Based on the plurality of received signal clusters, the plurality of chip rate synchronously sampled signals may be generated. The channel response vector and the correlation vector are updated based on a Minimum Mean Square Error (MMSE) algorithm. Estimates for the plurality of received signal clusters may be generated based on the filtering.

Fig. 1 is a representative block diagram of a Spatial Multiplexing (SM) multiple-input multiple-output (MIMO) antenna system using a conjugate gradient branch optimizer (taps optimizer) in accordance with an embodiment of the present invention. Referring to fig. 1, a transceiver system 120 is shown that includes a Baseband Transmitter Station (BTS) BTS1, a plurality of receive antennas 128_1…NrA plurality of Radio Frequency (RF) receiving modules 132_1…NrMultiple Chip Matched Filter (CMF)134_1…NrMultiple Cluster Path Processors (CPP)136_1…NrAnd a baseband processor 138.

At the transmitting end, the baseband transmitting station BTS1 may comprise a pre-coding phasing and/or amplitude calibration module 121 for N of BTS1_tAn RF transmitter module 124_1…NtAnd N_tAn antenna 126_1…Nt. The BTS1 may transmit one or more spatially multiplexed signals over a channel having an actual time-varying impulse response. The overall time-varying impulse response 127 of all receive and transmit channels used in the transceiver system 120 may correspond to the channel matrix HH. In one aspect of the disclosure, BTS1 may use spatial multiplexing techniques to utilize transmit antenna 126 corresponding to BTS1_1…NtOne or more signals are transmitted. However, the present invention is not limited in this regard. For example, the transmitting end may include additional baseband transmitting stations, and may use one or more antennas from other BTSs during the same transmission of the spatially multiplexed signal. Alternatively, BTS1 may utilize a pre-coding phasing and/or amplitude calibration module 121 and transmit antennas 126 using transmission diversity techniques_1…NtOne or more signals are transmitted.

RF transmit module 124_1…NtMay comprise suitable logic, circuitry and/orCode for processing the RF signal. RF transmit module 124_1…NtFiltering, amplification and/or analog-to-digital conversion operations, for example, may be performed. Multiple transmit antennas 126_1…NtCan transmit from multiple RF transmit modules 124_1…NtTo a plurality of receive antennas 128_1…Nr。

Multiple RF receiving modules 132_1…NrMay comprise suitable logic, circuitry and/or code that may be adapted to amplify and downconvert a received analog RF signal R_1...NrTo baseband frequency. Multiple RF receiving modules 132_1…NrMay include an analog-to-digital (a/D) converter for digitizing the received analog baseband signal, as well as a voltage controlled oscillator, a mixer, and/or a low pass filter.

Multiple Chip Matched Filter (CMF)134_1…NrMay comprise suitable logic, circuitry and/or code that may enable filtering of multiple RF receive modules 132_1…NrTo generate an in-phase component (I) and a quadrature component (Q). In this regard, in one embodiment of the invention, a plurality of Chip Matched Filters (CMFs) 134_1…NrA pair of digital filters may be included, for example, which may be used to filter the I and Q components to within the bandwidth of WCDMA, e.g., 3.84 MHz.

Multiple Cluster Path Processor (CPP)136_1…NrA plurality of Nr x Nt channel estimates of the actual time-varying impulse response may be generated. CPP_iN, (i 1.. Nt) is generated at the antenna R_1...NrReceived channel estimation valuesThe baseband processor 138 may be configured to receive signals from a plurality of Chip Matched Filters (CMFs) 134_1...NrA plurality of in-phase (I) outputs Xi (I1.. Nr) of (a)_i) And integral (Q)_i) And (4) components. Block 138 also receives the estimateThe baseband processor 138 may then generate an initial input signal X based on each baseband transmitter₁To X_pIs estimated value ofTo

In operation, transceiver system 120 may receive wireless signals that may be distorted due to fading effects and other distortion phenomena. In this regard, the baseband processor 138 may use signal equalization or filtering to reverse the effects of the communication channel or media interface. In an exemplary embodiment of the invention, the baseband processor 138 may include one or more conjugate gradient branch optimization modules (CGTO)150 and one or more equalizers 152. CGTO150 may comprise suitable logic, circuitry, and/or code and may use a conjugate gradient based algorithm to calculate one or more equalizer filter leg settings. Equalizer 152 may use the calculated equalizer taps to equalize or filter the received signal estimates. The equalizer 152 may also update the error function at a particular rate, while the conjugate gradient based algorithm in the CGTO150 may also iterate over and over again, e.g., perform multiple loops for each update of the error function, so that the CGTO150 may update and optimize the equalizer taps for the received wireless signal. In another embodiment of the present invention, CGTO150 may use an algorithm based on a Minimum Mean Square Error (MMSE) algorithm. In this regard, CGTO150 may use a fewer number of calculation cycles, which may lead to increased processing time and reduced execution cost by, for example, excluding matrix vector multiplication.

Fig. 2 is a block diagram of a Radio Frequency (RF) processing module used in accordance with an aspect of the present invention. Referring to fig. 2, the RF processing module 200 may comprise suitable logic, circuitry, and/or code and may be operable to amplify and downconvert a received analog signal to baseband and then digitize it. In an exemplary aspect of the invention, the RF processing module 200 may include an LNA 204, a Voltage Controlled Oscillator (VCO)208, a mixer 206, a Low Pass Filter (LPF)212, and an analog-to-digital converter (a/D) 213. LNA 204 may be used to receive RF signal 202 and amplify it based on the determined gain level. The VCO 208 may comprise suitable logic, circuitry, and/or code and may be operable to output a signal having a particular frequency that may be predetermined or controlled by a voltage signal input to the VCO. The mixer 206 may mix the VCO signal 210 with the amplified signal received from the LNA 204. The LPF 212 may comprise suitable logic, circuitry, and/or code and may receive the mixed signal from the mixer 206. The LPF 212 may limit the frequency of the mixed signal to a specific frequency range up to a certain upper frequency limit, and the LPF 212 may output this frequency range as a baseband signal to the a/D213. The a/D213 may comprise suitable logic, circuitry, and/or code and may be operable to receive the limited analog baseband signal from the LPF 212 and output a digital signal 214 that may sample the analog signal at a predetermined frequency.

Fig. 3 is an exemplary block diagram of fig. 1, which illustrates a block diagram of a receiver front-end of a two transmit-two receive (Nt-2; Nr-2) MIMO antenna system using a conjugate gradient optimizer, according to an embodiment of the present invention. Referring to FIG. 3, a receiver front end is shown including cluster path processors CPP 1302 and CPP 2304, a correlator module 306, CGTO modules 308 and 310, and equalizer modules 312 and 314.

CPPs 302 and 304 may comprise suitable logic, circuitry, and/or code and may be operable to generate channel estimatesA designated CPP, named Master CPP (302), provides a chip rate (or multi-chip rate) clock signal to all receivers. This allows the time tracking circuitry to be removed from all other CPPs and enables the generation of timely synchronized outputs (channel estimates) from all CPPs. In addition, the signal received by the master CPP from each CPP (304) indicates the strength of the aggregate channel (e.g., as measured by the average power of all channels) and the aggregate time position of the channel processing relative to the master CPP clock signal. The master CPP (302) is provided with circuitry/software that facilitates a clock signal that can track the aggregate received time and power signal from all of the CPPs in a manner and with the requisite accuracy. In this respectA connection 303 between the host CPP302 and the CPP 304 facilitates the flow of time, power signals, and may include other information to the host CPP. Module 302 also outputs a timing signal to the entire receiver via connection 303. Channel response estimates from CPPs 302 and 304320. 328, 322, 330 and signals X '1324 and X' 2326 may be completely synchronized in a sense by a single clock sample.

The correlator module 306 may comprise suitable logic, circuitry, and/or code and may generate correlation vectors 332 and 334 for the two receive antennas based on chip rate synchronously sampled signals X '1324 and X' 2326 received from a time-master (time-master) CPP 302. Relevance vector 332 may include relevance R11 and R12, while relevance vector 334 may include relevance R21 and R22.

The CGTO modules 308 and 310 may comprise suitable logic, circuitry, and/or code that may enable generation and updating of equalizer tap values 336 based on, for example, a conjugate gradient algorithm. The generated equalizer branch values 336., 342 may be passed to the equalizer modules 312 and 314 for further processing.

The equalizer modules 312 and 314 may comprise suitable logic, circuitry, and/or code that may enable the generation of the estimated values 344 and 346 of the received signals based on the generated chip rate synchronous sampled signals X '1324 and X' 2326 and the updated equalizer branches 336.

In operation, CPPs 302 and 304 may receive input signal X1316 from a first antenna and input signal X2318 from a second antenna. Received signals 316 and 318 may be transmitted from two transmit antennas. CPP302 may generate a channel response based on wireless signals X1316 and X2318 received through two receive antennas320 and322. the received signal may be denoted as X_r(r is 1: 2). CPP 304 may also generate signal responses based on input wireless signals X1316 and X2318328 and330. each channel responseMay include N_CHVector of branches, here N_CHIncluding the delay spread of the channel. Generated channel response320 and322 may be transmitted to CGTO 308 and the generated channel response328 and330 may also be transmitted to CGTO 310.

The inbound signal may be sent through two transmit antennas and may be received first by two receive antennas and then processed by two CPPs (cluster path processors) 302 and 304. Each CPP_i(i-1, 2)302, 304 may generate multiple channel responses of the desired signal320. 322, 328, 330, where each channel response may include NCH branchesVector and NCH is the delay spread of the channel.

As described above, the CPP302 may be defined as a time-master CPP and may be used to receive timing signals from all other CPPs and to generate a chip clock signal. The chip clock or other time signal (including multi-chip clock time) may be used to sample the input signals Xr (r 1: 2)316, 318, generate the outputs X1 '316 and X2' 318, and channel response320. 322, 328, 330, and other generated signals. The received signals Xr (r 1: 2)316, 318, clocked by the chip rate, may be further processed within the correlation generator 306 module to generate sets of correlation vectors { Rr1, r2}332, 334. Each vector Rr1, r2(r1 ═ 1: NR; r2 ═ 1: NR) may include a correlation branch given by the following equation:

Rr1，r2(n)＝E{Xr1·X*r1-n}，

here, n is 0: Nch-1 and "-" represents a complex conjugate.

A set of correlation vectors { Rr1, r2 (n); 332, 334 and channel response vector320. 322, 328, 330 may be input together to CG-i (i 1: 2)308, 310 which may generate an equalizer branch (w CG). The branch may be updated according to changes in channel estimates, SNR, and other conditions described in the summary of the invention.

The CG branch optimizer modules 308, 310 may use the CG algorithm described below (see description below in connection with fig. 5), and may use the MMSE criterion. One or more revisions associated with this algorithm may also be used, such as an initialization/re-initialization module, a control module for the number of iterations, and/or a module that estimates the convergence status.

In an exemplary embodiment of the invention, the CGTO modules 308 and 310 may generate and update the equalizer branches 336.., 342 using a Conjugate Gradient (CG) based algorithm. The CG algorithm may be represented by the following pseudo-code:

step 1

if initialization_flag

alf ＝alf_0

bet ＝bet_0

w_cg ＝zeros(2*M，1)；

end

Step 2

if updating_clk

r ＝h；

p ＝r；

R ＝R_in；

end

Step 3

If Iteration_clk&iteration_flg

Rp ＝R*p；

r_curr ＝r’*r；

pRp ＝p’*Rp；

w_cg ＝w_cg+alf*p；

r ＝h-R*w_cg；

p ＝r+bet*p；

nm_iter ＝nm_iter+1；

end

Step 4

snr_cg ＝Get_CG_SNR(w_cg，H)；

Step 5

if(snr_cg＜snr_0)&(iter_flag＝＝0)

w_cg ＝h；

iter_flag ＝1；

nm_iter ＝0；

elseit snr_cg＜snr 1

if nm_iter＜N_interations

update alf；

update bet；

else

interation_flag＝0；

end

end

In a typical equalizer tap calculation according to the algorithm described above, the algorithm parameters alf and beta may be initialized to a1f _0 and beta _0 at step 1. The initial ideal solution w _ cg may also be initialized to a 0-vector. The algorithm parameters alf and beta can be expressed by the following equations:

alf_k＝r^T _K-1·r_k-1/p^T _k-1Rp_k-1(ii) a And is

bet_k＝p^T _k-1A r_k-1/p^T _k-1Rp_k-1，

Wherein r is_kIs given by k^thN-dimensional vector p obtained by sub-iterative computation_kIs given by k^thAnd (4) obtaining vectors of the same dimension by the iteration calculation, wherein R is an array of dimensions of NxN. Thus, N is used for each iteration of the computation²+3 xn multiplication operations and 2 division operations. At this point, by presetting the alf _0 and beta _0 values as alf and beta parameters, the computational complexity of the CG algorithm can be significantly reduced. In the CG algorithm, the values of alf _0 and beta _0 can be pre-calculated and used. In addition, these values may be dynamically changed based on preset states during execution of the CG algorithm. For example, the preset state may be characterized as a signal-to-noise ratio (SNR). For example, the algorithm parameters alf and beta may be associated with a range of SNR values measured during signal reception, and may be reset when SNR values within the range are reached. In other cases, the algorithm parameters alf and beta may be set to expected values that can be determined in an offline test.

In step 2 in the CG algorithm, the external conditions may be updated. At this point, channel response vectors H11, H12, H21, and H22 (represented by H) and correlation vectors r11, r12, r21, and r22 (represented by Rin) may be input together. In step 3, if the number of iterations is less than the value N _ iteration, one iteration of the CG algorithm is performed. In step 4, the estimation of the equalizer branch is performed by calculating the SNR value. In step 5, an estimated SNR decision is obtained in relation to the subsequent loop. When the algorithm is inactive and therefore not used, the value snr _0 represents the signal/noise level. The value snr _1 defines a higher level of signal-to-noise ratio where the improvement in performance becomes small and thus the algorithm is not applied. In this regard, the CG algorithm works for a range of SNR values.

For example, if snr < snr _0, the CG algorithm may output h, and the equalizer modules 312 and 314 may operate as maximum ratio combiners. The CG algorithm may then initialize to the next iteration group. If snr < snr1, and if the number of iterations performed is less than N _ iteration, another cycle of the CG algorithm is performed. Otherwise, the CG algorithm may be interrupted until the next update period. The number of cycles N to which the CG algorithm is applied is reduced within a specified SNR range. However, the CG algorithm is not limited to any preset range of SNR values. Thus, algorithm parameters N, alf and beta may be determined for multiple SNR ranges. It is known to those skilled in the art that with the chosen dimension of N-w cg (number of branches), the equalizer filter can be located in the range of two to four times the delay spread (measured in number of chips-Nch defining the channel response). However, the calculated correlation vectors R11, R12, R21, and R22 (also called R11, R22, R21, and R22, and being outputs 334 and 332) may be limited to the delay spread Nch. The relevance vector is assigned to a larger vector and the undefined value will be replaced by a value of 0. The implementation of the invention therefore involves limiting the computation of the inner product between two vectors to a unique non-0 value and thus reduces the computation and complex load.

Fig. 4 is a block diagram of a receiver front end of a multiple transmit-multiple receive MIMO antenna system using conjugate gradient optimization according to an embodiment of the present invention. Which is a building structure of typically Nt transmitters or antennas and Nr receivers. Referring to fig. 4, a receiver front-end is shown comprising a cluster path processor CPP_1...Nr420, a., 404, the correlator module 406, the CGTO module 408, a., 410, and the equalizer module 412, a., 414. The input wireless signals 416, 418 may be transmitted by Nt transmit antennas and received by Nr receive antennas.

In operation, CPP 402. -, 404 may receive input signals 416. -, 418 Xr (r 1: Nr) via Nr receive antennas. The CPP402, a.., 404 may generate a channel response H based on the received wireless signal 416_r，i(r ═ 1: Nr; i ═ 1: Nt). Each channel response H_r，iMay include N_CHVector of branches, here N_CHIncluding the delay spread of the channel. Generated channel response 420_r，i(r 1: Nr; i 1: Nt) may be transmitted to the CGTO module 408.

The CPP402 may receive a plurality of timing signals 403 from each remaining CPP and generate a chip rate synchronous sampling signal X based on an input signal 416_1...Nr424. Can synchronously sample the chip rate by the signal X_1...Nr424 to correlator module 406. Correlator module 406 may be based on the slave time-master CPP402Received generated chip rate synchronous sampling signal X_1...Nr424 generate correlation values R for Nr receive antennas_r1，r2Set of vectors 426. Correlation value { R_r1，r2The set of vectors of 426 may comprise a single vector. Each individual vector Rr_1，r2(r1 ═ 1: Nr, r2 ═ 1: Nr) includes a correlation branch that can be expressed by the following equation:

R_r1.r2(n)＝E{X_r1·X^* _r2-n}

wherein N is 0: N_ch-1 and ". sup." represent a complex conjugate. Set of dependencies { R }_r1，r2(n) 426 and a set of channel response vectors H_r，i(r 1: Nr; i 1: Nt) may be transmitted to the CGTO module 408. The CGTO module 408.., 410 may generate an equalizer branch 428.., 430 for the equalizer module 412.., 414, and may continuously update it. The equalizer module 412, 414 may synchronize the sampled signal X based on the generated chip rate_1...Nr424 generate an estimate 432, 434 of the received signal and an updated equalizer branch.

Fig. 5 is an exemplary flowchart of method steps for processing a signal in a receiver according to an embodiment of the present invention. Referring to fig. 5, an exemplary flow chart for the CG algorithm shown in fig. 3 is shown. The exemplary steps begin at step 502. At step 504, the algorithm parameters alf and beta may be initialized to predetermined values. The Weighted Conjugate Gradient (WCG) value is reset to 0. At step 506, the algorithm parameter R may be updated with the channel impulse response, the algorithm parameter R_inMay be updated with the correlation vector values. At step 508, a single iteration may be performed by the CG algorithm and the WCG may be calculated.

At step 510, a signal-to-noise ratio (SNR) may be calculated. At step 514, it may be determined whether the calculated signal-to-noise ratio is less than snr _ 0. If SNR < SNR _0, then, at step 512, WCG can be determined to be h and output. The algorithm may then restart at step 502. If the SNR is not less than SNR _0, a determination is made at step 516 whether the SNR < SNR _ 1. If the SNR is not less than SNR _1, the algorithm will restart and restart at step 502. If SNR < SNR _1, at step 502, it is determined whether the number of iterations that have been performed is less than the value of N _ iterations. If the number of iterations that have been performed is less than the value of N _ iterations, the algorithm parameters alf and beta will be updated at step 518. The algorithm may then be reset and continue at step 502. If the number of iterations that have been performed is not less than the value of N _ iterations, the current algorithm cycle will end at step 522, and no WCG value is output. The CG algorithm will then restart and continue at step 502.

Accordingly, the present invention may be realized in hardware, software, or a combination of hardware and software. The present invention can be realized in a centralized fashion in at least one computer system, or in a distributed fashion where different elements are spread across several interconnected computer systems. Any kind of computer system or other apparatus adapted for carrying out the methods described herein is suited. A typical combination of hardware and software could be a general purpose computer system with a computer program that, when being loaded and executed, controls the computer system such that it carries out the methods described herein.

The present invention may also be implemented by a computer program product, comprising all the features enabling the implementation of the methods of the invention, when loaded in a computer system. The computer program in this document refers to: any expression, in any programming language, code or notation, of a set of instructions intended to cause a system having an information processing capability to perform a particular function either directly or after either or both of the following: a) conversion to other languages, codes or symbols; b) reproduced in a different format.

While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from its scope. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (9)

1. A method for processing a signal in a receiver, the method comprising:

updating a plurality of filtering branches of an equalization filter for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector based on initialization values related to the at least one channel response vector and the at least one correlation vector; wherein the channel response vector comprises a plurality of channel response estimates; the correlation vector comprises complex conjugates of a plurality of chip-synchronously sampled signals, wherein the plurality of chip-synchronously sampled signals are based on the plurality of received signal clusters;

filtering at least a portion of the received signal clusters using at least a portion of the updated plurality of filtering branches;

generating at least one estimate of the plurality of received signal clusters based on the filtering;

updating the at least one channel response vector and the at least one correlation vector based on a minimum mean square error algorithm.

2. The method of claim 1, further comprising: the updating is repeated as long as a certain signal-to-noise ratio for the received signal constellation is reached.

3. The method of claim 1, further comprising: updating the initialization value during a plurality of iterations of the least mean square error algorithm.

4. The method of claim 3, further comprising: the update is repeated as long as a certain number of iterations is reached.

5. The method of claim 1, further comprising: generating a plurality of chip rate synchronously sampled signals using the received plurality of signal clusters.

6. A system for processing a signal in a receiver, the system comprising:

at least one processor configured to update a plurality of filtering branches of an equalization filter for a plurality of received signal clusters using at least one channel response vector and at least one correlation vector based on initialization values related to the at least one channel response vector and the at least one correlation vector; the channel response vector comprises a plurality of channel response estimates; the correlation vector comprises complex conjugates of a plurality of chip-synchronously sampled signals, wherein the plurality of chip-synchronously sampled signals are based on the plurality of received signal clusters; and

the at least one processor filtering at least a portion of the received signal clusters using at least a portion of the updated plurality of filtering branches;

generating at least one estimate of the plurality of received signal clusters based on the filtering;

updating the at least one channel response vector and the at least one correlation vector based on a minimum mean square error algorithm.

7. The system of claim 6, wherein the at least one processor repeats the updating as long as a signal-to-noise ratio for the received signal constellation is achieved.

8. The system according to claim 6, wherein said at least one processor updates said initialization value in a plurality of iterations of a least mean square error algorithm.

9. The system of claim 8, wherein the at least one processor repeats the updating as long as a specified number of iterations is reached.