HK1119899A - Quick paging channel with reduced probability of missed page - Google Patents

Description

Quick paging channel with reduced likelihood of missed pages

Priority requirements under 35u.s.c. § 119

The benefit OF U.S. provisional application No.60/691,901 entitled "rapid paging channel with REDUCED likelihood OF missing pages" filed on 16.6.2005 AND provisional application S/n.60/731,037 entitled "METHODS AND APPARATUS FOR PROVIDING higher MAC FOR MOBILE broadband wireless" filed on 27.10.2005, both OF which are assigned to the assignee OF the present invention AND are hereby expressly incorporated herein by reference.

Background

In a random access wireless communication system, the communication link between an access terminal and an access point is discontinuous. An access terminal may register with an access point and may remain in an idle state. The access terminal may transition from the idle state to the active state to initiate an active communication link. In the active state, the access terminal can receive information from the access point and can transmit information to the access point.

Most of the time, the access terminal remains in the idle state waiting for transition to the active state. The access terminal is typically a mobile device that operates on batteries stored within the device. An access terminal may conserve energy and extend battery run time by transitioning to a low power state, often referred to as a sleep state. However, in many cases, the access terminal cannot immediately transition from the dormant state to the active state.

An access terminal typically does not have the ability to monitor information transmitted by an access point while in a dormant state. Therefore, the access terminal typically transitions to an idle state periodically to monitor for messages from the access point.

Some wireless communication systems incorporate quick paging channels that are used by an access point to indicate the presence of a paging message for an access terminal. The paging message can direct the particular access terminal to transition to an active state to support an active information exchange.

The wireless communication system can assign a particular bit in a particular message as a quick paging bit for a particular access terminal or group of access terminals. Each access terminal may thus wake up from the sleep state for a period of time sufficient to receive the quick paging bit. If the access terminal detects a valid quick paging bit, the access terminal is informed of a subsequent paging message and may remain in or transition to an idle state to monitor for the paging message. Conversely, if the access terminal fails to detect its assigned quick paging bit, it assumes that there is no upcoming paging message for it. In this way, access terminals may minimize the time they need to be in idle mode, thereby maximizing the time they can contribute to a lower power sleep state.

For example, CDMA2000 and WCDMA wireless communication systems have a quick paging channel that allows a mobile station to periodically monitor the assigned quick paging bits to detect the presence of a page. When a page is sent to the mobile station, the base station sets the corresponding bit to 1. If the bit is set, the mobile station representing the access terminal listens for a full page. However, if the access terminal incorrectly detects that the bit is a 0, or determines an erasure indicating that the state of the received bit cannot be discerned, then a missed page occurs. Therefore, there is a need to reduce the likelihood of missed pages. However, there is still a need to maintain or extend the battery powered operating time of the mobile device.

Summary of the invention

A quick paging channel in a random access wireless communication system includes at least one bit in a quick paging frame identifying the presence of a paging message for one or a group of access terminals. Quick paging bits identifying the presence of a paging message for a first access terminal are encoded with one or more quick paging bits corresponding to one or more other access terminals to generate one or more forward error correction bits. These jointly encoded quick paging bits are broadcast to each access terminal by time-division multiplexing the quick paging frame with other information frames.

Aspects of the present disclosure include a method of notifying an access terminal. The method includes determining that there is a scheduled message for the access terminal, setting one of a plurality of quick paging bits in a quick paging block corresponding to the access terminal, encoding the quick paging block to generate an encoded quick paging packet, generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block, and transmitting the at least one OFDM symbol.

Aspects of the present disclosure include a method of notifying an access terminal. The method includes setting a quick paging bit corresponding to an access terminal in a quick paging block having a plurality of bits corresponding to a plurality of access terminals, compressing the quick paging block to generate a compressed quick paging block, and encoding the compressed quick paging block to generate an encoded quick paging block.

Aspects of the present disclosure include a method of processing a quick page message. The method includes receiving a quick paging packet, decoding the quick paging packet to generate a quick paging block, decompressing the quick paging block, and determining a state of a quick paging bit associated with an access terminal based on an output of the decompression process.

Aspects of the present disclosure include a system for generating a quick page message, comprising: a scheduler configured to determine paging messages scheduled for an access terminal; a quick paging block generator coupled to the scheduler and configured to assert a quick paging bit corresponding to the access terminal and configured to generate a quick paging block having at least the quick paging bit and a different quick paging bit corresponding to a different access terminal; an encoder coupled to the quick paging block generator and configured to generate an encoded quick paging packet based on the quick paging block; and a transmit processor coupled to the encoder and configured to generate at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging packet.

Aspects of the present disclosure include a system for generating a quick page message, comprising: means for determining that there is a scheduled message for an access terminal; means for setting a quick paging bit corresponding to the access terminal among a plurality of quick paging bits in a quick paging block; means for encoding the quick paging block to generate an encoded quick paging packet; means for generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block; and means for transmitting the at least one OFDM symbol.

Aspects of the present disclosure include a system for generating a quick page message, comprising: means for setting a quick paging bit corresponding to the access terminal; means for jointly encoding the quick paging bit with at least one other quick paging bit corresponding to a different access terminal to generate an encoded quick paging block; and means for time division multiplexing the encoded quick paging block with different information on a channel.

Aspects of the present disclosure include a system for generating a quick page message, comprising: means for receiving a quick paging packet; means for decoding the quick paging packet to generate a quick paging block; means for decompressing the quick paging block; and means for determining a state of a quick paging bit associated with an access terminal based on an output of the decompression process.

Brief description of the drawings

The features, objects, and advantages of embodiments of the disclosure will become more apparent from the detailed description set forth below when taken in conjunction with the drawings in which like elements bear the same reference numerals.

Fig. 1 is a simplified functional block diagram of one embodiment of a multiple access wireless communication system.

Fig. 2 is a simplified functional block diagram of one embodiment of a transmitter and a receiver in a multiple access wireless communication system.

Fig. 3 is a simplified functional block diagram of one embodiment of a transmitter implementing a quick paging block.

Fig. 4 is a simplified functional block diagram of one embodiment of a receiver configured to process a quick paging block.

Fig. 5 is a simplified flow diagram of one embodiment of a method of generating a quick paging block.

Fig. 6 is a simplified flow diagram of one embodiment of a method of generating a quick paging block.

Fig. 7 is a simplified functional block diagram of one embodiment of a transmitter implementing the quick paging block.

Fig. 8 is a simplified functional block diagram of one embodiment of a receiver configured to process the quick paging block.

Detailed description of the invention

A wireless communication system may reduce the likelihood of missed pages by providing some form of redundancy associated with quick paging bits. The wireless communication system does not simply extend the number of quick paging bits assigned to each access terminal, but can provide redundancy by jointly encoding multiple quick paging bits. In this manner, each or each group of access terminals is assigned a single quick paging bit, but redundancy is provided by jointly encoding multiple quick paging bits. The wireless communication system may reduce the likelihood of missing paging messages by increasing the number of redundant bits, which may be forward error correction bits. There is no theoretical limit to the number of redundant bits that can be added from the joint encoding process. However, from a practical point of view, the number of redundant bits is likely to be less than the number of bits required to transmit the actual paging message.

The wireless communication system may periodically transmit a quick paging block with the jointly encoded quick paging message. Given that the wireless communication system schedules quick paging blocks at a sufficiently high rate, the number of quick paging bits set in each quick paging block is likely to be relatively small. The relatively sparse fill rate of the quick paging bits set in any particular quick paging frame enables the wireless communication system to compress the quick paging block to further reduce the number of bits transmitted to each access terminal. The wireless communication system may implement any of a variety of compression techniques, at least one of which is discussed in further detail below.

A dedicated quick paging channel may be used to transmit a quick paging channel with jointly encoded quick paging bits to individual access terminals. Alternatively, the quick paging channel may be multiplexed with other channels. For example, the quick paging channel may be time division multiplexed, frequency division multiplexed, code division multiplexed, or otherwise multiplexed with other information.

In an Orthogonal Frequency Division Multiplexing (OFDM) wireless communication system, a quick paging block or a compressed quick paging block may be configured to broadcast with a predetermined number of OFDM symbols. The wireless communication system may periodically transmit OFDM symbols with quick paging information. Thus, the system functions to time division multiplex the quick paging information on the channel used to carry other information.

Fig. 1 is a simplified functional block diagram of one embodiment of a multiple access wireless communication system 100. The multiple access wireless communication system 100 includes a plurality of cells, such as cells 102, 104, and 106. In the embodiment of fig. 1, each cell 102, 104, and 106 may include an access point 150 having multiple sectors.

The multiple sectors are formed by groups of antennas each responsible for communication with access terminals in a portion of the cell. In cell 102, antenna groups 112, 114, and 116 each correspond to a different sector. For example, cell 102 is divided into three sectors 120a-102 c. A first antenna 112 serves a first sector 102a, a second antenna 114 serves a second sector 102b, and a third antenna 116 serves a third sector 102 c. In cell 104, antenna groups 118, 120, and 122 each correspond to a different sector. In cell 106, antenna groups 124, 126, and 128 each correspond to a different sector.

Each cell is configured to support or serve a number of access terminals in communication with one or more sectors of a corresponding access point. For example, access terminals 130 and 132 are in communication with access point 142, access terminals 134 and 136 are in communication with access point 144, and access terminals 138 and 140 are in communication with access point 146. Although the access points 142, 144, and 146 are each illustrated as communicating with two access terminals, each access point 142, 144, and 146 is not limited to communicating with two access terminals, but may support any number of access terminals up to a limit, which may be a physical limit, or a limit imposed by a communication standard.

As used herein, an access point may be a fixed station used for communicating with the terminals and may also be referred to as, and include some or all the functionality of, a base station, a node B, or some other terminology. An Access Terminal (AT) may also be referred to as, and include some or all of the functionality of, a User Equipment (UE), a user terminal, a wireless communication device, a terminal, a mobile station, or some other terminology.

As can be seen in fig. 1, each access terminal 130, 132, 134, 136, 138, and 140 is located in a different portion of its respective cell than each other access terminal in the same cell. Moreover, each access terminal may be a different distance from the corresponding antenna group with which it is communicating. These two factors, coupled with environmental and other conditions in the cell, provide a situation where different channel conditions arise between each access terminal and the respective antenna group with which it is communicating.

Each access terminal, e.g., 130, typically experiences unique channel characteristics due to varying channel conditions that are not experienced by any other access terminal. Furthermore, these channel characteristics change over time and vary due to location changes.

An access point, e.g., 142, may broadcast a frame or block with quick paging information. Access terminals 130 and 132 within the coverage area of access point 142 may each receive the quick paging information and process it to determine whether its assigned quick paging bit is valid, i.e., indicates the presence of a paging message for that access terminal.

The different channel conditions experienced by access terminals 130 and 132 change their respective ability to accurately recover quick paging information. However, since the quick paging information is encoded to provide redundant information, such as one or more forward error correction bits, the access terminals 130 and 132 are more likely to successfully determine the assigned quick paging bits, thereby minimizing the likelihood of losing pages to the access terminals.

The wireless communication system 100 may multiplex the quick paging information on the same channel for other information. For example, in an OFDM system, the wireless communication system 100 may broadcast quick paging information using some or all of the subcarrier frequencies across channels. The subcarrier frequency used to carry the quick paging information may be the same subcarrier as used to carry other information to each access terminal. In this manner, the wireless communication system 100 may time-division multiplex the quick paging channel with other channels of the system.

The above embodiments may be implemented using Transmit (TX) processor 220 or 260, processor 230 or 270, and memory 232 or 272 as shown in fig. 2. The processes may be performed on any processor, controller, or other processing device, and may be stored as source code, object code, or other form of computer-readable instructions in a computer-readable medium.

Fig. 2 is a simplified functional block diagram of one embodiment of a transmitter and a receiver in a multiple access wireless communication system 200. At the transmitter system 210, traffic data for a number of data streams is provided from a data source 212 to a Transmit (TX) data processor 214. In one embodiment, each data stream is transmitted over a respective transmit antenna. TX data processor 214 formats, codes, and interleaves the traffic data for each data stream based on a particular coding scheme selected for that data stream to provide coded data. In some embodiments, TX data processor 214 applies beamforming weights to the symbols of the data streams based on to which user the symbol is being transmitted and from which antenna the symbol is being transmitted. In some embodiments, the beamforming weights may be generated based on channel response information indicative of the conditions of the transmission path between the access point and the access terminal. The channel response information may be generated using CQI information or channel estimates provided by the user. Further, in the case of scheduled transmissions, TX data processor 214 may select a packet format based on rank information transmitted from the user.

The coded data for each data stream may be multiplexed with pilot data using OFDM techniques. The pilot data is typically a known data pattern that is processed in a known manner and may be used at the receiver system to estimate the channel response. The multiplexed pilot and coded data for each data stream is then modulated (i.e., symbol mapped) based on a particular modulation scheme (e.g., BPSK, QPSK, M-PSK, or M-QAM) selected for that data stream. The data rate, coding, and modulation for each data stream may be determined by instructions provided by processor 230. In some embodiments, the number of parallel spatial streams may vary according to rank information transmitted from the user.

The modulation symbols for all data streams are then provided to a TX MIMO processor 220, which further processes the modulation symbols (e.g., for OFDM). TX MIMO processor 220 then passes N_TOne symbol stream is provided for N_TAnd Transmitters (TMTR)222a through 222 t. In some embodiments, TX MIMO processor 220 applies beamforming weights to the symbols of the data streams based on the user to which the symbol is being transmitted and the antenna from which the symbol is being transmitted based on the user channel response information.

Each transmitter 222a through 222t receives and processes a respective symbol stream to provide one or more analog signals, and further conditions (e.g., amplifies, filters, and upconverts) the analog signals to provide a modulated signal suitable for transmission over the MIMO channel. N from transmitters 222a through 222t_TThe modulated signals are then each from N_TThe individual antennas 224a through 224t transmit.

At receiver system 250, the transmitted modulated signal is divided by N_RReceived by antennas 252a through 252r, and the received signal from each antenna 252 is provided to a respective receiver (RCVR) 254. Each receiver 254 conditions (e.g., filters, amplifies, and downconverts) a respective received signal, digitizes the conditioned signal to provide samples, and further processes the samples to provide a corresponding "received" symbol stream.

RX data processor 260 then receives and processes data from N based on a particular receiver processing technique_RThe N of the receiver 254_REach received symbol stream to provide a rank number for the "detected" symbol stream. The processing by RX data processor 260 is described in further detail below. Each detected symbol stream includes symbols that are estimates of the modulation symbols transmitted for the corresponding data stream. RX data processor 260 then demodulates, deinterleaves, and decodes each detected dataThe symbol stream is decoded to recover the traffic data for the data stream. The processing by RX data processor 260 is complementary to that performed by TX MIMO processor 220 and TX data processor 214 at transmitter system 210.

The channel response estimate generated by RX processor 260 may be used to perform space, space/time processing at the receiver, adjust power levels, change modulation rates or schemes, or other actions. RX processor 260 may further estimate the signal-to-noise-and-interference ratios (SNRs) of the detected symbol streams, and possibly other channel characteristics, and provides these quantities to a processor 270. RX data processor 260 or processor 270 may further derive an estimate of the "effective" SNR for the system. Processor 270 then provides estimated channel information, such as a Channel Quality Indicator (CQI), which may comprise various types of information regarding the communication link and/or the received data stream. For example, the CQI may only include the operating SNR. This CQI is then processed by a TX data processor 278, which also receives traffic data for a number of data streams from a data source 276, which are modulated by a modulator 280, conditioned by transmitters 254a through 254r, and transmitted back to transmitter system 210.

At transmitter system 210, the modulated signals from receiver system 250 are received by antennas 224, conditioned by receivers 222, demodulated by a demodulator 240, and processed by a RX data processor 242 to recover the CQI reported by the receiver system. The reported CQI is then provided to processor 230 and used to (1) determine the data rate and coding and modulation schemes to be used for the data streams, and (2) generate various controls for TX data processor 214 and TX MIMO processor 220.

At the receiver, various processing techniques may be employed to process the N_RA received signal to detect N_TA stream of transmitted symbols. These receiver techniques can be divided into two broad categories: (i) spatial and space-time receiver processor techniques (which are also referred to as equalization techniques); and (ii) a "successive nulling/equalization and interference cancellation" receiver processing technique (which is also referred to as a "successive interference cancellation" or "successive cancellation" receiver processing technique).

From N_TA transmission sum N_RThe MIMO channel formed by the receiving antennas can be decomposed into N_SA separate channel of which N_S≤min{N_T，N_R}. This N_SEach of the independent channels may also be referred to as a spatial subchannel (or transmission channel) of the MIMO channel and corresponds to a dimension.

In the multiple-access wireless communication system 200 of fig. 2, the TX data processor 214 in combination with the processor 230 and memory 232 may function to determine the status of individual quick paging bits corresponding to individual receiver systems 250 in the coverage area. TX data processor 214 may be configured to encode quick paging bits to generate one or more redundancy bits, which may be forward error correction bits. These error correction bits may be, for example, parity bits, a Cyclic Redundancy Code (CRC), or some other type of bits. This encoding may be systematic or may be non-systematic.

Each receiver system 250 may function to receive the encoded quick paging information and recover the corresponding quick paging bits. RX processor 260, in combination with processor 270 and memory 272, may decode the quick page information and determine whether its assigned quick page bit is asserted. Receiver system 250 may detect or correct some errors in the quick paging information via a decoding process and thereby reduce the likelihood of missed pages due to incorrect decoding or erasure of the assigned quick paging bits.

Fig. 3 is a simplified functional block diagram of one embodiment of a transmitter 300 configured to implement an encoded quick paging channel. Transmitter 300 may be, for example, part of the transmitter system of fig. 2, or part of an access point as shown in fig. 1. The transmitter 300 may be implemented within the multiple-access wireless communication system of fig. 1 to minimize the likelihood that an access terminal will lose a scheduled paging message due to a lost or unrecovered portion of the quick paging block.

The simplified functional block diagram of fig. 3 illustrates only a portion of the transmitter system associated with the Quick Paging Channel (QPCH). This simplified functional block diagram does not show relevant modules such as those associated with generating or mapping paging messages associated with valid quick paging bits.

The embodiment of the transmitter 300 of fig. 3 includes a timing and synchronization module 302 coupled to a scheduler 304. Scheduler 304 is coupled to quick paging block generator 310 and initiates generation of a quick paging block. The quick paging block generator 310 is optionally coupled to a quick paging block compression module 312, which may be included to generate a compressed quick paging block. The quick paging block compression module 312 is coupled to an aggregator 330, which aggregator 330 may be a combiner. The load control block module 320 generates one or more load control bits. The output of the load control block module 320 is coupled to an aggregator 330. The aggregator 330 appends load control bits to the quick paging block or the compressed quick paging block depending on whether the quick paging block is compressed.

The aggregator 330 couples the combined quick page and load control bits to the encoder 340. Encoder 340 functions to encode these bits. The coded outputs are coupled to a TX MIMO processor 220. The TXMIMO processor 220 couples the signal to a transmitter stage 222, which transmits the signal using an antenna 224.

The embodiment of transmitter 330 of fig. 3 includes a timing and synchronization module 302 that tracks the timing of bits, frames, blocks, or packets generated by transmitter 300. In one embodiment, timing and synchronization module 302 maintains bit synchronization such that bits generated by transmitter 300 have substantially the same period. The timing and synchronization module 302 may also synchronize and track frame timing, where each frame includes a predetermined number of bits. In an OFDM system, it would be advantageous for each frame to include information for at least one OFDM symbol.

One superframe may include a predetermined number of frames. In addition, particular frames within a superframe may be dedicated to particular information. For example, each superframe may include a preamble of a predetermined length, such as 6 frames or 6 OFDM symbols.

The superframe preamble can be used to fill a broadcast channel transmitted to all access terminals within the coverage area of an access point. One portion of the superframe preamble may be allocated to a Quick Paging Channel (QPCH). For example, a QPCH packet may be one frame or one OFDM symbol within a superframe preamble. The length of the superframe preamble and the number of bits allocated to the QPCH packet may vary based on the information block size allocated to the quick paging block.

In one embodiment, the number of bits allocated to a QPCH packet is static. In another embodiment, the number of bits allocated to a QPCH packet is dynamic and is determined based at least in part on the number of valid quick paging bits. Where the number of bits allocated to a QPCH packet is dynamic, the transmitter 300 may allocate a number of bits for one of a predetermined set of QPCH packet lengths. Alternatively, the transmitter 300 may be configured to assign any number of bits to the QPCH packet that fall within a predetermined range or are in increments of a single bit.

The transmitter 300 may be configured to send the size of a QPCH packet or quick paging block within a QPCH packet or some other message. In another embodiment, the transmitter 300 does not send the size of the QPCH packet, but relies on the receiver to determine the size of the packet.

The timing and synchronization module is coupled to the scheduler 304. Scheduler 304 keeps track of the communication links and information to be transmitted by transmitter 300 and schedules this information based in part on system timing. In one embodiment, scheduler 304 determines that the wireless communication system is attempting to establish an active communication session with an access terminal that is currently in an idle state.

The wireless communication system sends a paging message to the access terminal via transmitter 300. In addition, the wireless communication system sets one or more quick paging bits assigned to the access terminal or the set of access terminals of which the desired access terminal is a member.

Although any number of quick paging bits may be assigned to each access terminal, typically only a single bit is assigned to each or each group of access terminals. For example, a quick paging block having a predetermined number of quick paging bits may be defined, and a particular access terminal within the coverage area of the access point may be assigned to the nth quick paging bit in the quick paging block.

Although the description is primarily directed to the case where a single quick paging bit is associated with a single access terminal within a particular coverage area, the wireless communication system may assign any number of quick paging bits to an access terminal. The quick paging bit, set-whether active high or low-indicates to the associated access terminal that a subsequent paging channel is intended for the access terminal.

As described above, a quick paging bit can be associated with a single access terminal or with a group of access terminals. When a quick paging bit is asserted or placed in an active state, the one or more access terminals associated with the quick paging bit are aware that at least one access terminal associated with the access paging bit may expect a paging message. The wireless communication system may assign paging bits to groups of paging terminals to minimize the total number of quick paging bits and thus the length of the quick paging block.

The quick paging block generator 310 determines from the scheduler 304 which quick paging bits to assert. In one example, the quick paging block generator typically sets each quick paging bit associated with an access for which a paging message is expected to be "1" at the next available opportunity for transmitting a paging message.

Quick paging block generator 310 couples quick paging blocks with appropriately asserted quick paging bits to optional quick paging block compression module 312. The quick paging block compression module 312 functions to reduce the number of bits required to represent the asserted quick paging bits.

The quick paging block compression module 312 may implement virtually any compression technique. The compression techniques may implement one or more compression algorithms capable of generating lossless compression, lossy compression, or some combination of lossless compression or lossy compression of the quick paging block based on the number of quick paging bits asserted, the location of the quick paging bits in the quick paging block, or some combination thereof.

The quick paging block compression module 312 compresses the length N_{QP_BLK}To generate a quick paging block of length N_{QP_MSG_COMP}Compressed quick paging block. In one embodiment, the length of the compressed quick paging block may be variable and may be one of three possible lengths depending on the number of 1's that represent the bits set or asserted in the quick paging block.

In one embodiment, the quick paging block compression module 312 generates a compressed quick paging block by sequentially indicating the location of each set bit in the quick paging block. The quick paging block compression module 312 may use oneA bit field to indicate this position, wherein the value of this field indicates the position of the set bit. The quick paging block compression module 312 may also reserve one or more values for the bit position field that indicate a particular situation. For example, a value of 0 indicates that no more bits are asserted in the quick paging block. In addition, the value 2^ (N)_{QP_MSG_COMP}) A 1 indicates that more than some predetermined number of quick paging bits, e.g., 5 bits, are set in the quick paging block.

Thus, in this embodiment, the total number of unique bits in the quick paging block is limited to N_{QP_BLK}-2 to account for the two reserved values. The allowable bit positions may be in the range of about 1 to N_{QP_BLK}-2. If more than the predetermined number of bits, e.g., 5 bits, in the quick paging block are set, the access network may interpret the message as all bits being set to 1 and may transmit a single field with a corresponding reserved value. In one embodiment, the quick paging block compression module 312 does not include any indication in the quick paging blockA field of the number of pages or bits included in the quick paging block. The transmitter 300 may instead rely on the receiver to determine the number of pages and bits in the quick paging block. For example, the receiver may test several hypotheses and determine therefrom the number of bits in the quick paging block. In another embodiment, the quick paging block compression module 312 may include a field indicating the number of quick pages or bits in the compressed quick paging block. The receiver determines the number of quick pages or quick paging bits by extracting the appropriate fields from the compressed quick paging block.

Table 1 shows the size of the compressed quick paging block as a function of the number of bits set in the quick paging block in an embodiment that does not include a field indicating the number of quick pages.

Table 1 compressing quick paging block size

The output of the quick paging block compression module 312 is coupled to the aggregator 330. In one embodiment, in which the quick paging block compression module 312 is omitted, the quick paging blocks from the quick paging block generator 310 are coupled to the aggregator 330.

The load control block module 320 concurrently generates a load control block having one or more bits. In one embodiment, the load control block is N in length_{LC_BLK}And set by the access network. The load control block may represent any additional information for one or more access terminals as part of the quick paging channel information. The load control information may be virtually any type of information. For example, the load control information may indicate a type of access terminal that is allowed to access the quick paging information. Alternatively, the load control information can indicate a type of access terminal to which quick paging information can be applied. Access terminals not belonging to the class indicated by the load control block information may be ignoredThis message is omitted.

The aggregator 330 functions to concatenate the compressed quick paging block or quick paging block with the load control block. In this embodiment, the QPCH packet carries two information blocks: a quick paging block and a load control block. The aggregator 330 may append the load control block to the end of the quick paging block or the compressed quick paging block.

The aggregator 330 couples the concatenated quick paging block and load control block to the encoder 340. Encoder 340 functions to encode this concatenated information. Encoder 340 may implement virtually any type of encoding and may implement, for example, systematic encoding, block encoding, convolutional encoding, turbo encoding, etc., or some combination thereof. The output of encoder 340 represents a quick page packet.

The QPCH packet may employ any one or more of techniques for encoding, channel interleaving, repetition, data scrambling, and modulation. In one embodiment, the initial state of the scrambler (not shown) may be generated using a mac id of 0 and a packet format of 0.

In one embodiment, the encoder 340 implements a systematic code such that the redundancy bits are appended to the end of the unmodified concatenated quick paging block and load control block. The systematic code may generate, for example, a cyclic redundancy check code (CRC), a syndrome, parity bits, or some other code bits that provide some degree of redundancy.

The encoder 340 couples the encoded QPCH packet to the TM MIMO processor 220. In one embodiment, TX MIMO processor 220 processes the encoded QPCH packet and generates OFDM symbols with complete QPCH packet information. TX MIMO processor 220 may generate OFDM symbols that allocate this QPCH packet across all OFDM subcarriers or across a predetermined subset of all subcarriers. In such an embodiment, the symbols with the QPCH packet are time division multiplexed with other channels in the OFDM system.

In some embodiments, TX MIMO processor 220 will be able to modulate the QPCH packet onto the subcarriers using any of a predetermined set of modulation types. In one embodiment, TX MIMO processor 220 uses QPSK modulation for all modulation symbols of the QPCH. In other embodiments, TX MIMO processor 220 may employ some other type of modulation, such as BPSK.

In another embodiment, QPCH packet information is assigned to a logical channel mapped to all subcarriers in the OFDM system. In such an embodiment, the mapping of logical channels to physical subcarriers may be static or may be dynamic.

If a multiple access wireless communication system employs Frequency Hopping (FH), the QPCH may be assigned as a logical channel, sometimes referred to as a hop port, and this logical channel may be mapped to a physical channel according to a predetermined frequency hopping algorithm. Thus, in a frequency hopping OFDMA system, the physical subcarrier frequencies assigned to each logical channel change over time. For example, this frequency hopping algorithm may update the mapping of logical channels to physical subcarriers periodically, e.g., every OFDM symbol, every slot, or after every predetermined number of OFDM symbols.

TX MIMO processor 220 couples the OFDM symbols to a transmitter stage 222. Transmitter stage 222 uses antennas 224 to transmit the symbols comprising the QPCH packet.

In the QPCH embodiment described above, the transmitter broadcasts a QPCH packet during an OFDM symbol that occurs during the preamble portion of the superframe. The transmitter broadcasts the QPCH packet to all access terminals in the coverage area.

By transmitting QPCH symbols in the preamble, a large number of access terminals can be addressed simultaneously. This is because, for example, each data bit in a QPCH packet may be addressed to a different mobile station. Transmitting the QPCH in a single OFDM symbol allows several access terminals to concurrently wake up to monitor their respective quick paging bits in the same OFDM symbol.

In addition, all bits in a TDM slot are jointly encoded and may be encoded with a strong CRC, which refers to redundant coded bits that provide a high likelihood of successfully receiving any particular quick paging bit in the packet. This has two advantages. First, the coding gain due to joint coding provides an additional margin that is not available using a single bit. Second, the probability of missing a page becomes very low due to the strong CRC.

Figure 4 is a simplified functional block diagram of one embodiment of a receiver 400 configured to process jointly encoded QPCH packets. Receiver 400 may be part of each access terminal of fig. 1 and may be part of the receiver system of fig. 2. The simplified functional block diagram of figure 4 illustrates only those portions of the receiver 400 that are associated with processing QPCH packets. Receiver 400 typically also includes other processing modules.

The receiver 400 functions to perform a process that is substantially complementary to the process used in the transmitter system to generate QPCH packets. The receiver 400 receives the OFDM symbols containing the QPCH packet and recovers the QPCH packet. The receiver 400 utilizes redundant coded information to improve the likelihood of successfully recovering the buried bits in the quick paging block and the load control block. The receiver 400 uses the recovered quick paging bit information to determine whether to wake up or keep actively monitoring a subsequent paging channel message.

In one embodiment, if the CRC fails, the access terminal monitors the paging channel as a default action. If the CRC succeeds and the corresponding quick paging bit is set, the access terminal is instructed to monitor the paging channel. If the CRC is successful and the assigned quick paging bit is 0 or not asserted, the access terminal returns to the sleep state. The probability of false detection is equal to the probability of false detection of CRC errors, and this probability is very low at a strong CRC such as a CRC with 8 or more bits.

The receiver 400 includes an antenna 252 that couples the received signal to a receiver front end 254. The synchronization module 410 operates in conjunction with the receiver front end. The synchronization module 410 determines symbol timing based on the received signal and determines frame and superframe timing from the symbol timing. The receiver front end 254 utilizes the synchronization information to recover OFDM symbols, and in particular, OFDM preambles having OFDM symbols with QPCH packets.

Receiver front end 254 couples the OFDM symbols with QPCH packets to RX MIMO data processor 260. RX MIMO data processor 260 acts to demodulate the OFDM subcarriers on which the QPCH packet is modulated to recover the QPCH packet.

RX MIMO data processor 260 demodulates the subcarriers in a manner complementary to the manner in which the subcarriers are modulated. That is, if the subcarriers are QPSK modulated, the RX MIMO data processor 260 performs QPSK demodulation of the subcarriers.

The QPCH packet is coupled to a QPCH decoder 420. The QPCH decoder 420 functions to decode QPCH packets in a pattern complementary to the way the packets are encoded in the transmitter. In general, QPCH decoder 420 performs processing complementary to that performed in the transmitter, including any interleaving, decoding, scrambling, repetition, etc., or a combination thereof, that is performed in generating the QPCH packet.

If the QPCH is encoded with a systematic code, the receiver 400 may conditionally process the redundant coded bits based on the associated quick paging bits. For example, if the associated quick paging bit, the receiver 400 may decide not to process the coded bit. In such an embodiment, the receiver 400 may make a trade-off between the processing energy associated with the decoding process and the likelihood of handling a false-asserted bit. In other embodiments, the receiver may be configured to always check the coded bits, such as the CRC or other redundant bits. In such an embodiment, decoder 420 may function to identify that there is received bit error, and in some instances, may identify the one or more received bits that are in error. Decoder 420 may then function to correct the identified erroneous bits.

The output of the decoder 420 or a portion of the QPCH packet may optionally be coupled to a quick paging block decompression module 430. In embodiments where the QPCH includes a compressed quick paging block and a load control block, the decoder 420 may couple at least the compressed quick paging block to the quick paging block decompression module 430 and need not couple any bits from the load control block to the decompression module.

The quick paging block decompression module 430 functions to decompress this compressed quick paging block in a manner complementary to the process used to compress the quick paging block. In the embodiment described above, i.e., where the quick paging block is compressed by including locations up to a predetermined number of quick paging bits, the quick paging block decompression module 430 functions to initially determine the number of asserted quick paging bits represented in the compressed quick paging block. The quick paging block decompression module 430 may determine the length of the compressed quick paging block and may then recover the respective locations of any asserted quick paging bits.

The quick paging block decompression module 430 may recover the quick paging block and output the quick paging block. Subsequent modules, such as a paging module (not shown), can check the quick paging block to determine whether the quick paging block assigned to the access terminal is asserted.

In another embodiment, the quick paging block decompression module 430 may check the location of the compressed quick paging block interrupt bit to determine whether the quick paging bit associated with the access terminal is asserted. In this embodiment, the quick paging block decompression module 430 is not required to actually recover the quick paging block.

Other modules within the receiver 400, such as a paging module (not shown) may operate on the quick paging block information. The paging module may direct the receiver to monitor for paging messages if a quick paging bit associated with the access terminal is asserted. Alternatively, if the quick paging bit associated with the access terminal is not asserted, the paging module may direct the receiver to transition to the sleep state until the next occurrence of the QPCH.

Fig. 5 is a simplified flow diagram of one embodiment of a method 500 of generating a quick paging block having one or more asserted quick paging bits for notifying an access terminal of a paging message. Method 500 may be implemented in, for example, the access point of fig. 1. More specifically, method 500 may be implemented by the transmitter system of fig. 2 or the transmitter of fig. 3.

The method 500 begins at block 510 where a transmitter in an access point determines the number and identity of access terminals scheduled to receive a paging message. Typically, the access terminals that are scheduled are those access terminals that are currently in an idle or dormant state for the desired communication link and that are currently scheduled for a page message that is yet to be transmitted or have a previous page message yet to be acknowledged.

The transmitter proceeds to block 520 to determine the status of the quick paging bit in the quick paging block based on the scheduled paging message. The transmitter may be configured to set or assert the quick paging bits associated with the one or more access terminals scheduled to receive the paging message. Further, the transmitter can be configured to clear or de-assert the quick paging bits associated with those access terminals for which no paging message is scheduled. In one embodiment, each bit value may be determined using a free-wheeling status protocol in the connectivity layer.

The transmitter proceeds to block 530 and generates a quick paging block in which the quick paging bit associated with the scheduled access terminal is asserted and all other quick paging bits are deasserted. After generating the quick paging block, the transmitter may optionally proceed to block 540 and compress the quick paging block to generate a compressed quick paging block. In some embodiments, the transmitter does not compress this quick paging block.

The transmitter proceeds to block 550 and aggregates the compressed quick paging block with other information sent on the QPCH. In one embodiment, the transmitter appends a load control block to the quick paging block, which is compressed or uncompressed depending on the embodiment. In other embodiments, the transmitter may append other information to the quick paging block before or after it.

The transmitter proceeds to block 560 and encodes the QPCH information. The encoder operates on the quick paging block and the additional information. Thus, the encoding of the quick paging bits is performed jointly. The quick paging bits are encoded with other quick paging bits and other information such as load control blocks, etc. The encoded output represents a QPCH packet.

The transmitter proceeds to block 570 and schedules the QPCH packet for transmission. In one embodiment, the transmitter schedules the QPCH packet to be transmitted in one of a plurality of OFDM symbols in the superframe preamble. If a QPCH packet occupies the information-carrying subcarriers of an OFDM system, all other channels in the system, including traffic channels and other overhead channels, are time-domain multiplexed with the QPCH. Similarly, if the QPCH occupies only a subset of the information carrying subcarriers in the OFDM system, at least a portion of the other channels are time domain multiplexed with the QPCH on the premise that these subcarriers are not dedicated for use by the QPCH.

The transmitter proceeds to block 580 and maps the QPCH packet to OFDM symbols at the appropriate time as determined by the schedule. In one embodiment, the OFDM symbol is one of the first six preamble symbols that occur in a superframe. Of course, other embodiments may have other symbol positions.

The transmitter may modulate the QPCH packet onto the subcarriers using a predetermined modulation type. The modulation type may be selected to be one that is relatively less noise sensitive while supporting modest information throughput. In one embodiment, the transmitter QPSK modulates QPCH packets onto the subcarriers of the OFDM symbols.

After generating the OFDM symbol, the transmitter proceeds to block 590 and transmits the OFDM symbol including the QPCH packet. The transmitter may, for example, frequency convert the OFDM symbol to a desired RF operating band and wirelessly transmit the OFDM symbol in the RF operating band.

Fig. 6 is a simplified flow diagram of one embodiment of a method 600 of processing a quick paging block. The method 600 may be implemented in, for example, the access terminal of fig. 1, the receiver system of fig. 2, or the receiver of fig. 3. In general, the method 600 of FIG. 6 functions as a method complementary to the QPCH generation method of FIG. 5.

Method 600 begins at block 610, where a receiver receives one or more OFDM symbols. The at least one symbol may comprise a QPCH packet. For example, in the method of fig. 5, a QPCH packet may be contained in a single OFDM symbol. In one embodiment, the receiver synchronizes to the superframe timing and extracts at least the OFDM symbols associated with the QPCH packet.

The receiver proceeds to block 620 and recovers the QPCH packet from the appropriate OFDM symbols. In one embodiment, the receiver demodulates the subcarriers of the OFDM symbols and recovers the QPCH packet information.

The receiver proceeds to block 630 and decodes the QPCH packet to determine if there are any errors. Depending on the type of encoding used to generate the QPCH packet, the receiver may have the ability to correct one or more errors in the QPCH packet as a result of the decoding process. The receiver also performs operations complementary to any encoding operations, such as those that function to scramble, interleave, repeat, or otherwise process QPCH block information.

The receiver may optionally proceed to block 640 and decompress the quick paging block portion of the QPCH packet. In one embodiment, the receiver determines the length of a variable length quick paging block and decompresses the variable length compressed quick paging block.

The receiver proceeds to block 650 and determines the state of the quick paging bit to determine whether the quick paging bit associated with the receiver or the access terminal having the receiver is asserted. Depending on the manner in which the blocks are compressed, the process of decompressing the quick paging block may be optional. In embodiments where the quick paging block is compressed by indicating the location of the quick paging bit that is asserted, the receiver can determine whether the associated quick paging bit is asserted without recovering the uncompressed quick paging block.

After the receiver determines the state of the associated quick paging bit, the receiver proceeds to block 660 to direct the operation of the receiver based on the state of the bit. If the associated quick paging bit is asserted, the receiver may monitor the paging channel for paging messages at the appropriate time. If the receiver determines that the associated quick paging bit is not asserted, the receiver may transition to a sleep state until the next scheduled QPCH packet.

Fig. 7 is a simplified functional block diagram of one embodiment of a transmitter 700 implementing a quick paging block. The transmitter 700 comprises means 702 for synchronizing a time base with a system time, coupled with means 704 for scheduling information according to the means 702 for synchronizing a time base. The means for scheduling information 704 can be configured to determine which of a plurality of access terminals has a paging message scheduled for transmission.

The means for scheduling information 704 is coupled to a means for generating QPCH block 710 configured to generate a quick paging block based on scheduled paging channel transmissions. Means for scheduling information 704 functions as means for determining that there is a scheduled message for an access terminal. The means for generating a QPCH block 710 is configured to set a quick paging bit among a plurality of quick paging bits in a quick paging block. The means for generating a QPCH block 710 sets a quick paging bit corresponding to an access terminal having a scheduled message. The means for generating a QPCH block 710 couples the quick paging block to the means for aggregating information 730.

The means for generating 720 is configured to generate information for one or more bits, blocks, or fields to be included with the QPCH packet. The means for generating additional information 720 couples this additional information to the means for aggregating information 730.

The means for aggregating information 730 functions to combine, aggregate, or concatenate the quick paging block with the additional information. In one embodiment, a load control block is concatenated with a quick paging block to generate a QPCH packet consisting of the concatenation of the quick paging block and the load control block.

The output of the means for aggregating information 730 is coupled to a means for encoding QPCH packet 740, which functions to encode this concatenated QPCH packet. The means for encoding the QPCH packet 740 encodes the quick paging block and generates an encoded quick paging block. That is, means for encoding the QPCH packet 740 jointly encodes each quick paging bit with at least one other quick paging bit corresponding to a different access terminal. Means for encoding the QPCH packet 740 couples the encoded QPCH packet to means for TX processing 750, which means may be used for TX MIMO processing depending on the system. Means for TX processing 750 operates to generate at least one OFDM symbol having at least a portion of this encoded QPCH packet. Means for TX processing 750 generates at least one OFDM symbol from the stream of OFDM symbols and thereby time division multiplexes the encoded quick paging packet with the quick paging block and different information on a channel. An output of the means for TX processing 750 is coupled to a means for transmitting 760, which acts to process the at least one OFDM symbol to an RF frequency for transmission using an antenna 762.

As seen in fig. 7, devices 702, 704, 712, 720, and 750 are optional and may be omitted based on the application and system design.

Fig. 8 is a simplified functional block diagram of one embodiment of a receiver 800 configured to process a quick paging block. Receiver 800 includes an antenna 852 configured to receive OFDM symbols with QPCH packets.

This antenna couples the OFDM symbol to means for receiving OFDM information 854, which is configured to receive the quick paging packet and process the received OFDM symbol into baseband OFDM symbols or samples. The means for synchronizing timing 810 functions to synchronize the received samples to align with OFDM symbol timing.

An output of the means for receiving OFDM information 854 is coupled to means for RX MIMO processing 860 configured to process the OFDM symbols to recover the latent information modulated on the OFDM subcarriers. For OFDM symbols with QPCH packets, means 860 for RX MIMO processing demodulates the OFDM subcarriers to recover the coded QPCH packets.

Means for RX MIMO processing 860 couples the encoded QPCH packet to means for decoding a QPCH packet 820 configured to decode this encoded PQCH packet to recover a QPCH packet including a quick paging block. The output of means for decoding 820 the QPCH packet is optionally coupled to means for decompressing the QPCH block of the QPCH packet 830 to determine which of the quick paging bits is asserted. The means for decompressing the QPCH block 830 can also function as means for determining the state of the quick paging bit associated with a particular access terminal based on the output of the decompression process. The receiver may determine what action to take based on the state of the associated quick paging bit.

Quick paging channel formats and quick paging channel packets, and processes for generating quick paging packets are described herein. The jointly encoded quick paging packet allows for the generation of redundant bits to assist in accurately recovering the quick paging bits at the wireless receiver. The improved ability to accurately recover quick paging bits reduces the likelihood of losing a paging message intended for the receiver.

As used herein, the terms "coupled" or "connected" are used to indicate not only a direct coupling or connection, but also an indirect coupling. Where two or more blocks, modules, devices, or apparatus are coupled, there may be one or more intervening blocks between the two coupled blocks.

The various illustrative logical blocks, modules, and circuits described in connection with the embodiments disclosed herein may be implemented or performed with a general purpose processor, a Digital Signal Processor (DSP), a Reduced Instruction Set Computer (RISC) processor, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any processor, controller, microprocessor, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.

For a firmware and/or software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. These firmware and/or software codes may be stored in a memory and executed by a processor. The memory may be implemented within the processor or external to the processor.

The steps of a method, process, or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The various steps or actions in a method or process may be performed in the order illustrated, or may be performed in other orders. In addition, one or more process or method steps may be omitted, or one or more process or method steps may be added to the methods and processes. Additional steps, blocks, or acts may be added to the methods and processes at the beginning, end, or in between the existing elements.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (44)

1. A method of notifying an access terminal, the method comprising:

determining that there is a scheduled message for the access terminal;

setting a quick paging bit among a plurality of quick paging bits in a quick paging block, the quick paging bit corresponding to the access terminal;

encoding the quick paging block to generate an encoded quick paging packet;

generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block; and

transmitting the at least one OFDM symbol.

2. The method of claim 1, wherein the generating at least one OFDM symbol comprises generating at least one OFDM symbol having an entire encoded quick paging block.

3. The method of claim 1, further comprising:

generating additional bits different from the quick paging block; and

appending the additional bits to the quick paging block prior to encoding the quick paging block.

4. The method of claim 1, further comprising:

compressing the quick paging block to generate a compressed quick paging block; and

wherein encoding the quick paging block comprises encoding the compressed quick paging block.

5. The method of claim 4, wherein compressing the quick paging block comprises:

determining a number of quick paging bits asserted among the plurality of quick paging bits; and

generating successive fields indicating the location of the respective asserted quick paging bits if the number of asserted bits is less than a predetermined amount.

6. The method of claim 4, wherein compressing the quick paging block comprises:

determining a number of quick paging bits asserted among the plurality of quick paging bits; and

generating a predetermined value representative of the quick paging block if the number of asserted quick paging bits is greater than a predetermined amount.

7. The method of claim 1, wherein encoding the quick paging block comprises system encoding the quick paging block.

8. The method of claim 1, wherein encoding the quick paging block comprises generating a cyclic redundancy code for a packet that includes the quick paging block.

9. The method of claim 1, wherein transmitting the at least one OFDM symbol comprises time division multiplexing the at least one OFDM symbol with other information on at least one channel.

10. The method of claim 1, wherein transmitting the at least one OFDM symbol comprises transmitting the at least one OFDM symbol during a superframe preamble.

11. A method of notifying an access terminal, the method comprising:

setting a quick paging bit corresponding to an access terminal in a quick paging block having a plurality of bits corresponding to a plurality of access terminals;

compressing the quick paging block to generate a compressed quick paging block; and

encoding the compressed quick paging block to generate an encoded quick paging block.

12. The method of claim 11, further comprising time division multiplexing the encoded quick paging block with other information on at least one channel of a wireless communication system.

13. The method of claim 11, further comprising:

generating an Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block; and

transmitting the OFDM symbol.

14. The method of claim 13, wherein generating the OFDM symbol comprises modulating at least a portion of the encoded quick paging block onto substantially all signal-bearing subcarriers of the OFDM symbol.

15. The method of claim 13, wherein generating the OFDM symbol comprises Quadrature Phase Shift Keying (QPSK) modulating at least a portion of the encoded quick paging block onto at least a subset of subcarriers of the OFDM symbol.

16. A method of processing a quick page message, the method comprising:

receiving a quick paging packet;

decoding the quick paging packet to generate a quick paging block;

decompressing the quick paging block; and

a state of a quick paging bit associated with an access terminal is determined based on an output of the decompression process.

17. The method of claim 16, wherein receiving the quick paging packet comprises receiving the quick paging packet including the quick paging block and a load control block.

18. The method of claim 16, wherein receiving the quick paging packet comprises receiving an Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the quick paging packet.

19. The method of claim 16, wherein determining the state of the quick paging bit comprises:

determining a location of an asserted bit in the quick paging block based on an output of the decompression process; and

comparing the location to a location of a quick paging bit associated with the access terminal.

20. An apparatus for generating a quick page message, the system comprising:

a scheduler configured to determine that a paging message for an access terminal has been scheduled;

a quick paging block generator coupled to the scheduler and configured to assert a quick paging bit corresponding to the access terminal and further configured to generate a quick paging block having at least the quick paging bit and a different quick paging bit corresponding to a different access terminal;

an encoder coupled to the quick paging block generator and configured to generate an encoded quick paging packet based on the quick paging block; and

a transmit processor coupled to the encoder and configured to generate at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging packet.

21. The apparatus of claim 20, further comprising:

a compression block coupled to the quick paging block generator and configured to compress the quick paging block and generate a compressed quick paging block; and is

Wherein the encoder is coupled to the compressed block and configured to generate the encoded quick paging packet based on the compressed quick paging block.

22. The apparatus of claim 20, further comprising:

a load control module configured to generate a load control block having at least one bit different from the quick paging bit;

an aggregator coupled to the quick paging block generator and the load control block and configured to aggregate the quick paging block with the load control block; and is

Wherein the encoder is configured to encode the aggregated output of the aggregator.

23. The system of claim 20, further comprising a transmitter coupled to the transmit processor and configured to transmit the at least one OFDM symbol during a superframe preamble.

24. The system of claim 20, further comprising a transmitter coupled to the encoder and configured to time division multiplex the encoded quick paging packet with other information on at least one channel.

25. An apparatus for notifying an access terminal, the system comprising:

means for determining that there is a scheduled message for the access terminal;

means for setting a quick paging bit among a plurality of quick paging bits in a quick paging block, the quick paging bit corresponding to the access terminal;

means for encoding the quick paging block to generate an encoded quick paging packet;

means for generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block; and

means for transmitting the at least one OFDM symbol.

26. The apparatus of claim 25, wherein the means for generating at least one OFDM symbol comprises means for generating at least one OFDM symbol with a full encoded quick paging block.

27. The apparatus of claim 25, further comprising:

means for generating additional bits different from the quick paging block; and

means for appending the additional bits to the quick paging block prior to encoding the quick paging block.

28. The apparatus of claim 25, further comprising:

means for compressing the quick paging block to generate a compressed quick paging block; and is

Wherein the means for encoding a quick paging block comprises means for encoding the compressed quick paging block.

29. The method of claim 25, wherein the means for compressing the quick paging block comprises:

means for detecting a number of quick paging bits asserted among the plurality of quick paging bits; and

generating successive fields indicating the location of the asserted quick paging bits within the quick paging block if the number of asserted bits is less than a predetermined amount.

30. The method of claim 28, wherein the means for compressing the quick paging block comprises:

means for determining a number of quick paging bits among the plurality of quick paging bits that are asserted; and

means for generating a predetermined value representative of the quick paging block if the number of asserted quick paging bits is greater than a predetermined amount.

31. An apparatus for notifying an access terminal, the system comprising:

means for setting a quick paging bit corresponding to the access terminal;

means for jointly encoding the quick paging bits with at least one additional quick paging bit corresponding to a different access terminal to generate an encoded quick paging block; and

means for time division multiplexing the encoded quick paging block with different information on a channel.

32. The apparatus of claim 31, further comprising means for time division multiplexing the encoded quick paging block with other information on at least one channel of a wireless communication system.

33. The apparatus of claim 31, further comprising:

means for generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block.

34. The apparatus of claim 33, wherein the means for generating at least one OFDM symbol comprises modulating at least a portion of the encoded quick paging block onto substantially all signal-bearing subcarriers of the at least one OFDM symbol.

35. The apparatus of claim 33, wherein generating the at least one OFDM symbol comprises Quadrature Phase Shift Keying (QPSK) modulating at least a portion of the encoded quick paging block onto at least a subset of subcarriers of the at least one OFDM symbol.

36. An apparatus for processing a quick page message, the system comprising:

means for receiving a quick paging packet;

means for decoding the quick paging packet to generate a quick paging block;

means for decompressing the quick paging block; and

means for determining a state of a quick paging bit associated with an access terminal based on an output of the decompression process.

37. The apparatus of claim 36, wherein said means for receiving a quick paging packet comprises means for receiving the quick paging packet including the quick paging block and a load control block.

38. The apparatus of claim 36, wherein the means for receiving the quick paging packet comprises means for receiving at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the quick paging packet.

39. The apparatus of claim 36, wherein the means for determining the state of the quick paging bit comprises:

means for determining a location of an asserted bit in the quick paging block based on an output of the decompression process; and

means for comparing the location to a location of a quick paging bit associated with the access terminal.

40. A processor-readable medium comprising instructions usable by one or more processors, the instructions comprising:

instructions for determining that there is a scheduled message for an access terminal;

instructions for setting a quick paging bit among a plurality of quick paging bits in a quick paging block, the quick paging bit corresponding to the access terminal;

instructions for encoding the quick paging block to generate an encoded quick paging packet;

instructions for generating at least one Orthogonal Frequency Division Multiplexing (OFDM) symbol having at least a portion of the encoded quick paging block;

instructions for transmitting the at least one OFDM symbol.

41. The processor-readable medium of claim 41, wherein the instructions further comprise:

instructions for compressing the quick paging block to generate a compressed quick paging block.

42. A processor-readable medium comprising instructions usable by one or more processors, the instructions comprising:

instructions for setting a quick paging bit corresponding to an access terminal in a quick paging block having a plurality of bits corresponding to a plurality of access terminals;

instructions for compressing the quick paging block to generate a compressed quick paging block; and

instructions for encoding the compressed quick paging block to generate an encoded quick paging block.

43. A processor-readable medium comprising instructions usable by one or more processors, the instructions comprising:

instructions for processing a quick paging packet;

instructions for decoding the quick paging packet to generate a quick paging block;

instructions for decompressing the quick paging block; and

instructions for determining a state of a quick paging bit associated with an access terminal based on an output of the decompression process.

44. The processor-readable medium of claim 41, wherein the instructions further comprise:

instructions for determining a location of a predicated bit in the quick paging block based on the decompression process; and

instructions for comparing the location to a location of a quick paging bit associated with the access terminal.