HK1119841B - Charge pump circuit and method therefor - Google Patents

Description

Charge pump circuit and method thereof

Technical Field

The present invention relates generally to electronics, and more particularly to methods and structures for forming semiconductor devices.

Background

In the past, the semiconductor industry utilized various methods and structures to form power supply controllers that helped regulate the output voltage to a desired value. In some power supply configurations, two transistors are connected in a stack or half-bridge circuit configuration to drive an inductor and form an output voltage. Each of these two transistors is driven by a separate transistor driver in the half-bridge circuit. The high-side driver is typically operated from a higher supply voltage than the low-side driver. The higher supply voltage is typically referred to as a boost voltage and is boosted by a bootstrap circuit from the voltage at the common node connected between the high-side and low-side transistors. In some modes of operation, the two transistors may not be switched (switch) for a period of time. These periods of time that do not transition are commonly referred to as burst modes or cycle-skipping (cycle-skipping). During such a period, the value of the boosted voltage generally decreases, which causes an inefficient operation of the power supply system.

Accordingly, it is desirable to have a power supply controller that can provide power to a high-side driver during periods when the power switch is not switching.

Drawings

FIG. 1 schematically illustrates an embodiment of a portion of a power supply system including a power supply controller having a charge pump circuit, in accordance with the present invention;

FIG. 2 schematically illustrates an embodiment of a portion of another power supply system including another power supply controller having a charge pump circuit, in accordance with the present invention;

FIG. 3 schematically illustrates an embodiment of a portion of a shifter circuit of the power supply controller of FIG. 1, in accordance with the present invention;

FIG. 4 shows a simplified enlarged plan view of a semiconductor die (die) on which the power supply controller of FIG. 1 is formed in accordance with the present invention;

fig. 5 shows a simplified enlarged cross-sectional view of a first portion of the semiconductor die of fig. 4 in accordance with the present invention;

fig. 6 shows an enlarged simplified cross-sectional view of a second portion of the semiconductor die of fig. 4 in accordance with the present invention;

fig. 7 shows an enlarged simplified cross-sectional view of a third portion of the semiconductor die of fig. 4 in accordance with the present invention;

fig. 8 illustrates an enlarged simplified cross-sectional view of a fourth portion of the semiconductor die of fig. 4 in accordance with the present invention.

Detailed Description

Fig. 1 schematically illustrates an embodiment of a portion of a power supply system 10 that includes an exemplary embodiment of a portion of a power supply controller 35, the power supply controller 35 being used to regulate an output voltage formed by the system 10. As will be seen further hereinafter, the controller 35 is arranged to charge the charge pump capacitor to a first voltage and to transfer charge from the pump capacitor to another capacitor for a period of time in response to the pump capacitor being charged to the first voltage. It will also be seen that the charging of the pump capacitor is terminated in dependence upon the differential voltage across the pump capacitor rather than in dependence upon the period of time over which the pump capacitor is charged.

System 10 receives power, such as a rectified ac voltage, between a power input terminal 11 and a power return (return) terminal 12 and forms an output voltage between a voltage output 14 and a voltage return 15. The voltage between terminals 11 and 12 is commonly referred to as bulk voltage (bulk voltage). The system 10 shown in fig. 1 is a buck power system. A first power switch, such as MOS transistor 28, and a second power switch, such as MOS transistor 29, are connected in a half-bridge configuration or stack configuration between terminals 11 and 12. The diodes in parallel with transistors 28 and 29 represent the body diodes (body diodes) of the transistors. Transistors 28 and 29 are connected together at a switching node or common node 27 of the half-bridge configuration, which node 27 is also connected to inductor 18. Although transistors 28 and 29 are shown in the embodiment of fig. 1 as being external to controller 35, those skilled in the art will recognize that transistors 28 and 29 may be internal to controller 35 in other embodiments. Generally, inductor 18 and capacitor 19 are connected to receive current from transistors 28 and 29 and form an output voltage between output 14 and return 15. Feedback network 26 is connected to receive the output voltage and form a feedback signal representative of the value of the output voltage. Feedback network 26 may be an optical coupler or other type of known feedback network.

In most embodiments, the voltage between terminals 11 and 12 is received from a rectified household power supply. To operate in various countries, system 10 is arranged to receive a voltage between terminals 11 and 12 that may be as high as six hundred volts (600V) or as low as two hundred fifty volts (250V), depending on the country in which the voltage is provided to terminals 11 and 12. Thus, system 10 typically receives a lower voltage on input 33 that is applied to controller 35 between power input 36 and power return 37 of controller 35. The voltage received on input 33 may be derived from the output voltage of system 10 or may be derived from another source. A boost network comprising a diode 30 and a boost capacitor 31 is connected between the input 33 and the switching node 27 of the half bridge. Controller 35 receives the half-bridge voltage from node 27 on switching input 42. The boost network of diode 30 and capacitor 31 is used to form a boost voltage that is used to form the drive signal to transistor 28. The controller 35 receives the boosted voltage on a boost input 39. Such booster networks are well known to those skilled in the art.

Controller 35 typically includes a switching power supply circuit such as a Pulse Frequency Modulation (PFM) controller or PFM66 that receives a feedback signal from network 26 through feedback input 44 of controller 35 and responsively forms a PFM control signal that is used to form the drive signals to transistors 28 and 29. The controller 66 may be any of a variety of well-known PFM controllers or may be a Pulse Width Modulation (PWM) controller or a hysteretic (hysteretic) controller. Controller 35 also includes a high-side control circuit 46 and a low-side driver 74, with high-side control circuit 46 for developing a first drive signal to control transistor 28 and low-side driver 74 for developing a second drive signal to control transistor 29. The output of circuit 46 is coupled to transistor 28 through output 40 of controller 35 and the output of driver 74 is coupled to transistor 29 through output 43 of controller 35. Controller 35 may also include low-side logic, not shown, that helps form the input signals for driver 74. In addition, controller 35 may include an internal regulator 71 connected between input 36 and return 37 to receive the input voltage and form an internal operating voltage on output 72 for operating components of controller 35, such as PFM controller 66 and low-side driver 74. The high-side control circuit 46 includes a driver circuit or driver 50, a logic circuit or logic 49, a charge pump circuit 52, and level shifter or level shifter circuits 47 and 48.

To develop the drive signal from driver 50 at a voltage sufficient to enable transistor 28, typically logic 49 of high-side control circuit 46 and at least driver 50 are connected between inputs 39 and 42 for self-boosting operation. The boosted voltage is formed by the charge stored on capacitor 31 as a result of the conversion by transistors 28 and 29 and is the differential voltage between inputs 39 and 42. The average voltage of the boosted voltage is approximately equal to the voltage received on input 36 minus the voltage drop across diode 30. When referring to terminal 12, the instantaneous value of the boosted voltage generally fluctuates and has a peak value greater than the input voltage received on terminal 11.

As will be seen further below, the high-side control circuit is typically formed within an isolation or floating region of the semiconductor die on which the controller 35 is formed to isolate the remainder of the controller 35 from the boost voltage used to operate the circuit 46. For embodiments in which circuitry 46 operates from a low-side voltage that does not harm the rest of controller 35, circuitry 46 may not be formed within such floating or isolated regions. The circuits 47 and 48 are arranged to receive signals from the PFM controller 66 and shift or translate the voltage value of the signals from the voltage of the reference output 72 to a higher voltage value in accordance with the boosted voltage used to operate the circuit 46. As will also be seen further hereinafter, a portion of circuits 47 and 48 are formed within the floating region.

During operation, PFM controller 66 forms a control signal 67 used by circuit 46 to assert the first drive signal on (assert) output 40 and enable transistor 28. Thereafter, the PFM controller 66 typically develops a second control signal 68 that is used by the circuit 46 to disable the transistor 28. During the time interval that transistor 28 is activated, transistor 28 couples a voltage from input terminal 11 to node 27. Thereafter, the PFM controller 66 asserts a control signal 69 used by a driver 74 to enable the transistor 29. The negating (inverting) signal 69 is used to disable transistor 29. Switching the half bridge forms a bridge voltage on node 27 that is received by controller 35 on switching input 42. As can be seen, the bridge voltage on input 42 is less than the boosted voltage on input 39. In addition, the switching of transistors 28 and 29 causes the bridge voltage to vary between two voltage values between the voltage at input terminal 11 and the voltage at return terminal 12. Thus, the bridge voltage value increases at least a portion of the time that transistor 28 is activated and decreases at least a portion of the time that transistor 29 is activated.

During operation, controller 35 may stop switching transistors 28 and 29 for a period of time. For example, the input voltage may be reduced to a value less than the desired output voltage value, and PFM control signal 67 may stop switching transistors 28 and 29 for a time greater than the switching period of controller 66. In this case, transistor 28 is normally on and transistor 29 is off. In some cases, this period of time may be long enough so that the voltage on capacitor 31 drops to a value that driver 50 cannot operate. The charge pump circuit 52 is arranged to provide power to operate the driver 50 during such long periods. Circuit 52 is a self-oscillating (self-oscillating) charge pump that operates independently of the switching of transistors 28 and 29.

Zener diode 53 forms an operating voltage for circuit 52 that allows circuit 52 to operate from the voltage between input 42 and output 41. Input 42 forms the high side rail for operating circuit 52 and output 41 forms the low side rail for operating circuit 52. If transistor 28 is enabled, the bridge voltage between input 42 and return 37 may be greater than the breakdown or zener voltage of diode 53. This will cause diode 53 to conduct and fix the voltage between the high side rail of input 42 and the low side rail of output 41 to the zener voltage of diode 53. Thus, in these cases, diode 53 forms the operating voltage of circuit 52. The zener voltage of diode 53 is selected to be a value suitable for operating the components of circuit 52, such as comparator 54 and one shot 57. In a preferred embodiment, the zener voltage is approximately twenty volts (20V). The current through diode 53 is directed by current source 65. In some embodiments, an optional external resistor 32 may be connected between output 41 and return 37. In such a case, a portion of the current through diode 53 is directed through current source 65 and another portion is directed through resistor 32. If the bridge voltage is below the zener voltage of diode 53, such as when transistor 28 is disabled and transistor 29 is enabled, output 41 is pulled to the voltage of return 37, such that the value of the voltage between input 42 and output 41 is substantially the bridge voltage. Because the bridge voltage is not approximately greater than the value of return 37, circuit 52 has no supply voltage and does not operate. Because circuit 52 only has to operate and provide power when transistor 28 is enabled, it is an acceptable condition for circuit 52 to not operate when the bridge voltage is low. The zener voltage of diode 53 is also greater than the reference voltage of reference circuit or reference 56.

To illustrate the operation of circuit 52, assume that the voltage of capacitor 63 is less than the value of reference 56. This condition causes the output of comparator 54 to be low. The comparator output is connected to the pulse generator circuit shown in fig. 1 as one shot circuit 57. The circuit 57 may be formed, for example, from a series of inverters connected to logic gates as an edge detector circuit or other well-known pulse generator circuit. The output of circuit 57 is a control signal that is used to drive the inverter formed by stack transistors 58 and 59. When circuit 57 is triggered by comparator 54, the non-triggered state of circuit 57 is high and the output goes low for a time interval. Because circuit 57 is not triggered, the output is high and transistor 59 is enabled to pull the output node 60 of the inverter low. The low on node 60 allows current source 65 to form a charging current 64 through diode 61 and transistor 59 to charge pump capacitor 63. The diode 61 is preferably a Schottky diode. An optional external resistor 32 may be connected to output 41 to increase the amount of current used to charge capacitor 63. Without resistor 32, current 64 is approximately the current of source 65 minus the current through diode 53. Circuit 52 continues to charge capacitor 63 until the voltage on capacitor 63 reaches the voltage value from reference 56. The output of comparator 54 changes state to logic high in response to capacitor 63 charging to the value of reference 56. The high activity signal from comparator 54 triggers circuit 57 and causes the output to go low for a period or interval of time, which is determined by the time control elements of circuit 57. The low from circuit 57 disables transistor 59 and enables transistor 58. Enable transistor 58 causes the bridge voltage of enable diode 62 to be applied to node 60. Start-up diode 62 couples pump capacitor 63 to input 39 in parallel with boost capacitor 31, thus starting up pump capacitor 63 to transfer charge to boost capacitor 31. The pulse width of circuit 57 is selected to provide sufficient time to distribute the maximum amount of charge from capacitor 63 to capacitor 31. When the time interval of the pulse from circuit 57 expires, the output of circuit 57 again goes high, which disables transistor 58 and enables transistor 59, which in turn charges capacitor 63 with current 64 again. This cycle of circuit 52 continues during operation of controller 35. As can be seen from the description, circuit 52 is a self-oscillating charge pump circuit that cycles independently of the switching of transistors 28 and 29, and thus the charging interval of capacitor 63 is a function of the voltage stored on capacitor 63 and a function of time. When transistors 28 and 29 are enabled and disabled, the voltage on node 27 and input 42 changes, however, circuit 52 always charges capacitor 63 to the fixed voltage of reference 56.

Because circuit 52 has a higher voltage supply for the high side rail connected to input 42 and a lower voltage supply for the low side rail connected to output 41, circuit 52 is dependent on the voltage on node 27. For example, if transistor 28 is enabled, the voltage on node 27 is pulled to the voltage of terminal 11, and if transistor 29 is enabled, the voltage on node 27 is pulled to the voltage of return terminal 12. When the voltage on node 27 is greater than the voltage of reference 56, charge pump circuit 52 operates and cycles to charge capacitor 63 to the voltage of reference 56 and then transfer charge from capacitor 63 to capacitor 31 for a time interval determined by the pulse width of circuit 57.

Because the charge supplied from capacitor 63 is only needed when drivers 50 and 74 and corresponding transistors 28 and 29 are not switching, the current required during the non-switching time is small and the charge required from capacitor 63 is also small. Thus, capacitor 63 may be incorporated into the semiconductor die as well as the circuitry of controller 35. In one embodiment, capacitor 63 is approximately twenty picofarads (20pf), and the width of the pulses generated by circuit 57 is approximately one hundred nanoseconds (100 nanoseconds). For larger values of the capacitor 63, the cycle frequency of the circuit 52 decreases.

To facilitate this function of controller 35, input 36 is configured to receive a voltage less than the bulk voltage, and return 37 is configured to be connected to terminal 12. Input 39 is arranged to receive the boosted voltage. Regulator 71 is connected between input 36 and return 37 to form an internal operating voltage on output 72. PFM controller 66 is connected between output 72 and return 37 and also has a feedback control input connected to input 44 to receive a feedback signal from feedback network 26. The PFM66 output of signal 69 is connected to the input of driver 74. An output of driver 74 is connected to output 43, output 43 being arranged in connection with a gate of transistor 29. An input of circuit 47 is connected to receive signal 67 from PFM66, and an output is connected to a first input of logic 49. An input of circuit 48 is connected to receive signal 68 from PFM66, and an output is connected to a second input of logic 49. An output of logic 49 is connected to an input of driver 50, and an output of driver 50 is arranged to be connected to output 40 and to a gate of transistor 28. An anode of diode 53 is connected to a first terminal of current source 65. A second terminal of current source 65 is connected to return 37. A cathode of diode 53 is connected to a first terminal of reference 56, reference 56 having a second terminal connected to a non-inverting input of comparator 54. An inverting input of comparator 54 is connected to node 60. An output of comparator 54 is connected to an input of circuit 57, and an output of circuit 57 is connected to a gate of transistor 58 and a gate of transistor 59. A source of transistor 59 is connected to a first terminal of a current source 65. A drain of transistor 59 is connected to node 60 and to a drain of transistor 58. A source of transistor 58 is commonly connected to a cathode of diode 53, an anode of diode 61, and input 42. The cathode of the diode 61 is connected to the anode of the diode 62 and to a first terminal of the capacitor 63. The cathode of diode 62 is connected to input 39. A second terminal of capacitor 63 is connected to node 60. Comparator 54 and circuit 57 are connected to receive power between a high-side power supply rail connected to the cathode of diode 53 and a low-side power supply rail connected to the anode of diode 53. Driver 50, logic 49, and circuits 47 and 48 are connected to receive power between input 39 and input 42.

Fig. 2 schematically illustrates an embodiment of a portion of a power supply system 80, which is an alternative embodiment of the system 10 described in the description of fig. 1. System 80 includes a power supply controller 81, which is an alternative embodiment of controller 35 also described in the description of fig. 1. Controller 81 is identical to controller 35 except that controller 81 includes a charge pump circuit 83, which is an alternative embodiment of charge pump 52 also described in the description of fig. 1. Circuit 83 is identical to circuit 52 except that circuit 83 has additional diodes 86 and 87 that form different connections to node 27.

In some cases, the voltage on node 27 may become negative with respect to terminal 12. In such a case, the isolation region in which the circuit 52 (fig. 1) is formed may trigger the parasitic substrate bipolar transistor. Diode 86 fixes the floating upper power rail of node 84 to the voltage of input 36 to prevent the parasitic bipolar transistor from being activated. Diode 87 is also added to buffer the voltage of node 84 from node 27.

Circuit 83 is similarly connected to circuit 52 except that the anode of diode 86 is connected to input 36 and the cathode is connected to the source of transistor 58. Likewise, diode 87 is inserted between the source of transistor 58 and the anode of diode 61 such that the anode of diode 87 is connected to the anode of diode 61 and input 42. A cathode of diode 87 is connected to a cathode of diode 86 and to a source of transistor 58.

Fig. 3 schematically illustrates an embodiment of a circuit suitable for use as circuits 47 and 48. Level shifter circuit 47 is operative to shift or convert the voltage of the logic level of a control signal, such as control signal 67, from the voltage of regulator 71 to the boosted voltage on input 39. Converter circuit 47 receives PFM control signal 67 and forms a negative activity pulse upon receiving a rising edge of signal 67. Signal 67 high causes transistor 101 to pull the bar (bar) signal input set low and set latch 92. Because the boosted voltage on input 39 may change abruptly during operation of transistor 28, and because the drain of transistor 101 has a parasitic capacitance to the substrate, represented as capacitor 104, circuit 47 also includes transistor 103, capacitor 107, and resistor 106, resistor 106 preventing abrupt changes in the boosted voltage from changing the output of circuit 47. A sudden change in the boosted voltage is coupled across capacitor 104 and generates a current that flows through resistor 102 to begin charging capacitor 104. This may produce unwanted spurious set pulses for latch 92. However, the rapid voltage change creates a current change through the resistor 106 and the resulting current flows therethrough to begin charging the capacitor 107. The current flowing to capacitor 107 forms a voltage drop across resistor 106 that enables transistor 103. Transistor 103 turns on which begins to conduct current to charge capacitor 104 and fix the voltage value on the set bar signal input of latch 92 to a voltage substantially equal to the boosted voltage value on input 39. Enabling transistor 103 prevents rapid changes in the value of the boosted voltage from erroneously changing the state of the latch.

Fig. 4 shows an enlarged simplified plan view of semiconductor die 110, with controller 35 formed on die 110. The controller 35 is shown in a general manner by the block labeled with the numeral 35. The portion 112 includes at least the transistor 101 of the converter circuit 47 shown in fig. 3. Portion 113 comprises a portion of converter circuit 48 shown in fig. 1. Controller 35 is formed on die 110 by semiconductor fabrication techniques, which are well known to those skilled in the art.

Fig. 5 shows an enlarged simplified cross-sectional view of die 110 along cross-sectional line 5-5. The cross-sectional line 5-5 is formed by the transistor 101 and the resistor 102 shown in fig. 3 and 4. The description refers to fig. 4 and 5. Doped region 110 forms a first isolation region in which some of the elements of circuit 46 are formed, including logic 49, driver 50, and a portion of inverter circuits 47 and 48. Typically, a part of the circuits 47 and 48 including the capacitor 107, the resistors 106 and 102, and the transistor 103 is also formed in the region 111. The die 110 is formed on a semiconductor substrate 118. The doped region 111 is formed on a surface of the substrate 118 and has a conductivity type opposite to that of the substrate 118. A doped region 120 is formed on the surface of the substrate 118, spaced apart from the region 111, to form the transistor 101. The region 120 has a conductivity type opposite to the conductivity of the substrate 118. Resistor 102 is formed as doped region 102 within region 111. Region 102 is formed with a conductivity type opposite that of region 111. The doped region 120 is connected to the resistor 102 by a conductor, such as a metal, which also provides a connection to the node 105. An example of the use of doped regions such as region 111 to isolate portions of a circuit from other portions of the circuit is described in U.S. patent No. 6,097,075 issued to Antonin Rozsypal et al on 9/13 2005.

Fig. 6 shows an enlarged simplified cross-sectional view of die 110 along cross-sectional line 6-6. Cross-sectional line 6-6 is formed through region 211 and through doped region 212. Region 212 is used to help form capacitor 63 and diode 61. Region 212 is formed as a doped region on the surface of substrate 118 and within region 211. Region 212 has a conductivity type opposite to that of substrate 118 and is the same as region 211. Region 212 functions as the cathode of diode 61, and metal 162 formed on the surface of region 212 and electrically connected to region 212 forms the anode of diode 61. Note that region 212 is surrounded by region 211 and separated from region 211 by a distance or spacing. Doped region 165 formed within region 212 forms a first plate (plate) of capacitor 63. The capacitor dielectric is formed by an insulator covering a portion of region 165 and a conductor is formed on the insulator to form the second plate of capacitor 63. A first terminal of capacitor 63, represented as node 163, is commonly connected to the anode of diode 62 (see fig. 1) and the cathode of diode 61. A second terminal of capacitor 63 is connected to node 60.

Fig. 7 shows an enlarged simplified cross-sectional view of die 110 along cross-sectional line 7-7. The cross-sectional line 7-7 is formed by a current source 65. The doped region 220 is formed on a surface of the substrate 118 and has a conductivity type opposite to that of the substrate 118. An LDMOS transistor 166 that is part of current source 65 is formed within region 220.

Fig. 8 shows an enlarged simplified cross-sectional view of die 110 along cross-sectional line 8-8. Cross-section line 8-8 is formed by regions 111 and 211. Regions 111 and 211 are separated by a distance 210. Distance 210 acts as an isolation gap that advantageously allows for a voltage differential between the voltages of regions 111 and 211 without affecting the breakdown voltage of circuit 52.

In view of the foregoing, it is apparent that a new apparatus and method is disclosed. Included, among other features, is forming a charge pump circuit that charges a pump capacitor until a voltage across the capacitor reaches a certain value, and then transfers at least a portion of the charge to a boost capacitor of a power supply system. Charging the boost capacitor independently of the timing for switching transistors 28 and 29 facilitates charging the pump capacitor when transistors 28 and 29 are not operating, which allows the use of the pump capacitor to keep the boost capacitor charged.

While the subject matter of the present invention has been described with specific preferred embodiments, it is evident that many alternatives and variations will be apparent to those skilled in the semiconductor arts. Although controller 35 is shown as part of a step-down power supply system, controller 35 may be used in other power supply configurations. In addition, the subject matter of the present invention is described with respect to specific N-channel and P-channel transistors, although the method is directly applicable to bipolar transistors as well as other MOS, BiMOS, metal-semiconductor FETs (MESFETs), HFETs and other transistor structures. In addition, the word "connected" is used throughout for clarity of description, but means having the same meaning as the word "coupled". Accordingly, "connected" should be interpreted as including both direct and indirect connections.

Claims (10)

1. A charge pump circuit, comprising:

a first capacitor having a first terminal and a second terminal;

a first input arranged to be coupled to a common node between first and second power switches, the first and second power switches being coupled in a stacked configuration and the first input being arranged to be coupled to an inductor coupled to the common node, the first input being arranged to receive a first voltage from the common node;

a second input arranged to receive a second voltage from a second capacitor, wherein the second voltage is greater than the first voltage, the second capacitor having a first terminal for coupling to the first input and also having a second terminal for coupling to the second input;

a current source having a first terminal and a second terminal;

a first circuit arranged to charge the first capacitor from the first voltage and to provide a first current from the first input to the first capacitor and the current source in response to a voltage on the first capacitor having a value less than a third voltage, wherein the third voltage is less than the first voltage on the first input; and

a second circuit arranged to couple the first capacitor to the second voltage at the second input and to transfer charge from the first capacitor to the second capacitor in response to a voltage of the first capacitor being no less than the third voltage.

2. The charge pump circuit of claim 1 wherein the first circuit comprises a first diode having a cathode coupled to the second terminal of the first capacitor and an anode coupled to receive the first voltage.

3. The charge pump circuit of claim 2 wherein the second circuit comprises a second diode having a cathode and an anode, the cathode of the second diode coupled to receive the second voltage, the anode of the second diode coupled to the second terminal of the first capacitor.

4. The charge pump circuit of claim 3, wherein a first terminal of the current source is coupled to a first current carrying electrode of a first transistor and a second current carrying electrode of the first transistor is coupled to the first terminal of the first capacitor, the first transistor having a control electrode, and a second transistor having a first current carrying electrode coupled to the second current carrying electrode of the first transistor, a second current carrying electrode coupled to receive the first voltage, and a control electrode.

5. The charge pump circuit of claim 1, wherein the second capacitor is a boost capacitor of a power supply circuit, the boost capacitor to provide power to a high-side driver of the power supply circuit.

6. A method of forming a charge pump circuit, comprising:

configuring a first input of the charge pump circuit for coupling to a common node located between first and second power switches coupled in a stacked configuration, wherein the common node is configured for coupling to an inductance and a first capacitor;

coupling a first switch between a current source and a pump capacitor of the charge pump circuit;

configuring the charge pump circuit to activate the first switch and couple the pump capacitor to the first input to receive a first voltage and to provide a first current from the first input through the first switch to the current source to charge the pump capacitor to a second voltage in response to a voltage on the pump capacitor having a value less than the first voltage, wherein the second voltage is different than the first voltage at the first input; and

configuring the charge pump circuit to disable the first switch and transfer charge from the pump capacitor to a first capacitor through a second input of the charge pump circuit for a first period of time in response to a voltage of the pump capacitor being no less than the first voltage.

7. The method of claim 6, wherein configuring the charge pump circuit to charge the pump capacitor comprises configuring the charge pump circuit to operate at a variable supply voltage, wherein the first voltage is fixed when the supply voltage varies.

8. A method of forming a charge pump circuit, comprising:

configuring a first input of the charge pump circuit for coupling to a common node located between first and second power switches coupled in a stacked configuration, wherein the common node is configured for coupling to an inductance, the first input is configured for receiving a first voltage from the common node;

configuring the charge pump circuit to activate a first switch and couple a pump capacitor to the first input to receive the first voltage, and to provide a first current from the first input to a current source through the first switch to charge the pump capacitor during a charging time interval in response to a voltage of the pump capacitor being less than a second voltage, wherein the second voltage is different from the first voltage, and to terminate charging of the pump capacitor in response to the voltage of the pump capacitor being greater than the second voltage; and

configuring the charge pump circuit to disable the first switch and transfer charge from the pump capacitor to a second capacitor in response to the voltage of the pump capacitor being greater than the second voltage, wherein the transfer occurs for a first period of time and terminates upon expiration of the period of time.

9. The method of claim 8, further comprising forming the charge pump circuit and the pump capacitor on a semiconductor die as part of a power supply controller.

10. The method of claim 9, further comprising coupling the second capacitor to provide operating power to a high-side driver of the power supply controller, wherein the high-side driver is formed on the semiconductor die.