HK1119790A - Low-leakage current sources and active circuits - Google Patents

Description

Low-leakage current source and active circuit

Technical Field

The present invention relates generally to electronic circuits, and more particularly to current sources and active circuits.

Background

Current sources are widely used to supply current to various circuits such as amplifiers, buffers, oscillators, and the like. The current source may be used as a bias circuit to provide a bias current, as an active load to provide an output current, and so on. The current source is typically fabricated on an Integrated Circuit (IC), but may also be implemented with discrete circuit components.

As IC fabrication technology continues to improve, the size of transistors continues to shrink. Smaller transistor sizes enable more transistors, and thus more complex circuitry, to be fabricated on an IC die, or smaller dies to be used for a given circuit. Smaller transistors also support faster operating speeds and provide other benefits.

Complementary Metal Oxide Semiconductor (CMOS) technology is widely used for digital circuitsAnd many analog circuits. A major problem in CMOS scaling down transistor size is leakage current, which is the current through the transistor when it is off. Smaller transistor geometries result in higher electric fields (E-fields), which stress the transistor and cause oxide breakdown. To reduce the E-field, lower supply voltages are typically used for smaller geometry transistors. However, the lower supply voltage also increases the propagation delay of the transistor, which is not desirable for high speed circuits. To reduce delay and improve operating speed, the threshold voltage (V) of the transistor_t) Is lowered. The threshold voltage determines the voltage at which the transistor is turned on. However, lower threshold voltages and smaller transistor geometries result in higher leakage currents.

Leakage current is more of a problem as CMOS technology scales smaller. This is because the leakage current increases at a high rate with respect to the reduction in the size of the transistor. Leakage currents can affect the performance of certain circuits such as Phase Locked Loops (PLLs), oscillators, digital-to-analog converters (DACs), and the like.

Some common techniques for combating leakage current include the use of high threshold voltages (high V)_t) Transistors and/or larger transistor sizes (e.g., longer gate lengths). High V_tTransistors can affect circuit performance (e.g., slower speed) and typically require additional masking steps in the IC fabrication process. Larger sized transistors are less effective against leakage current because (1) the leakage current is relatively less dependent on the variation of the channel length and (2) there is a practical limit to how long the channel length can be extended. Therefore, these two schemes are not sufficient for some circuits.

Therefore, there is a need in the art for a current source with low leakage current and good performance.

Disclosure of Invention

Low-leakage current sources and active circuits suitable for use in various circuit blocks (e.g., amplifiers, buffers, oscillators, DACs, etc.) are described herein. An active circuit is any circuit having at least one transistor, and a current source is one type of active circuit. For low-leakage circuits, a transistor provides an output current when enabled in an ON state and exhibits low-leakage current when disabled in an OFF state. Since leakage current is a strong function of threshold voltage, low leakage current is achieved by manipulating the voltages on the gate and source of the transistor to increase the threshold voltage of the transistor and thereby reduce leakage current.

In one embodiment, a circuit includes first, second, and third transistors, which may be P-channel field effect transistors (P-FETs) or N-channel field effect transistors (N-FETs). The first transistor provides an output current when enabled and exhibits a low leakage current when disabled. A second transistor is coupled to the first transistor and enables or disables the first transistor. The third transistor is coupled in series with the first transistor and connects or isolates the first transistor to a predetermined voltage, which may be a positive supply voltage, a circuit ground (circuit ground), a negative supply voltage, a controlled voltage, or some other voltage. The circuit may further include a pass transistor (pass transistor) that provides a reference voltage to a source of the first transistor when the first transistor is disabled. In the ON state, the first transistor provides an output current, and the second and third transistors do not affect performance. In the OFF state, the second and third transistors are used to provide the appropriate voltage to the first transistor to place it in a low-leakage state.

The first, second, and third transistors may be used for a low-leakage current source within a current mirror. In this case, the current mirror further includes fourth and fifth transistors. The fourth transistor is diode connected and receives a reference current from a current source. The fifth transistor is coupled in series with the fourth transistor. The first and third transistors mirror the fourth and fifth transistors and the output current is related to the reference current. The low-leakage current source may be used as an active load (e.g., for an amplifier), a bias circuit to provide a bias current, etc. The first, second, and third transistors may also be used for an amplifier stage. In this case, the first transistor may operate as a gain transistor that provides a signal gain.

Aspects and embodiments of the invention are described in more detail below.

Drawings

The features and nature of the present invention will become more apparent from the detailed description set forth below when taken in conjunction with the drawings wherein like reference numerals identify correspondingly throughout.

Fig. 1 shows a conventional current mirror.

Fig. 2 shows an N-MOS low-leakage current mirror.

Fig. 3A and 3B show the low-leakage current mirror of fig. 2 in ON and OFF states, respectively.

Fig. 4 shows a P-MOS low-leakage current mirror.

Fig. 5 shows another N-MOS low-leakage current mirror.

Fig. 6 shows a single-stage amplifier using the low-leakage current source of fig. 2 and 4.

Fig. 7 and 8 show two single-stage amplifiers utilizing the low-leakage current source of fig. 5.

Fig. 9 shows a two-stage amplifier utilizing low-leakage circuits.

Fig. 10 shows a PLL with low-leakage circuitry.

DETAILED DESCRIPTIONS

The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments or designs.

Herein describedThe low-leakage current source and active circuit described above may be implemented using various techniques with adjustable transistor threshold voltages. Some example technologies include P-channel Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), N-channel MOSFETs, and the like. For simplicity, the following description is for a circuit implemented with FETs, and further assumes that (1) the bulk (bulk)/substrate/body of the integrated circuit is connected to a low voltage supply (V) which may be circuit ground_SS) (2) the body of the N-FET is connected to the low voltage power supply, and (3) the body of the P-FET is connected to the high voltage power supply (V)_DD). Also for simplicity, the low voltage power supply is circuit ground in the following description.

Fig. 1 shows a schematic diagram of a conventional N-MOS current mirror 100. Current mirror 100 includes N-FETs 112 and 122 and current source 114. N-FET112 is diode connected and has its source coupled to circuit ground, its gate coupled to its drain, and its drain coupled to current source 114. The current source 114 provides a reference current I_ref. N-FET 122 has its source coupled to circuit ground, its gate coupled to the gate of N-FET112, and its drain providing an output current I_out。

During normal operation, the gate-source voltage (V) of N-FET112_gs) Is set such that the current I from the current source 114_refThrough N-FET 112. Same V_gsA voltage is applied to N-FET 122 because the gates of N-FETs 112 and 122 are coupled together and their sources are also coupled together. If N-FET 122 is identical to N-FET112, then since V is for both N-FETs_gsThe voltages are the same so that N-FET 122 is forced to provide the same I_refThe current is applied. N-FET 122 is thus a current source that mirrors N-FET 112. N-FET 122 may also be designed to provide AND I_refThe output currents are current dependent (and not necessarily equal). I from N-FET 122_outThe current depends on I flowing through N-FET112_refCurrent and the ratio of the size of N-FET 122 (size) to the size of N-FET 112.

By collapsing (collapse) or turning off the current source 114Turning the current mirror 100 off. When this occurs, only leakage current flows through N-FETs 112 and 122, where the amount of leakage current is determined by, for example, the threshold voltage (V) of these N-FETs_t) Drain-source voltage (V)_ds) And a gate-source voltage (V)_gs) And the like. For some applications, the leakage current of N-FET 122 may be too high, especially as transistor dimensions shrink.

Fig. 2 shows a schematic diagram of one embodiment of an N-MOS low-leakage current mirror 200. Current mirror 200 includes N-channel N-FETs 210, 212, 220, 222, and 224 and current source 214. N-FETs 210 and 212 and current source 214 are coupled in series. N-FET 210 has its source coupled to circuit ground and its gate coupled to V_DDA supply voltage and its drain coupled to the source of N-FET 212. N-FET 212 is diode connected and has its gate and drain coupled together and to provide a reference current I_refAnd a current source 214.

N-FETs 220 and 222 are coupled in series and constitute a low-leakage current source. N-FET has its source coupled to circuit ground, its gate receiving an enable control signal (Enb), and its drain coupled to the source of N-FET 222. N-FET222 has its gate coupled to the gate of N-FET 212 and its drain providing an output current I_out. N-FET224 has its source coupled to the source of N-FET222 and its gate receiving a complementary enable control signalAnd has its drain coupled to the gates of N-FETs 212 and 222.

N-FETs 210, 212, 220, and 222 are coupled such that the current flowing through N-FETs 220 and 222 mirrors the current flowing through N-FETs 210 and 212. N-FETs 210 and 220 may be scaled in size relative to N-FETs 212 and 222. N-FET222 is provided with I_outAn output transistor for the current. N-FET220 functions as a switch that connects or isolates the source of N-FET222 to circuit ground. N-FET224 is a control transistor that enables or disables N-FET 222. Current mirror 200 operates as follows.

Fig. 3A shows low-leakage current mirror 200 in an ON state, which may also be referred to as an active state or some other name. In the ON state, the Enb signal is at logic high and the Enb signal is at logic low. N-FET 210 is always on, and V of N-FET 212_gsThe voltage is set such that I from current source 214_refCurrent flows through N-FET 212. N-FET220 is turned on by the logic high of the Enb signal, and the voltage on node Nz is from V of N-FET220_dsThe voltage determines, which is typically small for switches, e.g., a few millivolts (mV). N-FET224 throughThe logic low of the signal is turned off. Since the gates of N-FETs 212 and 222 are coupled together, the same gate voltage (V) is applied thereto_g). N-FET222 is turned on and provides I_outThe current is applied. The first one is_outThe current depends on (1) the I flowing through N-FETs 210 and 212_refCurrent and (2) the ratio of the size of N-FETs 220 and 222 to the size of N-FETs 210 and 212. In the ON state, current mirror 200 functions similar to conventional current mirror 100, albeit with less resistive degradation due to N-FETs 210 and 220.

Fig. 3B shows low-leakage current mirror 200 in an OFF state, which may also be referred to as a low-leakage state or some other name. In the OFF state, the Enb signal is at logic lowThe signal is at logic high. N-FET220 is turned off by the logic low of the Enb signal and isolates the source of N-FET222 from circuit ground. N-FET224 throughThe logic high of the signal is turned on, which results in V for N-FET224_dsThe voltage is zero or lower. Since the drain of N-FET224 is coupled to the gate of N-FET222 and the sources of the two N-FETs are coupledCoupled together so V of N-FET222_gsVoltage equal to V of N-FET224_dsA voltage. Due to zero or lower V_gsVoltage, so N-FET222 is turned off as long as the drain voltage of N-FET222 is sufficiently high.

Table 1 summarizes the logic values of the control signals corresponding to the ON and OFF states, the states of N-FETs 220, 222, and 224, the current through N-FET222, and the voltage at node Nz.

TABLE 1 Current mirror 200

In the OFF state, low leakage current of N-FET222 is achieved through a number of mechanisms. First, V of N-FET220 due to N-FET224 being on_gsThe voltage is 0 or a lower value. Next, the source voltage (V) of N-FET222_s) Is raised above circuit ground. This is accomplished by turning N-FET220 off and isolating the source of N-FET222, resulting in node Nz being a high impedance (high Z) node. The voltage on node Nz is then boosted higher by diode-connected N-FET 212 and N-FET224 that is switched on and approximately equal to V of N-FET 212 that is switched on_gsA voltage. ON V of N-FET 212_gsThe voltage is from_refCurrent and the size of N-FET 212. The source of N-FET224 the bulk voltage (V) if the bulk/substrate of the integrated circuit is tied to circuit ground_sb) The voltage on node Nz is further increased by raising it. Higher V_sbThe voltage is increased by the threshold voltage V of N-FET222_tThe threshold voltage V_tWhich subsequently reduces leakage current through N-FET 222.

Threshold voltage V_tIs V_sbVoltage and can be expressed as:

formula (1)

Where γ is a parameter that depends on the electrical characteristics of the transistor;

φ_fis the Fermi (Fermi) potential; and

V_t0is V_sbThreshold voltage at 0 volts.

If V_gsWith a voltage less than the ON voltage of the transistor, the leakage current increases with V_dsThe voltage increases linearly and is at V_thThe voltage decreases exponentially as it increases. V that can be turned off by turning N-FET222 off_gsVoltage, V as small as possible_dsVoltage, and as high a threshold voltage as possible to obtain a smaller leakage current. Drain current (I) of MOS transistor_d) To V_gsThe transfer function of the voltage is similar to that of the known diode. V for "knee" voltages less than a few hundred millivolts_gsVoltage, the drain current of the MOS transistor is small. Thus, a sufficiently small V may be applied to N-FET222_gsVoltage to achieve low leakage current. Leakage current is a strong function of threshold voltage. Thus, low leakage current may be achieved by manipulating the gate and source voltages of N-FET222 to increase the threshold voltage. In addition, the leakage current of N-FET220 flows through N-FET224, which presents a lower impedance path than N-FET 222. Thus low leakage current flow in OFF stateAnd N-FET 222.

The gate voltage of N-FET222 may be set to ensure the gate-drain voltage (V) of N-FET222 when N-FET222 is turned off_gd) A lower voltage that is not forward biased. This may be accomplished by reducing the I of current source 214 in the OFF state_refCurrent to subsequently lower V of N-FET 212_gsWhich in turn lowers the gate voltage of N-FET 222. For example, V of N-FET 212_gsThe voltage may be reduced to less than the diode voltage drop (e.g., to 200 to 300mV), which ensures that N-FET222 is not forward biased even when the voltage on the output node (Vout) drops to 0 mV. In which case again a different biasing scheme is required.

Evaluate to have comparable I_outExemplary designs of conventional current mirror 100 in fig. 1 and low-leakage current mirror 200 in fig. 2 for current and transistor size. The leakage current of N-FET 122 within current mirror 100 is up to 100 nanoamperes (nA). In contrast, the leakage current of N-FET222 within current mirror 200 is approximately 70 picoamps (pA). The low-leakage design shown in fig. 2 may significantly reduce the amount of leakage current (by a factor of more than 1000 for this exemplary design). Low leakage current is highly desirable for many low leakage applications as described below.

Fig. 4 shows a schematic diagram of one embodiment of a P-MOS low-leakage current mirror 400. Current mirror 400 includes P-FETs 410, 412, 420, 422, and 424 and a current source 414. P-FETs 410 and 412 and current source 414 are coupled in series. P-FET 410 has its source coupled to V_DDThe power supply has its gate coupled to circuit ground and its drain coupled to the source of P-FET 412. P-FET412 is diode connected and has its gate and drain coupled together and to provide a reference current I_refCurrent source 414.

P-FETs 420 and 422 are coupled in series and form a low-leakage current source. P-FET 420 has its source coupled to V_DDPower supply to make its grid receiveAnd has its drain coupled to the source of P-FET 422. P-FET422 has its gate coupled to the gate of P-FET412 and its drain providing output current I_out. P-FET 424 has its source coupled to the source of P-FET422, its gate receiving the Enb signal, and its drain coupled to the gates of P-FETs 412 and 422.

P-FETs 410, 412, 420, and 422 are coupled such that the current flowing through P-FETs 420 and 422 mirror the current flowing through P-FETs 410 and 412. P-FET422 is provided with I_outAn output transistor for the current. P-FET 420 serves to connect the source of P-FET422 to V_DDThe power supply or a switch isolated therefrom. P-FET 424 is a control transistor that enables or disables P-FET 422. The current mirror 400 operates as follows.

In the ON state, the Enb signal is at logic high andthe signal is at logic low. P-FET 410 is always on, and the V of P-FET412_gsThe voltage is set such that I from current source 414_refCurrent passes through P-FET 412. P-FET 420 throughThe logic low of the signal is turned on and P-FET 424 is turned off by the logic high of the Enb signal. P-FET422 is turned on and provides a signal dependent on I_refCurrent and I of the ratio of the size of P-FETs 420 and 422 to the size of P-FETs 410 and 412_outThe current is applied.

In the OFF state, P-FET 420 passesThe logic high of the signal is turned off and P-FET 424 is turned on by the logic low of the Enb signal. 0 value or Low V for P-FET 424_dsThe voltage turns P-FET422 off. By (1) turning P-FET 420 off to obtain a high impedance at node Nz and (2) by P-FETs 412 and 424The source voltage of P-FET422 is lowered to achieve low leakage current of P-FET 422. This results in a threshold voltage V of P-FET422_tIncreasing and thereby reducing leakage current through P-FET 422. In addition, the leakage current of P-FET 420 passes through P-FET 424, which presents a lower impedance path than P-FET 422. Low leakage current therefore flows through P-FET422 in the OFF state.

Fig. 5 shows a schematic diagram of another embodiment of an N-MOS low-leakage current mirror 500. Current mirror 500 includes N-FETs 510, 512, 520, 522, 524, and 526 and a current source 514. N-FETs 510 and 512 and current source 514 are coupled in series in the same manner as N-FETs 210 and 212 and current source 214, respectively, in FIG. 2. N-FETs 520 and 522 are also coupled in series and constitute a low-leakage current source. N-FET 524 has its source coupled to circuit ground and its gate receivingAnd has its drain coupled to the gates of N-FETs 512 and 522. N-FET 526 has its source coupled to the source of N-FET 522 and its gate receivingSignal and its drain coupled to a reference voltage V_ref. N-FET 510 is always on.

Transistors 510, 512, 520, and 522 are coupled such that the current flowing through N-FETs 520 and 522 mirror the current flowing through N-FETs 510 and 512. N-FET 522 is provided with I_outAn output transistor for the current. N-FET 520 functions as a switch to connect or isolate the source of N-FET 522 to or from circuit ground. N-FET 524 is a control transistor that enables or disables N-FET 522. N-FET 526 is a transistor that will turn V when enabled_refA pass transistor (pass transistor) voltage coupled to node Nz. The current mirror 500 operates as follows.

In the ON state, N-FET 520 is turned ON by a logic high ON the Enb signal, and N-FETs 524 and 526 are both turned ONA logic low on the signal turns off. N-FET 522 is turned on by the gate voltage of N-FET 512 and provides a voltage dependent on I_refCurrent and I of the ratio of the size of N-FETs 520 and 522 to the size of N-FETs 510 and 512_outThe current is applied.

In the OFF state, N-FETs are turned OFF by a logic low on the Enb signal, and both N-FETs 524 and 526 passA logic high on the signal turns on. 0 or low V of N-FET 524_dsThe voltage turns N-FET 522 off. By (1) turning N-FET 520 off to get high impedance at node Nz and (2) providing V to the source of N-FET 522 via N-FET 526_refVoltage to achieve low leakage current of N-FET 522. This increases the threshold voltage of Nn-FET 522, thereby reducing leakage current through N-FET 522. In addition, the leakage current of N-FET 520 flows through N-FET 526, which presents a lower impedance path than N-FET 522.

For current mirror 500, in the OFF state, V on the drain of N-FET 522 may be buffered, for example_outVoltage and use this buffered voltage as V which is then provided to the source of N-FET 522 via N-FET 526_refVoltage to achieve a V of 0V for N-FET 522_dsA voltage. If the feedback mechanism is not utilized and V_outVoltage is unknown, then V_refThe voltage can be set to V_DDAnd/2 or to the desired voltage on the drain of N-FET 522.

As indicated by the various embodiments described above, low leakage of an output transistor (e.g., N-FET222, 422, or 522) providing an output current may be achieved by (1) applying a low, 0, or reverse biased V_gsVoltage to turn off the output transistor and (2) keep the source of the output transistor away from the supply voltage (e.g., V)_DDOr V_SS) And approach to V_outVoltage is applied. The second portion may be formed by using a switching transistor (e.g., FET 220)420, or 520) to isolate the source of the output transistor and manipulate (e.g., with FETs 224, 424, or 526) the voltage on the source of the output transistor.

Fig. 6 shows a schematic diagram of one embodiment of a single-stage amplifier 600 utilizing the low-leakage current sources of fig. 2 and 4. Amplifier 600 includes differential pair 640, N-MOS load circuit 200, and P-MOS low-leakage current mirror 400. Differential pair 640 includes P-FETs 642 and 644 that have their sources coupled together and their gates receiving the non-inverting input signal (Vin +) and the inverting input signal (Vin-), respectively. The P-MOS low-leakage current mirrors are coupled as described above with respect to fig. 4. The drain of P-FET422 is coupled to the sources of P-FETs 642 and 644 and provides a bias current I for differential pair 640_bias。

N-MOS load circuit 200 is coupled as described above with respect to FIG. 2, although current source 214 is composed ofControlled by the signal. The drain of N-FET 212 is coupled to the drain of P-FET 642 and provides a load current I_load1. N-FET222 has its drain coupled to the drain of P-FET 644 and provides a load current I_load1. The load circuit 200 is an active load for the differential pair 640. In a steady state, where the same voltage is applied to the gates of P-FETs 642 and 644, I flows through FETs 642 and 212_load1Current equal to I flows through FETs 644 and 222_load2Current, and the bias current is equal to the sum of the two load currents (i.e., I_bias＝I_load1+I_load2). Amplifier 600 operates as follows.

In the ON state, a logic high ON the Enb signal turns N-FET220 ON and P-FET 424 OFFThe logic low on the signal turns P-FET 420 ON and N-FET224 OFF. Current source 400 is turned on and provides a bias current for differential pair 640. The load circuit 200 is also turned on (although the current source 214 is turned on)Off) and functions as an active load for differential pair 640. Differential pair 640 receives and amplifies differential input signals (Vin + and Vin-) and provides an output signal (V)_out)。

In the OFF state, a logic low on the Enb signal turns N-FET220 OFF and P-FET 424 ONThe logic low on the signal turns P-FET 420 off and N-FET224 on. P-FET422 goes from a value of 0 or low V with P-FET 424 turned on_gsThe voltage turns off and low leakage current flows through P-FET 422. Similarly, N-FET222 goes from a value of 0 or low V with N-FET224 turned on_gsThe voltage turns off and low leakage current flows through N-FET222 and thus through the output of amplifier 600. Current source 214 is turned on within load circuit 200 to provide a low impedance path for leakage current of N-FET220 and to raise the gate voltage of N-FET 222.

Fig. 7 shows a schematic diagram of another embodiment of a single-stage amplifier 700 utilizing the low-leakage current source of fig. 5. Amplifier 700 includes a differential pair 740, an N-MOS low-leakage current mirror 500, and a P-MOS load circuit 708. Differential pair 740 includes N-FETs 742 and 744 whose sources are coupled together and whose gates receive the Vin + and Vin-input signals, respectively. N-MOS low-leakage current mirror 500 is coupled as described above with respect to fig. 5. The drain of N-FET 522 is coupled to the sources of N-FETs 742 and 744 and provides a bias current I for differential pair 740_bias。

P-MOS load circuit 708 includes P-FETs 710, 712, 720, 722, 724, and 726 and a current source 714 that are coupled in a complementary manner to N-FETs 510, 512, 520, 522, 524, and 526 and current source 514 of current mirror 500, respectively. P-FET 712 provides a bias voltage V_biasIt may also be generated by other circuits. Load circuit 708 also includes P-FETs 730, 732, and 736 that are coupled in the same manner as P-FETs 720, 722, and 726, respectively. The drain of P-FET722 is coupled to the drain of N-FET 742 and provides a load currentI_load1. The drain of P-FET 732 is coupled to the drain of N-FET 744 and provides a load current I_load2. P-FETs 722 and 732 are biased in the triode region of operation and are the load for differential pair 740. The load circuit 708 is an active load for the differential pair 740. The amplifier 700 operates as follows.

In the ON state, a logic high ON the Enb signal turns N-FET 520 ON and P-FETs 724, 726, and 736 OFF, andthe logic low on the signal turns P-FETs 720 and 730 ON and N-FETs 524 and 526 OFF. Current source 500 is turned on and provides a bias current for differential pair 740. The load circuit 708 is also turned on and acts as an active load for the differential pair 740. Differential pair 740 receives and amplifies differential input signals (Vin + and Vin-) and provides differential output signals (Vout + and Vout-).

In the OFF state, a logic low on the Enb signal turns N-FET 520 OFF and turns P-FETs 724, 726, and 736 ON, anda logic high on the signal turns P-FETs 720 and 730 off and N-FETs 524 and 526 on. N-FET 522 is turned off from a value of 0 or a low gate voltage with N-FET 524 turned on. N-FET 526 provides a reference voltage V to the source of N-FET 522_ref2This increases the threshold voltage of N-FET 522 and causes low leakage current to flow through N-FET 522. Similarly, P-FETs 722 and 732 are turned off from the high gate voltage with P-FET 724 turned on. P-FETs 726 and 736 provide a reference voltage V to the sources of P-FETs 722 and 732, respectively_ref1This increases the threshold voltage of P-FETs 722 and 732 and causes low leakage current to flow through P-FETs 722 and 732 and thus through the output of amplifier 700.

Fig. 8 shows a schematic diagram of yet another embodiment of a single stage amplifier 800 utilizing a folded cascode topology.Amplifier 800 includes a differential pair 840, pass P-FETs 846a and 846b, P-MOS load circuit 808, and N-MOS load circuit 848. Differential pair 840 includes P-FETs 842 and 844 whose sources are coupled together and whose gates receive the Vin + and Vin-input signals, respectively. P-FET 838 has a coupling to V_DDSource of supply voltage, receiving bias voltage V_bias0And drains coupled to the sources of P-FETs 842 and 844. P-FET 838 provides bias current for differential pair 840 and may be replaced with a current mirror 400 as shown in FIG. 6. P-FETs 846a and 846b function as switches that, when turned on, couple the drains of P-FETs 842 and 844 to the drains of N-FETs 860 and 850, respectively.

Load circuit 808 includes P-FETs 820, 822, 824, 830, 832, and 836 that are coupled in a similar manner as P-FETs 720, 722, 724, 730, 732, and 736 in FIG. 7, respectively. Load circuit 808 further includes a P-FET 834 having its source coupled to V_DDThe supply voltage, its gate receives the Enb signal, and its drain is coupled to the gates of P-FETs 820 and 830. The load circuit 808 acts as an active load for the output stage of the amplifier 800.

Load circuit 848 includes N-FETs 850, 852, 854, 860, 862, 864, and 866 that are coupled in a manner complementary to P-FETs 820, 822, 824, 830, 832, 834, and 836, respectively, in load circuit 808. The gates of N-FETs 850 and 860 have a bias voltage V_bias1. The gates of N-FETs 852 and 862 have a bias voltage of V_bias1. Load circuit 848 provides bias current for the output stage of amplifier 800. Amplifier 800 operates as follows.

In the ON state, a logic high ON the Enb signal turns P-FETs 824, 834, and 836 OFFA logic low on the signal turns N-FETs 854, 864, and 866 off. Both load circuits 808 and 848 are turned on and provide an output current for amplifier 800. Load circuit 848 presents a low impedance to differential pair 840 and a high impedance to the amplifier output.

In the OFF state, a logic low on the Enb signal turns P-FETs 824, 834, and 836 on, anda logic high on the signal turns N-FETs 854, 864, and 866 conductive. P-FET 836 provides a reference voltage V to the source of P-FET832_ref1This results in low leakage current through P-FET 832. Similarly, N-FET866 provides a reference voltage V to the source of N-FET 862_retf2This results in low leakage current through N-FET 862.

Fig. 9 shows a schematic diagram of one embodiment of a dual-stage amplifier 900 utilizing low-leakage current sources and active circuitry. The amplifier 900 includes a first stage 902, an output stage 904, and a load circuit 906. The first stage 902 may be implemented with various designs, for example, using a differential pair 640 and a current mirror 200 as shown in fig. 6. Output stage 904 includes a common-source amplifier 938 and an active load implemented with a low-leakage current source 928.

Within load circuit 906, P-FETs 910 and 912 and current source 914 are coupled in series and are coupled in the same manner as P-FETs 410, 412 and current source 414, respectively, in FIG. 4. P-FETs 920 and 922 are coupled in series and form the load circuit for first stage 902. P-FETs 910, 912, 920 and 922 are also coupled such that the average current flowing through P-FETs 920 and 922 is related to the current flowing through P-FETs 910 and 912.

Load circuit 928 includes P-FETs 924, 930, and 932 coupled in the same manner as P-FETs 824, 830, and 832, respectively, in FIG. 8. The load circuit 928 is an active load of the output stage 904 and is also part of the load circuit 906.

Common-source amplifier 938 includes N-FETs 954, 960, 962, and 966 that are coupled in the same manner as N-FETs 854, 860, 862, and 866, respectively, of FIG. 8. The gate of N-FET 962 is an input to output stage 904 and is coupled to the output of first stage 902. The drain of N-FET 926 is the output of output stage 904 and is coupled to the drain of N-FET 932 within load circuit 928. Amplifier 900 operates as follows.

In the ON state, a logic high ON the Enb signal turns N-FET 960 ON and P-FET 924 OFFThe logic low on the signal turns P-FET 930 ON and N-FET 954 OFF. Load circuit 928 is turned on and provides bias current to common-source amplifier 938. Common-source amplifier 928 is also enabled, receives and amplifies the output signal (Vol) from first stage 902, and provides the output signal (Vout) to amplifier 900.

In the OFF state, a logic low on the Enb signal turns N-FET 960 OFF and P-FET 924 ONA logic high on the signal turns P-FET 930 off and N-FET 954 on. P-FET 932 goes from a value of 0 or low V with P-FET 934 turned on_gsThe voltage is turned off, the load circuit 928 is turned off, and low leakage current flows through the P-FET 924. Similarly, N-FET 962 goes from 0 or low V with N-FET 954 turned on_gsThe voltage goes off, common-source amplifier 938 is disabled, and low leakage current flows through N-FET 962. P-FET 932 and N-FET 962 present low leakage current to the output of amplifier 900.

For the embodiment shown in fig. 9, only the output stage 904 is disabled in the OFF state. By providing for the gate of P-FET920The signal may also deactivate the first stage 902 in the OFF state.

In general, the amplifier may include any number of stages. To obtain low-leakage current in the OFF state, the output stage of the amplifier may use a low-leakage current source for the bias circuit (e.g., as shown in fig. 6-8) and/or a low-leakage current source for the active load (e.g., as shown in fig. 6-9). The output stage may also use low-leakage active circuitry for the gain portion of the stage (e.g., as shown in fig. 9).

The low-leakage current sources and active circuits described herein may be used in various circuit blocks such as amplifiers (e.g., as shown in fig. 6-9), unity gain buffers, charge pumps, active loop filters, DACs, and other circuit blocks requiring low leakage. Low-leakage current sources and active circuits may also be used in various applications such as PLLs, Automatic Gain Control (AGC), time tracking loops, and the like. The use of low-leakage circuits for an exemplary PLL is described below.

Fig. 10 illustrates a PLL 1000 suitable for use in various end applications (e.g., wireless communications). A Voltage Controlled Oscillator (VCO)1050 generates an oscillator signal whose frequency is determined by a VCO control signal (e.g., voltage) from the loop filter 1040. Frequency divider 1060 divides the oscillator signal by a factor of N in frequency, where N ≧ 1, and provides a feedback signal.

Phase-frequency detector 1010 receives a reference signal and the feedback signal, compares the phases of the two signals, and provides a detector signal indicative of the detected phase difference or error between the two signals. For example, detector 1010 may provide Early and Late digital signals indicating whether the reference signal is Early or Late with respect to the feedback signal. Low-leakage charge pump 1020 receives the detector signal and generates a current signal that is determined by (and related to) the detected phase difference. Charge pump 1020 may utilize low-leakage current sources and/or low-leakage active circuits to provide low-leakage current when disabled.

Tuning/calibration circuitry 1030 may provide adjustment signals (e.g., voltages) to tune VCO 1050, calibrate VCO 1050, and so on. The adjustment signal is buffered by low-leakage buffer 1032 and provided to summer 1022. Adder 1022 adds the current signal from charge pump 1020 to the buffered signal from buffer 1032 and provides the added signal to loop filter 1040. Loop filter 1040 filters the signal from summer 1022 and provides the VCO control signal. Summer 1022 may also be placed after (rather than before) loop filter 1040, and the signal from buffer 1032 may be summed with the signal from loop filter 1040 to obtain the VCO control signal.

The VCO control signal controls the frequency of the oscillator signal. Any noise on the VCO control signal is converted to phase noise on the oscillator signal. Low-leakage circuits may be used in PLL 1000 to reduce noise and errors on the VCO control signal. During normal operation, loop filter 1040 may be active and regulation/calibration circuit 1030 and buffer 1032 may be disabled. Loop filter 1040 adjusts the VCO control signal to lock the phase of the feedback signal to the phase of the reference signal. Once the PLL is locked to the reference signal, the current signal from the charge pump 1020 typically only functions for a small portion of each clock cycle. The charge pump 1020 may be enabled during the time that the current signal is active and disabled at all other times. This results in low leakage current charging/discharging of the loop filter 1040 when the charge pump 1020 is disabled. During normal operation, buffer 1032 is disabled and presents low leakage current to summer 1022. Low leakage results in less noise since the leakage current interferes with the signal from the phase frequency detector 1010. During tuning/calibration, circuit 1030 is active and provides a conditioning signal, and low-leakage buffer 1032 provides a signal drive for the conditioning signal.

The low-leakage current sources and active circuits described herein may be implemented in various IC process technologies such as C-MOS, N-MOS, P-MOS, bipolar CMOS (Bi-CMOS), gallium arsenide (GaAs), and the like. CMOS technology can fabricate both N-FET and P-FET devices on the same die, while N-MOS and P-MOS technology can fabricate N-FETs and P-FETs, respectively. Low-leakage current sources and active circuits may also be fabricated using various device size technologies (e.g., 0.13mm, 90nm, 30nm, etc.). The low-leakage current sources and active circuits described herein may be more efficient and beneficial as IC process technology scales smaller (i.e., smaller "feature" or device length). Low-leakage current sources and active circuits may also be fabricated on various types of ICs, such as radio frequency ICs (rfics), digital ICs, mixed signal ICs, and the like.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (26)

1. An integrated circuit, comprising:

a first transistor to provide an output current when enabled and to exhibit a low leakage current when disabled;

a second transistor coupled to the first transistor and used to enable or disable the first transistor; and

a third transistor coupled in series with the first transistor and configured to isolate the first transistor from a predetermined voltage when the first transistor is disabled.

2. The integrated circuit of claim 1, further comprising:

a fourth transistor coupled in a diode configuration and configured to receive a reference current; and

a fifth transistor coupled in series with the fourth transistor, wherein the first, third, fourth, and fifth transistors are coupled as a current mirror, and the fourth and fifth transistors form a first path of the current mirror and the first and third transistors form a second path of the current mirror, and wherein the output current is related to the reference current.

3. The integrated circuit of claim 1, wherein the second transistor is coupled to a gate and a source of the first transistor and to provide a zero or low gate-to-source voltage to disable the first transistor.

4. The integrated circuit of claim 1, wherein the second transistor is further to manipulate a source voltage of the first transistor when the first transistor is disabled.

5. The integrated circuit of claim 1, wherein the second transistor is further to provide a low impedance path for leakage current of the third transistor when the third transistor is disabled.

6. The integrated circuit of claim 1, wherein the second transistor is coupled to a gate of the first transistor and to provide a gate voltage that can disable the first transistor.

7. The integrated circuit of claim 1, further comprising:

a fourth transistor coupled to the first transistor and to provide a reference voltage to a source of the first transistor when the first transistor is disabled.

8. The integrated circuit of claim 7, wherein the reference voltage is half of a supply voltage.

9. The integrated circuit of claim 7, wherein the reference voltage provides zero or a low drain-source voltage for the first transistor when the first transistor is disabled.

10. The integrated circuit of claim 1, wherein the first transistor is to provide signal gain.

11. The integrated circuit of claim 1, wherein the first, second, and third transistors are N-channel field effect transistors.

12. The integrated circuit of claim 1, wherein the first, second, and third transistors are P-channel field effect transistors.

13. The integrated circuit of claim 1, wherein the second transistor is enabled or disabled by a control signal and the third transistor is enabled or disabled by a complementary control signal.

14. A device, comprising:

a first transistor to provide an output current when enabled and to exhibit a low leakage current when disabled;

a second transistor coupled to the first transistor and used to enable or disable the first transistor; and

a third transistor coupled in series with the first transistor and configured to isolate the first transistor from a predetermined voltage when the first transistor is disabled.

15. The device of claim 14, further comprising:

a fourth transistor coupled in a diode configuration and configured to receive a reference current; and

a fifth transistor coupled in series with the fourth transistor, wherein the first, third, fourth, and fifth transistors are coupled as a current mirror, and the fourth and fifth transistors form a first path of the current mirror and the first and third transistors form a second path of the current mirror, and wherein the output current is related to the reference current.

16. The device of claim 14, further comprising:

a fourth transistor coupled to the first transistor and to provide a reference voltage to a source of the first transistor when the first transistor is disabled.

17. An integrated circuit, comprising:

a first transistor to provide an output current when enabled and to exhibit a low leakage current when disabled;

a second transistor coupled to the first transistor and used to enable or disable the first transistor; and

a third transistor coupled in series with the first transistor and configured to isolate the first transistor from a first predetermined voltage when the first transistor is disabled; and

a gain transistor coupled to the first transistor and configured to receive the output current from the first transistor, receive and amplify an input signal, and provide an output signal.

18. The integrated circuit of claim 17, wherein the first, second, and third transistors form a bias circuit for the gain transistor, and wherein the output current is a bias current for the gain transistor.

19. The integrated circuit of claim 17, wherein the first, second, and third transistors form an active load for the gain transistor, and wherein the output current is a load current for the gain transistor.

20. The integrated circuit of claim 19, further comprising:

a fourth transistor coupled to the gain transistor and to provide a bias current for the gain transistor when the fourth transistor is enabled and to present a low leakage current when disabled;

a fifth transistor coupled to the fourth transistor and to enable or disable the fourth transistor; and

a sixth transistor coupled in series with the fourth transistor and configured to isolate the fourth transistor from a second predetermined voltage when the fourth transistor is disabled.

21. The integrated circuit of claim 19, further comprising:

a fourth transistor coupled to the gain transistor and to enable or disable the gain transistor; and

a fifth transistor coupled in series with the gain transistor and to isolate the gain transistor from a second predetermined voltage when the gain transistor is disabled, and wherein the gain transistor exhibits low leakage current when disabled.

22. A device, comprising:

a first transistor to provide an output current when enabled and to exhibit a low leakage current when disabled;

a second transistor coupled to the first transistor and used to enable or disable the first transistor;

a third transistor coupled in series with the first transistor and configured to isolate the first transistor from a first predetermined voltage when the first transistor is disabled; and

a gain transistor coupled to the first transistor and configured to receive the output current from the first transistor, receive and amplify an input signal, and provide an output signal.

23. The device of claim 22, further comprising:

a fourth transistor coupled to the gain transistor and to provide a bias current for the gain transistor when the fourth transistor is enabled and to present a low leakage current when disabled;

a fifth transistor coupled to the fourth transistor and to enable or disable the fourth transistor; and

a sixth transistor coupled in series with the fourth transistor and configured to isolate the fourth transistor from a second predetermined voltage when the fourth transistor is disabled.

24. The device of claim 22, further comprising:

a fourth transistor coupled to the gain transistor and to enable or disable the gain transistor; and

a fifth transistor coupled in series with the gain transistor and to isolate the gain transistor from a second predetermined voltage when the gain transistor is disabled, and wherein the gain transistor exhibits low leakage current when disabled.

25. An integrated circuit, comprising:

a charge pump to provide a current signal when enabled and to present a low leakage current when disabled, the current signal being indicative of a phase error between a reference signal and a feedback signal; and

a loop filter to filter the current signal and provide a filtered signal.

26. The integrated circuit of claim 25, further comprising:

a buffer to receive and buffer the regulation signal when enabled and to present low leakage current when disabled; and

an adder coupled to the charge pump and the buffer and to receive and add outputs of the charge pump and the buffer and provide an added signal.