HK1119001B - Automatic format identification of analog video input signals - Google Patents

Description

Method and system for automatically identifying video signal format

Technical Field

The present invention relates to video signal processing, and more particularly to automatic format recognition of analog video input signals.

Background

Video images may be displayed in a variety of formats. Generally, successive still images (i.e., "frames") can be displayed, and the images can be displayed at different rates ("frame rates") according to different formats. Each frame typically includes a plurality of horizontal scan lines, each horizontal scan line including a plurality of pixels. The number of scan lines per frame and the number of pixels per scan line differ for different formats. A frame may be formed by displaying each scan line in sequence (i.e., "progressive scan") or may first display odd scan lines to produce a first field and then even scan lines to produce a second field (i.e., "interlaced scan"). Of course, the device that captures the video signal (for processing or display) should be configured for the particular format of the video signal that it receives as input. Knowing the frame frequency, scan line frequency, and sampling frequency is critical to (a) locking the input signal and (b) producing an image with the proper resolution for each frame.

Disclosure of Invention

One or more embodiments of a system and method for automatically recognizing the format of an analog input signal are described below in conjunction with the following figures.

According to one aspect of the present invention, there is provided a method of automatically recognizing a format of a video signal including a horizontal synchronization (HSync) pulse, a vertical synchronization (VSync) pulse, and video display data, the method including:

receiving a video signal;

extracting the time sequence and width characteristics of the HSync pulse and the VSync pulse from the video signal;

the format of the video signal is determined based on the extracted information.

Preferably, determining the format of the video data according to the extracted information includes:

comparing the extracted information with a plurality of pieces of characteristic information in different formats;

one format is selected based on the degree of correlation between the extracted information and the feature information of the selected format.

Preferably, the plurality of different formats of feature information includes information about a polarity of the HSync pulse, a polarity of the VSync pulse, a scan line length, a number of scan lines per field, and whether progressive or interlaced scanning is used for each of the different formats.

Preferably, the method further comprises normalizing the bias level of the received signal before extracting timing and width information of the HSync pulse and the VSync pulse from the video signal.

Preferably, the method further comprises normalizing the gain of the received signal before extracting timing and width information of the HSync pulse and the VSync pulse from the video signal.

Preferably, the video signal is selected from a standard definition ATSC (Advanced television systems Committee) video signal and a high definition ATSC video signal, the method further comprising determining from the extracted information whether a format of the signal corresponds to the standard definition signal or the ATSC signal.

Preferably, the method further comprises:

filtering the received signal by a low-pass filter;

the received signal is filtered by a matched filter.

Preferably, the method further comprises filtering the received signal through a matched filter, wherein the matched filter is matched with a predetermined HSync pulse width.

Preferably, the method further comprises configuring the video decoder to process the input signal and output the output signal to the display device in the determined format.

Preferably, the method further comprises:

filtering the received signal by a low-pass filter;

normalizing the bias level of the filtered signal;

normalizing a first gain of the bias level normalized signal;

extracting first information about the characteristics of the HSync pulse and the VSync pulse from the signal normalized by the first gain;

determining a hypothetical first format according to the extracted first information;

normalizing a second gain of the bias level normalized signal;

filtering the signal normalized by the second gain with a matched filter, wherein the matched filter is matched with the predetermined HSync pulse width;

extracting second information about features of the HSync pulses and the VSync pulses from the match-filtered signal;

determining a hypothetical second format from the extracted second information;

selecting either the hypothesized first format or the hypothesized second format as the format of the input signal according to a predetermined look-up table.

According to an aspect of the present invention, there is provided a system for automatically recognizing a format of a video signal including HSync pulses, VSync pulses, and video display data, the system including:

a first bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a second bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a matched filter for receiving the input signal adjusted by the second bias and compensation circuit and filtering the received signal according to the predetermined HSync pulse width in the received signal after tuning;

a synchronous pulse detection circuit for detecting the HSync pulse and the VSync pulse in the input signal adjusted by the first bias and compensation circuit, and detecting the HSync pulse and the VSync pulse in the filtered signal;

a metric extraction circuit for extracting information related to the timing and width characteristics of the detected HSync pulse and VSync pulse;

and a format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information with a predetermined characteristic of a known format.

Preferably, the system is located on a single chip.

Preferably, the system further comprises a low pass filter for filtering the input signal before adjusting the bias level and the gain level of the signal.

Preferably, the system further comprises:

a first sync pulse detection circuit for detecting HSync pulses and VSync pulses in the input signal adjusted by the first bias and compensation circuit, and a second sync pulse detection circuit for detecting HSync pulses and VSync pulses in the filtered signal;

a first metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the first sync pulse detection circuit, and a second metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the second sync pulse detection circuit;

a first format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the first sync pulse detection circuit with the known characteristics of the first format, and a second format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the second sync pulse detection circuit with the known characteristics of the second format.

Preferably, the known second format comprises a standard definition format.

Preferably, the system further comprises a format arbiter for arbitrating between the format recognized by the first format recognition circuit and the format recognized by the second format recognition circuit.

Preferably, the predetermined characteristics include information related to the polarity of the HSync pulses, the polarity of the VSync pulses, the scan line length, the number of scan lines per field, and whether progressive or interlaced scanning is used for different formats.

Preferably, the video signal is selected from a standard definition ATSC video signal and a high definition ATSC video signal, and the format identifying circuit further determines whether the format of the signal corresponds to the standard definition signal or the ATSC signal based on the extracted information.

According to an aspect of the present invention, there is provided a system for automatically recognizing a format of a video signal including HSync pulses, VSync pulses, and video display data, the system including:

a first bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a second bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a filter for receiving the input signal adjusted by the second bias and compensation circuit and filtering the received signal according to the predetermined HSync pulse width in the received signal after tuning;

a first sync pulse detection circuit for detecting HSync pulses and VSync pulses in the input signal adjusted by the first bias and compensation circuit, and a second sync pulse detection circuit for detecting HSync pulses and VSync pulses in the filtered signal;

a first metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the first sync pulse detection circuit, and a second metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the second sync pulse detection circuit;

a first format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the first sync pulse detection circuit with the known characteristics of the first format, and a second format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the second sync pulse detection circuit with the known characteristics of the second format.

Preferably, the first format recognition circuit recognizes a format of a high definition ATSC video signal and the second format recognition circuit recognizes a format of a standard definition ATSC video signal.

Drawings

Fig. 1 is a schematic diagram of a system for automatically recognizing a format of an analog video input signal and outputting the video signal in an output format to a display device according to the recognized input format;

FIG. 2 is a block diagram of a format recognition module for automatically recognizing an analog video input signal;

FIG. 3 is a schematic diagram of an input signal including synchronization pulses (shown as periodic polarity pulses in the input signal) having a certain amplitude and width;

FIG. 4 is a schematic diagram of a frequency response curve of an embodiment of a low pass filter for filtering an input signal;

FIG. 5 is a schematic diagram of a circuit for measuring the peak value (tip value) of an input signal while allowing the minimum to be reset without the occurrence of transient spikes;

FIG. 6 is a schematic diagram of two-stage cancellation (floating) of peaks of an input signal;

FIG. 7 is a schematic diagram of a DC restore module for restoring a DC value of an input signal;

FIG. 8 is a schematic diagram of measuring blanking level (blank level) and spike sync level (tip sync) by dividing the lower value range of the input signal into a plurality of segments (bins) and then noting the number of times the signal occurs in each segment;

FIG. 9 is a schematic diagram of a "general automatic gain control" circuit and an "adjust gain" circuit for clamping the blanking level to a predetermined range of values to match the desired performance by maintaining a segment count, identifying the number of value segments between the peak level and the blanking level, and adjusting the input to position the blanking level;

FIG. 10 is a schematic diagram of an input signal delayed by a delay block and then added to itself to produce a combined signal;

fig. 11 is a schematic diagram of an input signal passing through a matched filter.

FIG. 12 is a schematic diagram of a metric extraction circuit;

FIG. 13 is a schematic diagram of a circuit that compares a new metric value to a previous value;

FIG. 14 is a schematic diagram of a circuit that compares a metric to a previous value;

FIG. 15 is a timing diagram of how the number of multiple sawtooth pulses is maintained without a pair of HSyncs between pulses;

fig. 16 is a timing diagram of how the standard VSync pulses are distinguished from the VCR VSync pulses.

Detailed Description

The video display data may be carried by wireless electromagnetic signals or by analog video signals transmitted by wire (e.g., from a video tape recorder or from a processor of a personal computer), which will be converted to video images on a display device. The video signal also carries other information that tells the display hardware when the display of a frame ends, when the next frame starts, and when the display of a row of scan lines within a frame ends, and when the next scan line starts. This information may be given in the form of vertical synchronization ("VSync") pulses and horizontal synchronization pulses ("HSync") pulses. Different video format signals have different timing and width characteristics of the VSync and HSync pulses, so that accurate detection of the timing and width characteristics of the VSync and HSync pulses can be used to automatically determine the format of the video signal.

Fig. 1 is a block diagram of a system 100 that automatically recognizes the format of an analog video input signal 102 and outputs a video signal to a display device 104 according to the recognized input format. The input signal 102 is sent to a format recognition module 106, which may automatically recognize the format of the input and communicate the recognized format to the processor 108. The processor 108 configures a video decoder ("VDEC") 110 to process the input signal 102 and output an output signal 112 to the display device 104 in a format compatible with the display device 104. The output signal 112 is optionally processed by one or more additional video processors 114.

Table 1 (see below) shows 17 different advanced television systems committee ("ATSC") analog video formats and gives characteristic information for each format. The first column of the table lists the names of the formats. The second column of the table lists the frame rate of the video output, where the frame rate is measured in clock cycles per second (Hz). The format of progressive scanning using a 60Hz frame rate or interlaced scanning using 30Hz is generally applicable in the united states, and the format of progressive scanning using a 50Hz frame rate or interlaced scanning using 25Hz is applicable in europe. The third column lists the "pixel clock" value, i.e., the rate at which individual pixels are displayed, in MHz. The value of the pixel clock is equal to the product of the frame rate and the number of pixels per scan line (column in the fourth column) and the number of scan lines per field (column in the seventh column). The sixth column lists the scan line period, which is a measure of the time (in microseconds) required to display one scan line, and the ninth column, which is the "length of the scan line," which is the number of 108MHz clock cycles required to display one scan line. The fifth column lists the "sync time", which is a measure of the time occupied by the HSync pulses for each scan line (typically at the beginning or end of the scan line), given in terms of the number of pixel clocks (the third column). The eighth column lists the "sync width" (sync width), which is the "sync time" measured in constant units of measurement (108MHz clock periods). Because at least one pixel clock independent parameter can distinguish a particular format in table 1 from all other formats listed, measurements of the parameters given in table 1 can be used to uniquely identify the 17 different ATSC video formats presented in table 1.

TABLE 1

Table 2 (see below) shows 32 different analog video formats for displaying personal computer ("PC") video formats and provides similar information about each format as given in table 1. In addition, table 2 has two columns listing the polarities of the VSync and HSync pulses of the video signal. Different formats may be grouped based on the polarity of these Sync pulses. For example, the PC format in which both polarities of VSync and HSync pulses are negative belongs to the first group. The PC format in which the polarity of the VSync pulses is positive and the polarity of the HSync pulses is negative belongs to the second group. The PC format, in which both polarities of VSync and HSync pulses are positive, belongs to the third group. The PC format in which the polarity of the VSync pulses is negative and the polarity of the HSync pulses is positive belongs to the fourth group. The different values of the parameters listed in table 2 allow each PC format to be uniquely identified. In particular, the different formats listed in tables 1 and 2 may be identified according to whether they are ATSC format or PC format, the polarity of the HSync and VSync pulses (for PC format), the number of scan lines/fields, the length of the scan lines, whether the format is progressive or interlaced format, and the Sync width of the HSync used in the format.

TABLE 2

Fig. 2 is a schematic diagram of the format recognition module 106 for automatically recognizing the format of the analog video input signal. The module 106 is used to identify the video signal format from information extracted from the HSync and VSync signals of the input video signal when the system clock samples the signals. The video signal input to the module 106 may have a number of different formats. If the input signal is in the PC format, information on an image for display, information on HSync pulses, and information on VSync pulses are input on different scan lines. In this case, the information of the relevant HSync and VSync pulses is extracted relatively directly. The HSync signal 202 and the VSync signal 204 may be sent through a multiplexer 206 to a metric extraction module 208, which extracts relevant information about the HSync and VSync pulses to use to characterize the format of the input signal. After these metrics are extracted, they are input to a format identification module 210, where the format of the input is determined based on the extracted metrics.

However, the input signal may also be a composite synchronization (CSync) signal in which the video display data, HSync pulses, and VSync pulses are all embedded in a single signal (e.g., as is common in the ATSC format). Distinguishing between different sync types and their timing in the CSync signal is more difficult than with the specialized HSync and VSync signals associated with the PC format. The CSync signal (i.e., the signal containing the video display data, HSync pulses, and VSync pulses) can be used for both component (component) video signals, i.e., the signal containing the video display data for one color, and composite (composite) video signals, i.e., the signal containing information encoding the three-color spatial video display data. Thus, a composite synchronization signal (CSync) refers to a combination of HSync data, VSync data, and some video display data, but a CSync signal may be used with a component (i.e., one color) video signal or a composite (i.e., three colors) video signal. The format identification module 106 operates in a similar manner for the component signals and the composite signal.

To extract this information from a relatively high-noise CSync signal (e.g., a standard definition ("SD") signal), format identification module 106 may simulate the functionality of a VDEC front-end to identify and characterize HSync and VSync pulses embedded in the CSync. For example, module 106 may normalize the offset of the input signal with a DC reduction ("DCR") module 214, may normalize the gain of the signal with an automatic gain control ("AGC") module, and may lock onto the HSync component in the CSync signal by performing quasi-PLL locking on the signal with a matched filter. For a high noise CSync signal, the gain of the normalized signal may be normalized using SD-AGC module 216 before passing the signal to a matched filter. The normalized and filtered signal is then passed through a threshold detector 218 (also referred to as a slicer) to detect the HSync and VSync pulses. Once the Sync pulse is detected, metrics on the Sync pulse are extracted in the metric extraction module 220, and the format of the input signal may be determined in the format recognition module 210 according to the extracted metrics.

However, to extract relevant information from the relatively low noise CSync signal, after the offset of the signal is normalized in the DCR module, the normalized signal may be sent to the Gen-AGC module 222 to normalize its gain before passing it to the slicer 224, which identifies Sync pulses. Once a Sync pulse is detected, metrics relating to the Sync pulse are extracted in a metric extraction module 208, and the format of the input signal may be determined in a format identification module 210 based on the extracted metrics.

Since it is difficult to determine in advance whether the CSync signal is a high noise or low noise signal, and since the noise level of the signal may vary, the CSync signal is sent to both the high noise path including the SD-AGC block 216 and the low noise path including the Gen-AGC block 222, and identification of the format is made based on the analysis performed in each path. Finally, format arbiter 226 arbitrates between the formats identified by the two lanes. The format of the arbitration result is output to register 228 for use by video signal processing software.

To extract information about the HSync and VSync pulses that characterize the CSync input signal 212, the Sync pulses embedded in the input signal need to be identified. For example, as shown in FIG. 3, the input signal includes Sync pulses, which are shown as periodic negative polarity pulses in the input signal, having a certain amplitude and width. The amplitude of the Sync pulse is defined as the amplitude between the baseline blanking level and the maximum negative spike level. Between Sync pulses, the input signal contains video display data that is output to the display device 104. The amplitude and spike levels of Sync pulses within the input video signal may not be normalized and thus may be used to normalize the spike levels by DCR circuit 214 and the blanking levels by AGC circuits 216 and/or 222 before extracting HSync and VSync metrics from the signal. For example, in one implementation, when the analog input signal is sampled at a clock frequency of 108MHz and the amplitude of the signal is digitized to 256 levels, the spike level may be normalized to an amplitude of approximately 16 units and the blanking level may be normalized to a level of 240 units.

Referring to fig. 2, when the CSync signal is input to format identification module 106, the signal may be sent to a low pass filter ("LPF") 230, which may be used to clear the analog CSync input. The LPF 230 may be an infinite impulse response filter ("IIR") with fixed coefficients. The frequency response of one example of an LPF is plotted in fig. 4, where the x-axis is in units of 108MHz sampling rate and the attenuation of the y-axis is in units of decibels.

After passing through the LPF 230, the spike level of the CSync signal is measured in the spike measurement circuit 232, and the DCR circuit 214 is used to normalize the bias level of the CSync signal, as shown in the upper left part of fig. 2. As will be described in more detail below, DCR circuit 214 outputs an analog error signal, i.e., a "pull up/pull down" signal, which is fed back to the analog version of the input CSync signal 212 to drive the baseline of the input signal to a target value, while format identification module 106 identifies the format of the CSync signal. To extract information about the Sync pulse from the CSync signal 212, the format recognition module 106 aligns the input signal (i.e., sets the bias level) to make the spike level slightly above zero. However, referring to FIG. 1, after the format of the input signal is determined, when VDEC 110 decodes the signal, VDEC 110 aligns the input signal so that the blanking level is at a desired value, and thus the video display data that occurs between the Sync pulses has the greatest resolution, but this also results in the spike not being slightly above zero. Thus, the processor 108 may configure the system 100 such that the format recognition module 106 can control the DCR value of the input signal until the signal format is recognized, and once the format is recognized, control of the DCR value is handed over to the VDEC 110.

During format identification, format identification module 106 identifies a spike level, which can be done without knowing the input format, since the spike gives a local minimum of the signal. To mitigate the effects of noise when identifying spikes, the CSync signal may be passed through the LPF 230 as described above, the output of the filter may be passed through a 32 sample moving averager, and the locally measured minimum may be eliminated after a programmable delay (e.g., about 32k samples).

The peaked value of the input signal may be determined by comparing the local minimum of the signal with the output of the averager. The local minimum can be reset in a stable manner to capture any drift in the spike level of the signal. The resulting spike level may then be used to adjust the DCR value and may be subtracted from the incoming CSync signal 212. Whether VDEC 110 or format identification module 106 is controlling the DCR value, this subtraction will shift the signal around the determined peak value.

In one implementation, as shown in FIG. 5, the peaked value may be measured with a local minimum (local _ min)502 and a previous minimum (prev _ min)504 two-order floating point operation (flop) to reset the minimum without any transient peaks. The signal output from the local _ min floating-point operation 502 may track the minimum value of the input sample. After each programmable delay period has elapsed (e.g., after every 32k samples), the system may move the output of the local _ min floating-point operation 502 to the prev _ min floating-point operation 504, overwriting the value of local _ min with the value of the most recently sampled sample. This "removal" of spikes means that the spike is updated every n scan lines, where n depends on the format but is always greater than 1.

Thus, FIG. 6 illustrates the effect of two-step "cancellation" in a simplified example. In FIG. 6, the input signal is shown as a solid line, the output of the local _ min floating-point operation is shown as a dashed line, and the output of the prev _ min floating-point operation is shown as a dashed-dotted line. The chain double-dashed line indicates the minimum value output in response to the input and the spike (flush _ tip) elimination command. For the sake of clarity, the lines are vertically offset from each other. Specifically, the input signal (solid line) is shifted by 3 units in the vertical direction, and the value of the local _ min floating-point operation (broken line) is shifted by 2 units. The value of the prev _ min floating-point operation (dotted line) is offset by one unit.

The value of local _ min is set to the instantaneous value of the input signal every time a spike is eliminated, and then stabilizes again as the actual spike value of the input signal. The stability of the value of local _ min is suppressed by the minimum value (two-dot chain line) output because the minimum value output is always smaller than the value of local _ min and the value of prev _ min. The value of prev _ min gives a stable default value because it has stabilized. Note that in this case between the second and third flush tip arrows, the value of prev _ min shifts the spike value excessively. This can help to eliminate the effects of noise and also force the value of prev _ min to lag behind the overall upward trend of the spike. In either case, this effect continues until the next flush _ tip pulse. It should be noted that fig. 6 is a schematic diagram, and in practice, the flush tip may be distributed over more spikes than the few spikes shown in fig. 6.

The upper left DCR block of fig. 2 may receive the spike and generate pull up/pull down signals to normalize the bias of the input signal. FIG. 7 is a more detailed block diagram of a DCR module. As shown in fig. 7, the measured spike value 702 is received and compared to a reference value 704, the difference between the spike value and a spike reference value (tippref) is compared in a comparator 706, and an error signal 708 is output, which is adjusted in a tuner 710 and output to an IIR filter 712 (e.g., using the same control signal 714 used by the measured spike module in fig. 5) at each "spike elimination" cycle. IIR filter 712 smoothes the feedback signal to make the peaked value equal to the spike reference value. A pulse width modulator ("PWM") 716 may generate a pull-up pulse or a pull-down pulse as indicated by the error signal output by IIR filter 712, and the duration of the pull-up/pull-down pulse is defined by the amplitude of the signal output by IIR filter 712. The pull-up signal or pull-down signal is then output from DCR block 214 and fed back into the analog input of the CSync input signal to drive the bias of the input signal to a level such that the measured spike value is equal to the spike reference value.

The spike normalized signal is then passed to the Gen AGC module 222 and the SDAGC module 216 shown in fig. 2, where gain normalization is performed to ensure that the amplitude between the spike and blanking levels is normalized. As shown in fig. 8, the format identification module may measure the sync level by dividing the lower value range into a series of segments (bins) and then determining the number of times the signal occurs in each segment. The distribution of the segments may be used to identify spike and blanking levels. The AGC blocks 222 and 216 may be used to scale the signal to achieve a defined segment profile. FIG. 8 shows an example waveform superimposed over a segment distribution range. The right side is the distribution plot of the sampled samples falling into each segment.

Fig. 9 is a schematic diagram of the "Gen AGC" (generic AGC) module 222 and the "adjust gain" module 902, which are used to maintain a segment count and can be used to identify the number of segments between the peak level and the blanking level, as already described in fig. 8. The AGC block 222 is generally divided into three stages. The first stage 904 receives a current input signal 906 whose bias level has been adjusted to 16 units above zero by a bias level circuit 908, a multiplier 910, and a bias compensation circuit 912. The second stage 914 evaluates the segment in which the input signal 906 is located to determine the current blanking level and to calculate an error signal that is output to the third stage 902 for accumulation and clamping for scaling the input signal. The third stage 902 may receive the error signal and multiply it by the scaling adjustment signal in multiplier 916.

The "Gen AGC" block 222 and the "adjust gain" block 902 may obtain the appropriate gain to properly scale the input signal with the analog signal statistics by dividing the amplitude OF the CSync signal into a number OF discrete segments, the number OF segments being NUM OF SBINS (e.g., 12 for use). Each segment (e.g., "bin _ acc [ j ]") may accumulate input CSync amplitude levels between certain minimum and maximum levels, where the value of the maximum level minus the minimum level is predefined by a parameter, i.e., "SBIN _ WIDTH" (e.g., nominally taken at 32 units). The algorithm for accumulating the amplitude levels of the CSync signal can be described in the following pseudo-code:

PRE-DEFINED_WINDOW ＝(nominally)32678(32K)

PRE-DEFINED_THRESHOLD＝(nominally)32678(32K)

DELTA_AGC ＝(nominally)0.002(～2^-9)

BLANK_THRESHOLD ＝(nominally)2000 (2K)

for (j＝0；j＜NUM_OF_SBINS；j++)

{// distributing the filtered input into the appropriate segments

if(j＜NUM_OF_SBINS-1)

{

if((state_mc_input＞＝tip_out+(j＊SBIN_WIDTH))&&

(state_mc_input＜tip_out+

((j+1)＊SBIN_WIDTH)))++bin_acc[j]；

}

else// last segment accumulates all values over 1023-SBIN _ WIDTH

{

if(state_mc_input＞＝1023-SBIN_WIDTH)

++bin_acc[NUM_OF_SBINS-1]；

}

}

// Next step

Then, the minimum segment index (i.e., the first non-zero index, first _ nzero _ index) containing the non-zero value and the segment index (i.e., the maximum value index, max _ index) containing the maximum value can be obtained. Thereafter, the segment index (i.e., blanking index blank _ index) containing the blanking level can be obtained according to the following pseudo code instructions:

to obtain the index corresponding to the blanking level

for(j＝1；((j＜NUM_OF_SBINS)&&((bin_acc_out[j]＜

BLANK_THRESHOLD)||(bin_acc_out[j]＜

0.5＊bin_acc_out[first_nzero_index])))；j++)；

blank_index＝j+1；

These segments may be normalized, if desired, according to the instructions in the following pseudo-code:

if(bin_acc[max_index]＞＝PRE_DEFINED_THRESHOLD)

{

for(j＝0；j＜NUM_OF_SBINS；j++)

{// halving the segment accumulator

bin_acc[j]＝bin_acc[j]/2；

}

}

If the end of the accumulator window is reached, the current value of each segment may be buffered.

With this adjustment method, a suitable spike with 16 unit level values can be defined, and a suitable blanking level with 240 unit level values can be defined. Thus, all spikes may accumulate to bin _ acc [0] and all blanking levels to bin _ acc [7], assuming SBIN _ WIDTH is 32. This condition results in a simple method to determine the value of "agc _ gain", as represented in the following pseudo code:

if(sample_count％PRE-DEFINED_WINDOW＝＝0)

{// Next, update section accumulator output buffer

for(j＝0；j＜NUM_OF_SBINS；j++)

{

bin_acc_out[j]＝bin_acc[j]；

}

// finally, calculate the AGC scaling ratio

if(bin_acc_out[NUM_OF_SBINS-1]＜

(bin_acc_out[0]+bin_acc_out[1]+

bin_acc_out[2]))

agc_gain＝agc_gain+DELTA_AGC＊(7.0-(blank_index-

first_nzero_index))；

else

agc_gain＝agc_gain-DELTA_AGC；

}

Thus, at "steady state," the value of the first non-zero index of the accumulated spike level should be 0, and the value of the blanking index of the accumulated blanking level should be 7. With the concept of segmentation, these techniques can be extended to calculate a coarse DCR value to use to set the offset of the signal, as described above. The DCR value may be accumulated in a register called DCR _ offset by setting DCR _ offset DCR _ offset + (average (tip) -16) × DELTA _ DCR, where DELTA _ DCR is nominally selected to be 0.0004 (i.e., about 1.6 × 2)^-12)。

A local AGC loop may be used to adjust the amplitude of the sampled CSync signal, which is then analyzed for identifying the format of the signal. To establish this loop, a histogram of incoming CSync sample samples is computed, with all incoming signal samples sorted into predefined stages (i.e., segments). Next, the desired AGC condition is one in which the peak value is near zero (e.g., about 16 units) and the blanking level is near a maximum value (e.g., 240 units when the maximum signal level is 256 units). For example, if the incoming samples are divided into 12 segments (bin _ acc [0] to bin _ acc [11]), and each segment is 32 units wide, then all spikes can be accumulated among bin _ acc [0], which accumulates all samples with levels between [0, 31 ]. Similarly, all blanking levels may be accumulated into bin _ acc [7], which accumulates all samples between [224, 255 ]. Then, the segment containing the peaked value is identified as the first segment containing non-zero content, and its index value may be set to the first non-zero index (first _ nzero _ index) variable. Finally in steady state, the first non-zero index is equal to 0 due to the adjustment of the DCR module.

The segments containing blanking levels can then be identified according to the following rules:

if (bin _ acc [ j ] > BLANK _ THRESHOLD

And is

If (bin _ acc [ j ] >)

0.5＊bin_acc[first_nzero_index])，

Then, the index value corresponding to the segment "j" is set to blank _ index

Finally, at steady state, the value of BLANK _ index will equal the value of the BLANK _ LEVEL variable.

The variable BLANK THRESHOLD defines the minimum number of samples of the input signal corresponding to the blanking level. In the case of national television systems committee ("NTSC") format signals, this value cannot be less than the combined length of the "leading edge" (front porch) and the "trailing edge" (back porch) of each scan line. The "leading" portion of the signal for one scan line is a short period (e.g., about 1.5 microseconds) inserted between the end of each scan line of video data and the beginning edge of the next HSync pulse. Its purpose is to stabilize the voltage level in older television sets, preventing interference between picture scanning lines. The "trailing edge" of a scan line refers to the portion of each scan line between the end (rising edge) of the HSync pulse and the beginning of the valid video data. The back porch was originally designed to enable the slow electronics in early televisions to respond to the synchronization pulse and prepare the active scan line cycle. Thus, in the case of an NTSC signal, BLANK _ THRESHOLD is equal to a value of approximately 6.5 microseconds, or approximately 702 samples of a 108MHz sampling clock multiplied by the number of scan lines over which accumulation occurs (as defined by the ACC _ WINDOW setting).

Using these two identified segments, the AGC loop can be controlled as follows: AGC _ gain + DELTA AGC (BLANK _ LEVEL- (BLANK _ index-first _ nzero _ index)), where DELTA AGC is a predefined scalar loop gain. To ensure that no segments overflow, the normalization process may be performed periodically on each segment.

The registers controlling the AGC function may be defined as described in the fields of table 3 below.

Name of field	Field description	Field assignment
			NUM_OF_BINS[3:0]	Number of levels or "segments" into which sampled ATSC signals are statistically divided	The recommended value is 12
SBIN_WIDTH[5:0]	Defining the width of each segment	The recommended value is 32. Thus, if the ATSC input sample is at [0, 31]]In between, belong to segment 0, if at [32, 63 ]]In between segment 1, and so on.
			ACC_WINDOW[6:0]	Defining the size of a window over which to normalize continuously monitored segment statistics	The recommended value is 32678 (32K). The window size is calculated using the following equation: ACC _ WINDOW 1024
BLANK_THRESHOLD[12:0]	Defining a threshold for identifying segments containing blanking levels	Recommended value is 2000
			AGC_GAIN[3:0]	The gain of the AGC loop is controlled. Actual GAIN AGC _ GAIN 2	The recommended value is 4 (note: a value of 0 would render the AGC loop inoperable)
BLANK_LEVEL[3:0]	Defining target segment indices corresponding to blanking levels	The recommended value is 7

TABLE 3

Although the general AGC algorithms and techniques described above with reference to fig. 8 and 9 are adequate for clean and low noise signals, they can produce false positives due to signals having too much noise or distortion as well as standard definition ("SD") signals (e.g., formats 576i, 288i, 480i, and 240i listed in table 1).

Thus, in addition to passing to Gen AGC module 222 in fig. 2, the spike normalized CSync signal is also sent to the inclusion SD specific AGC module 232 shown in fig. 2, which includes SD AGC module 216 and matched filter module 234. The SD specific AGC block 232 may be used to condition the high noise input CSync signal before analyzing the signal to extract parameters that identify the signal format.

The SD specific AGC block 232 assumes that the CSync input has an HSync width associated with the SD signal. For example, as shown in table 1, each SD format, but not the other, has an HSync width of 504 clock cycles. If this assumption is false, the signal should be processed by the normal AGC path through the Gen AGC module 222. However, if the assumption is correct, a more accurate pedestal level measurement and adjustment may be achieved using the SD specific AGC module 232 because the matched filter may lock onto the information within the HSync pulses and reject signals between the HSync pulses.

As shown in fig. 10, the SD AGC block 216 may overlap the HSync spike with the blanking level by delaying the signal and adding it to itself, using known constraints on the HSync width and retrace interval (fly back region). In fig. 10, an input signal 1002 may be delayed with a delay module to produce a delayed signal 1004, and the delayed signal 1004 is added to the input signal 1002 in a summing circuit 1006 to produce a combined signal 1008. When the peak value of the delayed signal 1004 overlaps the blanking level of the undelayed input signal 1002, the resulting combined signal waveform 1008 exhibits a minimum value and is output from the register 1010. Because the peak value may be determined by the "measurement spike" module 236 of fig. 2, the blanking level value may be derived by simply subtracting the known peak value from the minimum value of the combined signal 1008 and then comparing it to an expected reference blanking level value, as described in more detail above in connection with fig. 5-7. The gain may then be adjusted to normalize the blanking level to be equal to the expected reference blanking level.

The frequency response of the matched filter shown in fig. 2 may be defined based on the assumption of an "ideal" HSync grating for NTSC signals, interlaced scan line ("PAL") signals, and sequential color and storage ("SECAM") signals, where the HSync pulse width is 512 samples (sample rate provided in a 108MHz clock). As shown in fig. 11, when the portion of the scan line corresponding to the HSync pulse is multiplied by 1 and the portion of the scan line other than-HSync is multiplied by 0, the output of the matched filter is reduced to a running average of 512 samples. Thus, after passing through the matched filter, the Sync pulse can be easily identified from the CSync signal.

Thus, as explained above, the incoming CSync signal can be considered to fall into one of two categories: a high-noise or low-noise SD signal (e.g., as defined by formats 240p, 480i, 288p, or 576i listed in table 1); or a low noise ATSC signal (e.g., defined by the 240p, 480i, 288p, or 576i formats listed in table 1), which may be an SD or HD signal. Two isoroads for handling each of these cases are given in fig. 2: including the Gen AGC block 222 and simple limiter 224 for the path of low noise signals and the SD AGC block 222, matched filter 234 and limiter 218 for the path of high noise signals.

Once the low noise condition is filtered and biased (using the DCR module 214 and Gen AGC module 222), a programmable slicer level may be used to identify synchronization spikes within the CSync signal. The analysis of high noise signals uses the fact that: all available formats have similar or identical timing for the synchronization width. Therefore, a fixed matched filter of fixed sampling rate matched to this HSync width can be used to identify the synchronization region.

Limiters 218 and 224 in fig. 2 may be used to detect synchronization pulses from the normalized and filtered signal in the low noise and high noise paths. Slicers are used as threshold detectors that receive the input signal and output a positive signal when the input level is below a predetermined threshold, otherwise the output level is set to 0. The slicer shown in fig. 2 does not distinguish between HSync pulses and VSync pulses. However, this analysis may be performed by the metric extraction modules 208 and 230 shown in FIG. 2.

Metrics that may be determined from the HSync and VSync pulses embedded within the CSync signal and that may be used to uniquely identify a format in format identification module 240 or 242 include: polarity of HSync and VSync (for PC input), width of HSync, length of scan line, number of scan lines/fields, whether a field is progressive or interlaced. In calculating each metric, a hit (coincidence) counter may be used, which is incremented if the measured metric coincides with a previous measurement of the same metric. Once the hit counter exceeds the VALID _ THRESHOLD value, the metric is considered locked. If the hit counter changes and falls below the INVALID _ THRESHOLD value, each metric is considered unlocked. Therefore, a hysteresis is provided in the metric extraction module to maintain the locked state of the metrics to ensure that the locked state is not established prematurely.

The metric extraction modules 208 and 220 may identify a plurality of characteristic metrics about the input signal. For example, the polarity of the HSync pulses and the VSync pulses may be monitored for HSync and VSync scan line activity. The sync spike polarity may be defined as a polarity that is less than 45% of the time used during the display frame. Other metrics (i.e., width of HSync, scan line length, number of scan lines/fields, whether fields are progressive or interlaced) can be derived by monitoring HSync and VSync pulses directly from the digital H and V channels 202 and 204 (i.e., for the PC format signals shown in table 2) or from the output of one sync detection (slicer) sub-module 224 or 218. The determination of HSync width and line length may be given directly by the digital HSync or slicer output. The scan line length may be determined by measuring the distance between two rising edges, and the HSync width may be determined by measuring the distance between a rising edge and a falling edge. The ATSC input signal from slicer 224 may distinguish between VSync pulses and HSync pulses due to an increase in the "sync width" of the VSync pulses. The VSync pulse may be a series of pulses (e.g., more than 4 pulses), each of which is longer than several times (e.g., 4 times) the width of the established HSync pulse. Alternatively, the VSync pulses may be identified as a single synchronization pulse that is longer than the scan line being established. These extended sync pulses are not confused with changes in sync polarity because the ATSC CSync signal has a fixed polarity. The number of scan lines per field is calculated by dividing the number of samples between two VSync (field length) by the established scan line length. Whether the display is progressive or interlaced may be determined by counting the number of samples between the first VSync and the first HSync for each field. If the number is stable, the picture is progressive, but if the number changes, the picture is interlaced.

Fig. 12 is a schematic structural diagram of the metric extraction module. Along the left side of fig. 12, from top to bottom, are a counter 1202(H count) for counting the time between two HSync edges and a counter 1204(V count) for counting the time between two VSync edges. When edge detector 1206 or 1208 detects each edge that occurs corresponding to an HSync and VSync pulse, the previous values in scan line length measurement module 1210, HSync width measurement module 1212, frame length measurement module 1214, or VSync width measurement module 1216 are compared with an appropriate value to determine the consistency of the measured values and whether the values are "locked in". A more detailed explanation will be given below in conjunction with fig. 13. The remaining components in fig. 12 are used to process VSync identification (for ATSC input), progressive/interlaced determination, and final metric computation.

As shown in fig. 12, all counts can be measured in terms of sample counts. The field length tolerance can be in units of n scan line lengths (llng). For an ATSC input signal, the VSync input may be ignored because the VSync signal is embedded within the CSync signal assigned to the HSync input port. Because the HSync and VSync polarities are known to the ATSC, these ports are negligible to the ATSC input. The VSync width may be used to measure the VSync polarity, but it is not used for the ATSC input. The output metric may be calculated as follows: the number of scan lines per frame is obtained by dividing flng by llng, i.e., lines _ per _ f ═ flng/llng. The HSync polarity may be determined by comparing hwith with half the length of the scan line (HSync _ polarity ═ hwith < llng/2), and the VSync polarity may be determined by comparing vwidth with half the frame length (VSync _ polarity ═ vwidth < flng/2). The tolerances for the various metrics derived from fig. 12 are shown in table 4 below.

Name of field	Field description	Setting fields
			LLENGTH_TOLERANCE[3:0]	Defining allowable tolerance of average LLNG measurement values in a sample	The effective range of the measured LLNG is defined as: { LLNG-LLENGTH _ LLERANCE, LLNG + LLENGTH _ LLERANCE }
HWIDTH_TOLERANCE[3:0]	Defining allowable tolerance of average HWIDTH measurements in samples	The effective range of hwidtth measured is defined as: { HWIDTH-HWIDTH _ TOLERANCE, HWIDTH + WIDTH _ TOLERANCE }
			FLENGTH_TOLERANCE[3:0]	Defining allowable tolerance in LLNG of average FLNG measurement in samples	The effective range of measured FLNG is defined as: { FLNG-FLENGTH _ TOLERANCE } LLNG, FLNG + FLENGTH _ TOLERANCE }
VWIDTH_TOLERANCE[3:0]	Defining allowable tolerance of average LLNG measurement values in a sample	The effective range of VWIDTH measured is defined as: { VWIDTH-VWIDTH _ TOLERANCE, VWIDTH + VWIDTH _ TOLERANCE }

TABLE 4 (measurement tolerance)

Fig. 13 illustrates how the new metric value is compared to the previous value for the F _ length or VSync _ width (e.g., identified as the "X" metric in fig. 13) parameter. Note that floating point operations use the "load" signal to simplify the figure. Sub-module 1302 in FIG. 13 receives two inputs: a metric input 1304 that provides a new value; an edge input 1306 which triggers the calculation of a new value. The system may operate in an "unlocked" mode and a "locked" mode. In these modes, the new value may be compared to the previous value or the average of n values previously determined to be a "match", respectively, where n may be selected to be 8, 4 or 2. The average may be calculated by averaging module 1308. A match is said to exist when the new value is within the tolerance of the old reference value. The "hit" counter 1309 is incremented on each match and decremented on each mismatch. The third input, "overflow" 1310 may be used to decrement the hit count. This feature is only used by the F _ length metric to ensure that constant inputs eventually do not lock on F _ length. The lock status may be defined by the value of the hit counter as controlled by the register settings as listed in table 5 below. Sub-module 1312 shown in fig. 13 reports whether the metric is locked and another module 1314 reports the occurrence of a match.

Fig. 14 shows a slightly different module for comparing the metric with the previous L _ length and HSync _ width parameter values. This figure is similar to fig. 13 except as described below. First, there is no overflow logic in FIG. 14. Second, the hit counter 1402 is not updated on an edge. Instead, the result of the "match" test is triggered on an edge. Thereafter, when the "beat counter" 1220 (shown in FIG. 12) overflows, the state of the match counter 1404 may be used to increment (set match) or decrement (clear match) the hit counter.

Name of field	Field description	Field assignment
			METRIC_HIT_MAX[6:0]	Defining the saturation value of a metric hit counter	The recommended value is 127
AVERAGE_SIZE[1:0]	Defining the number of elements of the shift register for averaging 0-two elements 1-four elements 2-eight elements 3-sixteen elements	The recommended value is 3
			VALID_THRESHOLD[6:0]	An "on" hysteresis threshold is defined. When the metric hit counter reaches this value, the previously computed metric data is saved.	The recommended value is 16
INVALID_THRESHOLD[6:0]	A "turn off" hysteresis threshold is defined. When the metric collision counter reaches this value, the previously calculated metric data is allowed to be updated.	The recommended value is 0

TABLE 5

Referring to fig. 14, to analyze VSync pulses, we note that there are two types of ATSC VSyncs. A standard VSync may have a series of NUM _ SERR consecutive sawtooth pulses, where the sawtooth is defined by the value HSync width > SERR avg HSync width (hwidth), where numserr is a programmable integer value (see bottom of fig. 14). The VCR VSync has an HSyncwidth NUM LINE length (ling) that can be calculated by comparing the HCount value and by determining that the HSync input is still low, where NUM LINE is a programmable integer value (see top of fig. 14).

By "consecutive sawtooth pulses" is meant counting the number of sawtooth pulses without a pair of HSyncs in between. This is necessary for a three-layer format that puts the HSyncs between the sawtooth pulses. Fig. 15 depicts how this count is maintained with HSync and sawtooth accumulators. For each sawtooth pulse, the HSync accumulator may be cleared and the sawtooth accumulator may be incremented. Based on each "matching HSync", the HSync accumulator is incremented. If the value of the HSync accumulator reaches 2, the value of the sawtooth accumulator may be cleared. If the sawtooth accumulator is allowed to accumulate to a particular NUM _ SERR value, a Std VSync signal may be generated.

An additional state machine may be introduced to select between VCR VSync pulses and standard VSync pulses so that once a CR VSync pulse is encountered, the standard VSync pulses are ignored as they may incur a noise burst. The VSync pulses should continue to be received until 3 standard field lengths have passed without the VCR VSync pulses occurring. In this regard, it may be restored with a standard VSync pulse. Fig. 16 depicts the desired waveform in this case. As shown in fig. 16, once a VCR VSync pulse is detected, the system may assert that VCR-only mode is enabled because it resets the Vcount signal to zero. The Vcount pulse may be reset to zero each time an additional VCR VSync pulse occurs. The Vcount signal counts the samples between VCR VSyncs and when Vcount exceeds a predetermined number (e.g., 6480000(0x62e080)), the VCR unique mode is deactivated, allowing a standard VSync pulse to set the ATSC VSync.

The type of grating in the input signal may be identified by monitoring the time between the detection of the VSync pulse and the first detection of the HSync pulse. This time may be determined by taking the value of the Vcount signal on the rising edge of the first HSync pulse after the VSync pulse. The difference between this measurement and the previous measurement is calculated and if the difference is within +/-1/4 scan lines, the raster type is considered to be row-by-row. While this measurement method may incorrectly identify the raster type during a dummy stream (trib stream), accurate identification of the raster type of the ATSC input may be deferred to VDEC because it has a more sophisticated field identification system.

The final metric may be reported using register assignments similar to those shown in table 6 below. This register may be double buffered and may be read by software at any time and may be updated each time a VSync pulse is detected.

Name of field	Field description	Field assignment
			HSYNC_POLARITY	The polarity of the incoming HSync signal is defined. The positive polarity corresponds to a high level signal shorter than the "low level".	0-positive 1-negative
VSYNC_POLARITY	The polarity of the input vsync signal is defined. The positive polarity corresponds to a high level signal shorter than the "low level".	0-positive 1-negative
			LINES_PER_FIELD[14:0]	Defining the number of scan lines per field as the quotient of the length of the field divided by the average scan line length measured in the preceding field	The number 11.4 represents the precision of a binary number of 4 decimal digits. The interlaced format should have 4b '1000 or similar fractional bits and the progressive format should have 4 b' 0000 or similar fractional bits. Note that: the 1250i/50 format is an exception.
LINE_LENGTH[9:0]	Average scan line length measured in top field	The 13-bit number represents the average scan line length measured over multiple system clock cycles
			HSYNC_WIDTH[9:0]	Average HSync width measured in top field	The 10-bit number represents the average HSync width measured over multiple system clock cycles
RASTER_TYPE	Defining raster type (interlaced vs. progressive)	0-progressive 1-interlace

TABLE 6

Once the metrics are measured, the metrics can be used to identify the format of the incoming analog video stream, as described above. Format identification may include 3 steps: determining when a format has changed; searching for a new format; arbitration is performed between the format identified by the Gen-AGC path for low noise input signals and the format identified by the SD-AGC path for high noise signals.

The definition of format change is different for an input signal in ATSC format and an input signal in PC format. The basis for these different requirements is that the PC format requires Sync polarity values and raster type identification (i.e., progressive or interlaced) while the ATSC signal does not. Thus, for an ATSC signal, a change in format for an ATSC signal may be defined to exist if there is gain lock on both the scan line length and the field length, then either the scan line length or the field length loses lock, or the current metric no longer matches the identified format. For a PC signal, if there is gain lock on hWidth, scan line length, vWidth, field length, and raster type, then hWidth, scan line length, vWidth, field length, and raster type are out of lock, or the current metric no longer matches the identified format, a change in the format in which the PC signal exists may be defined.

If the format change is the result of a loss of lock on the metric, the format is listed as "MISSING _ INPUT". If the desired metric is locked, a new format index may be identified by comparing the current metric to a list of format attributes (similar to the values listed in Table 7 below). A first match between a current metric and a set of attributes may identify a format. The format index is recorded and reported to the software. In addition, the format attribute is copied locally to track subsequent consistency with the selected format. If no set of format attributes describes the current metric, the format is listed as "unknown".

Name of field	Field description	Field assignment
			FT_HSYNC_POLARITY	Only for PC format. In the case of ATSC signal format identification, the value of this field is ignored.	1-positive 0-negative
FT_VSYNC_POLARITY	Only for PC format. In the case of ATSC signal format identification, the value of this field is ignored.	1-positive 0-negative
			FT_LINES_PER_FIELD[14:0]	The number of scan lines per field for a given format is defined. If set to a value of "0," this field is ignored during format recognition.	The 4 lsb bits represent the decimal value. These bits should be set to: 4 b' 0000 for progressive format and 1250/50; 4 b' 1000 is used for interlaced formats other than 1250/50,
FT_DELTA_LPF[3:0]	defining an allowable margin of the measured LINES _ PER _ FIELD value versus FT _ LINES _ PER _ FIELD	The valid range of LINES _ PER _ FIELD is defined as: { FT _ LINES _ PER _ FIELD-FT _ DELTA _ LPF, FT _ LINES _ PER _ FIELD + FT _ DELTA _ LPF }

Name of field	Field description	Field assignment
			FT_LINE_LENGTH[12:0]	The scan line length for a given format is defined. If set to a value of "0," this field is ignored during format recognition.	This value is given in the system clock samples.
FT_DELTA_LL[3:0]	An allowable tolerance of the measured LINE _ length value versus the FT _ LINE _ length value is defined.	The effective range of LINE _ length is defined as: { FT _ LINE _ LENGTH-FT _ DELTA _ LL, FT _ LINE _ LENGTH + FT _ DELTA _ LL }
			FT_HSYNC_WIDTH[9:0]	Defining the HSync width in a given format. If set to a value of "0," this field is ignored during format recognition.	This value is given in the system clock samples.
FT_DELTA_HW[3:0]	Defining an allowable tolerance for the measured LINE _ LENGTH direct-to-FT-LINE _ LENGTH value	The effective range of HSYNC _ WIDTH is defined as: { FT _ HSYNC _ WIDTH-FT _ DELTA _ HW, FT _ HSYNC _ WIDTH + FT _ DELTA _ HW })
			FT_RASTER_TYPE[1:0]	Defining raster type (interlaced vs. progressive)	2-interlaced 1-progressive 0-is not limited to

TABLE 7

The FORMAT attribute table may be stored in memory and may be accessed by a FORMAT _ START memory address and a FORMAT _ COUNT value. A FROMAT _ COUNT ═ 0 awakenable system indicates that there is no format comparison. Once the software sets the table values and memory pointers, the counters may be set to the appropriate values.

The first element is available through the FORMAT _ COUNT entry in the table when deciding to look up a new FORMAT. Each attribute in the table may be compared to a corresponding metric if the attribute is non-zero. If each metric corresponding to a non-zero attribute is within the range of that attribute, then the selected format is correct. After each format recognition cycle is completed, the elements of table 8 may be updated.

Name of field	Field description	Field assignment
			FORMAT_INDEX[9:0]	An index of the input format is defined. The maximum number of formats supported is 1023.	Used by SW to recognize the format and generate the appropriate VDEC setting. 0 unknown 1- > 1023 valid format read-only register field
MISSING_INPUT	Indicating that the metric is not locked	Metric read-only register field locked 0, unstable 1
			NEW_FORMAT	The completion of the format recognition processing is indicated to SW. This bit is set even if no valid format is identified.	Reading: READY 0 NOT READY 1 RESET 0 NO Action

Table 8 (Format ready register)

To arbitrate between the possible formats identified in the high noise matched filter path and the low noise Gen AGC path, a format arbiter 244 in fig. 2 may be used. If the metrics extracted in the metric extraction modules 208 and 220 remain unlocked after a programmable period of time, the input format may be determined to be a "floating input". If the metric locks, format arbiter 244 determines the format by a series of comparisons based on a programmable format table stored in memory. The format identification may read an entry from memory that lists the value and tolerance for each metric. A first entry describing that the current metric is within a defined tolerance may be identified as an analog input signal format. If no match is found after reading the entire table, the current format is marked as "undefined/invalid".

If the high noise, matched filter path and the low noise, Gen AGC path all produce metrics that lock onto a certain format, format arbiter 244 selects the format that locks first for use in system 100. Alternatively, in the event that a high noise, matched filter path and a low noise, Gen AGC path identify a format that conflicts, format arbiter 244 may select the format identified by the predetermined path.

Embodiments of the various techniques described herein may be implemented in digital electronic circuitry, or in computer hardware, firmware, software, or in combinations of them. Embodiments may be implemented as a computer program product, i.e., a computer program tangibly embodied in an information carrier, e.g., in a machine-readable storage device or in a propagated signal, for execution by, or to control the operation of, data processing apparatus, e.g., a programmable processor, a computer, or multiple computers. A computer program, such as the one described above, may be written in any form of programming language, including compiled or interpreted languages, and it may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. A computer program can be deployed to be run on one computer or on multiple computers at one site or distributed across multiple sites and interacting across a communication network.

Method steps can also be performed by, or apparatus can be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application-specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. Elements of a computer include at least one processor for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer will also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic, magneto-optical disks, or optical disks. Information carriers suitable for embodying computer program instructions and data include all forms of non-volatile memory, including semiconductor memory devices, e.g., EPROM, EEPROM, and flash memory, magnetic disks such as internal hard disks or removable disks, magneto-optical disks, and CD-ROM and DVD-ROM optical disks. The processor and the memory can be implemented by, or incorporated in, special purpose logic circuitry.

To provide for interaction with a user, implementation can be on the following computer: having a display device, such as a Cathode Ray Tube (CRT) or Liquid Crystal Display (LCD) monitor, to display information to a user; having a keyboard and a pointing device, such as a mouse or trackball, by which a user can provide input to the computer. Various other devices may also be used to provide interaction with the user, for example, feedback provided to the user may be any type of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; input from the user may be received in any form, including acoustic, verbal, or tactile input.

While certain features of the embodiments have been described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit of the embodiments of the invention.

Claims (5)

1. A system for automatically identifying the format of a video signal, the video signal including HSync pulses, VSync pulses, and video display data, the system comprising:

a first bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a second bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a matched filter for receiving the input signal adjusted by the second bias and compensation circuit and filtering the received signal according to the predetermined HSync pulse width in the received signal after tuning;

a synchronous pulse detection circuit for detecting the HSync pulse and the VSync pulse in the input signal adjusted by the first bias and compensation circuit, and detecting the HSync pulse and the VSync pulse in the filtered signal;

a metric extraction circuit for extracting information related to the timing and width characteristics of the detected HSync pulse and VSync pulse;

and a format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information with a predetermined characteristic of a known format.

2. The system of claim 1, wherein the system is located on a single chip.

3. The system of claim 1, further comprising a low pass filter for filtering the input signal prior to adjusting the bias level and the gain level of the signal.

4. The system of claim 1, further comprising:

a first sync pulse detection circuit for detecting HSync pulses and VSync pulses in the input signal adjusted by the first bias and compensation circuit, and a second sync pulse detection circuit for detecting HSync pulses and VSync pulses in the filtered signal;

a first metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the first sync pulse detection circuit, and a second metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the second sync pulse detection circuit;

a first format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the first sync pulse detection circuit with the known characteristics of the first format, and a second format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the second sync pulse detection circuit with the known characteristics of the second format.

5. A system for automatically identifying the format of a video signal, the video signal including HSync pulses, VSync pulses, and video display data, the system comprising:

a first bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a second bias and compensation circuit for receiving the video signal and adjusting the bias level and gain level of the signal such that the minimum and maximum levels of the adjusted input signal conform to predetermined minimum and maximum levels;

a filter for receiving the input signal adjusted by the second bias and compensation circuit and filtering the received signal according to the predetermined HSync pulse width in the received signal after tuning;

a first sync pulse detection circuit for detecting HSync pulses and VSync pulses in the input signal adjusted by the first bias and compensation circuit, and a second sync pulse detection circuit for detecting HSync pulses and VSync pulses in the filtered signal;

a first metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the first sync pulse detection circuit, and a second metric extraction circuit for extracting information related to timing and width characteristics of the HSync pulses and the VSync pulses detected by the second sync pulse detection circuit;

a first format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the first sync pulse detection circuit with the known characteristics of the first format, and a second format recognition circuit for recognizing the format of the video signal based on a comparison of the extracted information about the time and width characteristics of the HSync pulse and the VSync pulse detected by the second sync pulse detection circuit with the known characteristics of the second format.