HK1118398A - Frame synchronisation in an ofdm system - Google Patents

Description

Frame synchronization in OFDM systems

Cross Reference to Related Applications

This application claims priority from U.S. provisional patent application No.60/660,915 entitled "TDM pilot Processor (TDM pilot1 Processor), filed on 11/3/2005, which is incorporated herein by reference in its entirety.

Technical Field

The subject technology relates generally to communication systems and methods, and more particularly to systems and methods for determining frame synchronization in an OFDM system by applying time domain processing to received pilot symbols.

Background

One technology that has dominated wireless systems is the Code Division Multiple Access (CDMA) digital radio technology. In addition to CDMA, the air interface specification defines FLO (Forward Link Only) technology that has been developed by industry-leading wireless provider organizations. For FLO^TMThe basic signal unit of transmission is an Orthogonal Frequency Division Multiplexing (OFDM) symbol consisting of 4642 time-domain baseband samples, called OFDM chips. Among these OFDM chips, there are 4096 data chips. These chips are cyclically extended on both sides and 529 cyclically extended chips precede the data portion and 17 follow the data portion. To reduce the out-of-band energy of the OFDM signal, the front 17 chips and the end 17 chips in the OFDM symbol have a raised cosine envelope. The 17 chips at the front of the OFDM symbol overlap with the 17 chips at the end of the previous OFDM symbol. As a result, the duration of each OFDM symbol is 4625 chips in duration.

Before transmission, FLO data is typically grouped into superframes. Each superframe has a duration of one second. A superframe is typically composed of 1200 symbols (or varying number of OFDM symbols based on the bandwidth used), which are modulated using 4096 subcarriers. The 1200 OFDM symbols in a superframe are: two TDM pilot symbols (TDM1, TDM 2); a wide area and a local identification channel (WIC and LIC) symbol; fourteen OIS channel symbols, which include four Transition Pilot Channel (TPC) symbols; a number of PPC symbols for aiding positioning that may be selected from two, six, ten, or fourteen; and four data frames.

Time Division Multiplexed (TDM) pilot symbol 1(TDM1) is the first OFDM symbol of each superframe, where TDM1 cycles with a period of 128 OFDM chips. The receiver uses TDM1 for frame synchronization as well as start timing (coarse timing) and frequency acquisition. TDM1 is followed by two symbols carrying wide area and local IDs, respectively. The receiver uses this information and performs the appropriate decoding operation using the corresponding PN sequence. Time division multiplexed pilot symbol 2(TDM2) follows the wide and local ID symbols, where TDM2 cycles periodically with a period of 2048 OFDM chips and contains two more bit periods. The receiver uses TDM2 when determining the fine determination for demodulation.

After TDM2 are: a wide area tpc (wtpc) symbol; five wide-area OSI symbols; another WTPC; a local tpc (ltpc) symbol; five local OIS symbols; another LTPC; and four data frames following the first 18 OFDM symbols described above. A data frame is divided into a wide area data portion and a local data portion. One at each end of the wide area TPC is added before and after the wide area data. This configuration is also used for the local data part. The initial processing of the superframe information is an important aspect in order to determine these portions as the start of a new superframe so that subsequent frame information can be synchronized and determined therefrom. In the past, these determinations were done via frequency domain processing, but such processing resulted in an increase in complexity and overhead when processing OFDM information.

Disclosure of Invention

The following presents a simplified summary of various embodiments in order to provide a basic understanding of some aspects of the embodiments. This summary is not an extensive overview. It is not intended to identify key/critical elements or to delineate the scope of the embodiments disclosed herein. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.

Systems and methods for determining timing and frame synchronization in an Orthogonal Frequency Division Multiplexing (OFDM) system are provided. In one embodiment, time domain processing is applied to received time division multiplexed pilot 1(TDM1) symbols, where TDM1 is applied to a delayed correlator component. The output of the delay correlator generates a well-defined ramp in the time domain, which can then be detected by comparing the edges of the ramp to a predetermined threshold. In one example, the TDM1 detection block provides delay-dependent components or circuits; where the component correlates the received sample sequence with a sequence delayed by 128 samples. Because TDM1 is cyclically cycled and has 128 samples per cycle, and other OFDM symbols do not share this characteristic, the output of the detector has a significantly larger amplitude when TDM1 is present than when TDM1 is not present. In addition, the phase of the correlator output and the carrier frequency of the received signal are proportional to the frequency offset between the receiver local oscillator frequency.

When the detector determines that TDM1 is present, an Automatic Frequency Control (AFC) circuit uses the phase output of the correlator to initiate initial frequency acquisition during a correction operation based on the magnitude of the correlator output. At approximately the same time, it continues to check the reliability of the detection and at the same time monitors the end of TDM1 (trailing edge of detector output). When the output exceeds a predetermined threshold, then the data and next timing acquisition may be based on multiple observations of the correlator output. In one embodiment, a method of determining synchronization information in an Orthogonal Frequency Division Multiplexing (OFDM) broadcast is provided. The method includes performing frame synchronization on samples in an OFDM superframe using time-domain correlation, and synchronizing a receiver with a frequency component of the OFDM superframe using the time-domain correlation samples. At the end of the TDM1 detection process, the automatic frequency loop is updated by the phase of the correlator output, which is proportional to the frequency offset between the receiver local oscillators.

To the accomplishment of the foregoing and related ends, certain embodiments are described herein in connection with the following description and the annexed drawings. These aspects are indicative of various ways in which the embodiments may be practiced, and are intended to encompass all such ways.

Drawings

Fig. 1 is a schematic block diagram illustrating a time-domain correlator for a wireless receiver.

Fig. 2 shows an example superframe structure.

Figure 3 illustrates an example delay correlator component for a wireless receiver.

Figure 4 illustrates an example amplitude output for a time-domain correlator detector.

Fig. 5 illustrates an example state machine for time domain multiplexed pilot processing.

Fig. 6 and 7 are flow diagrams illustrating example processes for time-domain multiplexing pilot signals.

Fig. 8 is a diagram illustrating an example user equipment for a wireless system.

Fig. 9 is a diagram illustrating an example base station for a wireless system.

Fig. 10 is a diagram illustrating an example transceiver for a wireless system.

Detailed Description

Systems and methods are provided for processing time domain multiplexed pilot 1(TDM1) symbols by correlating with delayed samples in the time domain. In one embodiment, a method of determining synchronization information in an Orthogonal Frequency Division Multiplexing (OFDM) broadcast is provided. The method includes detecting a start of an OFDM superframe using time domain correlation and correcting an initial frequency offset between a transmitter frequency and a local receiver frequency using a time domain correlation operation. In one example, the samples may be used in a single forward link system.

As used in this application, the terms "component," "network," "system," and the like are intended to refer to a computer-related entity, either hardware, a combination of hardware and software, or software in execution. For example, components may include, but are not limited to: a process running on a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of example, both an application running on a communication device and the device can be a component. One or more components may reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. These components can also execute from various computer readable media having various data stored thereon. The components may communicate over local and/or remote integration such as in accordance with a signal having one or more data packets (e.g., data for one component interacting with another component in a local system, distributed system, and/or across a network, such as the internet, whether wired or wireless).

Fig. 1 illustrates time domain correlation of a wireless network system 100 for determining timing synchronization and frequency offset. The system 100 includes one or more transmitters 110 in communication with one or more receivers 120 over a wireless network. Receiver 120 may comprise substantially any type of communication device, such as a cellular circuit, a computer, a personal assistant, a handheld or laptop device, and so forth. Portions of the receiver 120 may be used to decode and process the superframe 130 and other data, such as multimedia data. The superframe 130 is typically transmitted over an Orthogonal Frequency Division Multiplexing (OFDM) network that uses a single Forward Link (FLO) protocol for multimedia data transmission. As shown, a time division multiplexed pilot1 processor is used to process the superframe and determine timing and frequency offsets. When a TDM1 OFDM symbol is encountered, time-domain correlator 150 receives superframe 130 and generates ramp output signal 160, where it is noted that: TDM1 and TDM pilot1 are equivalent terms. From the ramp output 160, the threshold detector 170 uses the threshold to determine when the leading or trailing edge of the ramp exceeds a predetermined threshold, which can be programmed into the TDM processor 140 if desired. If the threshold has been exceeded for a predetermined time, a TDM1 may be signaled to have been detected and may be used to synchronize the receiver 120 with the superframe 130 operation in TDM 1. Other aspects include detecting and transmitting real and imaginary phase components (e.g., I/Q) to an automatic frequency control block (not shown).

The output of the time-domain correlator 150 generates a well-defined ramp in the time domain, which can then be detected by comparing the edges of the ramp to predetermined thresholds in the detector 170. In one example, the TDM1 processor 140 provides a delay-correlation circuit 150 that correlates a received sequence of samples with a sequence delayed by 128 samples. Because TDM1 is cyclically cycled and has 128 samples per cycle, and because other OFDM symbols do not share this characteristic, the output of detector 170 has a significantly larger amplitude when TDM1 is present than when TDM1 is not present. In addition, the phase output by the time-domain correlator 150 and the carrier frequency of the received signal are proportional to the frequency offset between the receiver 120 local oscillator frequency. After detecting the rising edge of the correlator output, it continues to check the reliability of the detection while monitoring the TDM1 for the end-detector output 160 trailing edge. When the output exceeds a predetermined threshold stored or programmed into the detector 170, then the data and subsequent timing acquisition may be based on multiple observations of the correlator output 160. In one embodiment, the system 100 determines timing data in a wireless network. The system 100 includes means for analyzing the superframe to detect a signal size in the time domain (reference 150), and means for detecting the signal size to determine a start timing signal for the superframe 130 (reference 170). Upon detecting the end of a TDM1 OFDM symbol, the automatic frequency loop (AFC) is updated by a value proportional to the phase of the correlator output.

Fig. 2 shows an example superframe structure 200. At initial power-on, after Automatic Gain Control (AGC) stabilization, the modem collects the frame and OFDM symbol coarse timing and frequency by processing TDM1 pilot1 symbols 210. In the time domain, the TDM pilot 210 consists of a sequence of 36 cycles with a length of 128 per cycle. The structure of TDM pilot1 simplifies the implementation of the correlator used to detect it. This structure is also suitable for frequency estimation in harsh multipath channels because the stored waveform is performed periodically for most parts. At 220, TDM1 is shown to have 4096 subcarriers in the frequency domain, where only thirty-half is non-zero, while at 230, TDM1 is split into 128 samples in the time domain and then repeated 36 times.

Because TDM pilot1 (symbol) 210 serves as a marker for the start of every 1 second superframe, the task of frame synchronization becomes detection of TDM pilot1 symbols. The time domain periodic structure of TDM pilot1 (symbol) 210 is used to detect it and estimate the coarse OFDM symbol timing. The TDM pilot1 symbol 210 is also used for initial frequency estimation. Initial frame, timing and frequency synchronization is achieved by processing the output of the delay dependent components as described in more detail below. The received signal, with an initial phase offset of φ and a frequency offset of Δ f, is given by:

r(t)＝x(t)e^{j(2πΔfi+φ)}+n(t) (1)

where x (t) is the TDM pilot1 signal. Note that: x (T) x (T + T), where T is the period of TDM pilot 1. The sampled form of the received signal is:

wherein T is_sIs the sampling period and K represents the time coefficient. If r is_k＝r(KT_s)，x_k＝x(KT_s)，n_k＝n(KT_s) And Δ f ═ Δ f/f_s(frequency error normalized to sampling frequency), then:

r_k＝x_ke^{j2πΔf′+φ}+n_k (3)

then, the following decision statistics are formed:

where P is the period in the form of TDM pilot1 samples. The acquisition is based on the event that the magnitude of the correlator output exceeds a predetermined threshold T, as will be described in more detail below.

Fig. 3 illustrates an example delayed correlator assembly 300. In general, timing and data acquisition may be based on multiple observations of the correlator output when the correlator output exceeds a threshold T310. Integration over a sliding window of 128 samples in length may be achieved by adding a new term (r) to the accumulator 320_kr_k-128 ^*) And subtracts the old term (r) at 330_k-128r_k-256 ^*) To be implemented. An autocorrelation periodic waveform of period P may include an input buffer 340 of length P for holding the last (periodic) P input samples, and a single complex multiplier 350. A shift register or memory 360 of length P holds the last (cycle of) P product terms, where component 330 provides a complex adder and subtractor. The magnitude squared term is fed to a threshold correlator 310 to determine the presence of TDM1 in the time domain. The magnitude of the delayed correlator output on the noiseless single-path channel when TDM pilot1 is present is shown in 400 of fig. 4. The delayed correlator outputs detection of TDM pilot1, which can be used for frame synchronization, and timing estimation of the initial OFDM symbol. The phase of the correlator output can be used for estimation of the initial frequency offset.

Fig. 5 illustrates an example implementation 500 of TDM pilot1 processing. At 510, samp _ data _ i/q and del _ samp _ data _ i/q delayed by 128 samples are input from the AFC module. At each sample clock, the samp _ data value and del _ samp _ data are correlated 514 as r_jr_j-128 ^*. The output of the correlator (complex multiplier) 514 is stored in a shift register FIFO520, which may be an SRAM having a capacity of 128 x 12. The correlator output 514 is also added 524 to the value stored in the sum _ correlated _ data accumulator 530-a sliding window sum of 128 consecutive correlation outputs. Within the same sampling clock interval, the sum _ corrected _ data accumulator is subtracted 524 from the 128 sample delayed correlation value read from the shift register FIFO 520. The shift register FIFO520 is a circular buffer in which the read pointer lags the write pointer by 128 bits. At 540, the squared magnitude of the "shortened" version of sum _ corrected _ data at 534 is compared to a software programmable threshold at 544, each clock interval, andand records the result into state machine 550 for TDM pilot 1. The output of sum _ corrected _ data at 554 (I and Q) is written to the sum accumulator once every 128 sample clocks during the flat zone of TDM pilot detection as shown at 400 of fig. 4. In the detection of the end of TDM1, the sum accumulator value is written to the AFC block. Using an AFC block tan^-1(Q/I) formula to calculate the frequency error between the TX clock and the local RX clock.

ARM interface module 560 enables software to be written to control registers that operate with this block 500 and the AFC block. When TDM1 detection is reliable and confirms the end of TDM1, the receiver assumes that the local clock has been approximately synchronized to the carrier frequency after the AFC block is updated. While frame synchronization is achieved with a high probability. A coarse OFDM signal timing estimate is determined based on measuring the falling edge of the correlator output during TDM 1. The determined timing accuracy should not exceed the precise timing by several hundred chips. The AFC block has two counters that determine timing. The OFDM _ symbol _ counter keeps track of the number of OFDM symbols in the super frame. The falling edge of the TDM pilot1 correlator output is labeled OFDM symbol "1" and TDM pilot1 is treated as OFDM symbol "0". Note that: the falling edge of the correlator output is present in the symbol following the OFDM symbol of TDM pilot 1. A second counter, intra _ OFDM _ counter, in the AFC tracks the number of samples in the OFDM symbol. Upon detecting a falling edge in the correlator output, the intra _ ofdm _ counter is initialized to a value equal to (256-17). At this point, the receiver is ready to demodulate the WIC and LIC symbols and then process the TDM pilot 2 (also referred to as TDM2) to obtain accurate time synchronization.

ARM interface module 560 implements software registers that control the TDM pilot1 and AFC blocks. TDM pilot1 FSM implements a state machine responsible for detecting TDM pilot 1. The receiver determines the local and wide area networks on which it operates from the WOI and LOI ID symbols after TDM 1. The information is used to establish a correction scrambling sequence to correctly decode the data symbols. TDM2 is cyclically cycled with 2048 chips per cycle. From the coarse timing estimate determined based on TDM1, the fine timing determination module operates based on 2048 sample segments of TDM2 to generate an estimate of the time domain transmission signal. A channel estimate of length 2048 is generated from 2048 chips of TDM2 and it is cyclically shifted by an amount equal to the coarse timing error. If the true channel spacing is less than 1024 chips, the receiver can uniquely determine the delay and distribution of the channel. The initial precise timing (i.e., the position of the FFT window) can be obtained from the distribution of channel estimates and the delay.

Typically, the initial acquisition step based on correlating TDM1 symbols has three phases. It should be understood that the hard-coded values in the following description are for the purpose of illustrating an example embodiment. In one implementation of these embodiments, these values may be programmed via software. In the first phase, the algorithm searches for the leading edge of the correlation curve. At 540, the squared magnitude of the correlator output is compared to a programmable threshold T. If the correlator output exceeds the threshold for 64 output samples (or other determined amount), the algorithm enters the second phase of the acquisition process.

In the second phase, each time the square of the magnitude of the correlator output at 540 exceeds the threshold, the click count (hit count) at 564 is incremented. If the observed leading edge is determined to be false, the algorithm may return to the first stage. This is indicated by the correlator output remaining less than the threshold value greater than or equal to 128 input samples and the click count being less than 400.

The algorithm continues to remain in the second phase for at least 34 cycles, or until it observes a stable trailing edge of the correlation curve. If no trailing edge is observed in the second stage, observation continues in the third stage. In the third phase, TDM1 is declared detected if the correlator output remains below the threshold for a minimum of 32 consecutive input samples, and if the correlator exceeds the threshold for at least 2000 input samples in the second phase. An accumulator is used and the AFC loop is updated. The phase value of the accumulator sum, which is proportional to the frequency offset, is used to correct the frequency error between the transmitter and the receiver.

The initial OFDM symbol time estimate is based on the trailing edge of the waveform shown in fig. 4. The time instance is taken as the 239(256-17) th sample of the next OFDM symbol (TDM pilot 2) when the correlator output last transitions to less than the threshold during the observed trailing edge. If at 560 the click count is found to be less than 2000, or no stable trailing edge is observed for a period of time exceeding 1024 input sample periods in phase 3, the algorithm resets the count and returns to the first phase to observe another leading edge. The accumulator sum of the correlator is not transmitted to the AFC block and the sum accumulator is reset.

The programmable threshold T444 may depend on the AGC setting and recommend T ═ 1/4 (128 ═ σ ═ d_s ²)²Is calculated in a manner that σ is_s ²Is the power of the received signal. Because AGC provides constant signal power plus noise power: m ═ σ_s ²+σ_n ²So a signal-to-noise ratio (SNR) of 0dB can be used for a given operation M in order to calculate the threshold T. For ADC range ± 1, the full scale power may be 2. If significant AGC error is expected (in fast fading) this should be taken into account when calculating the threshold. A threshold for non-AFC errors should be calculated to facilitate high SNR operation; otherwise, the detection performance at high SNR will deteriorate.

Due to gain sensitivity variations, a frequency error detector is used for initial frequency acquisition data collection based on the periodic structure of TDM1 and large loop bandwidth when the correlator output is greater than a threshold. After assertion of leading edge detection, data acquisition for initial frequency acquisition is performed during the flat zone (or second phase) of the acquisition step. The sum accumulator of the correlator is updated every 128 input samples. Although the algorithm may last 34 or more cycles in the second phase, the number of times the correlator and accumulator are updated is limited to 28 times. The ends of TDM1 symbols are typically aperiodic because the channel may have excessive delay spread. As a result, frequency estimation based on the end of the plateau may be unreliable. The frequency offset is calculated by taking the inverse tangent of the sum accumulator of the correlators.

Fig. 6 and 7 illustrate example processes 600 and 700 for time-domain multiplexing pilot signals. For purposes of simplicity of explanation, however, the methodologies are shown and described as a series or number of acts, it is to be understood and appreciated that the processes described herein are not limited by the order of acts, as some acts may, in accordance with the illustrations and descriptions herein, occur in different orders and/or concurrently with other acts. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all illustrated acts may be required to implement a methodology in accordance with the subject matter disclosed herein.

The processes 600 and 700 shown in fig. 6 and 7 are associated with the state machine described above with reference to fig. 5. Typically, at 610, the state machine is in an idle state until enabled by software, and all memory cells in corr _ mem (shift register FIFO) are written to "0". At 620, the next state START _ RIS _ EDGE _ DETECT is the starting point for detecting the rising EDGE of the comparator. In this state, the run _ count counter is held in a reset state. If the comparator output is "1," indicating that the sum-correlator (sum-correlator) value is greater than the threshold, the state machine transitions to the RIS _ EDGE _ ON state at 630. At each sampling clock edge, if the comparator output is "1", the run _ count counter is incremented by 1. If the comparator is "0" at any sampling clock EDGE, the state machine transitions from the RIS _ EDGE _ ON state at 630 to START _ RIS _ EDGE _ DETECT at 620 and the process restarts. When run _ count reaches 64, indicating that the correlator outputs are all "1" for 64 consecutive samples, the state machine goes to the START _ FLAT _ RRENGINE state at 640 and resets the counters interval _ count, hit _ count and run _ count.

The interval _ count counter is incremented on each sampling clock edge and tracks the number of samples that have elapsed; the hit _ count counter tracks the number of sampling clocks for which the comparator output is "1" (i.e., the output of the comparator is greater than the threshold); the run count counter tracks the number of sample clocks the comparator continues to "0". Starting at START _ flag _ REGION at 640, the state machine goes to flag _ ABOVE _ THRESHOLD at 650 if the comparator is "1", or to flag _ BELOW _ THRESHOLD at 660 if the comparator is "0". The state machine moves between the two states of 650 and 660 depending on the value of the comparator at each sampling clock edge. At the FLAT _ ABOVE _ THRESHOLD state of 650, if interval _ count is greater than sw _ jc _ FLAT (i.e., held long enough) and the comparator output is "0," the state machine goes to the START _ FALL _ EDGE _ DETECT state. Starting from the FLAT _ BELOW _ THRESHOLD state at 660, the next state is also START _ FALL _ EDGE _ DETECT based on any of the three conditions shown in FIG. 6.

The condition ((run _ count > ═ sw _ rc _ false _ rise) AND (hit _ count < sw _ hc _ false _ rise)) is related to false rising edge detection in the output of the comparator. The condition ((run _ count > ═ sw _ rc _ fall) AND (hit _ count > -. The condition ((interval _ count >) - (sw _ ic _ flat) AND (run _ count > 0)) ensures that if a falling edge is not detected, it is not stuck in this state. In the START _ false _ EDGE _ DETECT state of 670, interval _ count is reset. If hit _ count is less than sw _ hc _ flat, the state machine goes to START _ RIS _ EDGE _ DETECT at 620 and the process restarts because it indicates that the correlator output is not greater than the threshold for a sufficiently long time. Otherwise: if the comparator output is "1," the state machine goes to FALL _ ABOVE _ THRESHOLD at 650. Then, if the interval _ count is equal to sw _ ic _ after _ fall, which indicates that the expected "droop" has not occurred, the state machine goes to START _ RIS _ EDGE _ DETECT at 620. If the comparator output is "0," the state machine goes to FALL _ BELOW _ THRESHOLD at 660. Then, if the interval _ count exceeds sw _ ic _ after _ fall or if the run _ count exceeds sw _ rc _ after _ fall, the state machine goes to the TDM _ PILOT1_ DET state shown at 710 of FIG. 7 (i.e., TDM has been successfully detected).

Fig. 8 is an example of a user device 800 for use in a wireless communication environment according to one or more aspects set forth herein. User device 800 comprises a receiver 802 that receives a signal from, for instance, a receive antenna (not shown), performs standard actions on the received signal, and digitizes the conditioned signal to obtain samples. Receiver 802 may be a non-linear receiver. A demodulator 804 can demodulate and provide received pilot symbols to a processor 806 for channel estimation. FLO channel component 810 is arranged to process FLO signals. This may include digital stream processing and/or positioning calculations in other processes. Processor 806 can be a processor dedicated to analyzing information received by receiver 802 and/or generating information for transmission by a transmitter 816, a processor that controls one or more components of user device 800, and/or a processor that both analyzes information received by receiver 802, generates information for transmission by transmitter 816, and controls one or more components of user device 800. Memory may also be provided to make the processor easier to execute. Note that: the device 800 is exemplary in nature and is intended to impart general functionality. As for single Forward Link (FLO) functionality, FLO flow can coexist with wireless devices such as (cellular) telephones, but it does not rely essentially on standard device transmission and reception operations. Thus, the FLO channel will not employ the transmitter 816.

It will be appreciated that the data store (e.g., memories) components described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), electrically erasable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which acts as external cache memory. By way of example and not limitation, RAM may be such as Synchronous RAM (SRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESSDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 808 of the subject systems and methods is intended to comprise, without being limited to: these and any other suitable types of memory. User device 800 further comprises a background detector 814 for processing FLO data, a symbol modulator 814, and a transmitter 816 for transmitting the modulated signal.

Fig. 9 shows an example system 900 that includes a base station 902 having a receiver 910 that receives signals from one or more user devices 904 via a plurality of receive antennas 906 and a transmitter 924 that transmits to the one or more user devices 904 via a transmit antenna 908. Receiver 910 can receive information from receive antennas 906 and operates in conjunction with a demodulator 912 that demodulates received information. Demodulated symbols are processed by a processor 914 that is similar to the processor and that is coupled to a memory that stores information related to the user layer, lookup tables related thereto, and/or information related to processing various acts and functions described herein. Processor 914 can also be coupled to a FLO channel component 918 that facilitates transmitting FLO information to one or more separate user devices 904. A modulator 922 can multiplex a signal through a transmitter 924 via transmit antenna 908 to user devices 904.

Fig. 10 illustrates an exemplary wireless communication system 1000. The wireless communication system 1000 illustrates one base station and one terminal for sake of brevity. However, it is to be appreciated that the system can include multiple base stations and/or multiple terminals, wherein additional base stations and/or terminals can be substantially similar or different for the exemplary base station and terminal described below.

Referring now to fig. 10, at access point 1005, on the downlink, a Transmit (TX) data processor 1010 receives, formats, codes, interleaves, and modulates (or symbol maps) traffic data and provides modulation symbols ("data symbols"). A symbol modulator 1015 receives and processes the data symbols and pilot symbols and provides a stream of symbols. Symbol modulator 1015 multiplexes data and pilot symbols and provides them to a transmitter unit (TMTR) 1020. Each transmit symbol may be a data symbol, a pilot symbol, or a signal value of zero. The pilot symbols may be transmitted continuously in each symbol period. The pilot symbols may be Frequency Division Multiplexed (FDM), Orthogonal Frequency Division Multiplexed (OFDM), Time Division Multiplexed (TDM), Frequency Division Multiplexed (FDM), or Code Division Multiplexed (CDM).

TMTR 1020 receives and converts the stream of symbols into one or more analog signals and further conditions (e.g., amplifies, filters, and frequency upconverts) the analog signals to generate a downlink signal suitable for transmission over the wireless channel. The downlink signal is then transmitted through an antenna 1025 to the terminals. At terminal 1030, an antenna 1035 receives the downlink signal and provides a received signal to a receiver unit (RCVR) 1040. Receiver unit 1040 conditions (e.g., filters, amplifies, and frequency downconverts) the received signal and digitizes the conditioned signal to obtain samples. A symbol demodulator 1045 demodulates and provides received pilot symbols to a processor 1050 for channel estimation. Symbol demodulator 1045 further receives a downlink frequency response estimate from processor 1050, performs data demodulation on the received data symbols to obtain data symbol estimates (estimates of the transmitted data symbols), and provides the data symbol estimates to an RX data processor 1055, which demodulates (e.g., symbol maps), deinterleaves, and decodes the data symbol estimates to recover the transmitted traffic data. The processing by symbol demodulator 1045 and RX data demodulator 1055 is complementary to the processing by symbol modulator 1015 and TX data processor 1010, respectively, at access point 1005.

Processors 1090 and 1050 direct operation (e.g., control, coordinate, manage, etc.) at access point 1005 and terminal 1030, respectively. Processors 1090 and 1050 can each be associated with a memory unit (not shown) that stores program codes and data. Processors 1090 and 1050 can also execute sets of computing instructions to obtain frequency and impulse response estimates for the uplink and downlink, respectively.

The systems and devices described herein may be implemented in hardware, software, or a combination thereof. For a hardware implementation, the processing units for channel estimation may be implemented within one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), processors, controllers, micro-controllers, microprocessors, other electronic units designed to perform the functions described herein, or a combination thereof. For software, implementation can be through modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory unit and executed by the processors 1090 and 1050.

For a software implementation, the techniques described herein may be implemented with modules (e.g., procedures, functions, and so on) that perform the functions described herein. The software codes may be stored in memory units and executed by processors. The memory unit may be implemented within the processor or external to the processor, and in the case of being external to the processor, may be communicatively coupled to the processor via various techniques as is known in the art.

What has been described above includes exemplary embodiments. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the embodiments, but one of ordinary skill in the art may recognize that many further combinations and permutations are possible. Accordingly, the embodiments are intended to embrace all such alternatives, modifications and variances which fall within the spirit and scope of the appended claims. Furthermore, to the extent that the term "includes" is used in either the detailed description or the claims, such term is intended to be inclusive in a manner similar to the term "comprising" as "comprising" is interpreted when employed as a transitional word.

Claims (33)

1. A method for determining synchronization information, comprising:

detecting a start of an OFDM superframe using time domain correlation; and

utilizing the time domain correlation to synchronize a receiver with a frequency component of the OFDM superframe.

2. The method of claim 1, further comprising using samples in a single forward link system.

3. The method of claim 1, further comprising sampling at least 128 samples for an input buffer from a gain amplifier.

4. The method of claim 3, further comprising performing a complex multiplication at an output of the input buffer as a correlation operation.

5. The method of claim 4, further comprising performing a shift register function from the complex multiplication.

6. The method of claim 5, further comprising performing complex addition and complex subtraction at an output of the shift register.

7. The method of claim 6, further comprising storing the complex addition and the complex subtraction in a register.

8. The method of claim 7, further comprising determining a magnitude squared value from the register.

9. The method of claim 8, further comprising comparing the magnitude squared to a predetermined threshold to determine detection of a pilot1 symbol.

10. The method of claim 9, wherein the predetermined threshold is programmable.

11. The method of claim 1, further comprising detecting a rising edge of a pilot symbol.

12. The method of claim 11, further comprising detecting a flat region after detecting the rising edge.

13. The method of claim 12, further comprising setting a timer to detect a length of time of the flat zone.

14. The method of claim 13, further comprising resetting a counter and re-determining a next rising edge if the flat region is not detected.

15. The method of claim 13, further comprising comparing the flat region to values greater than and less than a threshold value.

16. The method of claim 15, further comprising initiating a falling edge detection sequence.

17. The method of claim 16, further comprising detecting pilot symbols based on the falling edge detection sequence.

18. The method of claim 17, further comprising determining a correlation value of I and Q supplied to an automatic frequency control component.

19. A correlator module for a wireless network system, comprising:

a time domain correlator processing a superframe field to detect a signal magnitude in the time domain; and

a threshold detector to use the signal magnitude to obtain a start synchronization signal for the superframe field.

20. The module of claim 19, further comprising at least one sample data buffer and one delayed sample buffer.

21. The module of claim 19, further comprising a complex multiplier component that processes pilot data.

22. The module of claim 19, further comprising at least one shift register FIFO to process pilot data.

23. The module of claim 19, further comprising a complex adder and a complex subtractor that process pilot data.

24. The module of claim 19, further comprising an amplitude component that determines the signal amplitude.

25. The module of claim 24, further comprising a comparator that determines a pilot start from the signal amplitude and a predetermined threshold.

26. The module of claim 25, further comprising a component for programming the predetermined threshold.

27. The module of claim 26, further comprising at least one state machine for determining a pilot start time.

28. The module of claim 19, having a machine-readable medium having stored thereon executable instructions for executing the time-domain correlator or the threshold detector.

29. A system for determining timing data in a wireless network, comprising:

means for analyzing the superframe to detect a signal amplitude in a time domain; and

means for detecting the signal amplitude to determine a start timing signal of the superframe.

30. A machine-readable medium having stored thereon machine-executable instructions, comprising:

processing the OFDM packet to detect a signal amplitude in a time domain; and

means for detecting the signal amplitude to determine a start timing signal for the OFDM packet.

31. A machine-readable medium having stored thereon a data structure, comprising:

a plurality of data fields storing correlation values from the OFDM broadcast packet;

a data field storing a threshold value for analyzing the OFDM broadcast packet; and

a comparator field to determine a starting sequence based in part on the threshold and the OFDM broadcast packet.

32. A wireless communications apparatus, comprising:

a memory comprising a component that determines a value of a time-domain correlator from a received OFDM broadcast; and

a processor that determines a start time by comparing a value of the time-domain correlator to a programmable threshold.

33. A processor that executes instructions for determining timing information for a wireless communication environment, the instructions comprising:

receiving an OFDM broadcast packet;

determining a time domain correlation for the OFDM broadcast packet; and

determining a start time synchronization for a wireless receiver based in part on the time domain correlation and at least one threshold.