HK1118135B

HK1118135B - Analog to digital converter with interference rejection capability

Info

Publication number: HK1118135B
Application number: HK08108975.4A
Authority: HK
Inventors: Seeteck Tan; Wenhuan Chen
Original assignee: O2 Micro International Limited
Priority date: 2006-07-14
Filing date: 2008-08-13
Publication date: 2012-08-31

Description

Analog-digital converter with anti-interference capability

Technical Field

The present invention relates to analog-to-digital converters (ADCs), and more particularly, to an ADC having interference rejection capability.

Background

Today, because of the proliferation of wireless communications, signals in the radio interface are subject to a wide variety of interference. In particular, Global Positioning System (GPS) applications potentially experience mixed interference of both narrowband and wideband interference. The nominal power of the signal at the antenna port of the GPS receiver is approximately-130 dBm and the thermal noise level is approximately-110 dBm. Thus, in normal operation, the received GPS signals are overlaid under the noise plane.

Fig. 1 is a block diagram of a prior art GPS receiver 100. Typically, the GPS signal and thermal noise are first converted to an Intermediate Frequency (IF) signal by a conventional RF filter, low noise amplifier, and down conversion mixer. Then, after the complex filtering process, the IF signal is further amplified by a Variable Gain Amplifier (VGA)110 and converted from an analog format to a digital format by a 2-bit analog-to-digital converter (ADC) 120. The amplified IF signal should have a voltage level that meets the dynamic range requirements of the ADC 120. In order to control the voltage level of the amplified IF signal, an Automatic Gain Control (AGC) loop 130 having a capacitor 140 is designed to adjust the gain of the VGA 110. VGA110, ADC 120, AGC loop 130, and capacitor 140 comprise a signal amplification and digitization circuit.

Fig. 2 is a schematic diagram of the signal amplification and digitization circuit of fig. 1. After being amplified by the VGA110 according to a predetermined gain, the IF signal is then converted into a digital quantity signal MGNA and a digital SIGN signal SIGN by the 2-bit ADC 120. The 2-bit ADC 120 includes a current source 121 and a current sink 123. When the output from the VGA110 is greater than the positive reference signal Vref or less than the negative reference signal-Vref, the current sink 123 will sink a current Iout from the capacitor 140. Otherwise, the current source 121 will provide a current Iout input to the capacitor 140. In steady state conditions, the DC voltage at capacitor 140 is constant and is fed back to VGA 110. This feedback loop is commonly referred to as an AGC loop and is used to adjust the predetermined gain. Typically, the time constant of the AGC loop must be in the order of milliseconds (ms), and thus the capacitance value of capacitor 140 must be in the order of nanofarads (nF). To have the large capacitance values described above, the capacitor 140 must be implemented off-chip as discrete, thus increasing the overall cost of the circuit.

After the foregoing processing, although thermal noise still exists, the baseband correlator 150 in fig. 1 can obtain an appropriate post-correlation signal-to-noise ratio (SNR) by correlating the digital signals MAGN and SIGN for a long period. However, for constant envelope Continuous Wave (CW) interference, the SNR degradation is much larger than that caused by thermal noise, so the GPS receiver must reduce the SNR degradation caused by CW before correlation processing. The interference is typically mitigated at the ADC 120. Also, the CW interference has more power than the thermal noise, so the AGC loop 130 should ensure that the gain of the VGA is varied over a dynamic range to maintain an optimum amount of signal at the input of the ADC 120.

It is therefore desirable to have an ADC with interference rejection capability that can directly implement the aforementioned AGC loop, so that no large external capacitance is required. The present invention is therefore directed to such an ADC and AGC method.

Disclosure of Invention

The present invention relates to an adaptive a/D conversion device of the following 1, wherein 2 to 11 are preferred embodiments of the adaptive a/D conversion device:

1. an adaptive a/D conversion apparatus for converting an analog signal into a digital signal, comprising:

a threshold generator capable of providing a first threshold signal and a second threshold signal;

a comparator circuit coupled to the threshold generator, the comparator circuit capable of comparing the analog signal to a first threshold signal and a second threshold signal to generate a digital quantity signal having a first state and a second state, the comparator circuit further capable of comparing the analog signal to a signature threshold signal to generate a digital signature signal;

a calculator coupled to the comparator circuit, the calculator being capable of calculating a percentage of the digital quantity signal in the first state during a predetermined period to produce an accumulated signal, the calculator being further capable of comparing the accumulated signal with a percentage threshold signal to produce a bit signal; and

an integrator coupled between the calculator and the threshold generator, the integrator being capable of providing a control signal to the threshold generator in response to a bit signal from the calculator and of adjusting the first threshold signal and the second threshold signal.

2. The adaptive a/D conversion apparatus according to 1, wherein the first and second threshold signals are adjusted by relatively changing by the same amount.

3. The adaptive a/D conversion device according to 1, wherein the first threshold signal defines an upper threshold and the second threshold signal defines a lower threshold, and the upper and lower thresholds are respectively higher and lower than the marking threshold by an equal absolute difference.

4. The adaptive a/D conversion apparatus according to 1, wherein the digital quantity signal is set to a first state when the analog signal is higher than a first threshold signal or lower than a second threshold signal; and the digital signal is set to a second state when the analog signal is between the first and second threshold signals.

5. The adaptive a/D conversion apparatus according to 1, wherein the calculator further includes:

an accumulator capable of calculating a digital quantity signal and providing an accumulation signal;

a comparator coupled to the accumulator, the comparator capable of comparing the accumulated signal to a percentage threshold signal and generating a comparison signal; and

a flip-flop coupled to the comparator, the flip-flop capable of sampling the comparison signal and generating a bit signal.

6. The adaptive a/D conversion apparatus according to claim 5, wherein the calculator further comprises a frequency divider for supplying a clock signal to the flip-flop.

7. The adaptive a/D converting apparatus according to claim 6, wherein a frequency of the clock signal is determined by a predetermined period, and the frequency determines a speed of generating the bit signal.

8. The adaptive a/D conversion apparatus according to claim 1, wherein the integrator further comprises:

a switch controller capable of receiving a bit signal and generating a first switch control signal and a second switch control signal;

a first switch coupled to the switch controller, the first switch capable of receiving a positive reference signal under control of a first switch control signal;

a second switch coupled to the switch controller, the second switch capable of receiving a negative reference signal under control of a second switch control signal, the second switch further coupled to the first switch; and

a discrete-time integrator coupled to the first and second switches, the discrete-time integrator capable of generating a control signal based on the first and second switch control signals and the positive and negative reference signals.

9. The adaptive a/D conversion apparatus according to 1, wherein the threshold generator further includes:

a converter capable of converting the control signal into a current signal;

a current mirror unit coupled to the converter, the current mirror unit capable of receiving the current signal and providing a first mirrored current and a second mirrored current;

a first resistor coupled to the current mirror unit, the first resistor capable of receiving the first mirror current and generating a first threshold signal; and

a second resistor coupled to the current mirror unit, the second resistor capable of receiving the second mirror current and generating a second threshold signal.

10. The adaptive a/D conversion apparatus according to claim 9, wherein the first resistance and the second resistance have equal resistance values.

11. The adaptive a/D conversion device of claim 9, wherein the first mirrored current is equal to the second mirrored current.

The present invention also relates to the following 12 a/D conversion apparatus adapted by an automatic gain control circuit of a variable gain amplifier, wherein 13-24 are preferred embodiments of the automatic gain control circuit of the variable gain amplifier:

12. an automatic gain control circuit for a variable gain amplifier, the variable gain amplifier having a predetermined gain and capable of generating a voltage signal according to the predetermined gain, the automatic gain control circuit comprising:

a comparator circuit coupled to the variable gain amplifier, the comparator circuit being capable of comparing the voltage signal from the variable gain amplifier with a first threshold signal and a second threshold signal to generate a digital quantity signal having a first state and a second state;

a calculator coupled to the comparator circuit, the calculator being capable of calculating a percentage of the digital quantity signal in the first state during a predetermined period to produce an accumulated signal, the calculator being further capable of comparing the accumulated signal to a percentage threshold to produce a bit signal; and

an integrator coupled between the calculator and the variable gain amplifier, the integrator being capable of providing a control signal in response to the bit signal from the calculator and of adjusting the predetermined gain of the variable gain amplifier.

13. The automatic gain control circuit of claim 12 wherein the first and second threshold signals are differential inputs.

14. The automatic gain control circuit of claim 12, wherein the digital signal is set to a first state when the voltage signal is above a first threshold signal or below a second threshold signal; and setting the digital quantity signal to a second state when the voltage signal is between the first and second threshold signals.

15. A circuit for digitizing an analog signal, wherein it comprises:

a variable gain amplifier capable of amplifying the analog signal according to a predetermined gain;

a comparator circuit coupled to the variable gain amplifier, the comparator circuit capable of comparing the amplified analog signal to a first threshold signal and a second threshold signal to produce a digital quantity signal having a first state and a second state, the comparator circuit further capable of comparing the amplified analog signal to a marking threshold to produce a digital marking signal;

a calculator coupled to the comparator circuit, the calculator being capable of calculating a percentage of the digital quantity signal in the first state over a predetermined period to produce an accumulated signal, the calculator being further capable of comparing the accumulated signal to a percentage threshold to produce a bit signal; and

16. The circuit of claim 15, wherein the first threshold signal determines an upper threshold, the second threshold signal determines a lower threshold, and the upper and lower thresholds are respectively above and below the marking threshold by equal absolute differences.

17. The circuit of claim 15, wherein the digital signal is set to a first state when the analog signal is above the first threshold signal or below the second threshold signal; and setting the digital quantity signal to a second state when the analog signal is between the first and second threshold signals.

18. A method for converting an analog signal to a digital signal with an adjustable voltage window, wherein the method comprises the steps of:

generating a first threshold signal and a second threshold signal for a voltage window;

comparing the analog signal with a first threshold signal and a second threshold signal to generate a digital quantity signal having a first state and a second state with respect to the voltage window, and comparing the analog signal with a signature threshold signal to generate a digital signature signal;

calculating the percentage of the digital quantity signal in the first state;

generating a bit signal based on the calculated percentage and the percentage threshold;

generating a control signal in response to the bit signal; and

the first and second threshold signals are adjusted under control of the control signal.

19. The method of claim 18, wherein the digital signal is set to a first state when the analog signal is outside the voltage window; and setting the digital quantity signal to a second state when the analog signal is within the voltage window.

20. The method of 18, wherein the first and second threshold signals are adjusted to be relatively changed by equal amounts.

21. The method of claim 18, further comprising the step of adjusting the predetermined gain of the variable amplifier under control of the control signal when the analog signal is provided by the variable gain amplifier according to the predetermined gain.

22. A method for controlling the gain of a variable gain amplifier, said variable gain amplifier producing an analog signal, wherein said method comprises the steps of:

comparing the analog signal with a first threshold signal and a second threshold signal to generate a digital quantity signal, the digital quantity signal having a first state and a second state based on the voltage window and the analog signal;

calculating the percentage of the digital quantity signal in the first state;

obtaining a bit signal based on the calculated percentage and the percentage threshold;

generating a control signal in response to the bit signal; and

the gain of the variable gain amplifier is adjusted under control of the control signal.

23. A receiver for receiving a radio frequency signal subject to interference, wherein the receiver comprises:

a conversion circuit for converting the radio frequency signal into an intermediate frequency signal;

a variable gain amplifier circuit coupled to the conversion circuit, the variable gain amplifier circuit capable of amplifying the intermediate frequency signal according to a predetermined gain;

an analog-to-digital converter coupled to the variable gain amplifier circuit, the analog-to-digital converter capable of converting the intermediate frequency signal from an analog format to a digital format, wherein the analog-to-digital converter comprises:

an adaptive threshold loop and a comparator circuit, wherein the adaptive threshold loop comprises:

a threshold generator, a calculator and an integrator;

the threshold generator is capable of providing a voltage window defined by a first threshold signal and a second threshold signal;

a comparator circuit coupled to the threshold generator, the comparator circuit being capable of comparing the intermediate frequency signal with a first threshold signal and a second threshold signal of the voltage window to generate a digital quantity signal having a first state and a second state, the comparator circuit being further capable of comparing the intermediate frequency signal with a flag threshold signal to generate a digital flag signal;

the calculator is coupled to the comparator circuit, the calculator can calculate the percentage that the digital quantity signal is in the first state in the predetermined cycle and produce a cumulative signal, the calculator can compare the cumulative signal with a percentage threshold signal and produce a bit signal; and

an integrator coupled between the calculator and the threshold generator, the integrator being capable of providing a control signal to the threshold generator in response to a bit signal from the calculator and of adjusting the first threshold signal and the second threshold signal of the voltage window to suppress interference in the intermediate frequency signal;

a baseband correlator coupled to the analog-to-digital converter, the baseband correlator capable of correlating the digital quantity signal and the digital signature signal.

24. The receiver of claim 23, wherein the control signal is fed back to the variable gain amplifier circuit for adjusting the predetermined gain.

In one embodiment, an adaptive analog-to-digital (A/D) conversion apparatus is provided for converting an analog signal to a digital signal. The A/D conversion apparatus includes a threshold generator, a comparator circuit, a calculator, and an integrator. The threshold generator is capable of providing a first threshold signal and a second threshold signal. The comparator circuit is coupled to the threshold generator and is capable of comparing the first threshold signal and the second threshold signal with the analog signal to generate a digital quantity signal. The comparator circuit is also capable of comparing the marking threshold signal with the analog signal to generate a digital marking signal. The calculator is coupled to the comparator circuit and is capable of calculating the digital quantity signal in a predetermined period and generating an accumulation signal. The calculator is further capable of comparing the accumulated signal with a percentage threshold signal and generating a bit signal. The integrator is coupled between the calculator and the threshold generator, and is capable of providing a control signal to the threshold generator in response to a bit signal from the calculator, and of adjusting the first threshold signal and the second threshold signal.

In yet another embodiment, an automatic gain control circuit for a variable gain amplifier is provided, which has a predetermined gain and is capable of generating a voltage signal according to the predetermined gain. The automatic gain control circuit includes a comparator circuit, a calculator, and an integrator. The comparator circuit is coupled to the variable gain amplifier and is capable of comparing the voltage signal from the variable gain amplifier with a first threshold signal and a second threshold signal to generate a digital quantity signal. The calculator is coupled to the comparator circuit and is capable of calculating the digital quantity signal in a predetermined period and generating an accumulation signal. The calculator is further capable of comparing the accumulated signal to a percentage threshold and generating a bit signal. The integrator is coupled between the calculator and the variable gain amplifier, and is capable of providing a control signal in response to a bit signal from the calculator and of adjusting a predetermined gain of the variable gain amplifier.

In another embodiment, a circuit for digitizing an analog signal is provided. The circuit includes a variable gain amplifier, a comparator circuit, a calculator, and an integrator. The variable gain amplifier is capable of amplifying an analog signal according to a predetermined gain. The comparator circuit is coupled to the variable gain amplifier and is capable of comparing the amplified analog signal to a first threshold signal and a second threshold signal to generate a digital quantity signal. The comparator circuit is also capable of comparing the amplified analog signal to a signature threshold to generate a digital signature signal. The calculator is coupled to the comparator circuit and is capable of calculating the digital quantity signal in a predetermined period and generating an accumulation signal. The calculator is further capable of comparing the accumulated signal with a percentage threshold and generating a bit signal. An integrator is coupled between the calculator and the variable gain amplifier, the integrator being capable of providing a control signal in response to a bit signal from the calculator and of adjusting a predetermined gain of the variable gain amplifier.

In another embodiment, a method for converting an analog signal to a digital signal with an adjustable voltage window is provided. The method includes the steps of generating a first threshold signal and a second threshold signal for a voltage window, converting the analog signal into a digital signature signal and a digital quantity signal, the digital quantity signal having a first state and a second state with respect to the voltage window, calculating a percentage of the digital quantity signal in the first state, generating a bit signal based on the calculated percentage and percentage threshold, generating a control signal in response to the bit signal, and adjusting the first and second threshold signals under control of the control signal.

In another embodiment, a method for controlling the gain of a variable gain amplifier that generates an analog signal is provided. The method includes the steps of generating a first threshold signal and a second threshold signal for a voltage window, generating a digital quantity signal having a first state and a second state based on the voltage window and the analog signal, calculating a percentage of the digital quantity signal that becomes the first state, obtaining a bit signal based on the calculated percentage and the percentage threshold, generating a control signal in response to the bit signal, and adjusting a gain of the variable gain amplifier under the control of the control signal.

In another embodiment, a receiver for receiving a Radio Frequency (RF) signal that is subject to interference is provided. The receiver includes a conversion circuit for converting the RF signal to an Intermediate Frequency (IF) signal, a Variable Gain Amplifier (VGA) circuit coupled to the conversion circuit and capable of amplifying the IF signal according to a predetermined gain, an analog-to-digital converter (ADC), and a baseband correlator. The ADC is coupled to the VGA circuit and is capable of converting the IF signal from an analog format to a digital format and generating a control signal based on the calculated percentage of the digitized IF signal. The ADC is also capable of suppressing interference in the IF signal under control of the control signal. A baseband correlator is coupled to the ADC and is capable of correlating the digitized IF signals.

Drawings

The benefits of the present invention will become apparent as the following detailed description of exemplary embodiments proceeds, and this description should be considered in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a prior art GPS receiver;

FIG. 2 is a schematic diagram of the ADC and AGC loop shown in FIG. 1;

FIG. 3 is a block diagram of a signal amplification and digitization circuit according to one embodiment of the invention;

FIG. 4 is a graph of the digitization strategy for the ADC shown in FIG. 3;

FIG. 5 is a schematic diagram illustrating analog-to-digital signal conversion using the ADC shown in FIG. 3;

FIG. 6 is a schematic diagram of a calculator according to an embodiment of the invention;

FIG. 7 is a schematic diagram of an integrator in accordance with one embodiment of the present invention;

FIG. 8 is a timing diagram of the integrator shown in FIG. 7;

FIG. 9 is a schematic diagram of a threshold generator according to one embodiment of the invention;

fig. 10 is a block diagram of a signal amplifying and digitizing circuit according to yet another embodiment of the present invention;

FIG. 11 is a block diagram of an ADC according to one embodiment of the present invention;

fig. 12 is a block diagram of an automatic gain control circuit according to an embodiment of the present invention;

FIG. 13 is a block diagram of a GPS receiver according to one embodiment of the invention; and

fig. 14 is a block diagram of a GPS receiver according to still another embodiment of the present invention.

Detailed Description

Fig. 3 shows a block diagram of the signal amplification and digitization circuit 200. In this circuit 200, in order to keep the output of VGA 100 constant and optimal, AGC loop 201 and capacitor 203 are connected to VGA 110. The VGA output is then converted from analog to digital by an ADC 205 with an adaptive threshold, the ADC 205 being able to suppress CW interference in the signal by adjusting the adaptive threshold. The ADC 205 herein includes a comparator circuit 210, a calculator 220, an integrator 230, and a threshold generator 240.

The VGA output mixed with the CW interference is first received by comparator circuit 210. Meanwhile, the negative threshold signal Vth _ N and the positive threshold signal Vth _ P generated by the threshold generator 240 are transmitted to the comparator circuit 210. While the constant mark threshold signal V _ sign is supplied to the comparator circuit 210. The mark threshold signal V sign indicates that the mark threshold is typically equal to 0V. Comparator circuit 210 includes comparators 211, 213, 215 and an OR gate 217. The comparator 211 compares the VGA output with the SIGN threshold signal V _ SIGN to generate a digital SIGN signal SIGN. The comparators 213 and 215 compare the VGA output with the positive threshold signal Vth _ p and the negative threshold signal Vth _ N, respectively, and then both comparison results are provided to the OR gate 217 to generate a digital quantity signal MAGN. Comparators 211, 213, and 215 also provide a clock signal for sampling the input signal.

The digital signal MAGN has two logic states: a logic 1 and a logic 0. The calculator 220 calculates the number of times when the digital quantity MAGN is at logic 1 in a predetermined period. The result of this calculation is then compared with the percentage threshold signal in calculator 220 to produce a bit signal. The percentage threshold signal represents a percentage threshold having a predetermined value, for example 33%. Typically, to ensure that the ADC 205 has the best interference rejection capability, the percentage threshold should be 30% to 40%. In response to the bit signal, the integrator 230 provides a control signal to the threshold generator 240. Finally, the threshold generator 240 may adjust the negative and positive threshold signals Vth _ N, Vth _ P according to the control signal.

There are two time constants in the circuit 200. One is AGCThe time constant of loop 201 and the time constant of ADC 205. The presence of these two time constants provides some flexibility in system design. Fig. 4 is a graph 202 illustrating the digitization strategy of the ADC of fig. 3. The marking threshold signal V _ sign determines a marking threshold, which is denoted T in horizontal coordinates₀The positive and negative threshold signals Vth _ P, Vth _ N determine an upper threshold and a lower threshold, respectively, which are respectively denoted as T on the horizontal coordinate₀+ Δ and T₀- Δ. It may be noted that the upper and lower thresholds are above and below the marking threshold, respectively, by an equal absolute difference.

As shown in fig. 4, there are four ADC output levels: + R, +1, -1, and-R. When the signal sampled by the ADC 205 is above the upper threshold T₀+ Δ, the digital signature signal SIGN and the digital quantity signal MIGN will be set to logic 1. In other words, samples that exceed the upper threshold are given a weight R in a baseband correlator (not shown) that performs the correlation function. Similarly, when the sample value is below the upper threshold T₀+ Delta but above the mark threshold T₀The digital signature signal SIGN and the digital MIGN signal are set to logic 1 and logic 0, respectively, and the sample value is given a weight of +1 in the baseband correlator. When the sampled value is lower than the mark threshold T₀And is higher than the lower threshold value T₀Delta, the digital signature signal SIGN and the digital quantity signal MIGN are set to logic 0, respectively, and the sample value is given a weight of-1 in the baseband correlator. When the sampling value is lower than the lower threshold value T₀Delta, the digital SIGN signal SIGN and the digital quantity signal MIGN are set to logic 0 and logic 1, respectively, and the sample value is given a weight-R in the baseband correlator.

To achieve optimal interference rejection, all samples having a magnitude covered by a voltage window defined by upper and lower thresholds should be excluded from the baseband correlator. Only those sample values that have sufficient magnitudes to exceed the voltage window are passed to the baseband correlator. Typically, the transfer percentage should be 30% to 40%. In other words, the percentage of the digital magnitude signal MAGN at logic 1 should be kept at 30% to 40%.

Fig. 5 is a schematic diagram 204 illustrating analog-to-digital signal conversion by the ADC 205 in fig. 3. As shown, the dashed curve 40 represents CW interference, while the solid curve 42 represents a signal mix of GPS signals, thermal noise, and CW interference. In this embodiment, the goal of the ADC 205 is to keep the digital magnitude signal MAGN at 33% of logic 1. To achieve this, an adaptive voltage window defined by upper and lower thresholds is provided to the ADC 205. The threshold generator 240 adjusts the voltage window by increasing the positive threshold signal Vth _ P and decreasing the negative threshold signal Vth _ N by the same magnitude when the control signal from the integrator 230 increases by a certain magnitude, or the threshold generator 240 adjusts the voltage window by decreasing the positive threshold signal Vth _ P and increasing the negative threshold signal Vth _ N by the same magnitude when the control signal decreases by a certain magnitude.

Fig. 6 shows a schematic diagram of the calculator 220 in fig. 3. The calculator 220 includes an N-bit accumulator 201, a digital comparator 203, a flip-flop 205, and a divider 207. The N-bit accumulator 201 is comprised of a digital adder 202 and a register 204. The N-bit accumulator 201 is capable of counting the number of times the digital quantity signal MAGN is set to logic 1. The calculated value is output as an accumulation signal. The N-bit accumulator 201 is also clocked by the same clock signal that is used to clock the comparator circuit 210 in fig. 2. If N equals 14 and the clock signal frequency is 16MHz, the calculation period lasts 1.024ms and the maximum value that the 14-bit accumulator 201 can count to is 16,384. Furthermore, given that the total number of bits is 16,384 per calculation cycle, the accumulated signal also indicates that the calculated digital magnitude signal MAGN is at a percentage of logic 1. The accumulated signal is then provided to a digital comparator 203 to compare it to a percentage threshold. If the target percentage of the digital quantity MAGN at logic 1 in the calculation cycle is 33%, the percentage threshold should be set to 5406, the number being 33% of the total number of bits 16,384. Finally, a comparison signal representing the comparison result is supplied from the digital comparator 203 to the flip-flop 205. Further, since the comparison at the digital comparator 203 is performed every 1.024ms, the clock signal is down-converted from 16MHz to 976KHz by the divider 207, and the down-converted clock signal is supplied to the flip-flop 205. Based on this comparison signal, the flip-flop 205 generates a bit signal Y.

Fig. 7 shows a schematic diagram of the integrator 230 in fig. 3. The integrator 230 includes a switch controller 231, switches 232 and 233, and a discrete-time integrator 237. Responsive to a bit signal Y and a pair of non-overlapping clocks phi₁And phi₂The integrator 237 generates a control signal Vth.

Fig. 8 shows a timing diagram of the integrator 230. By applying a bit-wise number Y and a clock phi₁Up and Y inverse signal and clock phi₁The upper distribution performs an AND operation, AND the switch controller 231 generates a first switch control signal AND a second switch control signal for alternately turning on the switches 232 AND 233. When the switch 232 is turned on, the positive reference voltage Vref is supplied to the discrete-time integrator 237 through the switch 232. The discrete-time integrator 237 sets the voltage level of the control signal Vth according to the positive reference voltage Vref. When the second switch 233 is turned on, the negative reference voltage-Vref is supplied to the discrete-time integrator 237 through the second switch 233. The discrete-time integrator 237 sets the voltage level of the control signal Vth according to the negative reference voltage-Vref.

Fig. 9 shows a schematic diagram of the threshold generator 240 in fig. 3. The threshold generator 240 includes a voltage applied to a current converter 241, resistors 243 and 245, and a current mirror unit formed of transistors 253, 257, 259 and 261. The voltage applied to the current converter 241 further includes a voltage follower composed of an operational amplifier 242 and a transistor 251. The voltage follower receives the control signal Vth and transfers the voltage of the control signal to a resistor 249 disposed between the voltage follower and ground. Yield equals Vth/R₃Current of (I)₃Then through a transistor 253 interposed between the voltage follower and the power supply VDD, where R₃Is defined as the resistance value of the resistor 249. In a current mirror unit, the current I₃And then reflected to resistor 243 via a current mirror comprised of transistors 253 and 255. The current I₃Further via a transistor 253,257. 259 and 261 mirror the current to resistor 245. When the definition is I₂When the mirror current of (1) flows through the resistor 243, a positive threshold signal Vth _ P can be obtained. When the definition is I₁When the mirror current of (1) flows through the resistor 245, the negative threshold signal Vth _ N can be obtained. In turn, the junction node of resistors 243 and 245 is also coupled to a common terminal 247 through which the common mode voltage Vcm is received.

When the transistors in the current mirror unit are matched with each other, and the resistance value R of the resistor 243₁Is also equal to the resistance value R of the resistor 245₂Then, the following formula 1) can be generalized.

1)

Referring to this equation 1), when the control signal Vth increases, the positive and negative threshold signals Vth _ P and Vth _ N will increase and decrease by the same amount, respectively, and when the control signal Vth decreases, the positive and negative threshold signals Vth _ P and Vth _ N will decrease and increase by the same amount, respectively.

Fig. 10 shows a block diagram of a signal amplification and digitization circuit 200'. In some environments, the IF signal is in the form of a differential input. Thus, the circuit 200' is specifically designed for this differential input. For the ADC of circuit 200 ', the differential inputs Vin + and Vin-are connected to the non-inverting and inverting terminals, respectively, of comparator 211' to generate the digital signature signal SIGN, and the comparators 213 and 215 are replaced by differential comparators 213 'and 215', respectively. Each differential comparator 213 'and 215' includes a first differential input pair and a second differential input pair. In contrast, the circuitry for these differential comparators should be redesigned. Specifically, the input Vin + and the negative threshold signal Vth _ N are provided to the non-inverting and inverting terminals, respectively, of the first differential input pair of the differential comparator 213'. The input Vin-and the positive threshold signal Vth _ P are provided to the inverting and non-inverting terminals, respectively, of the second differential input pair of the differential comparator 213'. The input Vin-and the negative threshold signal Vth _ N are provided to the non-inverting and inverting terminals, respectively, of a first differential input pair of the differential comparator 215'. The input Vin + and the positive threshold signal Vth _ P are provided to inverting and non-inverting terminals, respectively, of the second differential input pair of the differential comparator 215'.

Fig. 11 shows a block diagram of an exemplary ADC300 that implements both automatic gain control and interference suppression. The ADC300 further comprises a comparator circuit 210, a calculator 220, an integrator 230 and a threshold generator 240. However, the control signal Vth from the integrator 230 is directly fed back to the VGA110, and is used to adjust the gain of the VGA 110.

Specifically, when the calculated percentage of the digital quantity signal MAGN at logic 1 is below a predetermined percentage threshold, e.g., 33%, the gain is increased, otherwise the gain is decreased. It will be appreciated by those skilled in the art that the integrator 230 is here simply modified to ensure that the AGC loop is reversed. In addition, the threshold generator 240 receives a constant voltage signal Vcon and generates positive and negative threshold signals Vth _ P and Vth _ N, which are also constant in this case. By implementing the automatic gain control directly by the ADC300, the percentage of the digital quantity signal MAGN at logic 1 is eventually maintained at the percentage threshold, so that the CW interference is suppressed and at the same time the dynamic range requirements of the ADC300 are met.

Fig. 12 shows a block diagram of an exemplary AGC circuit 400. AGC circuit 400 implements automatic gain control in digital form so that large external capacitor 140 is not required. AGC circuit 400 may be used in conventional communication systems that use frequency or phase modulation, such as Frequency Shift Keying (FSK), Phase Shift Keying (PSK), and the like. In such conventional communication systems, the percentage threshold is set based on design considerations.

With respect to differential input signals, those skilled in the art will appreciate that the circuit of fig. 10 may be modified in the block diagrams of fig. 11 and 12. For clarity of the lines, detailed modifications are omitted here.

Fig. 13 shows a block diagram of the GPS receiver 500. GPS receiver 500 includes circuitry 510, signal amplification and digitization circuit 200, and baseband correlator 150. This circuit 510 is used to down-convert the RF signal to an IF signal after the RF signal continues to be bandpass filtered, low noise amplified, and mixed with the local carrier signal. The IF signal is provided to a signal amplification and digitization circuit 200, which includes an ADC 205, the ADC 205 including a comparator circuit 210 and an adaptive threshold loop 520, the adaptive threshold loop 520 being formed by a calculator 220, an integrator 230, and a threshold generator 240. The signal amplifying and digitizing circuit 200 provides the 2-bit digital signals MAGN and SIGN to the baseband correlator 150 for correlation processing.

Fig. 14 shows a block diagram of the GPS receiver 600. In the GPS receiver 600, the ADC300 is used. As previously described, the ADC300 includes the comparator circuit 210 and the AGC loop 610 for adjusting the gain of the VGA 110. The AGC loop 610 consists of the calculator 220 and the integrator 230.

In operation, the ADC 205 in fig. 3 converts the signal from analog to digital and simultaneously suppresses CW interference mixed in the signal. The ADC includes a comparator circuit 210, a calculator 220, an integrator 230, and a threshold generator 240. The comparator circuit 210 compares the signal to the positive and negative threshold signals provided by the threshold generator 240. Based on the result of the comparison, the signal is converted into digital signals MAGN and SIGN of 2 bits. The calculator 220 calculates a percentage of the digital quantity signal MAGN at logic 1 to generate a bit signal based on the calculated percentage. A control signal is then generated by the integrator 230 and provided to the threshold generator 240 in response to the bit signal and used to adjust the positive and negative threshold signals. With continuous adjustment, the calculated percentage is eventually kept at a predetermined percentage threshold, e.g., 33%, and the CW interference mixed in the signal is effectively suppressed by the ADC 205.

Alternatively, the control signal from integrator 230 may also be used to adjust the gain of VGA110, where VGA110 is placed before ADC300 as shown in fig. 11, while the positive and negative threshold signals remain constant. In this way, the CW interference mixed in the signal is also effectively suppressed, and at the same time, the AGC loop is constructed by directly connecting the ADC300 to the VGA 110.

In addition, the AGC circuit 400 may be implemented in a digital form as shown in fig. 12. In this case, the AGC circuit 400 can be used in a conventional communication system using frequency or phase modulation.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Other modifications, variations, and alternatives are also possible. The claims are therefore intended to cover all equivalents of the foregoing.

Claims

2. The adaptive a/D conversion device according to claim 1, characterized in that the first and second threshold signals are adjusted by relatively changing by the same amount.

3. The adaptive a/D conversion device of claim 1, wherein the first threshold signal defines an upper threshold, the second threshold signal defines a lower threshold, and the upper and lower thresholds are respectively higher and lower than the marking threshold by an equal absolute difference.

4. The adaptive a/D conversion apparatus according to claim 1, characterized in that the digital quantity signal is set to the first state when the analog signal is higher than the first threshold signal or lower than the second threshold signal; and the digital signal is set to a second state when the analog signal is between the first and second threshold signals.

5. The adaptive a/D conversion apparatus according to claim 1, wherein the calculator further comprises:

6. The adaptive a/D conversion device of claim 5, wherein the calculator further comprises a frequency divider for providing a clock signal to the flip-flop.

7. The adaptive a/D conversion device according to claim 6, characterized in that the frequency of the clock signal is determined by a predetermined period, and the frequency determines the speed at which the bit signal is generated.

9. The adaptive a/D conversion apparatus according to claim 1, wherein the threshold generator further comprises:

a converter capable of converting the control signal into a current signal;

10. The adaptive a/D conversion device of claim 9, wherein the first and second resistors have equal resistance values.

11. The adaptive a/D conversion device of claim 9, wherein the first image current is equal to the second image current.

14. The automatic gain control circuit of claim 12 wherein the digital signal is set to the first state when the voltage signal is above the first threshold signal or below the second threshold signal; and setting the digital quantity signal to a second state when the voltage signal is between the first and second threshold signals.

15. A circuit for digitizing an analog signal, comprising:

17. The circuit of claim 15, wherein the digital signal is set to the first state when the analog signal is above the first threshold signal or below the second threshold signal; and setting the digital quantity signal to a second state when the analog signal is between the first and second threshold signals.

18. A method for converting an analog signal to a digital signal with an adjustable voltage window, the method comprising the steps of:

calculating the percentage of the digital quantity signal in the first state;

generating a control signal in response to the bit signal; and

19. The method of claim 18, wherein the digital signal is set to the first state when the analog signal is outside the voltage window; and setting the digital quantity signal to a second state when the analog signal is within the voltage window.

20. The method of claim 18, wherein the first and second threshold signals are adjusted to vary relatively by equal amounts.

22. A method for controlling the gain of a variable gain amplifier that produces an analog signal, the method comprising the steps of:

calculating the percentage of the digital quantity signal in the first state;

generating a control signal in response to the bit signal; and

23. A receiver for receiving a radio frequency signal subject to interference, the receiver comprising:

a threshold generator, a calculator and an integrator;