HK1118133B - Dc-dc converter and method - Google Patents

Description

DC-DC converter and method

Technical Field

The present invention relates generally to regulator circuits and more particularly to DC converters.

Background

Battery operated devices such as mobile phones, portable computers, calculators, video cameras, Personal Digital Assistants (PDAs), video game controllers, etc. typically include a DC-DC converter that produces a constant supply voltage at a load. Although a constant voltage is provided at the load, the battery voltage decreases as the battery discharges. These circuits include switches that alternately connect inductors between the battery and the load and between the load and ground using low loss switches, which typically operate at a fixed frequency. In other words, the circuit switches the connection such that during one portion of the clock cycle the inductor is connected between the battery and the load, and during another portion of the clock cycle the switch connects the inductor between the load and ground. Alternatively, they can alternately connect inductors between the battery and ground and between the load and ground. The load is shunted by a large capacitor that absorbs the alternating current ("AC") component, which causes the load voltage to have low ripple.

The DC-DC converter includes a negative feedback loop that conforms a portion of the load voltage to the reference voltage by modifying the duty cycle of the switch. Stabilizing the negative feedback loop is difficult because it includes an inductor and a shunt capacitor and operates with a wide range of load currents. One technique for stabilizing the feedback loop includes designing the loop with two comparators in series, where a first comparator generates a current output in response to the load voltage error, and a second comparator controls the duty cycle of the switch to adapt the peak inductor current to the output of the first comparator. This technique is called current mode control or current programmed control.

During the time interval in which the inductor is connected across the load, its current may reverse if the load current is too low. To prevent this from occurring, a third comparator may be included in the feedback loop.

Current circuits typically use Complementary Metal Oxide Semiconductor (CMOS) technology to fabricate the comparator. The technique provides a comparator with low loss switching and that can enter a low power standby mode. However, they use many expensive resistors to limit the current of the controller circuit. Furthermore, the fabrication of expensive resistors using CMOS technology consumes large areas of semiconductor material. The use of large areas also introduces large parasitic capacitances, which are undesirable because they reduce switching speed and increase power consumption of CMOS devices.

Therefore, there is a need for a DC-DC converter and a method of compensating for offset errors in a DC-DC converter. Cost and time efficient manufacturing is advantageous for DC-DC converters.

Brief description of the drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference designators refer to like elements, and in which:

FIG. 1 is a schematic diagram of a DC-DC converter according to an embodiment of the invention;

FIG. 2 is a timing diagram for the DC-DC converter of FIG. 1;

FIG. 3 is a schematic diagram of a portion of the DC-DC converter of FIG. 1 configured to operate in an offset correction mode of operation;

FIG. 4 is a schematic diagram of a portion of the DC-DC converter of FIG. 3 configured to operate in a normal operating mode;

FIG. 5 is a schematic diagram of another portion of the DC-DC converter of FIG. 3 configured to operate in an offset correction mode of operation;

FIG. 6 is a schematic diagram of a portion of the DC-DC converter of FIG. 5 configured to operate in a normal operating mode;

FIG. 7 is a schematic diagram of another portion of the DC-DC converter of FIG. 1;

FIG. 8 is a schematic diagram of a DC-DC converter according to another embodiment of the invention; and

fig. 9 is a schematic diagram of a zero crossing detection circuit portion of the DC-DC converter of fig. 8.

Detailed Description

The present invention generally provides a switched DC-DC () "DC-DC ") converter capable of receiving an input voltage V from a battery_BATTAnd provides a regulated output voltage having a lower voltage level. According to one embodiment, the present invention includes a DC-DC converter having an inductor with one terminal coupled to receive an input power signal through a plurality of switches and another terminal coupled to a load. The switch repeatedly operates at a desired clock frequency and has a transition instant (commutation instant) in response to a signal generated from the control circuit. The control circuit has two circuit paths each consisting of a plurality of circuit elements and adjusts the load voltage to have a desired relationship with the reference voltage. The circuit paths operate such that one or more circuit elements of either path may be temporarily switched to an error correction mode while elements of the other path remain in a normal operating mode. This allows eliminating errors related to circuit elements without limiting the state of the switch. Preferably, during a first part of the first clock cycle, the elements of the path operate in the error correction mode, and during the remaining part of the first clock cycle and all subsequent or second clock cycles, the elements of the path operate in the normal mode. The outputs from the circuit elements are selected during a second clock cycle. An advantage of this embodiment is that transient interference effects resulting from a transition from the error correction mode to the normal operation mode are substantially eliminated.

According to another aspect, each circuit path includes a voltage comparator that generates an output in response to a difference between a portion of the load voltage and an applied reference voltage. The voltage comparator preferably comprises a circuit element with a filter adapted to stabilize (gate) the loop with dynamic behavior. The filter is coupled to provide an output signal component that is common to both circuit paths and is derived by integrating the signals that are equally generated from the input signals of the circuit elements of both comparators. Further, each circuit path includes a second comparator responsive to a difference between the output signal from the voltage comparator and a signal representative of the charge provided to the load during the concurrent clock cycles. The output of the second comparator commutates the switch.

According to another aspect, the voltage developed across the capacitor acts as a signal representative of the charge provided to the load. The capacitor is discharged at the beginning of each clock cycle and is charged by a current proportional to the current flowing through the inductor.

According to another aspect, the constant current combines a current proportional to a current flowing through the inductor to suppress circuit oscillation. The constant current has a magnitude derived from the input and load voltages.

It should be noted that the term "configuration" is used to describe the switch position. Thus, the switch may be configured to connect the changeover terminal of the switch to another circuit element, i.e. the switch is closed, or the switch may be configured to disconnect the changeover terminal from another circuit element, i.e. the switch is open.

Fig. 1 is a schematic diagram of a DC-DC converter 10 according to an embodiment of the invention. Shown in fig. 1 are a plurality of switched capacitor ("SC") comparators 12, 14, 16, and 18, a selector circuit 20, a driver circuit 22, and a voltage balancing circuit 24. SC comparators 12, 14, 16, and 18, selector circuit 20, and driver circuit 22 cooperate to form control circuit 23. SC comparators 12 and 16 form part of a circuit path or signal, while SC comparators 14 and 18 form part of a circuit path or signal. Further, the DC-DC converter 10 includes a plurality of transistors 26, 28, 30, and 32, and an integration capacitor 46. More particularly, SC comparator 12 has a comparator coupled to receive a reference voltage V_REF12 is input to₁And an input 12 coupled to an output node 34₂An input coupled to receive the clock signal CALA, an input coupled to receive the clock signal ACTA, and an input 16 connected to the SC comparator 16₂To output of (c). SC comparator 14 has a comparator coupled to receive a reference voltage V_REFInput 14 of₁And an input 14 coupled to an output node 34₂An input coupled to receive a clock signal CALB, an input coupled to receive a clock signal ACTB, and an input 18 connected to SC comparator 18₂To output of (c). Preferably, SC comparators 12 and 14 are matched to each other and include an attenuation element, a comparator element, and a filter element. SC comparators 12 and 14 are further described with reference to fig. 3 and 4. SC comparator 16 has a capacitor coupled to receive input voltage V_INTInput 16 of₁An input coupled to receive the clock signal CALA, an input coupled to receive the clock signal ACTA, and an output connected to an input of the selector circuit 20. The SC comparator 18 has a capacitor coupled to receive the input voltage V_INTInput 18 of₁An input coupled to receive a clock signal CALB, an input coupled to receive a clock signal ACTB, and an output connected to another input of selector circuit 20.

Selector circuit 20 has an output connected to driver circuit 22, an input connected to the output of SC comparator 16, an input connected to the output of SC comparator 18, and an input coupled to receive clock signal CLK/2. The clock signal CLK/2 has a frequency that is the master clock signal CLK provided by the master clock 50_MATRHalf of that.

Driver circuit 22 has an input connected to the output of selector circuit 20, an output connected to the gates of transistors 26 and 28, an output connected to the gate of transistor 30, an output connected to the gate of transistor 32, and an output coupled to receive a master clock signal CLK from a master clock 50_MATRIs input. According to one embodiment, transistors 26 and 28 are P-channel field effect transistors ("FETS") and transistors 30 and 32 are N-channel FETS. Each FET has a source, a drain and a gate. The source and drain are also referred to as current carrying electrodes and the gate is also referred to as a control electrode. The drains of transistors 26 and 28 are connected to respective inputs of voltage balancing circuit 24. A source of transistor 26 is connected to a source of transistor 28 and a drain of transistor 26 is connected to a drain of transistor 30, an input of voltage balancing circuit 24 and to output node 34 through an energy storage element 36. By way of example, the energy storage element 36 is an inductor. The sources of commonly connected transistors 26 and 28 are coupled to receive an operating voltage source, such as a voltage V_BATT. The source of transistor 30 is coupled to receive a source of operating voltage, e.g. electricityPressure V_SS. As an example, V_SSIs the ground voltage.

The output of voltage balancing circuit 24 is connected to the drain of transistor 32 and the output of driver circuit 22 is connected to the gate of transistor 32. The voltage balancing circuit 24 also has an input coupled to receive the clock signal CALA and an input coupled to receive the clock signal CALB. The source of transistor 32 is coupled to receive an operating voltage source, e.g., V_SS. An energy storage element 46, such as a capacitor, is coupled across transistor 32, i.e., one terminal of capacitor 46 is connected to the source of transistor 32 and one terminal of capacitor 46 is connected to the drain of transistor 32.

Clock signals CALA, ACTA, CALB, ACTB, and CLK/2 are coupled to receive a master clock signal CLK from a master clock 50_MATRIs generated by the clock generator.

A load 40 is coupled between the output node 34 and an operating voltage source, e.g., V_SSIn the meantime. By way of example, the load 40 includes a resistor 42 in parallel with a capacitor 44.

In operation, the battery V_BATTCoupled between the power supply terminal 15 and the reference terminal 35. More particularly, a battery V_BATTIs connected to the sources of commonly connected transistors 26 and 28, while the negative terminal is coupled to receive an operating voltage source, e.g., V_SS. As an example, the voltage source V is operated_SSAnd (4) grounding. SC comparators 12 and 14 are coupled to receive a load voltage V_LOADAnd a reference voltage V_REF. Load voltage V_LOADAlso referred to as the converter output signal. SC comparator 12 is coupled to receive clock signals CALA and ACTA, and SC comparator 14 is coupled to receive clock signals CALB and ACTB. The master clock 50 converts the master clock signal CLK_MATRTo the driver circuit 22 and to the clock generator 38. In response to a master clock signal CLK_MATRThe clock generator 38 generates clock signals CALA, ACTA, CALB, ACTB, and CLK/2. The clock signals CALA and CALB determine the error compensation interval, while the clock signals ACTA and ACTB serve as enable signals for the SC comparators 12 and 14, respectively. Clock signals CALA, ACTA, CALB and ACTBIn operation, SC comparators 12 and 14 are placed at their pair voltage V_LOADAnd V_REFThe status of the response. As an example, SC comparators 12 and 14 are responsive to logic high states of clock signals CALA, ACTA, CALB, and ACTB. The clock signal CLK/2 has a master clock signal CLK_MATRHalf of the frequency of (c).

The filter elements of the SC comparators 12 and 14 are coupled together by an interconnection 17 so that their output signals have a common component resulting from the integration of the combined input error signals. This allows the output signals of SC comparators 12 and 14 to settle over any portion of their achievable range with negligible error between the attenuated steady state load voltage and the reference voltage. According to an embodiment of the present invention, SC comparators 12 and 14 are inverted so that they produce an increased output voltage when the attenuated load voltage is lower than the reference voltage.

Referring now to FIG. 2, the clock signals CALA, ACTA, CALB, ACTB, CLK/2 and the master clock signal CLK are shown_MATRTiming diagram 60 of (a). Clock signals CALA, ACTA, CALB, ACTB, and CLK/2 are coupled to receive a master clock signal CLK from a master clock 50_MATRIs generated by the clock generator 38. According to the present example shown in timing diagram 60, master clock 50 has a clock period of 0.2 microseconds (μ s). The clock signal CLK/2 has a period of 0.4 mus. The time interval of the clock signal CALA during the first portion of one set of alternating clock cycles is high and the time interval of the clock signal CALB during the first portion of another set of alternating clock cycles is high. The portion of the clock cycle of the group during which clock signal CALA is high is referred to as an odd cycle, and the portion of the clock cycle of the group during which clock signal CALB is high is referred to as an even cycle. The clock signal ACTA is high for a period of time during the odd cycle after the clock signal CALA returns to zero and extends to the end of the following even cycle. Likewise, clock signal ACTB is high for a period of time after clock signal CALB returns to zero and extends to the end of the following odd cycle.

Reference voltage V_REFApplied to input 12₁And 14₁And is loadedVoltage V_LOADFrom output node 34 back to input 12₂And 14₂. Input 16₁And 18₁Is coupled to receive a voltage V appearing across capacitor 46_INT. Voltage V_INTAlso known as internal reference signals. Comparators 12 and 16 receive the same clock signals, i.e., clock signals CALA and ACTA, while comparators 14 and 18 receive the same clock signals, i.e., clock signals CALB and ACTB. SC comparators 12 and 14 cause load voltage V fed back from node 34_LOADAttenuating, comparing the attenuated signal with a reference voltage V as a zero offset comparator_REFAnd filters the comparison signal to generate filtered output signals that are transmitted to SC comparators 16 and 18, respectively. Responsive to load voltage V_LOADAnd a reference voltage V_REFThe SC comparators 12 and 14 filtering the input signal V for the difference between them_REFAnd a feedback signal to produce an integrated output signal. The output signals of the SC comparators 12 and 14 are also referred to as control path signals or secondary signals. More particularly, SC comparator 12 attenuates and filters converter output or load signal V_LOADAnd a reference signal V_REFThe attenuated and filtered load signal is then compared to the attenuated and filtered reference signal and an offset error correction signal is introduced to generate the secondary signal from the SC comparator 12. Likewise, SC comparator 14 attenuates and filters converter output or load signal V_LOADAnd a reference signal V_REFThe attenuated and filtered load signal is then compared to the attenuated and filtered reference signal and an offset error correction signal is introduced to generate the secondary signal from the SC comparator 14. Thus, SC comparators 12 and 14 are responsive to load voltage V_LOADAnd a reference voltage V_REFThe difference between them to produce an output.

SC comparators 16 and 18 serve as a second set of zero offset comparators that compare the output signals from SC comparators 12 and 14, i.e., the secondary signals, to a voltage V_INTI.e., the voltage developed across capacitor 46. In addition to comparing the secondary signals, the SC comparators 16 and 18 also introduce an offset error correction signal into the signals. Thus, comparator 16 compares the secondary signal from SC comparator 12, introduces an offset error correction signal, and outputs the secondary signal. Similarly, ratioComparator 18 compares the secondary signal from SC comparator 14, introduces an offset error correction signal, and outputs the secondary signal. The combination of the secondary signals from SC comparators 12 and 16 forms one path signal and the combination of the secondary signals from SC comparators 14 and 18 forms the other path signal.

Selector circuit 20 is clocked to select between the path signals of SC comparators 12 and 16 or between the path signals of SC comparators 14 and 18 to produce an output signal that is the selected path signal.

At the beginning of each clock cycle, the capacitor 46 is discharged in response to the short pulses generated by the driver circuit 22. After being discharged, capacitor 46 is charged by a map of the current flowing through transistor 26. Voltage balancing circuit 24 uses the current flowing through transistor 28 to generate image current I_IMAGEWhich is generally much smaller than the current flowing through transistor 28 and proportional to the current flowing through inductor 36. Thus, the driver circuit 22 generates the driving signal to generate the image current I_IMAGEWhich is a map of the current flowing through transistor 28. Voltage balancing circuit 24 ensures that the current flowing through transistor 28 matches the current flowing through transistor 26 by closely matching the voltages at the drains of transistors 26 and 28 during the time interval in which they are conducting. Thus, the voltage across capacitor 46 acts as a signal representing the charge applied to the load during the concurrent clock cycles. In addition to discharging capacitor 46 at the beginning of each clock cycle, driver circuit 22 is also switched to apply a logic low voltage to the gates of transistors 26, 28, and 30.

In response to the output signal from the selector circuit 20, the driver circuit 22 changes or converts the voltage appearing at its output. Thus, the voltage at the gates of transistors 26, 28, and 30 changes from a logic low voltage level to a logic high voltage level, thus turning off transistors 26 and 28 and turning on transistor 30. Therefore, transistor 26 conducts current between the beginning and transition instants of each clock cycle, and transistor 30 conducts current from the transition instant until the end of the clock cycle. Driver circuit 22 includes means for inhibiting both transistors 26 and 30 from conducting simultaneously, and means for providing a short pulse to the gate of transistor 32 at the beginning of each clock cycle that discharges capacitor 46.

The output signals of the comparators 16 and 18 are alternately selected by the selector circuit 20 in response to the clock signal CLK/2. Therefore, the output signal of the selector circuit 20 is also referred to as a selection signal. The output signal from comparator 16 is selected during even clock cycles when clock signal ACTA remains high, and the output from comparator 18 is selected during odd clock cycles when clock signal ACTB remains high. The transition transients generated by comparators 12 and 16 decay during the portion of the odd clock cycle in which clock signal ACTA is high. Likewise, the transition transients generated by comparators 14 and 18 decay during portions of the even clock cycle in which clock signal ACTB is high. Thus, the output from selector circuit 20 is always responsive to voltage V_LOAD、V_REFAnd V_INTAnd is independent of offset errors in the circuit and the absence of glitches.

Assuming an input voltage V_BATTLoad voltage V_LOADAnd a load current I_LOADIs selected so that inductor 36 does not reverse the direction of its current conduction and the DC-DC converter is stable, i.e. the voltage V_LOADLess than the battery voltage V_BATTHalf of each clock cycle, capacitor 46 will be charged from zero voltage by a map of the current flowing through inductor 36 at the beginning of each clock cycle, which is transferred from transistor 26 under steady state conditions. Capacitor 46 is charged to a voltage that matches the output voltage of SC comparator 12, at which point SC comparator 16 applies a signal to driver circuit 22 that causes transistor 26 to become non-conductive and transistor 30 to become conductive to maintain the current flowing into inductor 36.

The total charge delivered to the load is proportional to the charge provided by transistor 26 and monotonically increases over a fraction of the clock cycle, with transistor 26 remaining on and conducting current for that cycle. Under steady state conditions, the transition from transistor 26 being conductive to transistor 30 becoming conductive occurs during the portion of each clock cycle during which power is supplied to the loadConstant load voltage V_LOADThe charges of (a) and (b) coincide. Because integrating capacitor 46 receives a map of the current flowing into transistor 26, it receives a map of the total charge provided by transistor 26 during its conduction time interval. Thus, in steady state conditions, the output voltages of the SC comparators 12 and 14 are proportional to the charge provided to the load per clock cycle, and thus to the load current I_LOADAnd (4) in proportion. This linearity is an advantage of a DC-DC converter configured in accordance with the present invention. Another advantage is that when the load voltage V is attenuated_LOADAnd a reference voltage V_REFAt the same time, the output voltages of the SC comparators 12 and 14 are stable because they include integrating filters. Thus, the DC-DC converter is stabilized to a well-defined load voltage V_LOADAnd with the load current I_LOADIs irrelevant.

For dynamic behaviour, e.g. load current I_LOADIs increased to generate a load voltage V_LOADThis causes the output voltages of the SC comparators 12 and 14 to increase. Before switches 26 and 30 switch, integrating capacitor 46 charges to a higher voltage, resulting in a higher current being provided to load 40. The circuit is operated with a constant load voltage V_LOADStabilizes, but at a higher output voltage from SC comparators 12 and 14, and increases the conduction period of transistor 26. Similarly, a load voltage V is generated_LOADOf the instantaneous increase of the load current I_LOADThe output voltages of the SC comparators 12 and 14 are reduced. Before switches 26 and 30 switch, integrating capacitor 46 charges to a lower voltage, resulting in a lower current being provided to load 40. The circuit is operated with a constant load voltage V_LOADStabilizes, but at a lower output voltage from SC comparators 12 and 14, and reduces the conduction period of transistor 26.

Fig. 3 is a schematic diagram of SC comparators 12 and 14 according to an embodiment of the present invention, with SC comparators 12 and 14 configured to operate in an offset correction mode. Although the SC comparators 12 and 14 are preferably identical in structure, their input terminals 12₁、12₂、14₁And 14₂Are identified by different reference symbols because they are shown in fig. 1The discrete components of the DC-DC converter 10. Fig. 3 shows a three-terminal switch S41 having one as input 12₂、14₂One coupled to receive a signal such as V_SSAnd a terminal coupled to one terminal of capacitor C41. The other terminal of capacitor C41 is coupled to one terminal of capacitor CVL, one terminal of two-terminal switch S42, and a first terminal of three-terminal switch S43. The other terminal of capacitor CVL is coupled to receive an operating voltage source, e.g., V_SS. A second terminal of three-terminal switch S43 serves as respective inputs 12 of SC comparators 12 and 14₁、14₁And a third terminal of the switch S43 is coupled to one terminal of the capacitor C42 and the first terminal of the three-terminal switch S45. The second terminal of the capacitor C42 is coupled to the inverting input G41 of the transconductor G41_I1And one terminal of two-terminal switch S44. The transconductor G41 also has a terminal coupled to receive an operating voltage source V_SSNon-inverting input G41_I2Coupled to receive a signal such as V_SSOperating voltage source output G41_O1And an output G41 connected to the second terminal of the switch S44 and the first terminal of the three-terminal switch S46_O2. The third terminal of the three-terminal switch S46 is coupled to the third terminal of the three-terminal switch S45 through a capacitor C43. A second terminal of the switch S45 is coupled to a second terminal of the switch S46 through a capacitor C44. The commonly connected terminal of the capacitor C43 and the third terminal of the switch S46 serves as the outputs of the comparators 12 and 14. Although element G41 is shown and described as a transconductor, this is not a limitation of the present invention. The transconductor G41 may be an inverter, a comparator, etc. Likewise, the switches S41, S42, S43, S44, S45, and S46 may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), transmission gates, and the like. It should be noted that SC comparator 12 and SC comparator 14 each have a capacitor C44, which are connected together in parallel. Thus, SC comparator 12 and SC comparator 14 are coupled together through capacitor C44. This connection is represented in fig. 1 by the interconnection 17.

Fig. 4 is a schematic diagram of SC comparators 12 and 14 shown in fig. 3 configured to operate in an active mode. In other words, the circuit configuration of fig. 4 is the same as that of fig. 3 except that the switches S41, S42, S43, S44, S45, and S46 are in different positions.

The positions of switches S41, S42, S43, S44, S45, and S46 are set by clock input signals CALA and ACTA of SC comparator 12 and by clock input signals CALB and ACTB of SC comparator 14. By way of example, SC comparator 12 operates in an offset correction mode when clock input signal CALA is in a logic high state, and SC comparator 14 operates in an offset correction mode when clock input signal CALB is in a logic high state. Similarly, when the clock input signal ACTA is in a logic high state, the SC comparator 12 operates in an active mode, and when the clock input signal ACTB is in a logic high state, the SC comparator 14 operates in an active mode.

Referring again to fig. 3, SC comparator 12 operates in the offset correction mode when clock input signal CALA is in a logic high state, and SC comparator 14 operates in the offset correction mode when clock input signal CALB is in a logic high state. In this mode, switches S41 and S42 are configured such that the terminals of capacitor C41 are coupled to receive an operating voltage source, e.g., V_SS. Switch S43 is configured such that one terminal of capacitor C42 is connected to input 12₁、14₁And the switch S44 is configured such that the other terminal of the capacitor C42 is connected to the output G41 of the transconductor G41_O2. The switches S45 and S46 are configured such that the capacitors C43 and C44 are in parallel. In this configuration, switches S41, S42, and S44 are set to discharge capacitors C41 and CVL. In addition, the capacitor C43 and the output G41 of the transconductor G41_O2Disconnected and connected in parallel with a pair of integrating capacitors C44. It should be noted that capacitor C44 is represented in a complex sense as it relates to capacitor 44 present in SC comparators 12 and 14. The input coupling capacitor C42 is coupled to receive a reference voltage V_REFIt is charged to be at a reference voltage V_REFAnd the inverting input G41 of transconductor G41_I1The difference between the voltages on them to adjust its output current to zero. The charge stored in the capacitor C43 in the previous active mode combines with the charge stored in the capacitor C44.

As in aboveAs discussed herein, SC comparator 12 operates in an active mode when clock input signal ACTA is in a logic high state, and SC comparator 14 operates in an active mode when clock input signal ACTB is in a logic high state. In this mode, switches S41, S42, and S45 are configured such that one terminal of capacitor C41 is coupled to receive load voltage V_LOADAnd the other terminal of the capacitor C41 is connected to capacitors CVL, C42, and C43. The switch S46 is configured such that the other terminal of the capacitor C43 is connected to the output G41 of the transconductor G41_O2. The switch S44 is configured to connect the capacitor C42 with the output G41_O2The connection is broken. In this mode, if the voltage applied to the first terminal of capacitor C42 remains equal to the reference voltage V_REFThe output current of the transconductor G41 remains at zero. According to the law of conservation of charge, when:

V_LOAD＝(1+C_CVL/C_C41)*V_REF EQT.1

when the condition is satisfied. Wherein:

C_C41equal to the capacitance of capacitor C41; and

C_CVLequal to the capacitance of capacitor CVL.

If the output voltage of the DC-DC converter 10 is different from the value given by eqt.1, some charge will be transferred from the capacitor C41 in each active period. If the transconductance coefficient of transconductor G41 is sufficient, this charge will be provided by feedback capacitor C43, altering its voltage from the integrated value established in the previous offset correction mode.

Fig. 5 is a schematic diagram of SC comparator 16 and portion 21 of selector circuit 20 configured to operate in an offset compensation mode according to an embodiment of the present invention. The offset compensation mode is also referred to as an error correction mode. FIG. 5 shows a three-terminal switch S52 having a terminal coupled to receive an input voltage V_INTCoupled to receive a signal such as V_SSAnd a third terminal coupled to one terminal of capacitor C51. Capacitor C51A terminal coupled to the non-inverting input G51 of the balanced input transconductor G51_I1And a first terminal of two-terminal switch S54. The other terminal of the two-terminal switch S54 is coupled to receive a voltage source V_MIN. The balanced input transconductor G51 has an inverting input G51_I2Coupled to a first terminal of the three-terminal switch S53 and a first terminal of the capacitor C52. A second terminal of the three-terminal switch S53 is coupled to receive an operating voltage source, e.g., V_SS. The third terminal of the three-terminal switch S53 is connected to one terminal of a capacitor C53, while the other terminal of the capacitor C53 is commonly connected to the second terminal of the capacitor C52. The commonly connected terminal of capacitors C52 and C53 is connected to the third terminal of three-terminal switch S51. A first terminal of the three-terminal switch S51 is coupled to receive a control voltage V_CTRLAnd a second terminal of the three-terminal switch S51 is coupled to receive an operating voltage source, e.g., V_SS. The SC comparator 16 includes switches S51, S52, S53, and S54, capacitors C51 and C52, and a balanced input transconductor G51. Although element G51 is shown and described as a transconductor, this is not a limitation of the present invention. The transconductor G51 may be an inverter, a comparator, etc. Likewise, the switches S51, S52, S53, S54, and S55 may be Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), transmission gates, or the like.

The portion 21 of the selector circuit 20 shown in fig. 5 is a three-terminal switch S55 having an inverting input G51 connected to a balanced input transconductor G51_I2A second terminal connected to the input 114 of a two-input nand gate U51, and an output G51 connected to a balanced input transconductor G51_O2And a third terminal of (2). The inputs 116 of the two-input NAND gate U51 are coupled to receive the clock signal CLK/2. The balanced input transconductor G51 is also coupled to receive a signal such as V_SSSecond output G51 of the operating voltage source_O1。

Fig. 6 is a schematic diagram of SC comparator 16 and portion 21 of selector circuit 20 shown in fig. 5 configured to operate in an active mode. In other words, the circuit configuration of fig. 6 is the same as that of fig. 5 except that the switches S51, S52, S53, S54, and S55 are in different positions.

The positions of the switches S51, S52, S53, S54, and S55 are set by the clock input signals CALA and ACTA. In particular, when the clock input signal CALA is in a logic high state, SC comparator 16 operates in an offset correction mode, and when the clock input signal ACTA is in a logic high state, SC comparator 16 operates in an active mode.

In the offset correction mode, the switches S52 and S54 are configured such that one terminal of the capacitor C51 is coupled to receive the operating voltage source V_SSAnd input G51_I1Is coupled to receive a voltage V_MIN. Switches S53 and S51 are configured such that terminals of capacitor C53 are coupled to receive an operating voltage source, e.g., V_SS. Further, the configuration of switches S54 and S52 couples one terminal of capacitor C51 to operating voltage source V_SSAnd the other terminal of the capacitor C51 is coupled to the voltage V_MIN. Switches S51 and S55 are configured to connect one terminal of capacitor C52 to receive operating voltage source V_SSAnd the other terminal of capacitor C52 and the input G51 of transconductor G51_I2Is connected to the output G51_O2. The transconductor G51 is therefore arranged in a negative feedback configuration. Due to a negative feedback structure and coupled to receive a voltage V_MINNon-inverting input G51_I1At the reverse input G51_I2A similar voltage is established. Preferably, the voltage V_MINIs selected to be a value within the operating range of the transconductor G51. Capacitor C51 is charged to voltage V_MINAnd capacitor C52 is charged to voltage V_MINVoltage V of_MINModified by any offset voltage of the transconductor G51. Capacitor C53 is discharged and the transconductor output current settles to zero.

In the active mode, the discharged capacitor C53 is connected in parallel across the capacitor C52 to offset the voltage stored on the combination from the initial voltage that causes the output signal of the transconductor G51 to decrease to zero. This offset allows the voltage comparator and the filtering portion of SC comparator 12 to operate with an output voltage range that does not extend to zero. Because the input 116 of the two-input NAND gate U51 is coupled to receive the clock signal CLK/2 (shown in FIG. 1), only when clockedThe output of the two-input nand gate U51 is responsive to the output of the transconductor G51 when the signal CLK/2 is high. The integrating capacitor 46 (shown in FIG. 1) is discharged by the transistor 32 at each transition of the clock signal CLK/2, so that the image current I provided by the voltage balancing circuit 24 is equal to_IMAGECharging capacitor 46 to approximately equal V_CTRLWhen the voltage of the offset voltage is subtracted, the two-input NAND gate U51 transitions to a logic low voltage level after the transition point of the clock signal CLK/2. Thus, the current I is mapped_IMAGEFor generating an internal reference signal V_INT。

Although the corresponding portions of the SC comparator 18 and the selector circuit 20 are not shown, it should be noted that the circuit configuration of the SC comparator 18 is the same as that of fig. 5 showing the SC comparator 16. Due to the addition of the inverter coupled between input terminal 116 and clock signal CLK/2, portion 21 of selector circuit 20 coupled to SC comparator 18 is different from portion 21 of selector circuit 20 coupled to SC comparator 16. It should further be noted that for the SC comparator 18, the offset correction mode is established when the clock input signal CALA is high, and the active mode is established when the clock input signal ACTA is high.

Referring now to FIG. 7, shown is a schematic diagram of a voltage balancing circuit 24 in accordance with an embodiment of the present invention. The voltage balancing circuit 24 includes sub-circuits 70 and 72. The sub-circuit 70 includes three-terminal switches S61, S63, and S65, a P-channel FET M61, a current sink I61, and a capacitor C61. The sub-circuit 72 includes three-terminal switches S62, S64, and S66, a P-channel FET M62, a current sink I62, and a capacitor C62. Referring again to subcircuit 70, three-terminal switch S61 has a source connected to transistors 26 and 28 (the connection of transistors 26 and 28 is described with reference to FIG. 1) and receives input voltage V_BATTA second terminal connected to the drain of transistor 26 and the first terminal of switch S62, and a third terminal connected to the source of P-channel FET M61. The gate of P-channel FET M61 is connected to a first terminal of three-terminal switch S65 and one terminal of capacitor 61, and the drain of P-channel FET M61 is connected to a third terminal of three-terminal switch S65 and current sink I61. The other end of the capacitor 61Which is connected to the third terminal of the three-terminal switch S63. A first terminal of three-terminal switch S63 is connected to the sources of transistors 26 and 28 and receives voltage V_BATTAnd a second terminal of the three-terminal switch S63 is connected to the drain of P-channel transistor 28, the source of P-channel FET M63, and a first terminal of switch 64. Coupling the drain of P-channel FET M63 to converter 10 uses the image current I_IMAGEAnd the gate of P-channel fet 63 is connected to the second terminals of switches S65 and S66. It should be noted that P-channel FETM63 may be replaced by a plurality of P-channel transistors whose gates are commonly connected and whose sources are commonly connected to image current I_IMAGEDivided into a desired number of small fractional components for use in different parts of the DC-DC converter 10.

Three-terminal switch S62 has a first terminal connected to the drain of transistor 26, is connected to the sources of transistors 26 and 28, and receives voltage V_BATTAnd a third terminal connected to the source of P-channel FET M62. The gate of P-channel FET M62 is connected to the second terminal of three-terminal switch S66 and is coupled to the third terminal of three-terminal switch S64 through capacitor C62, and the drain of P-channel FET M62 is connected to the third terminal of three-terminal switch S66 and to current sink I62. A first terminal of three-terminal switch S64 is connected to the sources of transistors 26 and 28 and receives voltage V_BATTAnd a second terminal of the three-terminal switch S64 is connected to the drain of P-channel transistor 28, the source of P-channel FET M63, and a second terminal of switch 63.

In operation, voltage balancing circuit 24 transfers current originating from transistor 28 to other portions of DC-DC converter 10 while ensuring that the drain-to-source voltage of transistor 28 coincides with the drain-to-source voltage of transistor 26. The sub-circuits 70 and 72 operate in offset correction and active modes. When the clock input signal CALA is high, one sub-circuit switches to an offset correction mode, and when the clock input signal CALB is high, the other sub-circuit switches to an offset correction mode. In the active mode, the sub-circuits 70 and 72 operate in parallel.

In the embodiment shown in FIG. 7, sub-circuit 70 is configured to operate in an offset correction mode, with reference to sub-circuit 72, capacitor C62 being charged to the gate-to-source voltage required by P-channel FET M62 to obtain the current received by current sink 162. A negative feedback loop is established including FET M61, switches S61, S63 and S65, and capacitor C61, which forces P-channel FET M61 to provide the current received by current receiver I61. Capacitor C61 is charged to the gate-to-source voltage to enable transistor M62 to provide current. This voltage remains in the active mode because the first terminal of capacitor C61 is connected to the gate of P-channel FET M61, which does not provide a conductive path. Assuming substantially equal voltages at the drains of transistors 26 and 28, P-channel FET M62 will draw a current. A negative feedback loop including FETs M62 and M63, switches S66 and S64, and capacitor C41 adapts the gate voltage of P-channel FET M63 to establish this condition. Thus, when P-channel FET M63 passes the current provided by transistor 28 to the rest of DC-DC converter 10, the drain voltages of transistors 26 and 28 remain equal.

Fig. 8 is a schematic diagram of a DC-DC converter 100 according to an embodiment of the invention. DC-DC converter 100 differs from DC-DC converter 10 of fig. 1 by the addition of a current generator 102 coupled across capacitor 46 and a zero-crossing detector 104 coupled between the drain and source of N-channel FET 30. Current generator 102 has an input 106 connected to node 34, sources connected to transistors 26 and 28, and a voltage source V_BATTAn input 108 connected to one terminal of the capacitor 46, an output 110, and an output 112 coupled to the other terminal of the capacitor 46. Output 110 is therefore connected to the inputs of SC comparators 16 and 18.

Zero crossing detector 104 has an input connected to the drain of N-channel FET 30, an input connected to the source of N-channel FET 30, and an output 116 connected to driver circuit 22. Further, the zero-crossing detector 104 has inputs coupled to receive clock input signals CALA and CALB.

In operation, when the current through inductor 36 switches to flow through transistor 30, the drain-to-source voltage is initially negative. If the current through inductor 36 is reversed, the drain-to-source voltage of transistor 30 drops to zero and becomes positive. Zero crossing detector 104 monitors the drain-to-source voltage of transistor 30 and transmits a signal to the driver to remove the voltage at the gate of transistor 30 because its gate-to-source voltage is close to zero. Since the drain-to-source voltage is ideally zero and small in nature, there is preferably a low offset to the zero crossing detector 104 and can be active at any time during the clock cycle. Because transistor 30 is able to conduct during all clock cycles, two comparators are used, one to correct errors during odd clock cycles and one to correct errors during even clock cycles. During the time interval without error correction, the comparators may be connected in parallel. Thus, when the input clock signal CALA is high, one comparator is disconnected and corrects the error, and when the input clock signal CALB is high, the other comparator is disconnected and corrects the error. The combination of the two comparators is always responsive to the drain-to-source voltage of transistor 30 because the input clock signals CALA and CALB are non-overlapping and shorter than a clock cycle.

Further, when the load voltage is greater than half of the battery voltage, the DC-DC converter 100 may become unstable due to a low load. This instability can be suppressed by adding current to the current charging the integrating capacitor 46. The increased current may be provided by the current generator 102. The additional currents are specified as:

I＝((V_LOAD ²)*T)V_BATT*M*L) EQT.2

wherein:

l equals the value of the inductor (henry);

t is the clock period (seconds); and

m is the ratio of the current flowing into transistor 26 to the current charging capacitor 46.

Fig. 9 is a schematic diagram of a zero-crossing detector 104 according to an embodiment of the present invention. The zero-crossing detector 104 includes a sub-circuit 104A in parallel with a sub-circuit 104B. The sub-circuit 104A includes three-terminal switchesOff S71A, S72A, and S74A, a single two-terminal switch S73A, and a plurality of capacitors C71A, C72A, C73A, and C74A. Three-terminal switch S71A has a first terminal coupled to the drain of transistor 30, coupled to receive a signal such as V_SSAnd a third terminal connected to one terminal of capacitor C71A. The connection shown in fig. 9 to DRAIN30 indicates the connection of the terminal to the DRAIN of transistor 30. Three-terminal switch S72A has a terminal coupled to receive a bias voltage V_BIASCoupled to receive a signal such as V_SSAnd a third terminal connected to one terminal of capacitor C72A. A second terminal of the capacitor C72A is coupled to an operating voltage source V through a parallel combination of the two-terminal switch S73A and the capacitor C73A_SS. The second terminal of the capacitor C72A is also coupled to the second terminal of the capacitor C71A through a capacitor C74A. The two-input transconductor G71A has an input G71A connected to the second terminal of the capacitor C71A and to the second terminal of the three-input switch S74A_I1And is coupled to receive a signal such as V_SSOf the operating voltage source G71A_I2. A second terminal of the three-terminal switch S74A is connected to the driver circuit 22 (shown in FIG. 1), and a third terminal of the switch S74A is connected to the output G71A of the transconductor G71A_O1And the output G71A of transconductor G71A_O2Coupled to receive an operating voltage source, e.g. V_SS. The connection to DRAIN22 shown in fig. 9 represents the connection of the second terminal of three-terminal switch S74A.

The sub-circuit 104B includes three-terminal switches S71B, S72B, and S74B, a single two-terminal switch S73B, and a plurality of capacitors C71B, C72B, C73B, and C74B. Three-terminal switch S71B has a first terminal coupled to the drain of transistor 30, coupled to receive a signal such as V_SSAnd a third terminal connected to one terminal of capacitor C71B. The connection to DRAIN30 shown in fig. 9 is indicative of the connection of the terminal to the DRAIN of transistor 30. Three-terminal switch S72B has a terminal coupled to receive a bias voltage V_BIASCoupled to receive a signal such as V_SSAnd connection to the operating voltage source ofA third terminal to one terminal of capacitor C72B. A second terminal of the capacitor C72B is coupled to an operating voltage source V through a parallel combination of the two-terminal switch S73B and the capacitor C73B_SS. The second terminal of the capacitor C72B is also coupled to the second terminal of the capacitor C71B through a capacitor C74B. The two-input transconductor G71B has an input G71B connected to the second terminal of the capacitor C71B and to the second terminal of the three-input switch S74B_I1And is coupled to receive a signal such as V_SSOf the operating potential source G71B_I2. A second terminal of the three-terminal switch S74B is connected to the driver circuit 22 (shown in FIG. 1), and a third terminal of the switch S74B is connected to the output G71B of the transconductor G71B_O1And the output G71B of transconductor G71B_O2Coupled to receive an operating voltage source, e.g. V_SS. The connection to DRAIN22 shown in fig. 9 represents the connection of the second terminal of three-terminal switch S74B.

In operation, when the clock input signal CALA is high, the sub-circuit 104A transitions to the offset correction mode, and when the clock input signal CALB is high, the sub-circuit 104B transitions to the offset correction mode. When not in the offset correction mode, sub-circuits 104A and 104B operate in parallel, each in the active mode. In the offset correction mode, the switch S71A is configured to connect the first terminal of the capacitor C71A to the operating voltage source V_SS. Switches S72A and S73A are configured such that the terminals of capacitor C72A are connected to the same operating voltage source, e.g., V_SS. In addition, the switch S73A connects the other terminal of the capacitor C73A to the same operating voltage source, while its first terminal and one terminal of the capacitor C74A are connected to the operating voltage source, e.g., V_SS. The switch S74A is configured to couple the output terminal G71A of the transconductor G71A_O1Is connected to the input terminal G71A_I1. In this configuration, capacitors C71A and C74A are charged and coupled in a parallel configuration such that the voltage regulates the output current of transconductor G71A to zero. Capacitors C72A and C73A are discharged.

In the active mode operation of the sub-circuit 104B, the output terminal G71B_O1Connected to driver circuit 22, and input of transconductor G71BChild G71B_I1Coupled to the drain of transistor 30 through capacitor C71B. Output terminal G71B_O1Is also coupled to the voltage V through a network of capacitors T formed by capacitors C72B, C73B, and C74B_BIAS. The charge is transferred through the network to capacitor C71B, adding to the charge at input terminal G71B_I1The voltage of (c). Preferably, the capacitors C72B and C74B are small compared to the capacitors C71B and C73B, so that small voltage increments are made at the input terminal G71B_I1And (4) generating. When the voltage from the drain of transistor 30 is large and negative, the output voltage will be high, which therefore drops to zero when the input voltage is still negative.

Because subcircuits 104A and 104B are identical and in parallel, zero crossing detector 204 operates without concern that one or both subcircuits are in active mode. Thus, any subcircuit can be switched to the offset correction mode without interfering with the function of the complete section.

By now it should be appreciated that a DC-DC converter and a method for compensating for offset errors in a DC-DC converter are provided. The DC-DC converter includes an inductor coupled to receive a voltage through a plurality of switches. The switches are controlled by a control circuit having two circuit paths configured to operate in parallel. This configuration provides a copy of the control circuit paths so that at least one path is always active and responsive to an input signal. The inclusion of two paths allows for offset compensation to be applied to the system in the absence of a scale interval. The circuit paths cooperate to provide offset cancellation of errors in elements of the circuit paths. The invention is suitable for use in both charge control mode and current control mode configurations.

While certain preferred embodiments and methods have been disclosed herein, it will be apparent to those skilled in the art from this disclosure that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of appropriate law.

Claims (10)

1. A method for compensating for errors in a DC-DC converter, comprising:

providing a first signal path having at least one circuit element;

providing a second signal path having at least one circuit element; and

switching one of the first or second signal paths to an error correction mode to compensate for an error of the at least one circuit element in the first or second signal path in the error correction mode, wherein the other of the first or second signal paths is in a normal operating mode.

2. The method of claim 1, further comprising switching one of the first or second signal paths to the error correction mode during a first portion of a first clock cycle and switching one of the first or second signal paths to the normal operating mode during a second portion of the first clock cycle.

3. The method of claim 2, wherein the second portion of the first clock cycle is a remaining portion of the first clock cycle, and wherein the step of transitioning one of the first or second signal paths to the normal mode further comprises transitioning one of the first or second signal paths to the normal mode during an entirety of a second clock cycle; and further comprising selecting an output signal from the at least one circuit element of the first or second signal path during the second clock cycle.

4. The method of claim 1, further comprising:

integrating a signal derived from an input signal into the first signal path to produce a first integrated signal;

integrating a signal derived from an input signal into the second signal path to produce a second integrated signal;

generating first and second comparator output signal components from the first and second integrated signals;

generating a first control path signal by comparing the first comparator output signal to a charge indication signal, the charge indication signal indicating a charge provided to a load during concurrent clock cycles;

generating a second control path signal by comparing the second comparator output signal with the charge indication signal, the charge indication signal indicating the charge provided to a load during the concurrent clock cycles; and

the first and second control path signals are used to generate an output voltage associated with a plurality of switches.

5. The method of claim 4, further comprising:

discharging the first energy storage element at the beginning of each clock cycle;

charging the first energy storage element with a first current, wherein the first current is proportional to a second current flowing through a second energy storage element, and wherein the charge indication signal is a voltage developed across the first energy storage element, the charge indication signal indicating the charge provided to a load during the concurrent clock cycle; and further comprises

Providing a third current that combines a current proportional to the second current, wherein the third current suppresses formation of an oscillation mode.

6. A method for correcting offset errors in a DC-DC converter, comprising:

generating a first signal in response to a reference signal and a converter output signal, the first signal comprising a first sub-signal and a second sub-signal;

generating a second signal in response to the reference signal and the converter output signal, the second signal comprising a third sub-signal and a fourth sub-signal;

correcting a first offset error in the first signal during a first period of a clock signal; and

correcting a second offset error in the second signal during a second period of the clock signal, the first and second periods being different periods.

7. The method of claim 6, wherein the step of generating the first signal comprises:

attenuating and filtering the reference signal and the converter output signal;

comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal to generate the first sub-signal, wherein the step of comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal comprises introducing a first offset error correction signal into the first sub-signal;

comparing the first sub-signal to an internal reference voltage to generate the second sub-signal, wherein the step of comparing the first sub-signal to the internal reference voltage comprises introducing a second offset error correction signal into the second sub-signal;

attenuating and filtering the reference signal and the converter output signal;

comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal to generate the third sub-signal, wherein the step of comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal comprises introducing a third offset error correction signal into the third sub-signal; and

comparing the third sub-signal to the internal reference voltage to generate the fourth sub-signal, wherein the step of comparing the third sub-signal to the internal reference voltage comprises introducing a fourth offset error correction signal into a fourth sub-signal.

8. The method of claim 7, further comprising:

selecting one of the first signal or the second signal to produce a selected signal;

generating a driver signal from the selected signal;

generating an image current using the driver signal; and

generating the internal reference voltage using the image current.

9. A DC-DC converter comprising:

a control circuit having a plurality of inputs and a plurality of outputs, wherein the control circuit comprises:

a first circuit path having first and second inputs and an output; and

a second circuit path having first and second inputs and an output,

wherein the first and second circuit paths cooperate to provide offset cancellation of errors in elements of the first and second circuit paths; and

a switching network coupled to the control circuit.

10. The DC-DC converter of claim 9, wherein:

the first circuit path includes a first comparator that generates an output in response to a difference between a portion of a load voltage and a reference voltage;

the second circuit path includes a second comparator that generates an output in response to a difference between a portion of the load voltage and a reference voltage;

said first and second comparators comprise filtering means for stabilizing said first and second circuit paths, respectively; and

the filtering means comprises an integrator for providing an output signal component common to the first and second circuit paths.