HK1117954A - Receiver dc offset correction - Google Patents

Description

Receiver DC offset correction

Priority requirements according to 35 U.S.C. § 119

This patent application claims priority to provisional application 60/660,968 filed on 11/3/2005, which is assigned to the assignee and is expressly incorporated herein by reference.

Technical Field

The present invention relates generally to wireless communication devices, and more particularly to a system and method for correcting dc offset errors that occur within a receiver of a communication device.

Background

Fig. 13 is a schematic block diagram of a conventional receiver front end (prior art). Conventional wireless communication receivers include antennas for converting radiated signals into conducted signals. After initial filtering, the transmitted signal is amplified. If there is a sufficiently large power level, the carrier frequency of the signal can be converted by mixing (down-converting) the signal with a local oscillator signal. After frequency conversion, the analog signal may be converted to a digital signal with an analog-to-digital converter (ADC) for baseband processing. In addition to the noise introduced by the amplification process, the above process also introduces a dc offset value that is combined with the desired signal, thereby causing errors in the interpretation of the desired signal.

The dc offset associated with Zero Intermediate Frequency (ZIF) receivers may be more significant. Analog mixers are typically the primary source of dc offset. Typically, there is a mismatch in the current sources used to drive the mixer, resulting in a dc offset that varies slightly with temperature. The dc offset is also a function of the gain state of the mixer. However, it is possible to calibrate for the offset generated by the current source for a given mixer gain state and then remove the resulting static offset.

Dc offset also occurs when isolation between the Local Oscillator (LO) and the Radio Frequency (RF) front end is insufficient. Such error sources can result in static and dynamic offsets. Without proper isolation, the LO may leak into the signal path, radiate from the antenna, reflect from the environment, and cause self-mixing and static dc offset. Similarly, an interferer may leak into the LO, creating a time-varying dc offset. Although only a single channel is shown, for a receiver using quadrature phase modulation, parallel in-phase (I) and out-of-phase (Q) channels will be used.

The ADC also contributes to dc offset due to uncertainty in the Least Significant Bit (LSB), although such error sources are typically smaller than those associated with the mixer. AC coupling cannot be used at the input of the ADC to remove the dc offset because the capacitance of the coupling capacitor must be large to prevent distortion of the data subcarriers. Such capacitors will produce a long time constant and are likely to be too large to fit into many portable receivers.

It would be advantageous if a wireless communication device receiver could be calibrated at initialization to measure the resulting dc offset error and remove the measured error from the received signal.

It would be advantageous if the receiver could be constantly self-calibrated to measure dc offset errors and remove them from the received signal even during operation.

Disclosure of Invention

A system and method for correcting dc offset in a communication receiver is provided. The system includes two nested first-stage loops, one of which (the fine correction loop) operates in the digital domain, and the second (the coarse correction loop) takes an estimate of the dc bias from the digital samples and applies the correction in the analog domain. The coarse correction loop causes most of the dc bias to have been removed before the ADC (analog to digital converter) to prevent any saturation at the ADC. The fine correction loop then removes any remaining dc bias from the signal after the correction applied by the coarse correction loop. A memory is implemented in the system for storing the various corrections to be applied for each gain state of the analog front end in the device. There are two operating states for dc correction, which are essentially the initialization (or calibration) state and the tracking (or communication) state. During the calibration state, the communication signal received at the input of the analog front end is disconnected, so the dc loop can be calibrated to remove static dc bias from components within the receiver. During the tracking state, the fine correction loop is first updated. The coarse correction loop is then updated at a predetermined rate based on the updates performed on the fine correction loop. These updates are performed for each gain state of the receiver.

Accordingly, a method for correcting a dc offset in a wireless communication receiver is provided. The method disconnects the mixer signal input from the received communication signal (i.e. the LNA output) in the initialization state. The analog signal is received from the mixer output and converted to a digital signal. An initial fine correction value is generated and subtracted from the digital signal. Thus, the digital signal amplitude is minimized in response to the initial fine correction value.

In the communication state, the LNA output is connected to the mixer input, so the communication signal is received at the mixer signal input. The initial fine correction value is subtracted from the converted digital communication signal, thereby providing a dc offset to the initially fine corrected digital communication signal.

The method may also be used to generate a coarse correction value in the initialization state. The coarse correction value is used to adjust the current input to the mixer. As with the initial fine correction, the digital signal amplitude is minimized (in the initialization state) in response to the coarse correction value. In the communication state, a communication signal is supplied to the mixer input and the mixer is operated with coarse value correction. Then, a digital communication signal having the dc offset subjected to the coarse correction and the fine correction is provided.

On the other hand, after the coarse correction is determined, a final fine correction is made. In the initialization state, the final fine correction value is generated while operating the mixer with coarse value correction. Then, in the communication state, the final fine correction value is subtracted from the digital communication signal, and the digital communication signal having the dc offset subjected to the coarse correction and the final fine correction is provided.

On the other hand, the method also generates a tracking correction value while operating in a communication state. The tracking correction value is subtracted from the digital communication signal. A digital communication signal is provided having dc offset that is coarsely corrected and track corrected. If the communication signal is made up of a plurality of sub-carriers with a first sub-carrier having a first frequency (f1) offset from the carrier, then the correction values are tracked with a bandwidth less than f 1. That is, by measuring the error associated with only the carrier frequency, tracking corrections are made.

More details regarding the above-described method and system for correcting dc offset in a communication signal received by a wireless communication receiver are provided below.

Drawings

Fig. 1 is a schematic block diagram of a system for correcting dc offset in a communication signal received by a wireless communication receiver.

Fig. 2 is a schematic block diagram of a variation of a system for correcting a dc offset in a received communication signal.

Fig. 3 is a schematic block diagram of a processor device for correcting a dc offset in a communication signal received by a wireless communication receiver.

Fig. 4 is a high-level schematic block diagram of a typical receiver with a dc offset correction system.

Fig. 5 is a schematic block diagram of a dc offset correction system in which the first and second loops are depicted in greater detail.

Fig. 6 is a block diagram depicting the first loop in detail.

Figure 7 is a block diagram detailing the second loop.

Fig. 8 is a timing diagram associated with coarse correction of dc offset.

FIG. 9 is a schematic block diagram depicting correction of an inner loop accumulator value during an outer loop tracking update.

Fig. 10 is a schematic block diagram depicting a typical hardware implementation of a dc correction loop.

Fig. 11 is a timing diagram of signal flow for the dc correction process.

Fig. 12A and 12B are flowcharts illustrating a method of correcting a dc offset in a wireless communication receiver.

Fig. 13 is a schematic block diagram of a conventional receiver front end (prior art).

Detailed Description

Fig. 1 is a schematic block diagram of a system for correcting dc offset in a communication signal received by a wireless communication receiver. The system 100 includes a mixer 102 having a signal input on line 104 that is selectively disconnectable from a received communication signal in an initialization state. The mixer has an analog output on line 106. An analog-to-digital converter (ADC)108 has its input connected to the mixer output on line 106 and has an output on line 110 to provide a digital signal.

The summing circuit 112 has a first input on line 110 connected to the ADC output and a second input on line 114. The summing circuit 112 has an output on line 116 to provide a summed digital signal in which the second input is subtracted from the first input. The dc offset correction module 118 has an input on line 116 to receive the summed digital signal and an output on line 114 to provide the initial fine corrected value to the second input of the summing circuit. The combination of the summing circuit 112 and the dc offset module 118 can form a first loop 120 to minimize the summed digital signal amplitude during the initialization state. Ideally, the summed digital signal amplitude should not have any dc bias voltage after applying the correction in the initialization state.

In the communication state, the mixer signal input on line 104 is selectively connected to receive the communication signal. In some aspects, the selective connection function may be performed by a switch. In other aspects, however, the communication signal may be selectively coupled to the mixer 102 by applying a dc power supply to circuitry in front of the mixer. Here, a Low Noise Amplifier (LNA)122 is shown. The input signal is selectively provided to the mixer by connecting/disconnecting the dc power supply to/from the LNA122 or connecting/disconnecting the communication signal to the input of the LNA on line 123. The adder circuit 112 then subtracts the initial fine correction value from the ADC output on line 110 to provide the digital communication signal with the dc offset initially fine corrected in the communication state.

The assumptions behind this correction process are: the dc offset measured in the initialization or acquisition state is also present when receiving and processing communication signals. This assumption then predicts that: corrections made to remove dc offset in the initialization state will improve signal quality if applied in the communication state.

In some aspects, the system includes a second loop 124. The mixer 124 has an input on line 126 connected to a Local Oscillator (LO)128 and a power supply (dc voltage) input on line 130. The dc offset correction module 118 has its output connected to the mixer power supply input on line 132 to provide a coarse correction value to minimize the summed digital signal amplitude during the initialization state. Then, in the communication state, the summing circuit 112 provides on line 116 a digital communication signal having its dc offset coarsely corrected and initially finely corrected.

More specifically, the dc offset correction module 118 may generate the coarse correction value on line 132 as an accumulated coarse correction digital value. A digital-to-analog converter (DAC)134 has its input connected to line 132 to receive the coarse correction digital value and its output connected to the mixer power input 130. The process assumes that: the dc offset measured during initialization can be further reduced by making corrections at the mixer and at the summing circuit. Also, the process assumes: the two-step correction further improves signal quality when applied in a receiver communication state.

In general, the DC offset module 118 adjusts the fine correction value and provides the adjusted fine correction value as an initial coarse correction value. That is, the initial fine correction value is provided as a first "guess" of the coarse correction value. Note that the initial fine correction value may be pre-adjusted by a predetermined factor before being used as the initial coarse correction value. The second loop 124, which starts with the initial coarse correction value, takes the (final) coarse correction value, which in the initialization state yields the lowest signal amplitude from the ADC 108.

In a further step an initialization state correction procedure can be performed. After the coarse correction values are obtained, the system 100 again obtains the final fine correction values. The dc offset correction module 118 provides the final fine corrected value to the summing circuit 112 while providing the coarse value correction to the mixer 102 in an initialization state. Then, in the communication state, the summing circuit 112 can provide the dc offset coarsely corrected and finally finely corrected digital communication signal on line 116.

In one aspect of system 100, mixer 102 has multiple gain states. In the initialization state, the dc offset correction module 118 generates an initial fine correction value, a coarse correction value, and a final fine correction value for each mixer gain state. The summing circuit 112 provides a corrected digital communication signal on line 116 (in a communication state) having a dc offset corresponding to the mixer gain.

LNA122, on the other hand, may have multiple gain states. The LNA122 has an input on line 123 that is connected to a conventional wireless air interface represented by antenna 138. It should be understood, however, that additional duplexers, amplification and filtering circuits (not shown) may be associated with the air interface. The LNA has its output connected to the mixer signal input on line 104. In the initial state, the dc offset correction module 118 generates an initial fine correction value, a coarse correction value, and a final fine correction value for each LNA gain state. The summing circuit 112 provides a digital communication signal on line 116 with a corrected dc offset corresponding to the LNA gain.

On the other hand, the first loop correction can be further enhanced by modifying the final correction value while the receiver is operating in a communication state. That is, the dc offset correction module 118 provides the tracking corrected values to the summing circuit 112 on line 114 in the communication state, and the summing circuit provides the coarse corrected and tracking corrected digital communication signals on line 116 in the communication state. In one aspect, the dc offset correction module adjusts the tracking correction value and provides the adjusted tracking correction value as an updated coarse correction value. In another aspect, tracking corrections are made for each mixer and LNA gain state.

If the communication signal is formed by a carrier signal having information-carrying subcarriers, as is conventional, the first loop error can be tracked by using a smaller bandwidth than the first subcarrier frequency offset (the subcarrier closest to the carrier). For example, the mixer signal input on line 104 may be an Orthogonal Frequency Division Multiplexed (OFDM) signal having a first subcarrier offset from the carrier by a first frequency (f 1). The dc offset correction module 118 then generates a tracking correction value using a tracking bandwidth less than f 1.

In another aspect, the OFDM signal includes a periodic pilot signal. By applying the tracking correction, the summing circuit 112 is able to provide a digital communication signal on line 116 in response to the corrected dc offset while reducing the probability of a pilot signal false alarm.

Fig. 2 is a schematic block diagram of a variation of a system for correcting a dc offset in a received communication signal. The system 200 comprises means 202 for mixing an input signal with an LO signal. The mixing device 202 has a signal input on line 204 that is selectively disconnected from the received communication signal (by a device not shown) in an initialization state. The mixing device 202 also has an analog output on line 205. The system further comprises means 206 for converting the analog signal into a digital signal. The ADC device 206 has its input connected to the mixing device output on line 205 and also has an output on line 208 to provide a digital signal.

The summing circuit 210 has its first input connected to the ADC means output on line 208. The summing circuit 210 also has a second input on line 212 that is subtracted from the first input and an output on line 214 to provide a summed digital signal. The system 200 also includes means 216 for correcting the dc offset. The dc offset correction means 216 has an input to receive the signal from the summing means on line 214 and also has an output on line 212 to provide a fine correction value to a second input of the summing means 210. In the initialization state, the fine correction value minimizes the summed digital signal amplitude.

In the communication state, the signal inputs to the mixing device 202 are selectively connected, thereby permitting the mixing device 202 to receive communication signals. The summing device 210 subtracts the fine correction value from the output of the ADC device 206 to provide a fine corrected dc offset digital communication signal in the communication state.

Fig. 3 is a schematic block diagram of a processor device for correcting a dc offset in a communication signal received by a wireless communication receiver 300. The processor device 302 includes a mixer module 304 having a signal input on line 306 that is selectively disconnected from the received communication signal (by a means not shown) in an initialization state. The mixer module 304 has an analog output on line 307. The ADC block 308 has its input connected to the mixer block output on line 307 and also has an output to provide a digital signal on line 310.

The summing block 312 has its first input connected to the ADC block output on line 310 and also has a second input on line 314 and an output on line 315 to provide a summed digital signal. The addition module 312 subtracts the second input from the first input. The dc offset correction module 316 has an input on line 315 to receive the summed digital signal and an output on line 314 to provide the fine corrected value to the summing module second input. In the initialization state, the fine correction value is used to minimize the summed digital signal amplitude.

In the communication state, the mixer module signal inputs on line 306 are selectively connected to receive the communication signal. The summing block 312 subtracts the fine correction value from the ADC block output on line 310 to provide a digital communication signal having a fine corrected dc offset in the communication state.

Description of functions

Fig. 4 is a high-level schematic block diagram of a typical receiver with a dc offset correction system. The present invention is a design for a receiver with a dc offset correction loop, a common impairment factor in communications receivers, which is superimposed as a slowly varying bias voltage on the received signal. The dc offset may consist of static and dynamic components that originate from a Radio Frequency (RF) front-end mixer stage. The dc offset may have a more significant effect on ZIF receivers. The negative impact of the dc bias on the receiver is two-tiered: the dc offset reduces the allowable dynamic range of the input signal to the ADC to avoid saturation of the ADC. Furthermore, if the communication signal level is weak compared to the dc offset, the AGC may follow the dc offset instead of the signal level when making a gain step decision. Many conventional transmitters do not transmit useful data in direct current. Thus, the suppression in the receiver does not affect the data stream.

Ideally, a simple first stage loop that can correct the dc level of the signal before the ADC input would be sufficient. However, in practice, the resolution of the corrections that can be applied before the ADC input is limited.

One example of the present invention presents performing dc offset correction with two nested first stage loops. The first (inner) loop is used for fine offset correction and the second (outer) loop is used for coarse offset correction. Coarse correction is performed in the analog domain by the outer loop before the signal is fed into the ADC. A fine dc correction is performed by the inner loop to correct the dc offset after the ADC in the digital domain.

Fig. 5 is a schematic block diagram of a dc offset correction system in which the first and second loops are depicted in greater detail. The system uses an initialization or acquisition state for calibration and a tracking state. The inner and outer loops may be joined in either state. The initialization state is designed to ensure that the outer loop converges such that most of the dc bias has been removed before the signal is fed into the ADC, thereby preventing the ADC from saturating. In tracking mode, the fine correction ensures that the dc offset has been removed prior to AGC energy measurement so that the AGC setting is not affected by the dc bias in the signal. The fine correction is performed in the digital domain before the signal is fed into the DVGA block (see fig. 4).

k_cAnd k_fThe loop gains of the outer correction loop and the inner correction loop are indicated, respectively. For analog gain state G in inner and outer loops_jRespectively with A_iAnd B_iRepresents; x (n) is the ADC output signal, and y (n) is the signal after fine DC correction. The coarse correction signal input to the DAC is represented by a (n). The digital correction applied by the inner loop is given by d (n). At any instant in time n, the values d (n) and a (n) are given by: d (n) ═ A_i(n) and a (n) ═ B_j(n) of (a). The value accumulated in the inner loop provides an estimate of the dc offset present in the signal (initial fine correction). This value is used as an error signal to drive the outer loop. Once the outer loop is updated with the accumulator value of the inner loop (coarse correction), the accumulator of the inner loop is reset (final fine correction).

In the initialization (acquisition) and tracking states, fine dc correction is performed in the digital domain by the inner loop. The receiver is powered up and the initialization state begins with the LNA switched off (unpowered). Fine dc offset correction is performed for all gain states of the LNA and all gain states of the mixer. In the initialization state (i.e., calibration), the accumulator in the (first) digital loop is updated with the appropriate loop gain, and the analog offset correction accumulator (in the second loop) is updated with the appropriate loop gain for each gain state. A signal is then sent to the AGC block for indicating the end of the digital loop correction. In addition, both the enable signal and the offset corrected ADC samples are sent to the AGC block for processing.

After correcting the dc offset in the initialization state, the dc offset correction enters the tracking state. In the tracking state, the fine offset correction is updated. In some aspects, the coarse dc correction is updated only in the initialization state.

Fig. 6 is a block diagram depicting the first loop in detail. The transfer function of the first stage loop is given by:the loop time constant isWherein T is_LIs the time interval of the loop update. For very small values of k, k < 1, the loop time constant is approximated byThe resulting h (z) is essentially a high pass filter for removing frequency components near dc as expected. Furthermore, for loop stability, the loop gain k should be between 0 and 2 (i.e., -1 < (1-k) < 1). This can be easily achieved by observing the time domain response of the filter as expressed by: when n is greater than 0, h (n) ═ k (1-k)^n-1(ii) a h (0) ═ 1; and when n is less than 0, h (n) is 0. Note that, for stabilization, a requirement is madeWith limited, this result is achieved. Omega_3dBIs the frequency at which the filter gain is 3dB below its maximum value, which is about 1 for a small value of k. Omega_3dBIs given by the equationGiven that ω can be approximated when k is smallThis can be further approximated as ω_3dBK. Thus, when k is small, both the loop time constant and the bandwidth can be expressed as simple functions of the loop gain k.

Figure 7 is a block diagram detailing the second loop. The coarse dc correction loop spans the digital domain and the analog domain. The purpose of the coarse correction loop is: most of the dc bias (mainly introduced by the mixer) is removed in the analog domain before the signal is fed into the ADC (i.e., sigma-delta AGC) to prevent the ADC from saturating. By controlling the overall loop gain using the gains of the various blocks included in the loop (e.g., DAC, mixer, sigma-delta ADC) and the adjustable loop gain, a dc signal is measured in the digital domain and converted to the analog domain.

Considering the various blocks in the coarse loop, the overall loop gain of the coarse loop is given by:

G_LOOP＝DAC_gain(mv/LSB)×MixerGain(mV/mV)×

(Sigma-Delta+DigitalFilterGain)(LSB/mV)×2^AccShift×2^-M×2^{(DACbitWidth-AccbitWidth)}

based on the discussion in the previous paragraph, the various gain constants should be such that the overall loop gain is between 0 and 2. In particular, the required shift M is selected such that the overall loop gain is less than 1.

M＝ceil(log₂(DAC_gain×G_MLXER×G_{Sigma-Delta+Digftal Filter Gain}))

Note that the coarse loop includes a mixer and is therefore affected by variations in the gain of the mixer in various states. Accordingly, the shift constant M should be adjusted in the various mixer gain states so that the overall loop gain remains close to the desired value. Thus, during calibration and tracking, two values for M different values are used based on the mixer gain state.

Initial calibration (acquisition)

The receiver is calibrated to remove static dc offset, which is a function of the gain state of the mixer. Calibration is performed each time the receiver enters a different mode of operation, such as power-up or switching between CDMA and OFDM. A calibration process is performed for each mixer gain state and the time taken for each gain state is less than a portion of an OFDM symbol.

When turning on receptionOn the fly, the outer loop is turned off, while not letting any signal into the LNA. This helps measure the static dc offset due to each gain state with the inner loop. Removing the input signal at the LNA ensures that the ADC does not go into saturation for strong input signals. For this operation, a larger loop gain is selected for the inner loop because there is no concern about attenuating the useful frequencies of the signal components. In one aspect, k_fThis corresponds to a time constant of about 8 samples below the chip rate when the loop is updated for each sample, 1/8. Each analog gain state corresponds to one accumulator in bank a and one accumulator in bank B. These accumulators are selected based on the analog gain state.

Assume that the receiver is in gain state G_iIn (1). Suppose there is an accumulator A_iThe inner loop of (2) takes about 4 time constants to converge, and the inner loop requires about 32 samples. However, the effect of analog dc correction may take 5 microseconds (about 32 samples) to propagate to the ADC output. Therefore, the inner loop needs 32 additional samples to converge, i.e. 64 samples in total.

Taking into account the DAC gain, the outer loop gain k_cThe stability requirement of (2) requires that the overall loop gain should be less than 2. The outer loop gain parameter is selected such that the overall loop gain is close to 1. Some margin is allowed, assuming a low gain of 1/4. Suppose k for the outer loop_cFour time constants are required for this outer loop, corresponding to 4/k 1/4_c(16) And updating the secondary outer loop. To ensure convergence of both the inner loop and the outer loop at the end of the acquisition process, the inner loop needs to be updated after the outer accumulator value changes. Therefore, after the final outer loop update, the inner loop is updated for 64 samples to ensure convergence of the fine dc accumulator. The outer loop is updated 15 times, and after the 15 th update, the inner loop is updated for 64 samples. Thus, for each gain state, the outer loop needs to be (4/k)_c)×(8/k_f) 1024 samples stabilize. Note that for the first 15 updates, the switch position in FIG. 5 is changed every 64 samples to complete the outer loopOnce.

Fig. 8 is a timing diagram associated with coarse correction of dc offset. In updating the accumulator (B) in the outer loop_i) Thereafter, a switch is set to complete the inner loop. Accumulator content B corresponding to the outer loop_iIs fed into a DAC which applies dc offset correction in the analog domain prior to the ADC. Thus, when the receiver enters OFDM mode, the receiver is forced to switch gain stages after every 1024 samples (denoted T _ DC _ 1). When the receiver is in a given analog gain state, a coarse direct current measurement corresponding to that state is performed and the corresponding accumulator B is updated_i. This is done for each mixer gain state and the resulting accumulator value is used during analog correction to track the dc offset before the ADC input. The total time for calibration is 2.T _ DC _1 and is denoted T _ DC. After the acquisition process is completed for all mixer gain states, the values of the coarse and fine accumulators corresponding to the uninitialized analog gain states are initialized by copying the coarse and fine accumulator values corresponding to the same mixer gain states. The coarse and fine accumulators for states 0 and 2 are calibrated. The accumulator corresponding to state 1 is initialized by copying the value of the accumulator corresponding to state 0, since states 0 and 1 have the same mixer gain state. Similarly, the accumulator corresponding to state 3 is initialized by copying the value of the accumulator corresponding to state 2. Note that in general, the calibration process may be performed in any subset of analog gain states.

Tracking correction

Inner loop update

After the initial calibration is complete, the LNA is turned on, the receiver starts processing the input signal, and the inner loop is updated for each sample. The resulting ω is taken into account during the design of the inner loop_3dB. The subcarriers on either side of the dc are data subcarriers. To minimize the impact of dc nulling on system performance, ω_3dBNecessarily smaller than the first subcarrierFrequency. This ensures that the filter attenuation is not significant at the first OFDM subcarrier. To satisfy this condition, ω_3dBIs set to half the frequency of the first subcarrier. Furthermore, if the loop is updated for each sample, T_L1/W, where W is 5.55MHz is the entire communication bandwidth and the normalized frequency of the first carrier is given by 1/4096, where 4096 corresponds to the number of sub-carriers.

Will omega_3dBLet k ≈ π/4096 be half the frequency of the first subcarrier. This value corresponds to the loop time constant τ ═ T_LK such that τ is 0.28T_sWherein T is_sIs the OFDM symbol duration (833.33 mus). Assuming that four time constants are required to stabilize the loop, it takes at least one OFDM symbol duration for the loop to stabilize when the ACG is at a given gain level. When the gain state changes to i, register A in bank A is selected_i. Register A_iStarting with the value accumulated when the receiver was last in the same gain state.

Outer loop update

FIG. 9 is a schematic block diagram depicting correction of an inner loop accumulator value during an outer loop tracking update. The registers in bank B, which correspond to the coarse dc correction, are periodically updated based on the accumulated error in bank a. A typical update rate is one update per activation. All registers in bank B are updated each time they are activated. The register in bank a is divided down (scale down) each time the outer loop is updated, and if the inner loop accumulator is not divided down each time it is updated, the inner loop accumulator value (corresponding to the unused gain state) remains unchanged each time the coarse loop is updated. Thus, the outer accumulator corresponding to the unused gain state will eventually saturate. Thus, the outer loop update requires the following operations during tracking:

B_i(n)＝B_i(n-1)+k_c.A_i(n)

A_i(n+1)＝(1-k_c).A_i(n)

in the equivalent way,

B_i(n)＝B_i(n-1)+A_i(n)＞＞M2

A_i(n+1)＝A_i(n)-A_i(n)＞＞M2

wherein M2 is selected based on the loop gain of the outer dc loop.

Fig. 10 is a schematic block diagram depicting a typical hardware implementation of a dc correction loop.

Fig. 11 is a timing diagram of signal flow for the dc correction process. At start-up, the accumulators in both the first and second loops are reset. After initial power-up, the LNA is initially placed in the off state, ensuring that the dc offset in the input signal has been corrected before any samples (communication signals) are added to the AGC block for processing.

After the LNA is turned off, the dc offset loop is enabled in software. There are two dc correction loops in this block: digital (fine) loop correction, also referred to as first loop; and analog (coarse) loop correction, also referred to as a second loop. In this example, there are four stages of accumulators for the fine and coarse correction loops, corresponding to the LNA and gain stages of the mixer. That is, it is assumed that there are two gain stages for the LNA and two gain stages for the mixer. In the calibration mode, the accumulation length of the fine accumulator and the accumulation length of the coarse accumulator for each gain stage can be programmed by software. In the initialization state, the dc offset is corrected for gain stages 0 and 1. At the end of the initialization state, the calibrated values are updated for the accumulators of gain stages 3 and 4.

In the initialization state, at the end of the programmed accumulation length, the coarse accumulator is updated with the fine loop corrected value. After updating the four sets of accumulators for the programmed lengths, the coarse dc corrected values are applied to the mixers. Note that although only analog corrections to the mixer have been discussed above, in other aspects of the present system, these corrections may also be applied to other activated circuit elements (i.e., LNAs). After the initialization state correction is performed, a tracking state correction may be made.

Fig. 12A and 12B are flowcharts illustrating a method of correcting a dc offset in a wireless communication receiver. Although the method is depicted as a sequence of numbered steps for clarity, such numbering does not necessarily dictate the order of the steps. It should be understood that some of these steps may be skipped, performed in parallel, or performed without the requirement of maintaining a strict order of sequence. The method begins at step 1200.

In the initialization state, step 1202 disconnects the mixer signal input from the received communication signal. Step 1204 receives an analog signal from the mixer output. Step 1206 converts the analog signal to a digital signal. Step 1208 generates an initial fine correction value. Step 1210 subtracts an initial fine correction value from the digital signal. Step 1212 minimizes the digital signal amplitude in response to the initial fine correction value. In the communication state, step 1214 receives a communication signal at the mixer signal input. Step 1216 subtracts the initial fine correction value from the converted digital communication signal. Step 1218 provides the digital communication signal with the dc offset initially fine corrected.

In one aspect, step 1211a generates a coarse correction value in an initialization state. For example, step 1211a may generate an adjusted fine correction value and provide the adjusted fine correction value as an initial coarse correction value. Step 1211b uses the coarse correction value to adjust the current input to the mixer, and step 1212 minimizes the digital signal amplitude in response to the coarse correction value. Step 1217a operates the mixer with the coarse value correction and step 1218 provides a dc offset to the coarse corrected and initially fine corrected digital communication signal.

On the other hand, while in the initialization state, step 1211c generates the final fine correction value while operating the mixer with the coarse value correction. Step 1216 subtracts the final fine correction value from the digital communication signal in the communication state and step 1218 provides the digital communication signal with the dc offset subject to the coarse correction and the final fine correction.

In one aspect, receiving the analog signal from the mixer output in step 1204 includes: analog signals from mixers having various gains are received. Then, the process of generating an initial fine correction value in step 1208 includes: for each mixer gain, an initial fine correction value is generated. The process of generating the coarse correction value in step 1211a includes: a coarse correction value is generated for each mixer gain. The process of generating the final fine correction value in step 1211c includes: for each mixer gain, a final fine correction value is generated. Step 1218 then provides a digital communication signal having a dc offset corresponding to the mixer gain that has been corrected.

Likewise, step 1202 may receive a communication signal from an LNA having a plurality of gains at a mixer signal input. Then, the process of generating an initial fine correction value in step 1208 includes: an initial fine correction value is generated for each LNA gain. The process of generating the coarse correction value in step 1211a includes: for each LNA gain, a coarse correction value is generated. The process of generating the final fine correction value in step 1211c includes: a final fine correction value is generated for each LNA gain. Step 1218 then provides a digital communication signal that has been corrected for the dc offset corresponding to the LNA gain.

In one aspect, the process of generating the coarse correction value in step 1211a includes several sub-steps (not shown). Step 1211a1 produces an error represented by the accumulated coarse corrected digital value. Step 1211a2 converts the coarse corrected digital value to an analog corrected value, and step 1211a3 adds the analog corrected value to the current input to the mixer.

In another aspect, step 1217b generates a tracking correction value in the communication state. Step 1217c subtracts the tracking correction value from the digital communication signal and step 1218 provides a digital communication signal having the dc offset subject to coarse and tracking corrections. In one aspect, step 1217d adjusts the tracking correction value and provides the adjusted tracking correction value as an updated coarse correction value. In one aspect, tracking corrections may be made for each LNA and mixer gain state. If the signal has subcarriers that are offset from the carriers by the first frequency (f1) (i.e., an OFDM signal), step 1217b tracks the correction value with a tracking bandwidth that is less than f 1. If the OFDM signal includes a periodic pilot signal, providing the digital communication signal in step 1218 includes increasing a probability of acquiring the pilot signal in response to providing the dc offset corrected digital communication signal.

Alternatively, the flow diagrams of fig. 12A and 12B may be considered to represent a signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform operations for correcting dc offset in a portable wireless communications receiver.

The foregoing has provided systems and methods for correcting dc offset in a wireless communication receiver. Some specific examples of designs, circuits, etc., and potential assumptions have been presented above to illustrate the invention. However, the present invention is not limited to these examples. Although explained above in the context of a wireless receiver, the invention may be applied to other types of receivers. Those skilled in the art will appreciate other variations and embodiments of the invention.

Claims (27)

1. A method for correcting direct current (dc) offset in a wireless communication receiver, the method comprising:

in a communication state, receiving a communication signal at a mixer signal input;

subtracting the fine correction value from the analog-to-digital converted communication signal; and

a digital communication signal is provided with an initially fine corrected dc offset.

2. The method of claim 1, further comprising:

disconnecting the mixer signal input from the received communication signal in an initialization state occurring prior to the communication state;

receiving an analog signal from a mixer output;

converting the analog signal to a digital signal;

generating the initial fine correction value;

subtracting the initial fine correction value from the digital signal; and

in response to the initial fine correction value, the digital signal amplitude is minimized.

3. The method of claim 2, further comprising:

in an initialization state, generating a coarse correction value;

adjusting a current input to the mixer using the coarse correction value;

wherein minimizing the digital signal amplitude comprises minimizing the digital signal amplitude in response to the coarse correction value;

the method further comprises:

operating the mixer with coarse numerical correction in a communication state; and

wherein providing the digital communication signal comprises providing the digital communication signal with the coarse corrected and initial fine corrected dc offset.

4. A method as claimed in claim 3, wherein generating the coarse correction value comprises using an adjusted version of the initial fine correction value as the initial coarse value.

5. The method of claim 3, further comprising:

in an initialization state, generating a final fine correction value while operating the mixer with the coarse value correction;

wherein subtracting the fine correction value from the digital communication signal comprises subtracting the final fine correction value from the digital communication signal: and

wherein providing the digital communication signal comprises providing the digital communication signal with the coarsely corrected and finally finely corrected dc offset.

6. The method of claim 5, wherein receiving an analog signal from a mixer output comprises receiving an analog signal from a mixer having a plurality of gains;

wherein generating an initial fine correction value comprises generating an initial fine correction value for each mixer gain;

wherein generating the coarse correction value comprises generating the coarse correction value for each mixer gain;

wherein generating the final fine correction value comprises generating the final fine correction value for each mixer gain; and

wherein providing the digital communication signal comprises providing the digital communication signal with a corrected dc offset corresponding to the mixer gain.

7. The method of claim 5, wherein receiving the communication signal at the mixer signal input comprises receiving the communication signal from a Low Noise Amplifier (LNA) having a plurality of gains;

wherein generating an initial fine correction value comprises generating an initial fine correction value for each LNA gain;

wherein generating the coarse correction value comprises generating the coarse correction value for each LNA gain;

wherein generating the final fine correction value comprises generating the final fine correction value for each LNA gain; and

wherein providing the digital communication signal comprises providing the digital communication signal with the corrected dc offset corresponding to the LNA gain.

8. The method of claim 7, further comprising:

generating a tracking correction value in a communication state;

subtracting the tracking correction value from the digital communication signal; and

wherein providing the digital communication signal comprises providing the digital communication signal with the coarsely corrected and tracking-corrected dc offset.

9. The method of claim 8, further comprising:

updating the coarse correction value with the adjusted version of the tracking correction value.

10. The method of claim 8, wherein receiving a communication signal at a mixer signal input comprises receiving an Orthogonal Frequency Division Multiplexed (OFDM) signal with a first subcarrier located at a first frequency (f1) offset from the carrier;

wherein generating the tracking correction value comprises tracking the correction value with a tracking bandwidth less than f 1.

11. The method of claim 8, wherein receiving a communication signal comprises receiving an OFDM signal having a periodic pilot signal; and

wherein providing the digital communication signal comprises increasing a probability of acquiring the pilot signal in response to providing the digital communication signal with the corrected dc offset.

12. The method of claim 5, wherein generating a coarse correction value comprises:

generating an error represented by the accumulated coarse corrected digital value;

converting the coarsely corrected digital values to analog corrected values; and

the analog correction value is added to the current input to the mixer.

13. In a portable wireless communications receiver, a signal-bearing medium tangibly embodying a program of machine-readable instructions executable by a digital processing apparatus to perform operations for correcting direct current (dc) offset, the operations comprising:

in an initialization state, generating a fine correction value;

in a communication state, receiving a communication signal at a mixer signal input;

subtracting the fine correction value from the converted digital communication signal; and

a digital communication signal having a fine corrected dc offset is provided.

14. In a wireless communication receiver, a system for correcting direct current (dc) offset in a received communication signal, the system comprising:

a mixer having a signal input for receiving a communication signal in a communication state and an analog output;

an analog-to-digital converter (ADC) having an input coupled to the mixer output and having an output to provide a digital signal;

a summing circuit having a first input connected to the output of the ADC, a second input, and an output to provide a summed digital signal, wherein the second input is subtracted from the first input;

a dc offset correction module having an input to receive the summed digital signal and an output to provide an initial fine correction value to the second input of the summing circuit; and

wherein in the communication state the summing circuit subtracts the initial fine correction value from the ADC output to provide the digital communication signal with the initial fine corrected dc offset.

15. The system of claim 14, wherein the mixer signal input is selectively disconnected from the received communication signal in an initialization state occurring prior to the communication state; and

wherein the dc offset correction module provides the initial fine correction value to the second input of the summing circuit to minimize the summed digital signal amplitude in the initialization state.

16. The system of claim 15, wherein the mixer has a power supply input;

wherein the DC offset correction module has an output connected to the mixer power supply input to provide a coarse correction value to minimize the summed digital signal amplitude in an initialization state; and

wherein in a communication state the summing circuit provides the digital communication signal with the coarsely corrected and initially finely corrected dc offset.

17. The system of claim 16, wherein the dc offset module adjusts the initial fine correction value and provides the adjusted initial fine correction value as an initial coarse correction value.

18. The system of claim 15, wherein the dc offset correction module provides a final fine correction value to the summing circuit and a coarse correction value to the mixer in an initialization state; and

wherein in a communication state the summing circuit provides a digital communication signal having the coarsely corrected and finally finely corrected dc offset.

19. The system of claim 18, wherein the mixer has a plurality of gain states;

wherein in an initialization state, for each mixer gain state, the dc offset correction module generates an initial fine correction value, a coarse correction value, and a final fine correction value; and

wherein the summing circuit provides a digital communication signal having a corrected dc offset corresponding to the mixer gain.

20. The system of claim 18, further comprising:

a Low Noise Amplifier (LNA) having a plurality of gain states, an input connected to the wireless air interface and an output connected to the mixer signal input;

wherein in an initialization state, for each LNA gain state, the DC offset correction module generates an initial fine correction value, a coarse correction value, and a final fine correction value; and

wherein the summing circuit provides a digital communication signal having a corrected dc offset corresponding to the LNA gain.

21. The system of claim 18, wherein the dc offset correction module provides a tracking correction value to the summing circuit in the communication state; and

wherein the summing circuit provides a digital communication signal having the coarsely corrected and tracking-corrected DC offset during the communication state.

22. The system of claim 21, wherein the mixer signal input receives an Orthogonal Frequency Division Multiplexed (OFDM) signal with a first subcarrier located at a first frequency (f1) offset from the carrier; and

wherein the DC offset correction module generates the tracking correction value using a tracking bandwidth less than f 1.

23. The system of claim 21, wherein the mixer signal input receives an OFDM signal having a periodic pilot signal; and

wherein the summing circuit provides a digital communication signal having a reduced probability of pilot signal false alarm in response to the corrected DC offset.

24. The system of claim 18, wherein the dc offset correction module generates a coarse correction value as an accumulated coarse correction digital value; and

the system further comprises:

a digital-to-analog converter (DAC) having an input connected to receive the coarse corrected digital value and an output connected to the mixer power supply input.

25. The system of claim 21, wherein the dc offset correction module generates an adjusted tracking correction value and provides the adjusted tracking correction value as an updated coarse correction value.

26. In a wireless communication receiver, a system for correcting direct current (dc) offset in a received communication signal, the system comprising:

means for mixing an input signal with a Local Oscillator (LO) signal, having a signal input to receive a communication signal in a communication state, and having an analog output;

means for converting the analog signal to a digital signal having an input connected to the output of the mixing means and an output for providing the digital signal;

summing means having a first input connected to an output of the analog-to-digital conversion (ADC) means, a second input, and an output for providing a summed digital signal, wherein the second input is subtracted from the first input;

means for correcting the dc offset having an input for receiving a signal from the summing means and an output for providing a fine correction value to a second input of the summing means; and

wherein in the communication state the summing device subtracts the fine correction value from the output of the ADC device to provide the digital communication signal with the fine corrected dc offset.

27. In a wireless communication receiver, a processor device for correcting direct current (dc) offset in a received communication signal, the processor device comprising:

a mixer module having a signal input for receiving a communication signal in a communication state and an analog output;

an analog-to-digital converter (ADC) module having an input connected to the mixer module output and an output for providing a digital signal;

a summing module having a first input connected to the output of the ADC module, a second input, and an output for providing a summed digital signal, wherein the second input is subtracted from the first input;

a dc offset correction module having an input for receiving the summed digital signal and an output for providing a fine corrected value to a second input of the summing module; and

wherein in the communication state the summing module subtracts the fine correction value from the ADC module output to provide the digital communication signal with the fine corrected dc offset.