HK1117646B - Power mosfet wafer level chip-scale package - Google Patents

Abstract

The present invention discloses a chip level chip scale packaging method for power MOSFETs, which includes: chemically plating multiple contact areas on the back and front of the chip, and forming solder balls on the plated multiple contact areas before cutting the chip into multiple power MOSFET chips.In alternative embodiments, the method comprises the steps of setting a permanent protective layer on the back of the chip, chemically plating multiple contact areas on the front of the chip, and forming solder balls on the plated multiple contact areas before cutting the chip into multiple power MOSFET chips.

Description

Wafer level chip scale packaging of power MOSFETs

Technical Field

The present invention relates to packaging of power electronic devices, and more particularly to wafer-level chip-scale packaging of power MOSFETs and related packaging processes.

Background

Wafer level chip scale packaging produces semiconductor packages having dimensions similar to or slightly larger than the semiconductor chips. Typically, semiconductor packages are formed on a wafer having a plurality of semiconductor chips, and then individual packages are cut from the wafer.

In the case of a power MOSFET, the source and gate contact areas are typically located on the front side of the chip, while the drain is located on the back side of the chip, which is metallized. In a wafer-level chip-scale package of a power MOSFET, the drain must extend to the front side of the chip, or a common drain structure comprising two chips can be used, with solder balls for electrical connection to a printed circuit board being able to be formed on metal areas of the same front side of the chip. In each case, however, a metallized back side is still necessary and/or advantageous.

There are particular challenges in the fabrication of wafer-level chip-scale packages for power MOSFETs. More specifically, electroless plating is conventionally used in an Under Bump Metallization (UBM) process, which is simple and low cost because a mask is not required. Since the back side metal is typically different from the metal of the front side of the wafer, contamination of the electroless plating agent can occur during the electroless plating process if the back side is not properly protected.

Conventionally, a temporary protective layer of a thin film tape or a photoresist that blocks electroless plating agents and electroless plating temperatures in an electroless plating process is applied on the back metal. After the electroless plating process is completed, the temporary protective layer must be removed. The application and subsequent removal of the temporary protective layer increases the overall complexity of the packaging process, increasing cost but reducing yield.

As an alternative to protecting the backside of the wafer, the electroless plating step may be followed by a back grinding and backside metallization step. However, this process flow is not always feasible and/or convenient.

There is therefore a need for a wafer-level chip-scale packaging process for power MOSFETs that overcomes the limitations of the prior art. Preferably, the process employs electroless plating of the under bump metal plating and provides a wafer level chip scale package for the power MOSFET that is easy to manufacture in a low cost and efficient manner.

Disclosure of Invention

The invention aims to provide a wafer-level chip scale package of a power MOSFET, which adopts electroless plating for a lower convex point metal plating layer, and has low manufacturing cost and high manufacturing efficiency.

To achieve the above object, the present invention provides a wafer level chip scale package of a power MOSFET, the method comprising the steps of: electroless plating Ni to the back side material layer of the wafer and electroless plating Ni to the plurality of contact regions on the front side of the wafer; forming solder balls on the plated plurality of contact areas; the wafer is diced to form a plurality of power MOSFET chips.

The present invention also provides a method of fabricating a wafer level chip scale package of a power MOSFET, the method comprising the steps of: setting a permanent protective layer on the back of the wafer; chemically plating Ni to a plurality of contact regions of the front side of the wafer; solder balls are formed on the plated plurality of contact areas.

The present invention also provides a method of fabricating a wafer level chip scale package of a power MOSFET, the method comprising the steps of: providing a permanent blank substrate on the back side of the wafer; a plurality of contact areas on the front side of the under bump metallized wafer by sputtering and electrolytic plating; solder balls are formed on the plated plurality of contact areas.

The wafer-level chip scale package of the power MOSFET adopts chemical plating for the lower convex point metal plating layer, and has low manufacturing cost and high manufacturing efficiency.

So that the manner in which the following detailed description of the invention, as well as the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. There are, of course, additional features of the invention that will be described hereinafter and which will form the subject matter of the claims appended hereto.

In this respect, before explaining at least one embodiment of the invention in detail, it is to be understood that the invention is not limited in its application to the details of the functional components set forth in the following description or illustrated in the drawings and to the arrangements of these components. The invention is capable of other embodiments and of being practiced and carried out in various ways. Also, it is to be understood that the phraseology and terminology employed herein, as well as the abstract, are for the purpose of description and should not be regarded as limiting.

As such, those skilled in the art will appreciate that the conception, upon which this disclosure is based, may readily be utilized as a basis for the designing of other methods and systems for carrying out the several purposes of the present invention. It is important, therefore, that the claims be regarded as including such equivalent constructions insofar as they do not depart from the spirit and scope of the present invention.

Drawings

FIG. 1 is a flow chart illustrating an exemplary method of fabricating a wafer level chip scale package of a power MOSFET in accordance with the present invention;

FIG. 2 is a schematic diagram of a step in the method of FIG. 1;

FIG. 3 is a schematic diagram of another step in the method of FIG. 1;

FIG. 4 is a schematic illustration of another step in the method of FIG. 1;

FIG. 5 is a flow chart illustrating another exemplary method of fabricating a wafer level chip scale package of a power MOSFET in accordance with the present invention;

FIG. 6 is a schematic diagram of a step in the method of FIG. 5;

FIG. 7 is a schematic illustration of another step in the method of FIG. 5;

FIG. 8 is a schematic illustration of another step in the method of FIG. 5;

FIG. 9 is a schematic illustration of another step in the method of FIG. 5;

FIG. 10 is a flow chart illustrating yet another exemplary method of fabricating a wafer level chip scale package for a power MOSFET in accordance with the present invention;

FIG. 11 is a schematic diagram of a step in the method of FIG. 10;

FIG. 12 is a schematic view of another step in the method of FIG. 10;

FIG. 13 is a schematic illustration of another step in the method of FIG. 10;

FIG. 14 is a schematic illustration of another step in the method of FIG. 10; and

fig. 15 is a schematic diagram of a common drain power MOSFET package according to the present invention.

Detailed Description

The present invention will now be described in detail with reference to the attached drawings, which are illustrated in fig. 1-15, and which are provided as illustrative embodiments of the invention to enable one skilled in the art to practice the invention. It should be noted that the drawings and examples set forth below are not intended to limit the scope of the present invention. Where certain elements of the present invention can be partially or fully implemented using known elements, only those portions of such known elements that are necessary for an understanding of the present invention will be described, and detailed descriptions of other portions will be omitted so as not to obscure the features of the present invention. Additionally, the present invention also encompasses present known and future understood equivalents to the various components referred to herein by way of illustration.

The present invention finds applicability in chip scale packaging of a common drain power MOSFET chip structure or a single power MOSFET chip structure having a gate region, a source region and a drain region on the front side of the chip, and a back electrode electrically connected to the front side region by a heavily doped recess or other type of electrical connection, such as two or more MOSFETs electrically connected to the drain of a side MOSFET or a vertical MOSFET. Back side metal is still required in all these respects, but electrical contacts need not be made on the back side metal.

A wafer-level chip-scale packaging method for an exemplary power MOSFET, generally designated 100, will be discussed with reference to fig. 1-4. At step 110, a wafer 200 on which a plurality of power MOSFET chips have been formed is received. Wafer 200 includes a plurality of contact regions 210 that provide connections to chip contacts. The backside 215 of the wafer 200 includes a layer of material 220, which may include Al or Zn that can be electrolessly plated without contaminating the plating bath. Preferably, the material layer 220 is formed of Ti/Al or a Ti/Al alloy.

Ni electroless plating is then performed at step 120, followed by Au wetting to plate the plurality of contact areas 210 and the metallized backside 215. As shown in fig. 3, a Ni layer 230 is plated onto the contact region 210 and a Ni layer 240 is plated onto the metallized backside 215. A gold layer 235 is deposited on Ni layer 230 and a gold layer 245 is plated on Ni layer 240.

At step 130, solder balls 250 are formed on the plated contact regions 210 and the wafer is diced at step 140. The resulting wafer-level chip-scale packaging of the power MOSFET provides protection and good solderability to the backside of the wafer. The resulting back surface also facilitates laser mark engraving.

With respect to another aspect of the invention, a wafer level chip scale packaging method for a power MOSFET, generally designated 500, will be discussed with reference to fig. 5-9. At step 510, a wafer 600 having a plurality of power MOSFET chips formed thereon is received. Wafer 600 includes a plurality of contact regions 610 that provide connections to chip contacts. Contact region 610 is preferably Al or an Al alloy. The backside 615 of wafer 600 typically includes a Ti/Ni/Ag layer 620.

At step 520, a permanent passivation layer 625 is deposited over the Ti/Ni/Ag layer 620. The permanent passivation layer 625 may be deposited by spin-on coating, PVD, CVD, or the like. In another aspect of the invention, the permanent passivation layer 625 may be replaced with a high temperature thin film strip. The permanent passivation layer and the high temperature thin film strip may comprise glass, silicon nitride, PTFE and polyamide.

An electroless Ni plating is then performed at 530, followed by a gold wet to plate the plurality of contact regions 610. As shown in fig. 7, a Ni layer 630 is plated onto the contact region 610. A gold layer 635 is deposited onto the Ni layer 630. The permanent passivation layer 625 protects the metallized backside 615 during electroless Ni plating and prevents backside metals such as Ag from contaminating the electroless plating solution.

Solder balls 650 are formed on the plated contact regions 610 at step 540 and the wafer is diced at step 550. The wafer level chip scale packaging method 500 provides protection for the backside of the wafer and is easier to laser mark scribe.

With respect to another aspect of the present invention, a wafer level chip scale packaging method for a power MOSFET, generally designated 1000, will be discussed with reference to fig. 10-14. At step 1010, a wafer 1100 is received on which a plurality of power MOSFET chips have been formed. Wafer 1100 includes a plurality of contact regions 1110 that provide connections to chip contacts. Contact region 1110 is preferably Al or an Al alloy. The backside 1115 of wafer 1100 typically includes a Ti/Ni/Ag layer 1120.

At step 1120, a permanent green substrate 1140 is attached to the Ti/Ni/Ag layer 1120 with a layer 1130 of thermally conductive adhesive or epoxy. The permanent green substrate 1140 provides protection to the back side of the wafer as well as enhanced mechanical strength.

An electroless Ni plating is then performed at step 1030 followed by a gold wet to plate the plurality of contact regions 1110. As shown in fig. 13, a Ni layer 1130 is plated onto contact region 1110. A layer of gold 1135 is deposited onto the Ni layer 1130. The permanent green substrate 1140 protects the metallized backside 1115 during electroless Ni plating and prevents Ti/Ni/Ag contamination of the plating bath.

In an alternative embodiment, a permanent green substrate, such as permanent green substrate 1140, may be used to provide a protective layer as well as a support layer in the UBM process.

Solder balls 1150 are formed on plated contact areas 1110 at step 1040 and the wafer is diced at step 1050.

Although the described wafer-level chip-scale packaging method 1000 of a power MOSFET includes an electroless plating step 1030, the contact regions 1110 can be plated using other UBM processes. For example, Ni-V/Cu formed by a process including sputtering followed by electrolytic plating may replace electroless Ni plating step 1030.

The wafer level chip scale packaging method of the power MOSFET of the invention provides a wafer level chip scale package of the power MOSFET which is easy to manufacture in a low-cost and high-efficiency mode. Figure 15 shows a front view of a wafer level chip scale package according to the results of the claimed process after dicing of the common drain power MOSFET 1500. The common drain power MOSFET 1500 includes two MOSFETs 1501 and 1502 formed side-by-side on the same chip, with the drain electrically connected through a substrate 1510 and a metal layer 1520. The MOSFET 1501 has two source regions S1 and a gate region G1, both connected to solder balls. The MOSFET1502 has two source regions S2 and a gate region G2, both also connected to solder balls. In this exemplary layout, the solder balls have a diameter of about 370 μm, the spacing between the various regions is about 650 μm, and the overall chip size is about 1500 × 2500 μm.

It will be obvious that the above-described embodiments may be varied in many ways without departing from the scope of the present invention. In addition, aspects of particular embodiments may comprise patented subject matter independent of other aspects of the same embodiments. Also, various aspects of the different embodiments may be combined together. The scope of the invention should, therefore, be determined by the appended claims and their legal equivalents.

Claims (19)

1. A method of fabricating a wafer level chip scale package of a power MOSFET, the method comprising the steps of:

electroless plating Ni to the back side material layer of the wafer and electroless plating Ni to the plurality of contact regions on the front side of the wafer; and

solder balls are formed on the plated plurality of contact areas.

2. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, further comprising the step of dicing the wafer to form a plurality of power MOSFET chips.

3. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said contact region comprises Al.

4. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said contact region comprises an Al alloy.

5. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said layer of backside material comprises Ti/Al.

6. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said layer of backside material comprises a Ti/Al alloy.

7. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said back side material layer comprises a metal selected from the group consisting of Ti/Zn, Ti/Pd or any other metal that serves as a seed layer for electroless Ni plating.

8. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 1, wherein said power MOSFET comprises a common drain power MOSFET chip.

9. A method of fabricating a wafer level chip scale package for a power MOSFET as recited in claim 1, wherein said plurality of contact regions comprise source, gate and drain contact regions.

10. A method of fabricating a wafer level chip scale package of a power MOSFET, the method comprising the steps of:

setting a permanent protective layer on the back of the wafer;

chemically plating Ni to a plurality of contact regions of the front side of the wafer; and

solder balls are formed on the plated plurality of contact areas.

11. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 10, wherein said protective layer comprises a passivation layer.

12. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 10, wherein said protective layer comprises a thin film strip capable of withstanding electroless plating and temperatures associated with electroless plating and solder reflow.

13. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 10, wherein said protective layer comprises a green substrate.

14. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 13, wherein said green substrate is bonded to said back surface by an adhesive layer.

15. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 13, wherein said green substrate is bonded to said back surface by an epoxy layer.

16. A method of fabricating a wafer level chip scale package of power MOSFETs according to claim 10, further comprising the step of dicing the wafer to form a plurality of power MOSFET chip scale packages.

17. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 10, wherein said contact region comprises Al.

18. A method of fabricating a wafer level chip scale package of a power MOSFET as recited in claim 10, wherein said contact region comprises an Al alloy.

19. A method of fabricating a wafer level chip scale package of a power MOSFET, the method comprising the steps of:

providing a permanent blank substrate on the back side of the wafer;

a plurality of contact areas on the front side of the under bump metallized wafer by sputtering and electrolytic plating; and

solder balls are formed on the plated plurality of contact areas.