HK1115012A - Correlator for primary cell search using memory architecture - Google Patents

Description

Correlator for primary cell search using memory architecture

Technical Field

The present invention relates to mobile terminals, and more particularly to correlators used in primary cell search.

Background

The basic unit of time in a UMTS radio signal is a 10 millisecond (ms) radio frame that is divided into 15 slots of 2560 chips each. UMTS radio signals from a cell (or base station) to a UMTS receiver are "downlink signals" and signals in the opposite direction are referred to as "uplink signals".

The physical layer of the Universal Mobile Telecommunications System (UMTS) Wideband Code Division Multiple Access (WCDMA) standard uses Direct Sequence Spread Spectrum (DSSS) modulation at a chip rate of 3.84 Mcps. The frequency division multiplexing (FDD) mode carries uplink and downlink channels through separate frequency bands, each of which is 5 MHz. This mode is typically used for large outdoor cells, since it can support a larger number of users than Time Division Duplex (TDD) mode. In TDD mode, transmissions share the same uplink and downlink channels during different time slots. TDD mode does not support as many users as FDD mode, and thus TDD mode is more suitable for smaller cells. TDD mode is also better suited to carry asymmetric traffic than FDD mode.

An important process performed by a receiver (e.g., a CDMA mobile receiver) in a UMTS network is a cell search operation. Cell search is typically performed by a cell search system incorporated as part of the receiver. The cell search system is activated after the receiver is powered on to determine synchronization information related to the cell in which the receiver is located. The cell search operation is a three-stage process. That is, the cell search system performs slot synchronization (primary synchronization), frame synchronization and scrambling code group determination (secondary synchronization), and scrambling code determination.

After power-up, the Mobile Terminal (MT) must perform a number of operations before voice/data communication can begin. First, the receiver needs to implement Automatic Gain Control (AGC) to scale the received signal power and avoid clipping at the analog-to-digital converter. This process may be performed first on the Synchronization Channel (SCH), and then once the cell's scrambling code is acquired, the descrambled common pilot channel (CPICH) may be used.

The receiver then needs to acquire timing synchronization. Timing synchronization may be achieved from the SCH channel. The MT searches for the strongest SCH signal that the MT can find, which determines with which cell the MT will initiate communication. Since the SCH channel is periodic, the receiver can correlate with the primary SCH to derive a timing error. Based on the channel, the receiver can achieve chip synchronization, symbol synchronization, and slot synchronization.

The primary SCH carries the same signal for all cells in the system. The secondary SCH is different for each cell and carries a pattern of Secondary Synchronization Codes (SSCs) that repeat every frame. Once the MT receives the sequence, it will have frame synchronization.

In performing cell search, the cell search system accesses a Synchronization Channel (SCH) of a received wireless signal and a common pilot channel (CPICH). The SCH is a composite channel composed of a primary SCH and a secondary SCH. Within each slot, the primary SCH specifies a Primary Synchronization Code (PSC). However, the primary SCH only contains data during the first 256 chips of each 2560 chip slot. As is known, "chip" or "chip rate" indicates the rate of a spreading code in a CDMA communication system.

In addition, the pattern identifies which scrambling code group the scrambling code of the current cell belongs to. There are 64 scrambling code groups, each group containing eight scrambling codes. Once the MT determines the scrambling code group of the current cell, the search for the scrambling code of the current cell is narrowed to eight codes in the group.

A typical acquisition process for a carrier-based receiver is as follows:

1. primary cell search

2. Secondary cell search

3. Scrambling code determination

4. Multipath searching

5. Demodulator (finger) allocation

6. Code tracking and Automatic Frequency Control (AFC) loop locking

7. Maximal Ratio Combining (MRC) of demodulator outputs

8. Obtain receiver lock and send data to upper layer

This acquisition process is long and complex and may take several seconds to complete.

The problem solved is how to implement an area optimized correlation module for the second stage of the primary cell search process in a 3G WCDMA receiver. The first stage of the primary cell search process involves correlating 16 consecutive samples in a row and generating a correlation output every 16 chips. The storage requirement for the first stage correlator is therefore that for a given correlation, the correlator only needs to store 16 chips at a time, which is relatively easy to implement. Even for a receiver using 4 samples per chip, the memory requirement is still only 256 samples, and the samples are consecutive samples. This means that the first stage correlator processes successive sample groups as they arrive.

Each correlation in the second stage of processing also requires 16 chips. However, each of the 16 chips is spaced apart by 16 chips due to the characteristics of a hierarchical Golay code (Golay code) used in the 3GCDMA standard. Thus, for a receiver that uses 4 samples per chip, 256 chips still need to be processed, but the chips are not located consecutively. Conversely, a given correlation requires 265 chips that are 16 x 4-64 samples apart. To store all the samples required for a given second stage correlation, the receiver would need a tapped delay line with 1024 positions (16 chips apart is 256 chips, 4 samples per chip is 1024 samples). The prior art uses a register-based design to achieve this second level of correlation. This number of registers (e.g., 1024) is not practical in ASIC design because it consumes a lot of die space on the ASIC. Therefore, a more efficient area optimization approach would be beneficial.

Disclosure of Invention

The present invention is an architecture for the second stage of correlators used in the primary cell search process of a 3G WCDMA receiver. The architecture used is memory-based and makes the design area-optimized in terms of die space available on the ASIC.

The present invention uses a memory-based approach because, for a given number of locations, memory is more efficient than registers. However, the nature of dual port RAM memory modules means that the number of memory reads/writes that can be performed in a given clock cycle is limited to one read and one write per cycle. This presents some challenges to the design of the module, as it does not allow enough reads and writes to complete the entire process within the limit of 32 clock cycles per chip of the receiver. A number of features are added to the architecture to use a single read and a single write per clock cycle to accomplish the desired processing within 32 clock cycles per chip.

An apparatus is described that includes a second stage correlator for receiving input data from a first stage correlator, wherein the second stage correlator uses a memory architecture. Also described is a method for performing a second level of correlation on data, comprising: resetting the read pointer and the write pointer, alternately multiplexing input data into one of a pair of storage registers, linking contents of the pair of storage registers, writing the linked contents into the memory according to the write pointer, outputting the linked contents from the memory to the read register according to the read pointer, updating the read address pointer, and updating the write address pointer.

Drawings

The invention is best understood from the following detailed description when read with the accompanying drawing figures. The drawings comprise the following brief description of the drawings, in which like numerals represent like elements.

FIG. 1 is a top level block diagram of a cell search process;

FIG. 2 is a block diagram of the architecture of the present invention;

FIG. 3 is one embodiment of a read/write pointer usage for a memory in accordance with the principles of the present invention;

fig. 4 is a flow chart in accordance with the principles of the present invention.

Detailed Description

The cell search is performed in the mobile terminal. Referring now to fig. 1, fig. 1 is a top level block diagram of a cell search process, and the present invention includes correlators 125,130 used in the second stage of a primary cell search that receive real 115 and imaginary 120 inputs from the first stage correlators 105,110 of the primary cell search. The outputs of the first stage primary cell search correlators 105, 110 are input to second stage correlators 125, 130. The outputs of the second stage correlators 125, 130 are output to a non-coherent combiner 135, which non-coherent combiner 135 provides an input to a frame buffer 140. Frame buffer 140 provides results of the cell search.

FIG. 2 is a block diagram of the architecture of the present invention. In particular, fig. 2 is the correlator architecture of the present invention for the second stage of the primary cell search. The correlator of the present invention uses a memory architecture that has the advantage of area optimization in terms of die space on the ASIC. The memory read/write address generation module 235 in fig. 2 generates a read/write pointer value (also shown in fig. 3). The second stage correlator 123 of the present invention is effectively a pair of second stage correlators 125,130 which are functionally identical/equivalent. The difference between the pair of second stage correlators 125, 130 is the input data (real versus imaginary) received by each of the second stage correlators.

The correlation outputs (real and imaginary) of the first stage correlator (shown in fig. 1) arrive at multiplexer 205 in fig. 2. These samples arrive 4 times per chip and are alternately multiplexed into the store registers, first into the low store register (store _ low _ reg)210, then into the high store register (store _ high _ reg)215, and then alternating. Based on logic, which will be described in more detail later, the values of the low and high storage registers (each 16 bits wide) are linked at block 225 to form a single 32-bit value, which is then written to memory 230 at a predetermined clock cycle. With this approach, two samples are stored as one value due to the limitation of only one memory write per clock cycle, which design enables two samples to be stored in memory 230 for each given clock cycle. The use of memory 230 here saves chip die space. The prior art implementation uses a set of registers instead of memory.

The value is then read out of the memory from a predetermined location and stored in a read register (read _ reg) 240. From here, the bit is again parsed into a high value and a low value corresponding to the bit and processed into two separate samples. The index generator 245 generates a PSC index/sequence. In block 255, correlation is performed without area intensive multipliers by taking a sample from read _ reg240 and adding or subtracting the sample from the sample in corr _ reg (i.e., increasing the value if the PSC sequence is +1 and subtracting the value if the PSC sequence is-1) based on the stored sign of the PSC sequence block 250. Note that there are 16 corr _ reg registers: corr _ reg0[0] to corr _ reg0[3]270a, corr _ reg1[0] to corr _ reg1[3]270b, corr _ reg2[0] to corr _ reg2[3]270c, and corr _ reg3[0] to corr _ reg3[3]270 d. This is to enable the storage and processing of 4 simultaneous correlations computed in each of the 4 parallel modules. Each set of registers is for 8 clock cycles of the 32 clock cycles available, using only one set of registers at a time. The output of module 255 is multiplexed by multiplexers 260, 265 to associated registers 270a-270 d.

After all 16 values for a given correlation are accumulated in adder block 275, the value stored in corr _ reg is transferred via multiplexer 280 to one of 4 corresponding corr _ out registers 285a-285 d. That is, corr _ out [0] ═ corr _ reg0[0] + corr _ out1[0] + corr _ reg2[0] + corr _ reg3[0]285 a.

The output of the corr _ out register is multiplexed to the non-coherent combiner 135 of fig. 1. The absolute value (abs) of the contents of the corr _ out register must also be obtained. This block is not shown in fig. 2, but the function is performed at the corr _ out register or at an additional block after the multiplexer 290.

The pseudo code shown in table 1 gives more details about how the architecture works. The control module 220 of fig. 2 coordinates and controls the functions and components of the correlator of the present invention. The numbers on the left indicate clock cycles. The architecture of the present invention is based on a 32-cycle per sample clock cycle structure.

Pseudo code:

reset code

rp 3/read pointer-9 bits number

wp is 1// write pointer-9 bits number

corr_reg[0..3]＝0

corr_out[0..3]＝0

Correlation output code

0

corr_out[0]＝corr_reg0[0]+corr_reg1[0]+corr_reg2[0]+corr_reg3[0]

corr_out[1]＝corr_reg0[1]+corr_reg1[1]+corr_reg2[1]+corr_reg3[1]

1

corr_out[2]＝corr_reg0[2]+corr_reg1[2]+corr_reg2[2]+corr_reg3[2]

corr_out[3]＝corr_reg0[3]+corr_reg1[3]+corr_reg2[3]+corr_reg3[3]

Sampling output code

7

samp_out＝abs(corr_out[0])

15

samp_out＝abs(corr_out[1])

23

samp_out＝abs(corr_out[2])

31

samp_out＝abs(corr_out[3])

Memory input/output code:

0，16

storage_low_reg＝samp_in

8，24

storage_high_reg＝samp_in

memory write address＝wp

memory data in＝storage_high_reg concatenated with storage_low_reg

wp--

every clock

read_reg＝data_out from memory

correlation and memory interfacing code:

0

update corr_reg3[0]and corr_reg3[1]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp1

update corr_reg3[2]and corr_reg3[3]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp-1

rp＝rp+322，4，6，8

update corr_reg0[0]and corr_reg0[1]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp3，5，7，9

update corr_reg0[2]and corr_reg0[3]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp-1

rp＝rp+3210，12.14，16

update corr_reg1[0]and corr_reg1[1]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp11，13，15，17

update corr_reg1[2]and corr_reg1[3]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp-1

rp＝rp+3218，20，22，24

update corr_reg2[0]and corr_reg2[1]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp19，21，23，25

update corr_reg2[2]and corr_reg2[3]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp-1

rp＝rp+3226，28，30

update corr_reg3[0]and corr_reg3[1]with samples in read_reg(upper andlower)

write“read”address to memory for two clock cycles ahead-read address is rp27，29，31

update corr_reg3[2]and corr_reg3[3]with samples in read_reg(upper and lower)

write“read”address to memory for two clock cycles ahead-read address is rp-1

if not clock cycle＝31

rp＝rp+32

if clock cycle＝31

rp＝rp-482

the reset code of the pseudo code initializes a read pointer (rp) and a write pointer (wp), both of which are 9-bit numbers, before any other processing starts. The correlation register (corr _ reg) and the correlation output register (corr _ out) are also initialized.

The relevant output code of the pseudo code sets the corr _ out registers [0] and [1] to the contents of the corr _ reg register in clock cycle 0 and the corr _ out registers [2] and [3] to the contents of the corr _ reg register in clock cycle 1.

The sampled output code of the pseudo code provides an output sample of the absolute value (abs) of the corr _ out [0] register (samp _ out) at clock cycle 7. The sampled output code of the pseudo code provides an output sample (samp _ out) of the absolute value (abs) of the corr _ out [1] register at clock cycle 15. The sampled output code of the pseudo code provides an output sample of the absolute value (abs) of the corr _ out [2] register (samp _ out) at clock cycle 23. The sampled output code of the pseudo code provides an output sample of the absolute value (abs) of the corr _ out [3] register (samp _ out) at clock cycle 31.

At clock cycles 0 and 16, the memory input/output code of the pseudo code sets storage _ low _ reg to the output sample (samp _ in). At clock cycles 8 and 24, the memory input/output code of the pseudo code sets storage _ high _ reg to the output sample (samp _ in). Further, at clock cycles 8 and 24, the memory write address is set to the write pointer (wp), the memory address data is set to the storage _ high _ reg linked with the storage _ low _ reg, and then the write pointer is decremented. At each clock cycle, read _ reg is set to data _ out from the memory according to the read address generated by the memory read/write address generation module 235.

The correlation and memory interfacing code of the pseudo code operates as follows:

at clock cycle 0, corr _ reg3[0] and corr _ reg3[1] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp.

At clock cycle 1, corr _ reg3[2] and corr _ reg3[3] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp-1. The read pointer is then incremented 32.

At clock cycles 2, 4, 6, and 8, corr _ reg0[0] and corr _ reg0[1] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp.

At clock cycles 3, 5, 7, and 9, corr _ reg0[2] and corr _ reg0[3] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp-1. The read pointer is then incremented 32.

At clock cycles 10, 12, 14, and 16, corr _ reg1[0] and corr _ reg1[1] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp.

At clock cycles 11, 13, 15, and 17, corr _ reg1[2] and corr _ reg1[3] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp-1. The read pointer is then incremented 32.

At clock cycles 18, 20, 22, and 24, corr _ reg2[0] and corr _ reg2[1] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp.

At clock cycles 19, 21, 23, and 25, corr _ reg2[2] and corr _ reg2[3] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp-1. The read pointer is then incremented 32.

At clock cycles 26, 28, and 30, corr _ reg3[0] and corr _ reg3[1] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp.

At clock cycles 27, 29, and 31, corr _ reg3[2] and corr _ reg3[3] are updated with the high and low samples in the read _ reg. The "read" address is written to the memory two clock cycles in advance and is equal to rp-1. If this is not a clock cycle 31, the read pointer is incremented 32. If this is clock cycle 31, the read pointer is decremented 482.

Referring to fig. 3, the write pointer (wp) is initialized to a value of 1 and decremented twice during each 32 clock cycles (modulo 512). The read pointer (rp) is initialized to a value of 3, incremented 32 fifteen times every 32 clock cycles, and decremented 482(512-30) once every 32 clock cycles. The dual port memory and its use in the present invention is similar to a sliding window or buffer where the read pointer and write pointer address the same memory at different times. That is, there is no overlap between the read memory locations and the written memory locations. This is because there is only one read and one write per clock cycle. The indices of the read and write pointers, as well as the increment and decrement values, will vary if the number of samples/chips increases or decreases. In particular, referring to fig. 3, fig. 3 depicts a dual port memory having 512 locations in this example, each location being 32 bits, a write pointer (wp) being initialized to 1 at reset, and a read pointer being initialized to 3. After the first 32 clock cycles, the write pointer (wp) is 511 and the read pointer (rp) is 1.

Referring now to fig. 4, fig. 4 is a flow chart of the operation of the second stage correlator of the present invention. At step 405, the samples are alternately multiplexed into storage _ reg _ low and storage _ reg _ high. At step 410, the contents of storage _ reg _ low and storage _ reg _ high are linked and written to memory as a single value according to a write pointer (wp) specified by the memory read/write address generation module 235. At step 415, samples from the memory 230 are output into the read _ reg240 at each clock cycle according to the read pointer (rp) specified by the memory read/write address generator 235. At step 420, correlation is performed by adding (+/-) the value of read _ reg240 to the corresponding values of corr _ reg270a-270d based on the sign of the PSC index/sequence stored in block 250. At step 425, after sixteen accumulations, the value of corr _ reg is stored into the corresponding corr _ out 285a-285d registers via adder 275 and multiplexer 280, effectively completing four parallel correlations. At step 430, the absolute value (abs) of the values in the corr _ out 285a-285d registers is obtained at the corr _ out 285a-285d registers or the corr _ out 285a-285d registers are multiplexed to an absolute value block (not shown) and then the correlation values are output.

It is to be understood that the present invention may be implemented in hardware, software, firmware, special purpose processors, or a combination thereof, for example, within a mobile terminal, access point, or a cellular network. Preferably, the present invention is implemented as a combination of hardware and software. Further, the software is preferably implemented as an application program tangibly embodied on a program storage device. The application program may be uploaded to, and executed by, a machine comprising any suitable architecture. The machine is preferably implemented on a computer platform having hardware such as one or more Central Processing Units (CPU), a Random Access Memory (RAM), and input/output (I/O) interfaces. The computer platform also includes an operating system and microinstruction code. The various processes and functions described herein may either be part of the microinstruction code or part of the application program (or a combination thereof) and executed by the operating system. In addition, various other peripheral devices may be connected to the computer platform such as an additional data storage device and a printing device.

It is to be further understood that, because some of the constituent system components and method steps depicted in the accompanying figures are preferably implemented in software, the actual connections between the system components (or the process steps) may differ depending upon the manner in which the present invention is programmed. Given the teachings herein, one of ordinary skill in the related art will be able to contemplate these and similar implementations or configurations of the present invention.

Claims (15)

1. An apparatus comprising a second stage correlator for receiving input data from a first stage correlator, wherein the second stage correlator uses a memory architecture.

2. The apparatus of claim 1, wherein said second stage correlator comprises a pair of second stage correlators, further wherein a first one of said pair of second stage correlators receives and processes real valued input data and a second one of said pair of second stage correlators receives and processes imaginary valued input data.

3. The apparatus of claim 2, wherein each second stage correlator of the pair of second stage correlators is functionally equivalent.

4. The apparatus of claim 2, wherein each second stage correlator of the pair of second stage correlators further comprises:

a first multiplexer for receiving data;

a first storage register for receiving and storing a first location of the input data;

a second storage register for receiving and storing a second location of the input data;

a linker for linking the first unit of input data and the second unit of input data;

a memory for receiving and storing the linked input data;

a read/write address generation unit for generating a read/write pointer value for the memory; and

a read register for extracting and storing the linked input data.

5. The apparatus of claim 4, further comprising:

means for parsing the linked input data into two separate data units;

a plurality of correlation registers;

an adder and a sign changer for performing correlation by one of: adding the parsed data to data in one of the plurality of associative registers and subtracting the parsed data from data in one of the plurality of associative registers;

a second multiplexer for multiplexing outputs from the adder and the sign changer to the plurality of correlation registers;

a third multiplexer for multiplexing outputs from the adder and the sign changer to the plurality of correlation registers;

an adder for accumulating correlation values stored in the plurality of correlation registers;

a plurality of correlation output registers;

a fourth multiplexer for multiplexing the accumulated correlation value to one of the plurality of correlation output registers;

a fifth multiplexer for outputting the accumulated correlation value from the correlation output register;

an index generator for generating a primary synchronization code index;

a master sync storage unit for storing a master sync sequence; and

and the control unit is used for controlling the relevant process.

6. The apparatus of claim 5, wherein the primary synchronization unit makes the primary synchronization sequence available to the adder and sign changer to determine whether to add the parsed data to or subtract the parsed data from the data in the one of the plurality of correlation registers.

7. The apparatus of claim 4, wherein the memory is a dual port memory that is written using a write pointer and read using a read pointer.

8. The apparatus of claim 5, wherein the correlation registers process correlations simultaneously.

9. The apparatus of claim 5, further comprising means for performing an absolute value function on the accumulated correlation values.

10. The device of claim 1, wherein the device is a mobile device.

11. A method for performing a second level of correlation on data, the method comprising:

resetting the read pointer and the write pointer;

alternately multiplexing input data into one of a pair of storage registers;

linking the contents of the pair of storage registers;

writing the content of the link into a memory according to the write pointer;

outputting the linked content from the memory to a read register according to the read pointer;

updating the read address pointer; and

and updating the write address pointer.

12. The method of claim 11, further comprising:

clearing a plurality of associated registers;

updating the plurality of correlation registers using data in the read register;

storing the accumulated correlation values in a plurality of correlation output registers; and

performing an absolute value function on the accumulated correlation values stored in the plurality of correlation output registers.

13. The method of claim 12, wherein the step of updating the plurality of correlation registers using data in a read register is performed based on a sign of a primary synchronization code sequence.

14. The method of claim 13, wherein the step of updating the plurality of correlation registers using data in a read register performs parallel correlations.

15. The method of claim 12, wherein the step of updating the plurality of correlation registers using data in a read register performs correlation by one of: adding the data in the read register to the data stored in the plurality of correlation registers, and subtracting the data in the read register from the data stored in the plurality of correlation registers.