HK1114955B - Method for inhibiting thermal run-away - Google Patents

Description

Method for suppressing heat dissipation

Technical Field

The present invention relates generally to power converters, and more particularly, to multiphase power converters.

Background

Power converters are used in a variety of electronic products including automobiles, airplanes, radio communication systems, and consumer electronics. Power converters, such as direct current to direct current ("DC-DC") converters, are widely used in portable electronic products, such as notebook computers, personal digital assistants, pagers, mobile phones, and the like, which are typically powered by batteries. A DC-DC converter can release multiple voltages from a single voltage independent of the load current flowing from the converter or from any variation in the power supply to the converter. One type of DC-DC converter used in portable electronic applications is a buck converter. Such a converter, also referred to as a switched mode power supply, can convert an input voltage from a certain level to a lower level. Typically, the buck converter is controlled by a controller configured as a multi-phase controller having multiple output current paths that switch at different times. The output currents flowing in the output current channels are summed and discharged to the load. The advantage of this configuration is that each channel conducts a portion of the total load current. For example, in a four-phase buck controller, each channel conducts 25% of the output current. This reduces the power dissipation per output. One drawback of multi-phase buck controllers is that when the currents are unbalanced, one current path will conduct more current than the other, which will result in thermal failure. Another disadvantage is that the repetition rate of the power load connected to the controller may be the same as one output of the multi-phase buck converter. In this case, the current in the channels becomes unbalanced causing the converter to suffer thermal failure.

Therefore, there is a need for a multi-phase controller circuit and method of operating a multi-phase controller circuit that maintains current balance at its outputs. Furthermore, the manufacture of multi-phase controller circuits is expected to be cost and time efficient.

Drawings

The invention will be better understood from a reading of the following detailed description taken in conjunction with the drawings in which like reference designators refer to like elements and in which:

FIG. 1 is a schematic diagram of a multi-phase controller circuit consistent with an embodiment of the present invention;

FIG. 2 is a schematic diagram of a portion of the multi-phase controller circuit of FIG. 1;

FIG. 3 is a timing vector diagram for operating the multi-phase controller circuit of FIG. 1;

FIG. 4 is a schematic diagram of a multi-phase controller circuit consistent with another embodiment of the present invention;

FIG. 5 is a schematic diagram of a portion of the multi-phase controller circuit of FIG. 4; and

fig. 6 is a schematic diagram of a multi-phase controller circuit consistent with yet another embodiment of the present invention.

Detailed Description

In general, the present invention provides a method of balancing currents in a multiphase power converter at different load transition rates. The multiphase power converter includes an oscillator or other ramp signal generator, a pulse width modulator, and at least one power stage. In accordance with one aspect of the invention, the currents are balanced by dithering an output signal of an oscillator or other ramp signal generator. It should be understood that the dither output signal is defined as continuously changing the frequency of the oscillator output signal or the ramp signal. The dither oscillator output signal or ramp signal causes the load step rate (step rate) and the switching frequency of the multiphase power controller to not match for an active period. Balancing the currents suppresses heat dissipation in the multiphase power converter.

In accordance with another aspect of the invention, the currents are balanced by disabling the oscillator output signal. This introduces a phase delay in the output signal to bring the output signal out of sync with the load step rate.

In accordance with yet another aspect of the present invention, the current is balanced by dithering the oscillator output signal or ramp signal and pausing the oscillator output signal.

Fig. 1 is a block diagram of a multiphase power converter 10 fabricated in a semiconductor substrate consistent with an embodiment of the invention. Shown in FIG. 1 is that there are n sets of inputs 12₁、12₂、12₃......12_nA pulse width modulator ("PWM") circuit 12, where "n" is an integer. Each of the "n" sets of inputs includes an error input 12_nAAnd an oscillating input 12_nB. It should be noted that the letters "a" and "B" are reference marks for distinguishing error inputs and oscillation inputs, respectively. Thus, input 12₁Including an error input 12_1AAnd an oscillating input 12_1B(ii) a Input 12₂Including an error input 12_2AAnd an oscillating input 12_2B(ii) a Input 12₃Including an error input 12_3AAnd an oscillating input 12_3B(ii) a And an input 12_nIncluding an error input 12_nAAnd an oscillating input 12_nB。

Multiphase power converter 10 further includes an error amplifier 16 having an output 17 and an error input 12, and an oscillator 18_1A、12_2A、12_3A......12_nAConnected, the oscillator having an input 32 and a plurality of outputs, wherein the plurality of outputs are connected to respective oscillating inputs 12_1B、12_2B、12_3B......12_nBAnd (4) connecting. Consistent with one embodiment, error amplifier 16 includes an operational amplifier 20 connected in a negative feedback configuration in which an impedance 22 is connected between the output of operational amplifier 20 and its inverting input, and an impedance 24 is connected to the inverting input of operational amplifier 20.By way of example, impedance 22 includes a capacitor 26 in parallel with a resistor 28 and a capacitor 30 in series, and impedance 24 includes a resistor. The non-inverting input of operational amplifier 20 is coupled to receive a reference level V_REF1. It should be understood that the feedback configuration of error amplifier 16 is not a limitation of the present invention and may be implemented using other feedback configurations known to those skilled in the art.

Output 14 of PWM circuit 12₁、14₂、14₃......14_nEach associated with a respective power stage 34₁、34₂、34₃......34_nIs connected to the input of (1). Power stage 34₁Is connected to the output node 50. Similarly, power stage 34₂、34₃......34_nIs connected to the output node 50. Power stage 34₁、34₂、34₃......34_nRespectively having the generation of a feedback current I_FEED1、I_FEED2、I_FEED3......I_FEEDnCurrent sensing module 35₁、35₂、35₃......35_nThese feedback currents flow through the energy storage element 44₁、44₂、44₃......44_nIs proportional to the current. Feedback current signal I_FEED1、I_FEED2、I_FEED3......I_{FEED n}Respectively through feedback connection lines 37₁、37₂、37₃......37_nFed back to the PWM circuit 12. Circuits for current sensing modules are well known to those skilled in the art.

Power stage 34₁、34₂、34₃......34_nIncluding a drive circuit 54₁、54₂、54₃......54_nThe drive circuits in turn each have a power stage 34₁、34₂、34₃......34_nInput of input, and respective switching transistors 56₁、56₂、56₃......56_nAnd a high side driver output connected to the gate of, and a respective switching transistor 58₁、58₂、58₃......58_nIs connected to the low side driver output. High side switching transistor 56₁、56₂、56₃......56_nIs coupled to receive an operating voltage source such as V_CCHigh side switching transistor 56₁、56₂、56₃......56_nWith source electrodes of respective low-side switching transistors 58₁、58₂、58₃......58_nIs connected to the drain of (1). Low side switching transistor 58₁、58₂、58₃......58_nIs coupled to receive an operating voltage source such as V_ss. Transistor 56₁、56₂、56₃......56_nAnd a source and a drain of transistor 58, respectively₁、58₂、58₃......58_nAre commonly connected together and are each connected to a respective energy storage element 44₁、44₂、44₃......44_nIs connected to one end point. Energy storage element 44₁、44₂、44₃......44_nAs the other end point of the power stage 34₁、34₂、34₃......34_nTo output of (c). For example, the energy storage element 44₁、44₂、44₃......44_nIs an inductor. It should be noted that when n is equal to 2, the power converter 10 is a two-phase power converter; when n is equal to 3, power converter 10 is a three-phase power converter; when n equals 4, the power converter 10 is a four-phase power converter, and so on.

Oscillator control circuit 60 is coupled to input 32 of oscillator 18 through resistor 59. In particular, oscillator control circuit 60 includes a voltage regulator coupled to output 17 of error amplifier 16 to receive compensation voltage V_COMPIs coupled to receive a reference voltage V_REF2And an output 65 connected to the input 32 of the oscillator 18. Referring briefly to fig. 2, a schematic diagram of an oscillator control circuit 60 consistent with one embodiment of the present invention is illustrated. Fig. 2 shows a comparator 62 comprising an inverting input as input 61 of oscillator control circuit 60, an inverting input as input 63 of oscillator control circuit 60A non-inverting input, and an output. Preferably, the comparator 62 has hysteresis. The output of comparator 62 is connected to the gate of a field effect transistor ("FET") 76. The source of FET 76 is coupled to receive a source of operating voltage, such as V_SSAnd the drain of FET 76 serves as the open-drain output and output 65 of oscillator control circuit 18.

A load 80 is connected between the output node 50 and a source of operating voltage, such as V_SSIn the meantime. An output capacitor 82 is connected in parallel with the load 80. The output node 50 is connected to the impedance 24 in a feedback configuration.

Consistent with an embodiment, by adjusting the frequency of power converter 10 such that the load step period and the duration on-time of multiphase power converter 10 are in temporal association, current imbalance and thus heat dissipation is suppressed. It should be understood that the on-time of multiphase power converter 10 refers to one or more high-side switching transistors 56₁-56_nThe time in the on state. The temporal association is that the load step period and the sustained on-time of the multiphase power converter 10 are not consistent, the same or similar over an extended period of time. This is accomplished by setting oscillator 18 to produce a plurality of oscillator output signals having a predetermined frequency and phase relationship. Consistent with one embodiment, power converter 10 is a four-phase power converter, i.e., the variable "n" is equal to 4, and oscillator 18 generates four triangular waveforms separated by 90 degrees. The oscillator 18 may be operated by providing an operating voltage source such as V at an input 32 of the oscillator 18_SSAnd a resistor 84 is connected therebetween. The structure for controlling the output frequency of the oscillator 18 is not limited to one resistor. Other circuit networks can also be coupled to input 32. For example, a resistor divider network may be input 32 coupled. The oscillator 18 delivers an oscillator output signal to the input 12 of the PWM circuit 12_1B、12_2B、12_3B......12_nB. It should be noted that when power converter 10 is a two-phase power converter, oscillator 18 generates two triangular waveforms that are separated by an angle of 180 degrees; when power converter 10 is a three-phase power converter, oscillator 18 generates three triangular waveforms separated by 120 degrees; when the power converter 10 isFor an n-phase power converter, the oscillator 18 generates n triangular waveforms separated by 360/n degrees. As discussed above, the power converter may be a two-phase power converter, a three-phase power converter, a four-phase power converter, a five-phase power converter, or the like. It should further be noted that the oscillator output signal is also referred to as the ramp signal.

In addition, error amplifier 16 will compensate signal V_COMPTo the input 12 of the PWM circuit 12_1A、12_2A、12_3A......12_nA. Compensation signal V_COMPAlso referred to as error signal V_ERRORAnd appears at the output 17 of the error amplifier 16.

Referring now to fig. 3, a time vector diagram of a triangular waveform or ramp signal generated by the oscillator 18 for a four-phase power converter is illustrated. FIG. 3 shows the amplitude range at level V_L90Sum level V_H90Triangular waveform 90 between, with amplitude in the level V_L92Sum level V_H92Triangular waveform 92 between, and amplitude range at level V_L94Sum level V_H94Triangular waveform 94 between and amplitude range at level V_L96Sum level V_H96A triangular waveform 96 in between. The phase angles of the triangular waveforms 90 and 92 are separated by a 90 degree angle; the phase angles of the triangular waveforms 92 and 94 are separated by a 90 degree angle; the phase angles of the triangular waveforms 94 and 96 are separated by an angle of 90 degrees; the phase angles of the triangular waveforms 96 and 90 are separated by a 90 degree angle; at time t₀And t₈During this period, waveform 90 leads waveform 92 by 90 degrees, waveform 90 leads waveform 94 by 180 degrees, waveform 90 leads waveform 96 by 270 degrees, and compensation voltage V_COMPHaving a substantially constant voltage value V_COMP1. It should be noted that waveforms 90-96 are shown in separate diagrams for clarity, and that for each of waveforms 90-96, level V is shown_COMP1Are the same level.

When the voltage value of waveform 90 is less than V_COMPLarge time, PWM 12 output 14₁The signal 100 appears to have a logic low level, i.e., a logic 0 level. When the voltage value of waveform 90 is compared with voltage V_COMPHour, signal 100 has a logicalA high level, i.e., a logic 1 level. Similarly, when the voltage values of waveforms 92-96 are compared to voltage V_COMPLarge time, PWM 12 output 14₂-14_nThe appearing signals 102-106 have a logic low level, i.e., a logic 0 level, respectively, when the voltage values of the waveforms 92-96 are greater than the voltage V_COMPHour, PWM 12 output 14₂-14_nThe signals 102 and 106 are present with a logic high level, i.e., a logic 1 level, respectively. Thus, by comparing the compensation signals V separately_COMPAnd waveforms 90-96, signal 102 can be generated 106.

At t₈Time of day, load current I_LOADDecrease thereby increasing the voltage V_OUTAnd let the voltage V_COMPFrom level V_COMP1Reduced to a level V_COMP2. PWM output 14₁-14_nKept low, i.e. when the voltage signal V_COMPAt a level V_COMP2The corresponding pulse width modulator circuit of PWM 12 is inactive. Since the corresponding pulse width modulator is not active, waveforms 90-96 become time invariant and have levels V, respectively_S90、V_S92、V_S94And V_S96. Thus, the oscillator output signals 90-96 are disabled. Thus, a phase offset angle is introduced into the waveforms 90-96. In other words, the time at which the output signals 90-96 are suspended introduces only one delay in the waveforms 90-96. Thus, at time t₈Waveform 90 begins from level V_S90And decreases. However, at time t₉Waveform 90 at level V_S90Is suspended and held at this level until t₁₀At a time t₁₀The level continues to decrease to a level V_L90. Similarly, at t₉At time, waveform 92 is at level V_S92Is suspended and held at this level until t₁₀At a time t₁₀The level continues to increase to a level V_H92(ii) a Waveform 94 at level V_S94Is suspended and held at that level until time t₁₀At time t₁₀The level continues to increase to a level V_H94(ii) a And waveform 96 at level V_S96Is suspended and held at this level until t₁₀Time of day at whicht₁₀The level continues to decrease to a level V_L96. When the waveforms 90-96 are suspended, the duty cycle of the PWM signal 100-106 is zero, i.e., it is a logic low or logic 0 level.

It should be noted that for each waveform 90-96, level V is_COMP1Sum level V_COMP2Are respectively the same. Level V_H90、V_H92、V_H94And V_H96Sum of levels V_L90、V_L92、V_L94And V_L96The same is true.

At time t₁₀Output voltage V_OUTThe recovery is started so that the compensation voltage V appears at the output 17 of the error amplifier 16_COMPAnd (4) increasing. At time t₁₁Output level V_OUTThe compensation voltage V recovered and present at the output 17 of the error amplifier 16_COMPAt a level V_COMP1. Thus, the waveforms 90-96 resume from where they were stopped. At time t₁₀And t₁₅When the voltage value of the waveform 92-96 is greater than the voltage V_COMPAt large, appears at the output 14 of the PWM 12₁-14_nSignal 100 and 106 are at a logic low level; when the voltage value of the waveform 92-96 is compared with the voltage V_COMPWhen low, signals 100-106 are at a logic high level.

Fig. 4 is a block diagram of a multiphase power converter 150 consistent with another embodiment of the invention. FIG. 4 shows the PWM circuit 12, error amplifier 16, oscillator 18, power stage 34 described in FIG. 2₁-34_nA load 80 and a load capacitor 82. Multiphase power converter 150 further includes a dither network 152 having an output 153 coupled to input 32 of oscillator 18 through resistor 59.

Fig. 5 is a block diagram of a jitter network 152 consistent with an embodiment of the present invention. Dither network 152 may include operational amplifiers 154 and 162, each having an inverting input, a non-inverting input, and an output. A resistor 156 connected between the output of the operational amplifier 154 and its inverting input, and a resistor 158 connected between the output of the operational amplifier 154 and its non-inverting inputAnd (3) removing the solvent. In addition, a resistor 160 is connected between the non-inverting input of the operational amplifier 154 and a source of operating voltage, such as V_SSAnd capacitor 163 is connected between the inverting input of operational amplifier 154 and a source of operating voltage, such as V_SSIn the meantime. In a unity gain configuration, the non-inverting input of operational amplifier 162 is connected to the inverting input of operational amplifier 154, and the output of operational amplifier 162 is connected to its inverting input. The output of operational amplifier 162 is also connected to output 153 through resistor 164. Output 153 is coupled to receive an operating voltage source such as V through resistor 168_SS.

In operation, dither network 152 varies power level 34₁-34_nTo prevent load step rate and power stage 34₁-34_nIs matched over a considerable period of time. This prevents the build up of unbalanced currents in the channels.

Fig. 6 is a block diagram of a multiphase power converter 200 consistent with another embodiment of the invention. Fig. 6 shows the PWM circuit 12, error amplifier 16, oscillator 18, power stage 34 described in fig. 2 and 4₁-34_nA load 80 and a load capacitor 82. Multiphase power converter 200 further includes an oscillator control and dither network 202 having an output 203 coupled to input 32 of oscillator 18 through resistor 59.

In operation, oscillator control and dither network 202 varies power level 34₁-34_nAnd introduces a phase delay to prevent the load step rate and the switch 34₁-34_nIs matched over a considerable period of time. This prevents the build-up of unbalanced currents in the channels, thereby inhibiting heat dissipation and thermal failure of the multiphase power converter 200.

To this end, it should be appreciated that the present invention provides a method of balancing current in a multiphase power converter at different load transition rates to inhibit heat dissipation. Consistent with an embodiment of the present invention, heat dissipation is suppressed by adjusting the frequency or period of the multiphase power converter and the load step period to be non-uniform, the same, or similar over an extended period of time. Consistent with another embodiment, heat dissipation is suppressed by dithering the switching frequency of the power stage such that the load step rate and the switching frequency of the switch do not match over a substantial period of time. One advantage of the present invention is that it is cost effective to implement.

While certain preferred embodiments and methods are disclosed herein, it will be apparent to those skilled in the art from this disclosure that variations and modifications of these embodiments and methods may be made without departing from the spirit and scope of the invention. For example, the method may be implemented using digital techniques. It should be noted that, unless otherwise specified, the term "when. It is intended that the invention be limited only in the scope of the appended claims and the rules and principles of applicable law.

Claims (5)

1. A method of balancing currents in a multiphase power converter at different load transition rates, comprising:

providing the multiphase power converter, the multiphase power converter having a continuous on time; and

adjusting a frequency of the multiphase power converter such that a load step period and the duration on-time of the multiphase power converter are in a temporal association.

2. The method of claim 1, wherein the step of providing the multiphase power converter comprises:

providing an error amplifier, said error amplifier having an output;

providing an oscillator, said oscillator having an output;

connecting said output of said error amplifier to a first input of a pulse width modulator;

connecting the output of the oscillator to a second input of the pulse width modulator;

providing a first power stage having an input coupled to an output of said pulse width modulator;

connecting a second power stage having an input to another output of the pulse width modulator;

connecting a first inductor between an output of said first power stage and an output node;

connecting a second inductor between the output of the second power stage and the output node; and

the output node is connected to an input of the error amplifier.

3. The method of claim 1, further comprising coupling a dither circuit to the multiphase power converter.

4. The method of claim 1, wherein the step of adjusting the frequency of the multiphase power converter comprises dithering an oscillator signal, pausing the oscillator signal, or phase shifting the oscillator signal.

5. The method of claim 1, wherein the temporary association is a consistent association, a similar association, or the same association.