HK1114953B - Dc-to-dc converter and method therefor - Google Patents

Description

DC-DC converter and method thereof

Technical Field

The present invention relates generally to electronic devices and, more particularly, to methods and structures for forming semiconductor devices.

Background

In the past, the semiconductor industry utilized different methods and structures to produce dc-dc converters. Switched capacitor dc-dc converters are a particular implementation for low load current applications. One example of such a dc-dc converter is LM3352 sold by National Semiconductor of Santa Clara California (National Semiconductor of Santa Clara California). One problem with these previous switched capacitor dc-dc converters is noise. Typically, if the output voltage is higher than the desired output voltage value, the converter stops regulating the output voltage until the output voltage drops to the desired value. The alternation between regulation and non-regulation results in noise coupled with the output voltage.

Therefore, it is desirable to have a dc-dc converter that maintains regulated output voltage, improves efficiency, and reduces noise coupled with the output voltage.

Drawings

The invention discloses an operation method of a switched capacitor DC-DC converter, which comprises the following steps: configuring the converter to control a value of a charging current in response to a value of an output voltage, wherein the charging current is used to charge a plurality of capacitors; configuring the converter to form a difference signal representing a difference between a value of an input voltage and a value of the output voltage, forming a modulated reference signal having a value responsive to the charging current, and comparing the difference signal to the modulated reference signal to control both a charging configuration and a supply configuration of the plurality of capacitors.

In addition, the present invention also discloses a switched capacitor dc-dc converter, comprising: a first circuit configured to form a difference signal representing a difference between an input voltage and an output voltage; a variable current source configured to form a charging current to charge a plurality of capacitances; a current control circuit configured to form a reference signal responsive to a modulation of a value of the charging current; and a status circuit operably coupled to configure the plurality of capacitors to receive the charging current in a charging configuration and to configure the plurality of capacitors in a power supply configuration in response to a comparison of the difference signal and the modulated reference signal.

FIG. 1 schematically depicts a particular embodiment of a portion of a power control system that includes a switched capacitor DC-DC controller according to the present disclosure;

FIG. 2 schematically depicts a particular embodiment of a portion of the switched-capacitor DC-DC controller of FIG. 1, in accordance with the present invention;

FIG. 3 schematically depicts a specific embodiment of a charging arrangement according to the present invention;

FIG. 4 schematically depicts a particular embodiment of another charging arrangement according to the present invention;

FIG. 5 schematically depicts a specific embodiment of a power supply arrangement according to the present invention;

FIG. 6 schematically depicts a specific embodiment of a second power supply arrangement according to the present invention;

FIG. 7 schematically depicts a specific embodiment of a third power supply arrangement according to the present invention;

fig. 8 schematically depicts an enlarged plan view of a semiconductor device including the switched capacitor dc-dc controller of fig. 1 in accordance with the present invention.

For simplicity and clarity of illustration, elements in the figures are not necessarily drawn to scale, and the same reference numbers in different figures denote the same elements. In addition, descriptions and detailed descriptions of known steps and components are deleted in order to simplify the description. As used herein, current carrying electrode means a unit of a device that carries current through the device, such as a source or drain of an MOS transistor, or an emitter or collector of a bipolar transistor, or a cathode or anode of a diode, while a control electrode means a unit of a device that controls current through the device, such as a gate of an MOS transistor or a base of a bipolar transistor. Although the devices are explained herein as certain N-channel or P-channel devices, one skilled in the art will recognize that complementary devices according to the present invention are also possible.

Detailed Description

Fig. 1 schematically illustrates a particular embodiment of a portion of a power control system 10, the power control system 10 including a switched capacitor dc-dc controller 25. The controller 25 is configured to feasibly increase efficiency and reduce noise of the system 10. The system 10 receives an input voltage, such as a battery or other direct current voltage, between a voltage input 11 and a voltage return (return)12 and generates an output voltage between an output 13 and the return 12. System 10 also includes a load 14, a first switched capacitor 16, a second switched capacitor 17, and a feedback network 18, with feedback network 18 being configured to provide a Feedback (FB) signal that is representative of the value of the output voltage between output 13 and loop 12. In the preferred embodiment, feedback network 18 is a resistor divider, but may be other well-known feedback networks in other embodiments. Controller 25 receives a Feedback (FB) signal at feedback input 117. Controller 25 receives an input voltage between voltage input 115 and voltage return 116, voltage input 115 and voltage return 116 being connected to input 11 and return 12, respectively.

Controller 25 includes switch matrix 60, charge current sources 56 and 57, current control amplifiers 26 and 40, voltage status amplifier 94, input voltage comparator 93, regulation comparator 104, memory cells configured as D-type flip-flops 109, 110, 111, and 112, clock generator or clock 89, control logic block 113, internal reference generator or reference 90, frequency compensation filter 88, and over-voltage protection (OVP) and enable control block 87. Block 87 typically has overvoltage and start-up protection circuitry well known to those skilled in the art. Frequency compensation filter 88 is typically used to provide stability for the control loops of amplifiers 26 and 40, matrix 60, capacitors 16 and 17, and feedback network 18. Reference 90 is connected between input 115 and return 116 to receive the input voltage and form a reference voltage on the output of reference 90. Although described as a single clock, reference 90 may be made up of several parts such as a bandgap reference part and a buffer or repeater that protects the bandgap part from the circuitry receiving the reference voltage. In most embodiments, controller 25 also includes an internal regulator (not shown) that provides an internal operating voltage to the components of controller 25, such as amplifier 94, comparators 93 and 104, and logic 113. The internal regulator is typically an integral regulator that forms an internal operating voltage that is approximately equal to the value of the voltage at input 115. Amplifier 26 includes a current source 27 connected to receive the input voltage and provide current to differentially connected transistors 28, 29, 31, and 32. Similarly, amplifier 40 includes a current source 41, which current source 41 is connected to receive the input voltage and provide current to differentially connected transistors 42, 43, 44, and 45.

Fig. 2 schematically depicts a specific embodiment of a portion of a matrix 60, said matrix 60 being explained in the description of fig. 1. This description includes reference to fig. 1 and 2. Fig. 2 depicts one particular embodiment of a matrix 60 configuration, although other particular embodiments are possible. Controller 25 controls matrix 60 to provide different charging and powering configurations for capacitors 16 and 17. Matrix 60 includes transistor drivers 61, 64, 67, 69, 72, 76, 78, 80, and 83, which transistor drivers 61, 64, 67, 69, 72, 76, 78, 80, and 83 are connected to drive respective switching transistors 62, 65, 68, 70, 73, 77, 79, 81, and 84 to implement the configuration of capacitors 16 and 17. Capacitor 16 is connected between first capacitor terminal 63 and second capacitor terminal 66 of controller 25, and capacitor 17 is connected between third capacitor terminal 74 and fourth capacitor terminal 82 of controller 25.

Clock 89 generates a multi-phase clock signal (CLK) that logic 113 and flip-flops 109, 110, 111, and 112 receive to synchronize the operation of controller 25. In a preferred embodiment, CLK has a duty cycle of about 50-50, and preferably CLK is high to form the first phase and CLK is low to form the second phase. In at least a portion of the first phase, control logic 113 controls matrix 60 to couple capacitors 16 and 17 in the charging configuration. During at least a portion of the second phase, logic 113 controls matrix 60 to connect capacitors 16 and 17 in the supply configuration to provide the desired output voltage between output 13 and return 12, and to provide load current 15 to load 14. In the preferred embodiment, controller 25 has three modes of operation, and control logic 113 has three corresponding charging configurations and three supply configurations, which are encoded by the Q outputs of flip-flops 110 and 112. These three operating modes are hereinafter referred to as 1X mode, 1.5X mode, and 2X mode. As seen below, the 1.5X mode and the 2X mode are referred to as boost modes because they boost the voltage values used to form the desired output voltage. For ease of illustration, the description hereinafter refers to these three modes, however those skilled in the art will recognize that controller 25 may be configured to operate in more or less than these three modes of operation. If the input voltage is approximately no less than the desired value of the output voltage, which is represented by the reference voltage, controller 25 operates in 1 mode. If the value of the input voltage drops below the desired value of the output voltage and if the difference between the input voltage and the output voltage is not less than a first value represented by the value of the load current modulated reference voltage, then the controller 25 operates in the 1.5X mode. If the value of the input voltage is lower than the desired value of the output voltage and if the difference between the input voltage and the output voltage is greater than the first value, then the controller 25 operates in 2X mode. The reference voltage modulated by the load current will be further described hereinafter.

Amplifiers 26 and 40 are configured to provide current control signals to control the amount of current supplied by respective sources 56 and 57 to respective capacitors 16 and 17 during the charging configuration. The charging currents of sources 56 and 57 are used to charge capacitors 16 and 17, respectively, during this first CLK phase. Amplifiers 26 and 40 receive the Feedback (FB) signal from filter 88 at respective feedback inputs 36 and 50, receive the reference signal at respective inputs 34 and 48, and responsively form respective current control signals. If the FB signal is greater than the reference signal, the amount of current 15 required by load 14 is greater than the current used to charge capacitors 16 and 17, and therefore the charging current should be increased. In this case, transistor 31 conducts more current than transistor 28, and output 37 has a higher voltage than output 35. Charging current source 56 receives the current control signal at output 37 and increases the current supplied by source 56. Similarly for amplifier 40, transistor 45 conducts more current than transistor 42, and output 51 has a higher voltage than output 49. Charging current source 57 receives the current control signal at output 51 and increases the current supplied by source 57. Thus, the current control signal represents the value of the charging current for charging the capacitors 16 and 17, and also represents the load current 15. Amplifiers 26 and 40 are also configured to generate reference control signals at respective reference control outputs 35 and 49. The values of the reference control signal at outputs 35 and 49 represent load current 15.

Amplifier 94 and comparators 93 and 104 are configured to facilitate forming a state control word that is used by logic 113 to determine the mode of operation used by the charging and power supply configuration. The comparator 93 receives a signal representative of the input voltage at the non-inverting input and receives a reference voltage at the inverting input. Resistors 120 and 119 form a resistor divider to reduce the value of the input voltage to a value that can be used by comparator 93. Thus, the comparator 93 compares the input voltage with the desired value of the output voltage represented by the reference voltage. A high value at the output of comparator 93 indicates that the input voltage is greater than the desired output voltage value and therefore, a non-boost mode should be used for the charging and power configurations. A low value indicates that the input voltage is less than the desired output voltage value and therefore the boost mode should be used for the operational mode of the charging and powering arrangement. Amplifier 94 receives a signal representing the input voltage at the inverting input and a signal representing the output voltage at the non-inverting input and responsively forms an output signal representing the difference between the input voltage and the output voltage. Thus, the output signal at the output 92 of the amplifier 94 represents the output voltage value minus the input voltage value (Vout-Vin). In a preferred embodiment, to maintain the signal applied to amplifier 94 within a voltage range suitable for use by amplifier 94, resistors 95, 96 and 97 divide the value of the input voltage by 3, and resistors 99, 100 and 101 divide the value of the output voltage by 3 resistors 98 and 102 fix the gain of the signal applied to amplifier 94. In the preferred embodiment, resistors 95-102 all have the same value, and thus, output 92 is ((Vout-Vin)/3).

Comparator 104 receives the output of amplifier 94 and compares it to a signal representative of the value of the reference voltage modulated by load current 15. Resistors 105 and 106, along with modulation transistor 107, provide one specific embodiment of a circuit that facilitates using the value of load current 15 to help control the operating mode of controller 25. Modulation transistor 107 receives the reference control signal at output 35 and modulates the divided reference voltage value in response to the value of load current 15. If load current 15 is high, output 35 of amplifier 26 is low and the current conducted by transistor 107 is low, so the voltage formed at node 91 and received at the non-inverting input of comparator 104 is close to the divided reference voltage value. Thus, if the output 92 of amplifier 94 shows a large difference between Vin and a high load current, the output of comparator 104 is high. Such a situation shows power loss in the matrix 60. It can be appreciated that during the power configuration, the voltage drop across transistors 62, 65, 68, 70, 73, 77, 79, 81, and 84 affects the efficiency of controller 25 and system 10. The current supplied by sources 56 and 57 multiplied by the voltage dropped across transistors 62, 65, 68, 70, 73, 77, 79, 81 and 84 represents a loss of power. Because the output voltage is much larger than the input voltage to force the output of comparator 104 high, a larger boost mode must be used for the charging and power supply configuration. This may be represented by (V91> ((Vout-Vin)/3)) where V91 is the portion of the reference voltage received at node 91 and modulated by the value of load current 15 received at the non-inverting input of comparator 104. In a preferred embodiment, the controller 25 uses a 2X mode. If load current 15 is low, output 35 of amplifier 26 is high and the current conducted by transistor 107 is high, so the voltage received at the non-inverting input is less than the divided reference voltage value. Because a smaller difference between the output voltage and the input voltage can force the output of comparator 104 high, a smaller boost mode must be used for the charging and power configurations. This situation represents less energy loss. The output of comparator 104 in this case may be represented as (V91> ((Vout-Vin)/3)), where V91 is the portion of the reference voltage received at the non-inverting input of comparator 104 that is modulated by load current 15. In a preferred embodiment, the controller 25 uses a 1.5X mode. This situation represents less power loss. The value of load current 15 is therefore used to control the output of comparator 104 and the operating mode of controller 25 it can be seen that using the value of load current 15 to set the operating mode minimizes power consumption and improves efficiency by increasing the value of the voltage generated by matrix 60.

The output of comparator 104 is stored in flip-flop 109 and the Q output of flip-flop 109 is stored in flip-flop 110 on the rising edge of the second phase of the CLK signal similarly, on the same rising edge, the output of comparator 93 is stored in flip-flop 111 and the Q output of flip-flop 111 is stored in flip-flop 112. Note that the two flip-flops are configured in series to prevent hold time violation (hold time operation) at the inputs of flip-flops 109-112.

Also during the first phase of CLK, logic 113 receives the outputs of flip-flops 110 and 112, encodes the state word thus formed, and responsively configures capacitors 16 and 17 in a charging configuration to charge either capacitor to a voltage approximately equal to the input voltage, or both capacitors to a voltage approximately equal to one-half the input voltage. Capacitors 16 and 17 are connected to charging current sources 56 and 57 so that sources 56 and 57 can apply a number of charges controlled by amplifiers 26 and 40. Because there are two capacitors, the capacitors 16 and 17 are connected in parallel so that the input voltage is applied to each capacitor or the capacitors 16 and 17 are connected in series so that the input voltage is divided between the capacitors 16 and 17. Control logic 113 decodes the status words of flip-flops 110 and 112 to determine the mode of operation and which of two configurations to use in charging capacitors 16 and 17. The state of the output Q of flip-flops 110 and 112 is described in table 1 for the operating modes for the charging and power configurations and the corresponding states of transistors 62, 65, 68, 70, 73, 77, 79, 81, and 84.

Fig. 3 and 4 schematically depict a portion of an embodiment of two charging configurations of capacitors 16 and 17 formed by controller 25.

Fig. 5-7 schematically depict a portion of an embodiment of three supply configurations of capacitors 16 and 17 formed by controller 25. This description makes reference to fig. 1-7. If flip-flops 110 and 112 are high, the input voltage is at least equal to the desired output voltage, and thus capacitors 16 and 17 will be used to provide the output voltage during the power up configuration. To implement the power supply configuration, logic 113 enables transistors 62, 68, 79, and 84 so that capacitors 16 and 17 can be charged to the value of the input voltage during the charging configuration. In addition, sources 56 and 57 are controlled to form a charge on capacitors 16 and 17 so that capacitors 16 and 17 can provide a sufficient amount of load current 15 required by load 14. This charging configuration is described in table 1 and fig. 3. If flip-flop 110 is high and flip-flop 112 is low, then the input voltage is less than the desired value of the output voltage and the input voltage must be raised by about one-half the value of the input voltage in order to achieve the desired output voltage. Thus, logic 113 enables transistors 62, 70, and 84 so that capacitors 16 and 17 will be connected in series to receive the input voltage, each of which is charged to approximately half the input voltage. In addition, sources 56 and 57 are controlled to form a charge on capacitors 16 and 17 so that capacitors 16 and 17 can provide sufficient current for load current 15. This charging connection is illustrated in fig. 4.

If flip-flop 110 is low and flip-flop 112 is low, then the input voltage is much less than the desired value of the output voltage and, to achieve the desired output voltage, the input voltage must be raised by approximately the value of the input voltage. Thus, logic 113 again enables transistors 62, 68, 79, and 84 so that capacitors 16 and 17 will be in parallel to receive the input voltage, each of which is charged to approximately the input voltage. In addition, sources 56 and 57 are controlled to form a charge on capacitors 16 and 17 so that capacitors 16 and 17 can provide sufficient current for load current 15. This charging connection is illustrated in fig. 3.

Subsequently, CLK goes high in the second CLK phase. The rising edge of CLK stores the outputs of flip-flops 109 and 111 to respective flip-flops 110 and 112 and the outputs of comparators 104 and 93 to respective flip-flops 109 and 111. Logic 113 receives CLK and responsively switches to a power mode. Logic 113 decodes the Q outputs of flip-flops 110 and 112 to control transistors 62, 65, 68, 70, 73, 77, 79, 81, and 84 to connect capacitors 16 and 17 in the respective power supply configurations as shown in table 1. If the Q outputs of flip-flops 110 and 112 are both high, then the input voltage is not less than the desired output voltage, and the voltage stored on capacitors 16 and 17 is sufficient to provide the desired value of the output voltage. Thus, as shown in FIG. 5, logic 113 enables transistors 68, 73, 77, and 84 to connect capacitors 16 and 17 in parallel with each other and with output 13 and loop 12. If the Q output of flip-flop 110 is high and the Q output of flip-flop 112 is low, then the input voltage is less than the desired output voltage and the input voltage must be boosted to obtain the desired output voltage. Thus, as shown in FIG. 6, to form the output voltage between output 13 and loop 12, logic 113 enables transistors 65, 73, 77, and 81 to connect capacitors 16 and 17 in parallel with each other and in series with the input voltage. In this mode, capacitors 16 and 17 are charged to half the value of the input voltage, so the output voltage is almost 1.5 times (1.5X) the input voltage. If the outputs of flip-flops 110 and 112 are both low, the input voltage is much less than the desired value of the output voltage and the input voltage must be raised even more. Thus, capacitors 16 and 17 are again connected in series together and with the input voltage to form an output voltage that is almost 2 times (2X) the value of the input voltage. As shown in fig. 7, logic 113 enables transistors 65, 73, 77, and 81 to achieve this power supply configuration.

It should be appreciated that using the value of load current 15 to set the operating mode may minimize power losses. For example, assume that the desired output voltage is 5 volts (5.0V). Typically, the desired output voltage is allowed to have an error of about five percent, so the desired value is 4.75V to 5.25V. If the input voltage is greater than or equal to 5V, the controller 25 will operate in the 1X mode and the corresponding output voltage will be regulated to approximately 5V. This will result in a reduced voltage across transistors 62, 65, 68, 70, 73, 77, 79, 81 and 84, and therefore low power loss. If the input voltage is reduced to a value less than 4.75 volts (e.g., between about 4.0 and 4.75V), the controller operates in 1.5X mode and the corresponding output voltage will also be regulated to about 5V. This will also cause the voltage across transistors 62, 65, 68, 70, 73, 77, 79, 81 and 84 to be reduced, and therefore the power loss to be low. If the input voltage is reduced to a value less than about one-half of the maximum value (e.g., about one-half of 5.25 volts or about 2.7 volts), then the controller operates in 2 mode and the corresponding output voltage will also be regulated to about 5V. This will also cause the voltage across transistors 62, 65, 68, 70, 73, 77, 79, 81 and 84 to be reduced, and therefore the power loss to be low.

To facilitate the functions described herein, reference 90 is connected between input 115 and return 116, with the output of reference 90 typically being connected to input 34 of amplifier 26, input 48 of amplifier 40, the inverting input of comparator 93, and the first terminal of resistor 105. A second terminal of resistor 105 is commonly connected to the non-inverting input of comparator 104, the drain of transistor 107, and a first terminal of resistor 106. A second terminal of resistor 106 is commonly connected to the source of transistor 107, a first terminal of resistor 102, and return 116. A gate of transistor 107 is connected to output 35 of amplifier 26. A second terminal of resistor 102 is connected to a non-inverting input of amplifier 94 and a first terminal of resistor 101, resistor 101 having a second terminal connected to a first terminal of resistor 100. A second terminal of resistor 100 is connected to a first terminal of resistor 99, and resistor 99 has a second terminal connected to output 75 of controller 25. An inverting input of amplifier 94 is connected to a first terminal of resistor 97 and a first terminal of resistor 98, resistor 98 having a second terminal connected to output 92 and to a non-inverting input of comparator 104. A second terminal of the resistor 97 is connected to a first terminal of the resistor 96, and the resistor 96 has a second terminal connected to a first terminal of the resistor 95. A second terminal of resistor 95 is connected to input 115 and a first terminal of resistor 120. A second terminal of resistor 120 is commonly connected to a first terminal of resistor 119 and a non-inverting input of comparator 93. A second terminal of resistor 119 is connected to return 116. The output of comparator 93 is connected to the D input of flip-flop 111. The clock input of flip-flop 111 is commonly connected to the clock inputs of flip-flops 109, 110, and 112, the CLK output of clock 89, and the clock input of logic 113. The Q output of flip-flop 111 is connected to the D input of flip-flop 112, flip-flop 112 having a Q output connected to a first input of logic 113. The output of comparator 104 is connected to the D input of flip-flop 109, and flip-flop 109 has a Q output connected to the D input of flip-flop 110. Flip-flop 110 has a Q output connected to a second input of logic 113. Current source 27 of amplifier 26 has a first terminal connected to input 115 and a second terminal commonly connected to the sources of transistors 28 and 31. A gate of transistor 28 is connected to input 34 and a drain is commonly connected to a drain and gate of transistor 29 and to output 35. A source of transistor 29 is commonly connected to return 116 and to a source of transistor 32. A gate of transistor 32 is commonly connected to output 37, a drain of transistor 32, a drain of transistor 31, and a control input of current source 56. A gate of transistor 31 is commonly connected to input 36, the output of filter 88, and input 50 of amplifier 40. Current source 41 of amplifier 40 has a first terminal connected to input 115 and a second terminal commonly connected to the sources of transistors 42 and 45. A gate of transistor 42 is connected to input 48 and a drain is commonly connected to output 49 and to a gate and drain of transistor 43. A source of transistor 43 is commonly connected to return 116 and a source of transistor 44. A gate of transistor 44 is commonly connected to a drain of transistor 44, a drain of transistor 45, output 51, and a control input of current source 57. A gate of transistor 45 is connected to input 50. The input of filter 88 is connected to input 117. A first terminal of current source 56 is connected to input 115 and a second terminal is commonly connected to terminal 74, a drain of transistor 70, and a drain of transistor 77, and a drain of transistor 79. A first terminal of current source 57 is connected to input 115 and a second terminal is commonly connected to terminal 63, a drain of transistor 62, and a drain of transistor 73. A source of transistor 62 is commonly connected to input 115, a source of transistor 65, a source of transistor 79, and a source of transistor 81. A gate of transistor 62 is connected to an output of driver 61, driver 61 having an input connected to a first output of logic 113. A drain of transistor 65 is commonly connected to terminal 66, a source of transistor 70, and a source of transistor 68. A gate of transistor 65 is connected to an output of driver 64, which driver 64 has an input connected to a second output of logic 113. The drain of transistor 68 is connected to return 116 and the gate of transistor 68 is connected to the output of driver 67, said driver 67 having an input connected to the third output of logic 113. A gate of transistor 70 is connected to an output of driver 69 and an input of driver 69 is connected to a fourth output of logic 113. Transistor 73 has a drain connected to output 75 and a gate connected to the output of driver 72. An input of driver 72 is connected to a fifth output of logic 113. A source of transistor 77 is connected to output 75 and a gate is connected to the output of driver 76. An input of driver 76 is connected to a sixth output of logic 113. The gate of transistor 79 is connected to the output of driver 78, and driver 78 has an input connected to the seventh output of logic 113. A drain of transistor 81 is commonly connected to terminal 82 and a drain of transistor 84. The gate of transistor 81 is connected to an output of driver 80, which has an input connected to an eighth output of logic 113. The source of transistor 84 is connected to return 116 and the gate is connected to the output of driver 83. An input of the driver 83 is connected to the ninth output. Terminal 63 of controller 25 is connected to a first terminal of capacitor 16, capacitor 16 having a second terminal connected to terminal 66. A first terminal of capacitor 17 is connected to input 74 and a second terminal is connected to terminal 82. Output 75 is connected to output 13, a first terminal of network 18, and a first terminal of load 14. A second terminal of load 14 is commonly connected to loop 12, a second terminal of network 18, and loop 116. Block 87 is connected between input 115 and return 116 to receive the input voltage and has an output connected to a third input of logic 113.

Fig. 8 schematically depicts an enlarged plan view of a portion of a particular embodiment of a semiconductor device 125, the semiconductor device 125 being formed on a semiconductor die (die) 126. Controller 25 is formed on die 126. To simplify the drawing, die 126 also includes other circuitry not shown in fig. 8. Controller 25 and device 125 are formed on the die by semiconductor fabrication techniques well known to those skilled in the art.

From all of the foregoing, it should be apparent that novel devices and methods are disclosed. The method includes, among other features, forming the switched capacitor dc-dc controller to use a value of the load current in addition to values of the input voltage and the output voltage to determine an amount of charge to apply to the switched capacitor and to determine a voltage to which the capacitor is charged. Using the load current to set the charging and power configurations increases the efficiency of the system using the controller 25.

The invention has been described with specific preferred embodiments, and many alternatives and modifications will be apparent to those skilled in the semiconductor arts. More particularly, the present invention is described with respect to an amplifier circuit and a charging current source that controls a charging current. Other amplifier configurations and current source configurations may be used as long as the load current is used to help determine the charging current and to help determine the charging and supply configurations of the switched capacitor. Additionally, the word "connected" is used throughout for clarity of description, however, it is meant to have the same meaning as the word "coupled". Thus, "connected" should be interpreted as including either a direct connection or an indirect connection.

Claims (6)

1. A method of operating a switched capacitor dc-dc converter, comprising:

configuring the converter to control a value of a charging current in response to a value of an output voltage, wherein the charging current is used to charge a plurality of capacitors;

configuring the converter to form a difference signal representing a difference between a value of an input voltage and a value of the output voltage, forming a modulated reference signal having a value responsive to the charging current, and comparing the difference signal to the modulated reference signal to control both a charging configuration and a supply configuration of the plurality of capacitors.

2. The method of claim 1, wherein the power configuration comprises one of a boost configuration and a non-boost configuration.

3. The method of claim 1, further comprising comparing the difference signal and the modulated reference signal to form a control signal, wherein the charging and powering configuration is controlled in response to the control signal.

4. The method of claim 1, wherein the configuring the converter to control the charging configuration comprises configuring the converter to selectively set an operating state of the converter in a storage element.

5. A switched capacitor dc-dc converter comprising:

a first circuit configured to form a difference signal representing a difference between an input voltage and an output voltage;

a variable current source configured to form a charging current to charge a plurality of capacitances;

a current control circuit configured to form a reference signal responsive to a modulation of a value of the charging current; and a status circuit operably coupled to configure the plurality of capacitors to receive the charging current in a charging configuration and to couple the plurality of capacitors in a power supply configuration in response to a comparison of the difference signal and the modulated reference signal.

6. The converter of claim 5, wherein the current control circuit comprises a reference circuit configured to form a reference signal and a modulation circuit coupled to receive the reference signal and to form a modulated reference signal by adjusting a value of the reference signal in response to the value of the charging current.