HK1114237A - Integrated circuit transformer devices for on-chip millimeter-wave applications - Google Patents

Description

Integrated circuit transformer device for on-chip millimeter wave applications

Technical Field

The present invention relates generally to integrated circuit transformer devices having a compact and optimized architecture for use in MMW (millimeter wave) applications. More particularly, the present invention relates to integrated circuit transformer devices having a generic and scalable architecture that may be used as templates or building blocks for constructing various types of on-chip devices for millimeter wave applications.

Background

Generally, a transformer is a device that includes a core (e.g., magnetic), a primary coil, and one or more secondary coils. The primary coil receives electrical energy from a power source and couples that energy to the secondary coil by virtue of a varying magnetic field, where the energy appears as an electromagnetic field throughout the coil. If a load is connected to the secondary winding, the energy is transferred to the load. The output power of the transformer cannot exceed the power input to the transformer, so that the output current decreases in direct proportion to the voltage increase (and vice versa).

RF (radio frequency) transformers are commonly used in electronic circuits for applications such as resistance matching (for maximum power transfer), AC voltage step-up/step-down, DC isolation between two circuits, common mode rejection, filters, etc. Furthermore, the transformer may be used to construct a balanced-unbalanced transformer (BALUN) with, for example, a balanced input, where two input ports are isolated from ground to an unbalanced output and one output port is grounded.

For on-chip applications, transformers are typically constructed with coupling wires. A simple transformer structure consists of two conductors with the same winding on each side, which is called a 1: 1 transformer or simply a coupling conductor. As an example, fig. 1 is a perspective view of a semiconductor device with a conventional integrated transformer device. In fig. 1, a semiconductor device (10) includes a substrate (11) on a surface of which an integrated coplanar transformer (12) is formed. The transformer (12) comprises a first conductor (13) (primary) and a second conductor (14) (secondary) arranged in parallel on the same layer. These conductors are patterned starting with a metal layer formed on the surface of the substrate and then encapsulated in a dielectric or insulating layer.

Transformer devices such as that shown in fig. 1 typically have poor electrical performance (e.g., low coupling, k ═ 06) and exhibit high losses, especially when used in high frequency applications. In fact, for lossy substrates such as silicon, capacitive coupling between the metal lines (13), (14) and the substrate (11) can lead to increased power consumption. If the width of the metal line is reduced to limit this capacitive coupling, the resistance of the metal line increases (e.g., through skin effect), resulting in increased power consumption. Furthermore, conventional transformer designs such as fig. 1 do not have well-defined return paths for closed environment EM conditions, which results in electrical performance that is more sensitive to surrounding metal components. Thus, integrated circuit coplanar transformer devices such as that shown in fig. 1 are typically used at low frequencies where lower coupling factors, losses due to skin effects, and inaccuracies caused by models of hardware differences can be tolerated.

Disclosure of Invention

In general, exemplary embodiments of the invention include integrated circuit transformer devices having a compact and optimized architecture for use in MMW (millimeter wave) applications. More specifically, exemplary embodiments of the present invention include integrated circuit transformer devices having a generic and scalable architecture that may be used as templates or building blocks for constructing various types of on-chip devices for millimeter wave applications, including, for example, power combiner circuits, balanced-unbalanced transformers (baluns), distributed active transformers, and filters.

In one exemplary embodiment, an integrated circuit transformer includes a substrate, a ground shield formed on the substrate, a primary conductor including an elongated conductive strip, and a secondary conductor including an elongated conductive strip. The primary and secondary conductors are aligned to form a coupled conductor structure disposed adjacent the ground shield. In addition, the ground shield includes a pattern of closed-end parallel elongated slots disposed orthogonal to the primary and secondary conductors, and edge regions that provide current return paths that are collinear with the primary and secondary conductors.

In one exemplary embodiment of the invention, the ground shield, the primary conductor and the secondary conductor are disposed on different layers of the integrated circuit and are aligned with one another to form a stacked structure. A first insulating layer is disposed between the ground shield and the secondary conductor and a second insulating layer is disposed between the secondary conductor and the primary conductor. In one embodiment, the ground shield, primary and secondary conductors are formed from different BEOL (back end of line) metallization layers.

An exemplary 1: 1 integrated circuit transformer structure with a ground shield design having orthogonal closed-end slots and edge regions providing current return paths collinear with the primary and secondary conductors can be accurately modeled with 3D/2D simplified (compact) modeling to create a length scalable 1: 1 transformer template model. More specifically, the exemplary ground shield structure provides closed environment EM conditions that mitigate parasitics and boundary conditions, thereby allowing a simplified model of a length scalable 1: 1 integrated circuit transformer template to be defined that is independent of the proximity of other structures in the layout.

Thus, the exemplary 1: 1 integrated circuit transformer template device can be accurately modeled with a lumped equivalent element model (e.g., an RLC network) whose conductor length, Lc (and possibly other geometric parameters) are scalable. The lumped equivalent element model of an exemplary 1: 1 integrated circuit transformer template device may be used in circuit simulation applications to obtain an accurate simulation of a circuit having such a 1: 1 integrated circuit transformer template regardless of circuit layout.

These and other exemplary embodiments, features and advantages of the present invention will be described or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

Drawings

Fig. 1 illustrates a conventional integrated circuit transformer device.

Fig. 2A and 2B schematically illustrate an integrated circuit transformer device according to an exemplary embodiment of the invention.

Fig. 2C schematically illustrates an integrated circuit transformer device according to another exemplary embodiment of the invention.

Fig. 2D schematically illustrates a ground shield pattern according to an exemplary embodiment of the present invention.

Fig. 3 is a schematic circuit diagram of an integrated transformer matched power amplifier circuit according to an exemplary embodiment of the invention.

Fig. 4 is a schematic circuit diagram of an integrated power combiner circuit according to an exemplary embodiment of the present invention.

Fig. 5 is an exemplary schematic circuit layout of the integrated power combiner circuit of fig. 4, according to an exemplary embodiment of the invention.

Fig. 6 is an exemplary component icon (icon) representing a lumped equivalent model of a length scalable integrated circuit transformer template device according to an exemplary embodiment of the invention.

FIG. 7 is a flowchart of a method of performing circuit simulations using an integrated circuit transformer model that is scalable in length or other user-specific parameters according to an exemplary embodiment of the invention.

Detailed Description

Fig. 2A and 2B schematically illustrate an integrated circuit transformer device according to an exemplary embodiment of the invention. More specifically, fig. 2A is a schematic side view of a semiconductor device (20) including a substrate (21) with an integrated transformer device (22) formed on the substrate (21), and fig. 2B is a schematic top plan view of the exemplary device (20) of fig. 2A. As shown in fig. 2A and 2B, the transformer (22) includes a ground element (23) (or ground shield), a secondary conductor (24), and a primary conductor (25) formed on separate layers of an integrated circuit on a substrate (21) to form a stacked transformer structure (22). The transformer (22) is encapsulated in an insulating/dielectric material (26) (e.g., silicon dioxide or other insulating or dielectric material), with a thin layer of insulating/dielectric material disposed between the ground element (23) and the secondary conductor (24) and between the secondary conductor (24) and the primary conductor (25). The exemplary embodiment shown in fig. 2A and 2B shows the primary conductor (24) and the secondary conductor (25) as stacked coupling wires having equal length Lc and width Wc. Furthermore, the primary conductor (25) has a value t₁Thickness indicated, secondary conductor having a value of t₂The indicated thickness. As shown below, depending on the application, the primary conductor (25) may be formed thicker than the secondary conductor (24) to accommodate higher current densities (DC currents).

Fig. 2B further illustrates the pattern of the ground shield element (23) according to an exemplary embodiment of the invention. An exemplary ground shield member (23) comprises a planar metal sheet patterned to form a series of parallel closed-ended slots (23a) of length Ls. The formation of the closed-end slots (23a) results in the ground shield element (23) having a series of parallel conductive strips (23b) of the ground shield element (23) which are commonly connected at their end portions along the edge regions (23c) (or "side strip" elements) of the ground shield (23). The closed-end slots (23a) and conductive strips (23b) are arranged in relation to the primary conductors (24) and the secondary conductors (25) such that the slots (23a) and strips (23b) are arranged orthogonal to the direction of wave propagation along the length (longitudinal direction) of the stacked secondary conductors (24) and primary conductors (25) (as indicated by the directional arrows for the AC current I). An exemplary pattern of alternating grooves (23a) and strips (23b) extends along the entire length Lc of the stacked coupling wires (24) and (25). Furthermore, the side regions (23c) (or side bar elements) are designed to provide current return paths that extend co-linearly with the direction of longitudinal wave propagation along the length of the stacked conductors (24) and (25).

It will be appreciated that an integrated transformer device having stacked primary, secondary and slotted ground shield frames as shown in fig. 2A and 2B provides an efficient compact 1: 1 integrated circuit transformer structure and provides a high coupling factor (e.g., k 0.8 or better) for millimeter wave applications. In effect, the stacked coupled lead frame (compared to the conventional coplanar structure of fig. 1) confines the EM field between the primary and secondary conductors, thereby creating increased coupling between the primary and secondary conductors, and resulting in lower losses due to smaller current crowding effects (smaller skin effect by width), and reduced frequency dependence allowing higher bandwidth modeling.

Furthermore, a slotted ground shield frame having a series of closely spaced conductive strips (23b) and closed-end slots (23a) disposed orthogonal to wave propagation along the primary and secondary conductors provides effective EM shielding from a substrate (e.g., a silicon substrate), which effectively reduces substrate-induced losses and increases the coupling factor k between the primary and secondary conductors. More specifically, the conductive strip (23b) provides a means for preventing EM energy from flowing into the substrate (21). Furthermore, the use of closed-end slots (23a) arranged orthogonally to the wave propagation along the stacked conductors (24) and (25) provides a means for reducing the generation of image currents in the wave propagation direction that flow into the ground shield, thereby reducing the coupling between the conductors (24), (25) and the ground shield (23) and effectively increasing the coupling factor between the primary conductor (24) and the secondary conductor (25).

Furthermore, the edge region (23c) (or sidebar element) of the ground shield (23) provides a well-defined current return path (for closed ambient EM conditions) that is collinear with wave propagation. Furthermore, the edge region (23c) provides a means for shielding/isolating the transformer structure from other components/elements surrounding or near the transformer, such as vias (via), amplifiers, wiring, grounding, etc.

Indeed, as will be explained below, the slotted ground shield with the sidebar elements enables highly miniaturized modeling of integrated circuit transformer structures to form lumped equivalent models (e.g., RLC elements) that are scalable in length Lc. Lumped equivalent models for integrated transformer devices enable circuit/network analysis of an integrated circuit with one or more transformer templates without requiring a full 3D simulation of the integrated circuit. In this regard, it should also be understood that the integrated circuit 1: 1 transformer device as shown in fig. 2A and 2B can be readily used as a length-parameterized template (or building block) to construct various integrated circuit devices and modular structures, including, but not limited to, power amplifiers, n: 1 impedance transformer and power combiner. Exemplary embodiments of integrated circuit devices implementing a 1: 1 integrated transformer template are described below with reference to FIGS. 3-5.

Furthermore, the IC transformer device as shown in fig. 2A and 2B may be used as a resonance tuning circuit to provide an efficient resonance structure, such as using a simple capacitor across the secondary conductor, or by referencing the conductor length Lc to 1/2 equal to the wavelength of the fundamental operating frequency. The IC transformer structure provides a strong peak of the current coupling and can increase the voltage coupling compared to the coupling obtained due to the tank resonant circuit. Furthermore, the IC transformer structure provides a strong peak in power coupling and provides a real (rather than reactive) input impedance. Furthermore, the integrated circuit transformer may be designed with a symmetrical frame to provide equal input and output impedance (e.g., parallel, equally spaced closed-end slots designed into the ground shield).

It should be understood that various semiconductor fabrication methods may be used to construct the IC transformer device shown in fig. 2A and 2B. For high frequency applications, the exemplary IC transformer device may be fabricated based on compound semiconductor technologies such as GaAs (gallium arsenide) or SiGe (silicon germanium) or other technologies suitable for highly integrated circuits operating in the millimeter wave frequency range.

In one exemplary embodiment, the IC transformer device may be fabricated by forming the primary conductor, the secondary conductor, and the ground shield from different metallization layers deposited and processed using BEOL (back end of line) processes. More specifically, in one exemplary embodiment, after forming an active circuit region on a substrate, an insulating layer (e.g., silicon dioxide (SiO) to isolate the layer from the first metallization layer) may then be formed over the active region₂) The ground shield (23) may be formed by patterning a portion of the first metallization layer. After the first metallization, a second insulating layer and a second metal layer are sequentially formed. The portion of the second metal layer aligned with the ground shield (23) is patterned to form a secondary conductor (24). Thereafter, a third insulating layer and a third metallization layer are sequentially deposited and portions of the metal layer aligned with the secondary conductor (24) are patterned to form a primary conductor (25). In another exemplary embodiment of the present invention, the above process may be reversed to form a stacked IC transformer with a ground shield disposed over the secondary and primary conductors. In such embodiments, for certain applications described below, it is preferred that the metal layer forming the primary conductor be of sufficient thickness to handle the increased current density.

In one particular exemplary embodiment, the stacked IC transformer may be formed using current international business machines corporation SiGe8HP semiconductor technology, wherein the BEOL process includes five metallization layers formed on the active chip surface. With this technique, the upper three metal layers can be used as primary, secondary and ground shield elements, and the lower two layers can be used to form connections between active components and between components from the active components to the transformer element.

It should be understood that the dimensions of the IC transformer device as shown in fig. 2A and 2B will vary depending on the application and semiconductor processing technology implemented. For example, the slot length Ls should be long enough to pass through the sides of the conductors (24) and (25) to prevent longitudinal mirror currents from forming on the ground shield due to coupling of the EM field between the secondary element and the ground element. Furthermore, the width and spacing of the slots (23a) and strips (23b) should be sufficiently smaller than the operating wavelength to avoid longitudinal mirror currents on the conductive strips (23 b). In addition, a dense pattern of conductive strips (23b) is preferably provided to minimize capacitive coupling between the substrate and the secondary conductor. In practice, the slot/strip width is limited by the design rules of a given manufacturing process.

Furthermore, the spacing/isolation between the primary and secondary conductors should be sufficiently smaller than the operating wavelength. In addition, the conductor width WC will be selected based on factors such as the operating frequency and the resistivity of the materials used to form the primary and secondary conductors to thereby provide sufficient surface area to minimize resistive losses due to skin effect phenomena. In one exemplary embodiment of the present invention, the secondary conductor may be formed wider than the primary conductor to increase fringing field coupling with the primary conductor. The thicknesses t1 and t2 of the conductors will be determined by the manufacturing method implemented and/or may be selected to accommodate the current density for a given application.

In other exemplary embodiments of the invention, the coupled primary conductor (25) and secondary conductor (24) may be horizontally stacked (disposed close to each other) onto the ground shield (23), as shown in fig. 2C. In essence, the resulting structure can be viewed as coplanar conductors (13) and (14) as shown in FIG. 1, except that conductors (24) and (25) in FIG. 2C are thicker rather than wider. In this way, coupling between conductors (24) and (25) may be increased while conductors (24) and (25) are formed on the same layer of the integrated circuit.

In other exemplary embodiments of the present invention, the edge region of the ground shield may have a longitudinal slot formed therein, wherein the slot is formed to be collinear with wave propagation. For example, fig. 2D is an exemplary ground shield 23' similar to ground shield (23) of fig. 2B, except that the side edge regions have longitudinal slots (23D) forming conductive strips (23e) connected to the ground shield structure. The trough-shaped edge region enhances isolation from nearby objects and prevents coupling of eddy currents flowing on the substrate.

Fig. 3 schematically illustrates an integrated circuit power amplifier constructed with integrated circuit transformer devices according to an exemplary embodiment of the invention. More specifically, fig. 3 shows an exemplary integrated circuit power amplifier (30) for MMW applications that implements an integrated circuit transformer (33) for efficient coupling of output power. In general, a power amplifier (30) includes an input matching network (31) connected to a differential input of a cascode differential amplifier (32), an integrated transformer (33) connected to a differential output node of the differential amplifier (32), and an output matching network (34). An input matching circuit (31) inputs a differential V using an inductive microstrip (31a) in series and a capacitor (31b) in parallel_inMatching the desired characteristic impedance (e.g., 50 ohms). An output matching circuit (34) outputs a differential output V using an inductive microstrip (34a) in series and a capacitor (34b) in parallel_outMatching the desired characteristic impedance (50 ohms).

A cascode differential amplifier (32) comprises: a first cascode stage comprising series-connected transistors T1 and T3; and a second cascode stage comprising transistors T2 and T4 connected in series. Transistors T3 and T4 (common emitter input stage) drive transistors T1 and T2 (common base output stage), respectively. The bias voltage Vbias is applied across the base terminals of transistors T3 and T4, and a constant DC voltage Vgbs is applied across the base terminals of transistors T1 and T2. These bias voltages are selected to prevent the base-to-collector voltage of each transistor T1-T4 from exceeding the breakdown voltage of that transistor in a cascode array, and to divide the peak voltage applied between the collectors of T1 and T2 and the emitters of the respective transistors T3 and T4 to prevent breakdown.

In the exemplary embodiment of fig. 3, the integrated circuit transformer (33) is schematically depicted as including a primary conductor (33a) having input terminals (nodes N1 and N2) and a secondary conductor (33b) having output terminals (nodes N1 'and N2'). Collector terminals of the transistors T1 and T2 are connected to the nodes N1 and N2, respectively. In one exemplary embodiment, the integrated circuit transformer (33) comprises a 1: 1IC transformer having a frame as described in fig. 2A and 2B, wherein the primary conductor (33a) and the secondary conductor (33B) are stacked on a slotted ground shield. In this embodiment, the collectors (output nodes N1 and N2) of transistors T1 and T2 are connected to the length ends of the primary conductor (33a) of the integrated transformer (33), and the bias voltage VCC is connected in the central region between the length ends of the primary conductor (33 a).

With the exemplary framework of fig. 3, a 1: 1IC transformer (33) couples the differential output voltages (VN1-VN2) of the differential amplifier (32) to the secondary conductors (33b) at nodes N1 'and N2'. A1: 1IC transformer (33) is used as a resonator to provide efficient coupling of the output power of the amplifier. In another exemplary embodiment, a 1: 1IC transformer may be coupled to the input of the differential amplifier circuit.

Furthermore, in the exemplary embodiment of fig. 3, input terminal Vin is differentially driven with equal amplitude, opposite phase RF signals, which establishes a false (virtual) AC ground on primary conductor (33a) where the VCC supply connection is made, and at the ground G connection between the sources of transistors T3 and T4. The pseudo AC ground is a point of low loss and low resistance. In this way, the false AC ground on the VCC connection point eliminates the need for a separate choke inductor and/or a large on-chip bypass capacitor at the VCC supply connection.

It should be understood that multiple 1: 1IC transformer devices may be used as templates or building blocks for constructing other IC components/devices for MMW applications. For example, fig. 4 is a schematic circuit diagram illustrating an integrated power combiner circuit according to an exemplary embodiment of the present invention. More specifically, fig. 4 schematically illustrates a power combiner circuit (40) implemented with four transformer template devices (41, 42, 43, 44) arranged in a square or circular geometry and a plurality of differential push-pull amplifiers (45, 46, 47, 48). Each transformer template device (41, 42, 43, 44) is schematically depicted as having a primary conductor (41a, 42A, 43a, 44a), a secondary conductor (41B, 42B, 43B, 44B), and a slotted ground shield (41c, 42c, 43c, 44c), respectively, similar to the exemplary IC transformer frame of fig. 2A and 2B.

In an exemplary embodiment, the secondary conductors are connected in series, with the secondary conductor (41b) of the transformer (41) split in its middle to provide a differential + -output terminal Vout. In addition, each primary conductor (41a, 42a, 43a, 44a) is connected between the differential outputs of adjacent power amplifiers and has a center point connected to the VCC terminal to provide a DC bias to the amplifiers. The power combiner circuit (40) may be constructed with four push-pull amplifiers, each having a 1: 1 transformer (as shown in figure 3) with the secondary conductors of the transformers connected in series. With this exemplary embodiment, the input voltage Vin is divided into four equal amplitude, equal phase signals that are each simultaneously applied to one of the + differential inputs of the amplifiers (45, 46, 47, 48), while the inverted input voltage Vin is divided into four equal amplitude, equal phase signals that are each simultaneously applied to one of the-differential inputs of the amplifiers (45, 46, 47, 48), thereby producing an alternating current on each primary conductor. The AC current on the primary conductor is coupled to the serially connected secondary conductor to produce the combined output voltage Vout. With this exemplary embodiment, the distributed architecture provides a power combiner circuit and a 4: 1 impedance transformer, since the primary conductors are independent. In other words, the exemplary power combiner (40) provides combining and impedance transformation for power amplifier applications.

Fig. 5 schematically illustrates an exemplary circuit layout (50) of the power combiner circuit of fig. 4, according to an exemplary embodiment of the invention. More specifically, fig. 5 schematically shows an exemplary layout pattern (50) including a ground shield (51), a bias VCC network (52), a continuous secondary conductor (53), a connector (54) and shows an exemplary embodiment of a push-pull amplifier (45, 46, 47, 48). An exemplary ground shield (51) pattern integrally incorporates each individual ground shield (42c, 43c, 44e, 45c) of the transformer template devices (42, 43, 44, 45) shown in fig. 4. The ground shield (51) is patterned as a single pattern forming a closed-ended slot extending orthogonally to each transformer conductor.

The distributed transformer frame includes a continuous secondary conductor (53) having differential output terminals Vout, and separate primary conductors (41a, 42a, 43a, 44a) stacked on different portions along the length of the secondary conductor (53) and aligned therewith. The DC supply voltage network (52) comprises a plurality of wires connected to a central portion of each primary conductor (41a, 42a, 43a, 44 a).

Fig. 5 also shows each of the push-pull amplifiers (45), (46), (47), (48) implemented with pairs of common emitter gain stages (45a/45b), (46a/46b), (47a/47b), (48a/48b) having BJTs (bipolar junction transistors). It should be understood that the differential push-pull amplifier framework shown in fig. 5 is merely exemplary, and that other differential push-pull amplifier designs, such as that shown in fig. 3, may be implemented. Furthermore, the amplifier may be implemented with CMOS devices. Each primary conductor (41a, 42a, 43a, 44a) has an angled length end portion which is connected to the differential output of the respective push-pull amplifier by a connector (54).

In an exemplary embodiment, the differential amplifiers (45, 46, 47, 48) are connected to the primary conductors (42a, 43a, 44a, 45a) such that each primary conductor (42a, 43a, 44a, 45a) has a corresponding push/pull amplifier pair, namely amplifier pair (48a/45b) for primary conductor (41a), amplifier pair (45a/46b) for primary conductor (42a), amplifier pair (46a/47b) for primary conductor (43a), amplifier pair (47a/48b) for primary conductor (44 a). The primary conductor provides a low resistance path for the DC current to flow from the DC power supply to the drain of the transistor. The source terminals of adjacent transistors of adjacent amplifiers are connected together and share a common ground. As shown by the "+" and "-" signs, each pair of adjacent transistors is driven in opposite phase.

A power distribution network (not shown) is used to provide synchronized differential power to the gates of the transistors. For example, in the exemplary embodiment of fig. 4 and 5, two sets of three Wilkinson power dividers may be implemented to divide both the input signal Vin and the inverted input signal/Vin into four equal-phase, equal-amplitude input signals that are simultaneously applied to different inputs of amplifiers 45, 46, 47, 48. The exemplary power combiner circuit of fig. 5 achieves power combining by operating a push-pull amplifier to conduct the same synchronous ac current at a fundamental frequency on each primary conductor, thereby inducing a corresponding ac current in the continuous secondary conductor. The secondary conductor (53) uses the induced AC power to generate a voltage on terminal Vout equal to the sum of the differential voltages of the four push-pull amplifiers.

In another exemplary embodiment of the present invention, the circuits of fig. 4 and 5 may be extended to construct a power splitter. In this case, the continuous secondary conductor in fig. 5 is the primary conductor that receives the input signal (at the Vout terminal), and each separate primary conductor in fig. 5 is the secondary conductor that respectively couples about the primary EM energy 1/4. In this way, a symmetrical 1: 4 power divider can be achieved.

It should be appreciated that an integrated transformer device according to an exemplary embodiment of the invention may be accurately modeled with lumped equivalent elements to define a scalable model of conductor lengths Lc and other possible geometrical parameters of the integrated transformer. More specifically, an exemplary 1: 1 transformer structure having a ground shield design with orthogonal slots and collinear side bars, for example as described above with reference to fig. 2A and 2B, enables a simplified model of an integrated transformer structure by providing closed environment EM conditions that mitigate parasitic effects and boundary conditions. This provides a simplified model of defining a length scalable 1: 1 transformer template independent of the adjacency of other structures in the layout.

Various applications are currently available on the market for constructing and simulating various types of 2D/3D integrated circuits, components, and other structures for millimeter wave and RF applications. This application allows designers to construct 3D/2D integrated circuit layouts with interconnects and to apply full-wave 3D circuit EM simulators that determine the electrical characteristics and response of the integrated circuit design, taking into account the effects of other transformers, wires, interconnects, or other radiating structures, which provide undesirable impedances (parasitic capacitances and inductances) that in practice affect circuit performance. Some applications include methods for extracting frequency-dependent network representations of two ports of various circuit components using 3D processing results and generating lumped equivalent circuits for such components. However, when the 3D circuit layout is modified, the lumped equivalent circuit no longer accurately defines the features/characteristics of the modified 3D circuit, and a full 3D EM simulation must again be performed to extract the relevant parameters in order to recreate the lumped equivalent circuit for the circuit simulation using, for example, simple node analysis.

It should be appreciated that the exemplary 1: 1 transformer structure with the slotted ground shield design and the sidebars allows the transformer structure to be analyzed in isolation using circuit simulation without the need to perform a full-wave 3D analysis to account for the effects of metal objects (on-chip transmission lines, inductors, pads, interconnects, etc.) near the integrated transformer template. In this way, a simplified model of the 1: 1 transformer structure can be accurately defined with a lumped equivalent model that can be universally applied to circuit simulations. For example, the schematic power combiner circuit (40) may be accurately modeled with a lumped equivalent model of a 1: 1 transformer template structure for each schematically illustrated transformer (41, 42, 43, 44) according to embodiments of the invention, regardless of the 3D configuration and circuit layout (e.g., fig. 5). In this regard, the transformer models are decoupled from each other and other circuit components, allowing the circuit to be simulated using simple nodal analysis with lumped equivalent models. This is in contrast to conventional integrated circuit coupled line transformers (as shown in fig. 1), which require 3D EM simulation for different layouts and circuit configurations in MMW applications.

In one exemplary embodiment described below, an integrated circuit 1: 1 transformer device having a framework as shown in fig. 2A and 2B may be modeled using a simple RLC filter network (including coupled inductors and dependent sources) for circuit simulation applications. The simplified model of the integrated circuit transformer device can accurately describe the electrical characteristics/features of the integrated circuit transformer in all operating modes and electrical characteristics/features of all secondary/primary complex loads, as well as these characteristics up to the third harmonic of the fundamental millimeter wave frequency. The lumped equivalent model can be used to conveniently determine network values by simple 2D EM simulations.

In one exemplary embodiment of the invention, a simulation model for an exemplary stacked 1: 1 transformer template with a length scalable slotted ground shield may be built as follows. First, a 1: 1 integrated circuit transformer template structure can be designed with a 3D circuit layout tool. Then, a 3D EM solver method is employed to extract the parameters per unit length of the transformer structure. More specifically, a 2 x 2 capacitance matrix can be calculated for two signal lines (primary and secondary conductors) on a ground plane (comprising two collinear side bars and orthogonal conductive strips) with a 3D static capacitance resolver. The side bar structure enables the extraction of the model under the assumption of a closed EM environment using a 3D full wave simulation of the transformer template. It should be understood that when the pattern of orthogonal strips is sufficiently dense (which is preferable to shield silicon substrate losses), a 2D solver can be used as a good approximation. Furthermore, a static resolver is sufficient to determine the capacitance parameter when the separation between the metals is negligible compared to the wavelength.

Thereafter, a 2D simulation of a reduced transformer structure containing two signal lines and a reduced ground plane with only two collinear side bars (return path lines) and no orthogonal bars is used to obtain a frequency-dependent 2 x 2 inductance matrix and a frequency-dependent 2 x 2 resistance matrix. The analysis using this reduced structure is reasonable because the Z element of the model only describes the distribution of the longitudinal current. The minimum bandwidth required for these EM simulations ranges from the fundamental MMW frequency to the third harmonic. A complete solution to the skin effect and proximity effect is performed due to the millimeter wave frequency.

Then, using the EM resolver data, an RLC network was constructed for the two coupled lines on the ground plane. The RLC network includes a suitable filter network (ladder circuit) that describes the frequency dependence of the resistive and inductive matrices in a given bandwidth. In addition to the mutual inductive coupling element between the RLC passive element and the inductor, dependent sources are included to correctly describe the frequency dependence in odd and even modes. These dependent sources are connected in a way that ensures model passivity (absolute stability). A distributed model is implemented with several such RLC segments (e.g., using at least 10 segments for each wavelength).

Thus, the exemplary model building method described above may be used to define a lumped equivalent model for a 1: 1 integrated transformer template device, which is scalable in length (or other geometric parameters) and may be universally applicable to circuit design and simulation. In practice, for example, various simplified models for transformer template devices may be defined for structures having different geometric parameters, such as slot pitch, slot width, conductor width and thickness, and for structures formed using different semiconductor fabrication techniques.

With such an approach, one or more transformer models may be included in a circuit simulation application as part of a design toolkit or library of models to enable the design and simulation of integrated circuits for MMW applications that implement exemplary transformer template devices in accordance with the present invention. The model may be established to allow parameters to be specified by the user for simulation (e.g., conductor length, etc.). FIG. 6 illustrates an exemplary ICON (ICON) representation of a 1: 1 transformer template model that may be used in simulation applications. The diagram of fig. 6 is a schematic diagram of a transformer (60) with a primary conductor (61) and a secondary conductor (62) on a ground plane (63), a 1: 1 transformer template model defined by the user for values of conductor length L in allowed um units.

FIG. 7 is a flow diagram of a method of performing circuit simulation using a lumped equivalent model of an integrated circuit transformer that is scalable by length or other user specified parameters in accordance with an exemplary embodiment of the invention. The method of FIG. 7 may be implemented in any suitable 3D/2D design and simulation application having a user interface, where the 3D/2D design and simulation application enables a user to create, for example, a schematic circuit. Referring to fig. 7, a user may build a schematic circuit using a device/component icon, such as the transformer template icon of fig. 6 (step 70). In such a case, the application may have a library of models for each component. As described above, according to an exemplary embodiment of the present invention, a user may select one or more types of transformer template models (which are provided as part of the library), where one or more geometric parameters, such as length, may be a variable defined by the user (step 71). Other geometric parameters such as groove width, etc. may also be variables entered by the user, depending on the model design.

After the schematic circuit is created, a user may perform circuit simulation by specifying values for one or more parameters (e.g., voltage, frequency range, device values, etc.) of the lumped equivalent model that enable input of user specified parameters, and then executing appropriate commands to obtain a desired electrical response/characteristic of the circuit based on the user specified parameters (step 72). The circuit simulation is performed by performing a nodal analysis on a given circuit using lumped models of the constituent circuit components/devices with user-specified parameters as parameters (step 73). Thereafter, the results of the circuit simulation may be presented to the user for review (step 74).

It should be understood that the above exemplary modeling and circuit simulation methods are examples only. In one embodiment, the circuit design and simulation tool may include a library of one or more predefined transformer template device models with scalable parameters, which may be used for circuit analysis. In other exemplary embodiments, the 2D/3D circuit design and simulation tool may be extended to include the transformer template model building methods described above, which enable a user to create a customized, user-defined simplified transformer model by generating a customized transformer template structure, and then apply the relevant model building methods to extract the 2D/3D EM parameters needed to build the corresponding lumped equivalent model. In other embodiments, the 2D/3D tool may be implemented with a library of predefined transformer template models and tools required to generate custom transformer template models.

Although the illustrative embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention. All such changes and modifications are intended to be included within the scope of the present invention as defined in the appended claims.

Claims (26)

1. An integrated circuit transformer, comprising:

a substrate;

a ground shield formed on the substrate;

a primary conductor comprising an elongated conductive strip; and

a secondary conductor comprising an elongated conductive strip;

wherein the primary conductor and the secondary conductor are aligned to form a coupled wire structure disposed adjacent to the ground shield; and is

Wherein the ground shield includes a pattern of closed-end parallel elongated slots disposed orthogonal to the primary and secondary conductors, and wherein the ground shield includes an edge region that provides a current return path that is collinear with the primary and secondary conductors.

2. The integrated circuit transformer of claim 1, wherein the ground shield, primary conductor, and secondary conductor are disposed on different layers of an integrated circuit and aligned with one another to form a stacked structure.

3. The integrated circuit transformer of claim 2, further comprising:

a first insulating layer disposed between the ground shield and the secondary conductor; and

a second insulating layer disposed between the secondary conductor and the primary conductor.

4. The integrated circuit transformer of claim 1, wherein the ground shield, primary and secondary conductors are formed from different BEOL (back end of line) metallization layers.

5. The integrated circuit transformer of claim 1, wherein the primary and secondary conductors have the same length and width.

6. The integrated circuit transformer of claim 1, wherein a thickness of the primary conductor is greater than a thickness of the secondary conductor.

7. A semiconductor IC (integrated circuit) chip comprising:

an integrated circuit comprising a transformer, wherein the transformer comprises:

a ground shield;

a primary conductor comprising at least one elongated conductive strip; and

a secondary conductor comprising at least one elongated conductive strip;

wherein the primary conductor and the secondary conductor are aligned to form a coupled wire structure disposed adjacent to the ground shield; and is

Wherein the ground shield includes a pattern of close-ended parallel elongated slots arranged orthogonal to the primary and secondary conductors, and an edge region providing a current return path collinear with the primary and secondary conductors.

8. The IC chip of claim 7, wherein the ground shield, primary conductor, and secondary conductor are disposed on different layers and aligned with one another to form a stacked structure.

9. The semiconductor IC chip of claim 7, wherein the transformer is implemented as a resonant tuned circuit.

10. The semiconductor IC chip of claim 9, wherein the transformer is tuned to provide resonance at a frequency of 20GHz or greater.

11. The semiconductor IC chip of claim 7, wherein the integrated circuit comprises an amplifier.

12. The semiconductor IC chip of claim 11, wherein the transformer is connected to an input or an output of the amplifier.

13. The semiconductor IC chip of claim 11, wherein the amplifier comprises a differential push-pull amplifier, wherein the primary conductor is connected between differential output nodes of the amplifier, and wherein a DC bias is applied to the primary conductor.

14. The semiconductor IC chip of claim 7, wherein the integrated circuit is a power combiner circuit.

15. The semiconductor IC chip of claim 14, wherein the primary conductor of the transformer comprises a plurality of separate elongated conductive strips, wherein the secondary conductor of the transformer comprises a plurality of elongated conductive strips connected in series with each other, wherein each separate elongated conductive strip of the primary conductor is aligned with one of the series-connected elongated conductive strips of the secondary conductor.

16. The semiconductor chip of claim 15, wherein each separate elongated conductive strip of the primary conductor is connected between output nodes of a differential amplifier.

17. The semiconductor IC chip of claim 14, wherein the transformer comprises a ring-shaped layout pattern.

18. The semiconductor IC chip of claim 15, further comprising a DC supply voltage network comprising a supply voltage connection to a central region of each separate elongated conductive strip of primary conductors.

19. The semiconductor IC chip of claim 7, wherein the integrated circuit transformer is implemented as a balun.

20. A method of manufacturing a semiconductor device includes forming a ground shield, a primary conductor, and a secondary conductor, wherein forming the ground shield includes patterning a layer of conductive material to form parallel elongated slots arranged to be closed at ends orthogonal to the primary and secondary conductors, and edge regions providing current return paths that are collinear with the primary and secondary conductors.

21. The method of claim 20, wherein the ground shield, primary conductor, and secondary conductor are formed on different layers of an integrated circuit to form a stacked transformer device.

22. The method of claim 21 wherein the ground shield, primary conductor and secondary conductor are formed from different metallization layers using a BEOL process.

23. A computer-implemented method for integrated circuit design and simulation, comprising:

generating a virtual circuit model using a model of each component of the circuit, wherein at least one model comprises a lumped equivalent circuit representation of an integrated circuit transformer structure having stacked primary and secondary conductors on a ground plane, wherein conductor length is a user-specified parameter;

performing a simulation of the circuit based on one or more user-specified parameter values for the conductor lengths; and

the results of the simulation are displayed.

24. The method of claim 23, wherein the lumped equivalent circuit representation of the integrated transformer comprises an RLC filter network.

25. The method of claim 24, wherein generating a virtual model comprises:

providing a user interface that allows a user to establish a schematic depiction of the circuit using the schematic depiction of the circuit component; and

the model corresponding to each schematic icon depiction is obtained from a predefined model library.

26. The method of claim 24, wherein generating a virtual model comprises:

providing a user interface that allows a user to create a 3D circuit layout representation of the circuit;

performing 3D EM analysis on the 3D circuit; and

the results of this 3D EM analysis are used to generate an equivalent model for each circuit component.