HK1114175A - Semiconductor wafer metrology apparatus and methods - Google Patents

Description

Semiconductor wafer measuring apparatus and method

Technical Field

The present invention relates to testing semiconductor wafers during manufacturing, and more particularly to testing semiconductor wafers in-line in real time during integrated circuit manufacturing.

Background

In the manufacture of complex Integrated Circuits (ICs), a large number of individual operations or processing steps are performed on a silicon wafer in a strict order. Each of these operations must be precisely controlled to ensure that the integrated circuit produced throughout the fabrication process exhibits the desired electrical characteristics.

Often, failure of a single operation is detected after the completion of the entire very costly IC manufacturing process. This failure causes significant economic loss to the integrated circuit producer due to the very high cost of the advanced IC manufacturing process. Therefore, detecting errors in the production process immediately after the occurrence of the errors can prevent the malfunction-causing apparatuses from being unnecessarily continuously manufactured, so that economic loss due to the errors can be significantly reduced.

Process monitoring in the production of semiconductor devices relies on the examination of changes in the specific physical and/or chemical properties of the silicon wafers upon which the semiconductor devices are produced. These changes can occur after various processing steps are performed on the silicon wafer and are reflected by changes in the electrical properties of the silicon wafer. Thus, by monitoring selected electrical properties of the silicon wafer during IC fabrication, effective control of the manufacturing process can be achieved.

Not all electrical characteristics of the entire integrated circuit can be predicted based on measurements made on partially processed silicon wafers. However, most properties can be predicted directly or indirectly based on studies on the surface conditions of silicon wafers (substrates) in the IC production process. The electrical conditions of the silicon surface are very sensitive to the results of the various processing steps applied during IC fabrication. Therefore, measuring the electrical properties of the substrate surface is an efficient method by which monitoring of the results of the individual processing steps can be achieved.

Determining the electrical characteristics of the wafer surface typically requires physical contact with the wafer surface or placement of non-contact probes on a stationary wafer. For the latter, optical signals or high electric fields are used to disturb the equilibrium distribution of electrons at the semiconductor surface or near-surface region. Typically, the degree of departure from equilibrium is driven by changes in one or more electrical properties of the surface region, the near-surface region, and the overall semiconductor of the semiconductor. To obtain a more complete picture of the entire surface of the wafer, several measurements may be taken at various points of the surface. The process, referred to as "mapping", takes a measurement at each location and then the measurement device moves to the next location. The substrate typically does not maintain continuous motion during the process, and thus, the usefulness of this approach for real-time online process monitoring is limited.

Disclosure of Invention

Part of the present invention relates to a multimode optoelectronic measurement system that improves the sensitivity of currently available instruments. The improvement includes a combination of non-contact, real-time, on-line measurements throughout an extended process space. In particular, a low temperature heat treatment is described which can be added to existing measurement systems. The heat treatment accelerates the migration of gap defects before measurement starts; however, this process does not remove vacancy defects of interest to process engineers.

Moreover, the low temperature heat treatment has particular advantages when applied to a large number of wafers. Gap defects in each wafer are stabilized to nearly the same level due to thermal exposure. The application of the thermal treatment prevents each wafer from showing variations in the individual capacitance measurements due to variations in the gap. Thus, by using the disclosed low temperature techniques on groups of silicon wafers, the individual measurements can be compared relatively. This comparison is possible because the heating process produces a normalized gap defect baseline.

A common measurement technique disclosed herein relies on the measurement of the capacitance of modulated photogenerated carriers generated by absorption of light across a forbidden band with varying wavelengths and interacting with a silicon wafer (up to 300mm in diameter) at different stages in the device fabrication process. Thus, the apparatus and techniques disclosed herein are applicable to, but not limited to, epitaxial layer doping, ion implantation, rapid Thermal Processing (RTP), and trace metal contamination monitoring.

The interaction of high frequency chopped light with single crystal silicon has been theoretically addressed by modulation of the surface potential. Light at low intensity levels slightly changes the surface potential by generating electron-holes, but does not change the electrical or optical properties of the semiconductor. The doping density can be calculated correctly for uniform doping if the surface potential is sufficient to deplete the surface of the charge carriers. By the drift and diffusion of the photogenerated carriers, the charge potential associated with other physical conditions can be altered across the crystal depth (including polishing the back surface), resulting in a measurable surface potential modulation. The dynamic photogenerated carrier equation typically falls to a steady state that is easily analyzed with an equivalent circuit and can be used to correlate capacitance and conductivity with physical quantities of the semiconductor such as doping density, carrier lifetime, and defect density.

A first aspect of the present invention relates to a method of measuring defects of an ion-implanted semiconductor wafer. The method comprises the following steps: heating the wafer to a processing temperature for a processing time; transferring the wafer such that a surface thereof is substantially parallel to surface photovoltage electrodes of the head assembly; exposing at least a portion of the wafer to light having a wavelength and an intensity; detecting, using a surface photovoltage electrode, a photovoltage induced at the surface of the wafer in response to the modulated light intensity; and calculating the electrical properties of the wafer from the photovoltage induced at the wafer surface. In a variant of the first aspect, the following additional steps may also be included: adjusting the light intensity at a frequency; hydrogen fluoride washing is carried out on the wafer; inducing a reversal layer on the wafer surface, which may be achieved by applying corona or chemicals to the wafer; and comparing the electrical performance to a standard. One or more steps of the first aspect may be repeated. Also, the light intensity modulation frequency may be 0.1-100kHz and the electrical property may include net carrier concentration, which may be determined by a particular formula.

In a second aspect, an apparatus for measuring defects in an ion-implanted semiconductor wafer is provided. The device includes: a heating element adapted to heat each semiconductor wafer to a specified temperature for a specified time, thereby stabilizing the migration of gap defects; a head assembly including surface photovoltage electrodes; a conveyor for conveying the wafer so that the surface of the wafer is substantially parallel to the surface photovoltage electrodes of the head assembly during semiconductor processing; a light source for generating light having a wavelength and an intensity, the light source being modulated at a plurality of frequency ranges; a detector for detecting a photovoltage induced at the wafer surface in response to the light using the surface photovoltage electrode; and a processor, electrically connected to the detector, for calculating an electrical property of the wafer from the photovoltage induced at the surface of the wafer. In a variation of the second aspect, the apparatus may further comprise the following components: a grower, such as a rapid thermal furnace, for growing an oxide layer on the wafer; a scrubber for performing a hydrogen fluoride scrubbing on the wafer; and corona (generator). And the processor calculating the electrical property of the wafer, which may be the net carrier concentration determined by a particular formula, may perform the calculation by at least comparing the electrical property to a standard.

In a third aspect, a method of measuring damage to an ion implanted semiconductor wafer during semiconductor processing is provided. The method comprises the following steps: growing an oxide layer on a wafer; performing ion implantation on the wafer, heating the wafer to temperature T ₁ Duration P ₁ Make a pair T ₁ And P ₁ Substantially stabilizing gap defect migration; transferring the wafer such that a surface of the wafer is substantially parallel to surface photovoltage electrodes of the head assembly during semiconductor processing; exposing at least a portion of the wafer to light having a wavelength and an intensity, the intensity of light being modulated at a frequency; detecting at a wafer surface in response to the light using a surface photovoltage electrodeAn induced photovoltage; by induction at the surface of the waferCalculating the electrical property of the wafer by the photovoltage; and repeating some of the above steps for a plurality of light intensity modulation frequencies. In a variation of the third aspect, the electrical property may comprise a net carrier concentration, which may be determined by a specific formula.

The present invention also relates to an apparatus for measuring damage of an ion implanted semiconductor wafer during semiconductor processing. In one embodiment, the apparatus comprises: a head assembly including a surface photovoltage electrode; a conveyor for conveying the wafer so that the surface of the wafer is substantially parallel to the surface photovoltage electrodes of the head assembly during semiconductor processing; a light source for generating light having a certain wavelength and a certain intensity. The light intensity is modulated at a frequency, which is varied. The apparatus also includes a detector for detecting a photovoltage induced at the wafer surface in response to a change in the modulation frequency of the light; and a processor electrically connected to the detector for calculating the electrical properties of the wafer from the photovoltage induced at the wafer surface at each light intensity modulation frequency. A heat source for regulating the temperature of the wafer may also be included in accordance with the teachings provided herein.

Drawings

The invention is particularly disclosed in the claims. The above and other advantages of the invention will be better understood by reference to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1A is a graph depicting a decay study conducted in accordance with an exemplary embodiment of the present invention;

FIG. 1B is a graph depicting a series of repeated daily measurements made on a semiconductor wafer that has not been heat treated prior to measurement;

FIG. 1C is a graph depicting a series of repeated per-visual metrology results performed on a semiconductor wafer that has been heat treated according to an exemplary embodiment of the present invention prior to measurement;

FIG. 1D is a block diagram of an embodiment of an apparatus for real-time, in-line electrical characterization of semiconductors in a semiconductor manufacturing process;

FIG. 2 is a perspective view of an embodiment of a probe assembly of the apparatus of FIG. 1 positioned above a wafer transfer system;

FIG. 3 is a top cutaway perspective view of the probe assembly shown in FIG. 2;

FIG. 4 is a bottom perspective view of an embodiment of a sensor plate of the probe assembly shown in FIG. 3;

FIG. 5 is a schematic diagram of an embodiment of a circuit for measuring surface photovoltage using wafer front-side coupling;

FIG. 6A shows a block diagram of a corona control circuit for charging a wafer to create an inversion layer on the wafer surface;

FIG. 6B shows a block diagram of the corona control circuit of FIG. 6A for discharging a wafer;

FIG. 7 is a bottom cutaway perspective view of the embodiment of the coated inductor disk with polyimide coating shown in FIG. 4, used with inductor charging and high voltage biasing;

FIG. 8 is a schematic diagram of an embodiment of a preamplifier circuit for high voltage biasing a wafer using a sensor electrode;

FIG. 9 is a graph showing charge measurements of the front and back sides of a silicon wafer being cleaned;

FIG. 10 is a flowchart of steps for a system for monitoring just-implanted (pre-anneal) and implanted/annealed (post-anneal) wafer parameters in accordance with an exemplary embodiment of the present invention;

FIG. 11 is a schematic diagram of an equivalent circuit of AC-SPV measured in ion-implanted silicon;

FIG. 12 is an example of an exemplary decaying frequency sweep curve for freshly implanted silicon obtained using an embodiment of the present invention;

figure 13 is an example of a correction curve obtained from a frequency sweep curve of freshly implanted silicon derived in accordance with the teachings of the present invention.

Detailed description of the preferred embodiments

Embodiments of the present invention will be more fully understood from the detailed description that follows, which should be read in conjunction with the accompanying drawings. In the following description, like numerals represent like elements throughout the various embodiments of the present invention. In this detailed description, the claimed invention will be explained in conjunction with embodiments. However, those of ordinary skill in the art will readily appreciate that the embodiments described herein are merely exemplary and that various changes may be made without departing from the spirit and scope of the invention.

In view of the high costs associated with semiconductor processing, techniques and equipment that aid in the removal of defective wafers prior to and during wafer processing are of great importance. In particular, the ability to nondestructively detect defects by electrically characterizing the wafer is valuable because the approach is easily incorporated into existing manufacturing systems.

The apparatus and techniques disclosed herein use non-destructive means to detect defects of semiconductors at the single wafer level. In one aspect of the invention, certain types of defects are controlled by heat treating the wafer. However, before considering this particular heat treatment improvement approach, it is useful to review the supporting assumptions and relationships that support the exemplary form of capacitance measurement.

U.S. Pat. No.4,544,887 discloses an apparatus suitable for performing various electrical characterizations, which uses a method of measuring a photo-induced voltage, called Surface Photovoltage (SPV), at the surface of a semiconductor material. In the method, a light beam is directed to a surface area of a sample of semiconductor material, and a light-induced change in the electrical potential of the surface is measured. The wavelength of the emitted light beam is selected to be less than the wavelength of light corresponding to the energy gap of the semiconductor material being tested. The intensity of the light beam is adjusted and the light intensity and modulation frequency are chosen such that the AC component of the induced photovoltage is proportional to the light intensity and inversely proportional to the modulation frequency.

When measured under these conditions, it is expressed as δ V _s AC component of Surface Photovoltage (SPV) and semiconductor space charge capacitance C _sc Is proportional to the reciprocal of (c). When the sample surface is uniformly irradiated, at a sufficiently high light modulation frequency, the relationship between the Surface Photovoltage (SPV) and the space charge capacitance is given by the following relationship:

where Φ is the incident photon flux, R is the reflection coefficient of the semiconductor sample, f is the frequency at which the light is modulated, and q is the fundamental charge. The constant K is equal to 4 for square wave modulation of the light intensity and K is equal to 2 pi for sine wave modulation.

In the above cited patent, only a uniform configuration is considered, in which the area of the inductor is at least equal to the size of the semiconductor wafer, and the entire area of the sample is uniformly irradiated. When only a part of the surface of the semiconductor sample is coupled to the inductor, i.e. when the inductor is smaller than the wafer and when a semiconductor which is uniformly irradiated in this area is coupled to the inductor, the signal δ V measured from the following relation can be used _m Determination of surface photovoltage deltaV _s ：

Re(δV _s )＝Re(δV _m )-(1+C _L /C _p )+Im(δV _m )·(ω·C _p ·R _L ) ^-1

Im(δV _s )＝Im(δV _m )·(1+C _L /C _p )-Re(δV _m )·(ω·C _p ·R _L ) ^-1

Wherein Re (delta V) _s ) And Im (δ V) _s ) Are the real and imaginary components of the voltage, ω is the angular frequency of the light modulation, C _p Between inductor and waferA capacitance, and C _L And R _L Respectively, the input capacitance and resistance of the electronic detection system.

From the sign of the imaginary component, the type of conductivity can be determined. If the measurement is corrected for p-type material, the sign of the imaginary component will change if the material is n-type.

Using the above relationship, the depletion layer width W _d Given by the following equation:

where Φ (1-R) is the intensity of light absorbed by the semiconductor, q is the elementary charge, ε _s Is the dielectric constant of the semiconductor.

Except for space charge capacitance C _sc The surface charge density Q can be determined using the measurement result of the surface photovoltage by the following relational expression _ss Doping concentration N _sc And surface recombination lifetime τ. As can be seen from the following relation, the space charge capacitance C _sc And a semiconductor depletion layer width W _d Proportional to the reciprocal of:

where ε s is the semiconductor permittivity. Space charge density Q _sc And is further described by the following equation:

Q _sc ＝qN _sc W _d

where q is the basic charge, the net doping concentration N in the space charge region _sc Positive for n-type materials and negative for p-type materials. Moreover, the surface charge density Q is given by the following expression _sc ，

Q _sc ＝-Q _sc

The surface charge density is therefore easily determined from the space charge density.

And if can be atWhen an inversion layer is formed on the surface of the wafer, the depletion layer width W is expressed by the following relational expression under the inversion condition _d And net doping concentration N _sc And (3) correlation:

where kT is thermal energy, n _i Is the intrinsic concentration of free carriers in the semiconductor. Several methods of forming the inversion layer on the semiconductor surface are disclosed below.

In addition, the surface recombination rate can also be determined from the SPV. The recombination lifetime τ of the minority carriers of the surface is given by the following expression:

in general, the photovoltage signal can be expressed as:

here, I _eh Is the electron hole generation rate, G and C are the overall conductivity and capacitance of the system, ω is the light modulation frequency, and τ _s Is the carrier lifetime of the near-surface region. The electron-hole generation rate is given by:

where Φ is photon flux, R and α are reflectance and absorption coefficient, L is carrier diffusion length, W _d Is the depletion layer width. Using the high defect density condition of alpha W _d 1 and α L < 1, giving the following relation:

I _eh ∝ qΦ(1-R)αL。

diffusion lengthWherein D is the diffusion coefficient，N _D Is the number of defect/recombination centers, f (E) is a function of charge carrier energy, which depends on the dominant energy scattering mechanism, m is the charge carrier effective mass, and k is the boltzmann constant.

Combining the last two expressions above, the following equation is obtained:

whereinIndicating the effective defect density.

Finally, for ion implanted silicon wafers, it has been found that carrier lifetime is inversely proportional to implant damage, particularly under the as-implanted conditions. For very low dose implant cases, the concentration of free carriers decreasesLow. When high dose implants are applied, the increased crystal damage produces a photovoltage signal controlled by the photogenerated carrier lifetime rather than the free carrier concentration. In some cases, carrier lifetime is the dominant factor in the measured SPV signal. After annealing the wafer, the dopant-implanted substitutional sites contribute to the net carrier concentration N _sc It is derived from SPV. For a just-implanted p-type or n-type wafer, charged defect density is a measure of implant dose/energy. For implanted/annealed silicon wafers, the measured amount provides a doping concentration that is directly related to the implant dose/energy.

In the above overview, a method for analyzing a semiconductor wafer for defects is described. Other methods and relationships known in the art may be used to detect defects in a given semiconductor wafer. Additional details regarding the specific apparatus and methods are described in greater detail below. However, before describing embodiments of the general apparatus and equipment, it is useful to introduce heat treatment methods that may be incorporated into the various aspects of the invention disclosed herein.

Semiconductor manufacturing processes such as ion implantation introduce a large number of crystal defects that act as recombination centers for photogenerated electron-hole pairs. This defect density affects the surface photovoltage by shortening the lifetime of the photogenerated carriers. Manufacturers are concerned with the detection of various defects because the number and type of defects can limit the functionality of electronic devices made from implanted semiconductor materials.

Implanting single crystal silicon produces many types of radiation defects. Some defects are stable at room temperature and require high temperature annealing (500-1000 ℃) to remove them. The majority of defect types that are stable at room temperature are double vacancies-a complex consisting of two nearest neighbor vacancies. The distribution of these defects, as well as several other types of stable vacancy-based complexes, can be considered an "implant characteristic" that can be used to monitor implant uniformity.

Other post-implantation defects present in single crystal silicon at room temperature are unstable. The defects can migrate, change their configuration and distribution until they reach a "trap point", e.g., the wafer surface, where they can stabilize or disappear. The presence of these defects destabilizes any damage-related measurements made on implanted silicon wafers at room temperature. Most of these types of defects can be annealed at temperatures below 200 c. Most common unstable defects are single self-interstitials and pairs of self-interstitials (double interstitials) and their complexes with dopant impurities at room temperature. There is some evidence that shows that the single self-gap anneals away at about room temperature. At room temperature, the double gap of silicon is mobile almost as well as the single gap, and is annealed at about 170 ℃. Two major gap-impurity complexes, positively charged Si-P6 and neutral Si-A5, were annealed at 120 ℃ and 160 ℃ respectively to eliminate. The first defect complex is typically associated with boron implantation and the second defect complex is typically associated with phosphorous implantation.

The thermal processing parameters, such as temperature and time, required to stabilize the implanted wafer depend on the specific implantation conditions, including implant species, dose and energy, and implant temperature. The heating/annealing temperature is a function of the activation energy for migration of a given defect and defect complex. Thus, the type of implant determines the type of these composites. The annealing time depends on the defect activation energy and the defect density, and thus, the annealing time is a function of all the above listed implantation conditions, with the implant dose being the dominant factor. The dependence of the heating time on the type of implant is obvious. The larger the ion, the greater the number of elastic scattering events per ion and the greater the total number of atoms displaced. Although the influence of the implantation ability is small, it is still a factor. Elastic scattering increases and dominates up to a certain energy value. In addition to this threshold energy, inelastic scattering dominates the peak and the number of defects does not increase significantly.

Figure 1A shows decay studies for three different implants. To analyze movable defect migration, the next order rate equation is written:

where n is the concentration of one type of defect, E _A Is the activation energy for these defects to migrate, T is the temperature, and A is the pre-frequency factor. Integrating the equation, and setting t/t ₀ > 1, the following equation is obtained:

the activation energy characteristics for different implant species are calculated by substituting the measured data into the formula. The error due to the gap migration can be controlled by the preliminary heat treatment.

Semiconductor metrology is of particular interest for two types of crystal defects, vacancy defects and interstitial defects. If an atom is absent from one of the lattice sites that should be occupied, vacancy defects will result. In contrast, if atoms are pushed into the amorphous lattice sites of the crystal, interstitial defects are generated.

In connection with implantationThe gap is unstable at room temperature. As a result, pre-measurement heat treatment methods have been developed. At a predetermined temperature T ₁ Heating the semiconductor material for a prescribed time P ₁ The gap is stabilized by accelerating the relevant atoms to sink down the wafer surface. This pre-processing eliminates instability of the newly implanted wafer and enables the collection of accurate, repeatable measurements.

For semiconductor defect measurement methods, applicants have found that low temperature heat treatment prior to measurement accelerates the migration of interstitial defects without annealing vacancies. This discovery is important to the semiconductor industry as vacancy defects are the primary implantation result of concern.

Accordingly, one aspect of the present invention relates to heating for a time to stabilize the migration of the gap before beginning to measure the semiconductor photovoltage. This general concept can be used with existing semiconductor measurement techniques. In one embodiment, the heating time P for the treatment step ₁ And may be from about 3 minutes to about 15 minutes. Similarly, a temperature range T for heating a semiconductor wafer or some part thereof before measuring the surface photovoltage ₁ And may be from about 70 c to about 180 c. However, other heating times and temperatures can be determined without undue experimentation that falls within the general scope of the present invention. It is also desirable to maintain substantially uniform heating of the wafer as part of the pre-heat treatment process. Thus, in one embodiment, it is desirable to maintain the temperature variation range over the entire surface of the wafer below about 2% or 2%.

Also, various heating elements, such as hot zones, convection heaters, ROSTs, ovens, hot plates, processing stations, and other sources of thermal energy may be used to heat the wafer prior to measurement without limitation. In one embodiment, the heating station is incorporated into an in-line measurement system of a semiconductor manufacturing or measurement apparatus. In another embodiment, the local heating is performed using a laser or focusing optics. The localized heating embodiment allows a portion of the wafer to be heated. Furthermore, by measuring the local area, the heat treatment method of the present invention can be used without heating the entire wafer.

Moreover, by always performing the preliminary heat treatment step on a group of wafers, it is possible to control the variation in defects among different wafers. This occurs because the heating step uniformly normalizes the level of gap migration in each wafer. As a result, only the effect of other defects, i.e. vacancies, will affect the final measurement. An example of the advantages of the pre-heat treatment can be seen by comparing fig. 1A and 1B.

Figure 1B shows the characteristic decay of a just-implanted wafer and the resulting steady state over a period of several days. Dynamic charge is plotted versus time (days). The attenuation levels shown in FIG. 1B show a gradual change in the gap migration. Thus, the results in FIG. 1B show normal decay without the disclosed pre-heat treatment method.

In contrast, FIG. 1C is drawn to the same scale as FIG. 1B, but FIG. 1C shows a distinct result. The graph of fig. 1C shows repeatable daily measurements of a semiconductor wafer that has been pre-heat treated at 150℃ before each measurement. The advantages of the disclosed method are clear in that the standard deviation is 0.2% since essentially zero attenuation is present.

The low temperature heating method disclosed herein is not associated with high temperature annealing. The high temperature anneal is performed at a temperature several times higher than the temperatures disclosed herein. Also, although the disclosed pretreatment method serves to stabilize the gap migration, a high temperature anneal is used to reconstruct the crystal lattice and remove defects or reset dopants. Thus, while the designed low temperature approach improves wafer measurements, high temperature annealing is only used to permanently alter the semiconductor crystal. Thus, high temperature annealing will not be used in the defect measurement phase after ion implantation.

Different substances exhibit different decay rates and different energies. The best performance is obtained when the following parameters are controlled: type of matrix: oxide, thickness: 30A, corona, implant chuck temperature, beam current and tilt angle for low dose pre-heat treatment. Controlling these parameters can control the implant process to one percent or better for the three sigma control limit.

Different substances exhibit different decay rates and different activation energies. This in turn affects the actual pre-measurement stabilization temperature used. Typically, higher temperatures of about 150 ℃ are used for high damage implants; temperatures of about 130 ℃ are used for low-damage implantation. Very deep implants require higher temperatures of about 180 ℃. Since the measurement techniques disclosed herein are repeatable, an alternative approach is to correctly model the decay using a first order rate equation and compensate the measurements by a software algorithm.

Briefly, referring to FIG. 1D, an embodiment of an apparatus 10 for real-time, in-line electrical characterization of semiconductors using a surface photovoltage induced during semiconductor manufacturing includes a sensor head assembly 14, support electronics 18, and a wafer transport apparatus 22. In operation, a wafer transport device 22, such as a conveyor belt, robot arm, wafer carrier plate, or similar device, moves the wafers 28, 28 'through the production process, and in one embodiment, moves the wafers 28, 28' under the sensor head assembly 14.

Referring to fig. 2, the sensor head assembly 14 includes a probe head 32 mounted in a cradle 36 on a motorized plate 40. The motorized plate 40 moves the probe head 32 in the vertical direction (arrow z) to adjust the vertical position of the probe head 32 with an accuracy of 0.2 μm relative to the wafer 28. A mechanical plate 40 is attached to the probe arm 41.

The inclination of the probe arm 44 is adjusted, either manually (using set screws 46) or mechanically (using, for example, piezoelectric actuators 48), so as to adjust the longitudinal axis L-L' of the probe head 32 perpendicular to the plane of the wafer 28. The vertical position of the probe head 32 relative to the wafer 28 is controlled by feedback signals from capacitive position sensing electrodes described in detail below.

Briefly, three capacitive position sensing electrodes are positioned at the periphery of the sensor. To measure the capacitance between each of the three electrodes and the wafer, a 1V signal at 70kHz was applied through a 10 kilo-ohm resistor connected to each electrode. The AC current flowing through these resistors is measured using a preamplifier and a lock-in amplifier. The phase lock signal is further processed using a computer and transmitted to a motion control board, which in turn uses a vertical (Z-axis) motorized plate to position the probe at a predetermined distance from the wafer surface.

Referring to FIG. 3, the probe 32 includes an inductor mount assembly 50 that supports an inductor 54, the inductor 54 being connected to a preamplifier board 58 by a plurality of flexible connectors 60. Light emitted by a Light Emitting Diode (LED) 64 is collimated by a lens 68 before passing through a beam splitter 72.

The LEDs 64 are mounted on an LED driver board 74, which board 74 controls the intensity of the LEDs 64 (via a preamplifier 79) at an intensity level determined by the computer 60 in response to a signal from a reference photodiode 78. Light from the LED64 reaches the reference photodiode 78 by being partially reflected by the beam splitter 72. Light passing through the beam splitter 72 passes through the circuit board 86 and the openings 80, 82 of the preamplifier board 58, respectively, then through the sensor mount assembly 50 and impinges on the wafer 28 being tested.

Light reflected by the wafer 28 returns along the optical path described above and is then reflected by the beam splitter 72 to the measurement photodiode 92. Light phi reflected by the wafer 28 _R For detecting the edge of the wafer passing under the probe head 32 and triggering a measurement operation. This reflected light is also used to measure the light absorbed by the wafer 28 according to the following relationship;

Φ＝Φ ₀ -ΦhdR

wherein phi ₀ Is incident light and can be determined by measuring the light reflected by an aluminum mirror in place of the wafer 28. In this way, the reflectance of the wafer 28 can be determined. Although the above embodiments describe splitting light using a splitter, other embodiments are possible in which optical fiber splitting is used.

Referring again to fig. 1, the ledd 64 is controlled by signals from the support electronics 18, which the probe 32 returns to the support electronics 18. The support electronics 18 include an oscillator 100 that provides a 40kHz modulated control signal 104 that is used by the LED control 62 as a reference signal to control the LED driver 63 that powers the LED 64. The oscillator 100 also provides a reference signal 108 to a lock-in amplifier 112. The output signals 116 from the surface photovoltage sensor and the measurement photodiode 92 of the probe 32 (via the preamplifier 93) are input signals to a multiplexer 120, which multiplexer 120 alternately connects each signal to the input of the lock-in amplifier 112. The lock-in amplifier 112 demodulates the input signal and provides the demodulated signal to another multiplexer 150. A multiplexer 150 switches between the two input signals from the lock-in amplifiers 112 and 140, the multiplexer 150 connecting said lock-in amplifiers 112 and 140 to a Data Acquisition (DAQ) card 156, the data acquisition card 156 in turn digitizing the input signals so that they can be further processed in a computer 160. In an alternative embodiment, the multiplexer 150 is part of the data acquisition card 156.

Fig. 4 is a bottom perspective view of the inductor disk of inductor head 32. A plurality of electrodes are formed on the rigid insulating substrate 200. In one embodiment, a fused silica wafer having a diameter of 10mm is used. The central surface photovoltage electrode 204 senses the signal from the wafer 28. The center surface photovoltage electrode 204 is partially transmissive, allowing light from the LED or laser 64 to reach the wafer 28. The other three electrodes 208 located at the periphery of the substrate are used to sense the position of the sensor head 32 above the wafer 28 and to measure the parallelism of the sensor relative to the surface of the wafer 28. All electrodes 204, 208 are formed by depositing an indium-tin-oxide film through a shadow mask.

Similarly, a plurality of electrodes 212 are formed on the surface of the substrate 200 opposite the electrodes 204, 208 for connecting the sensor to the preamplifier circuit 58 by flexible connectors 60. Thin conductive electrodes 218 on the sidewalls of the substrate 200 are also deposited using shadow masks, the thin conductive electrodes 218 connecting the electrodes 204, 208 on the first surface and the corresponding electrodes 212 on the second surface. The deposition avoids the use of tubing through the substrate, thereby keeping the flatness of the inductor better than 0.2 μm. The front electrodes 204, 208 and the side electrodes 218 may be protected using a thin insulating coating, such as polyimide, formed by sputtering to maintain flatness of the inductor.

The electrode 208 is used to capacitively sense the position of the sensor above the wafer 28. Referring again to FIG. 1, the oscillator 128 provides a 70kHz input signal 124 to the position electrode 208 for measuring distance to the wafer 28. The same signal is also provided as a reference signal 132 for the lock-in amplifier 140. Position signals 146 from each of the three position sensing electrodes 208 are provided as input signals to a multiplexer 148 via a preamplifier 149. In turn, a multiplexer 148 that switches between each of the aforementioned signals alternately connects each signal to the lock-in amplifier 140. The demodulated output signals from the lock-in amplifiers 112 and 140 are input signals to a multiplexer 150, the multiplexer 150 alternately connecting each signal to a data acquisition card 156 located in a computer 160 including a CPU 164. Also, in an alternative embodiment, the multiplexer 150 is part of the data acquisition card 156.

The CPU164 compares the position signal 146 to a reference value corresponding to the desired distance (established by calibration and stored in the computer) between the sensor 54 and the wafer 28. The difference between these two values is communicated to the motion control board 170, which uses the motorized platen 40 to position the probe 32 at a predetermined distance from the wafer 28, which corresponds to the sensor-wafer distance offset from the desired value.

In operation, as the edge of the continuously moving wafer 28 intersects the intensity modulated beam from the LED or laser 64, the intensity of the reflected light increases, thereby increasing the signal from the photodiode 92. The measurement of the reflected light is repeated and the new value is compared with the previous value. The light intensity measurements were repeated until the difference between the sequenced values fell below 5%, indicating that the entire beam was within the flat portion of the wafer.

The reduction in the deviation causes the surface photovoltage electrode 204 to acquire the SPV signal, followed by the position electrode 208 to acquire the capacitance signal. If the capacitance signals from different electrodes (208) differ by more than 5%, the SPV signal is stored but not recalculated. The sequence of all measurements is then repeated until the capacitance from the electrode (208) at a different location falls within the 5% limit, indicating that the electrode is not located near the edge of the wafer 28. At this point, the average of the capacitances from the three positioning electrodes 208 is used to recalculate all previous values of the SPV signal.

The SPV measurement cycle is repeated, measuring the light intensity, SPV signal, and capacitance of the positioning electrode in sequence, until the capacitances from the three positioning electrodes (208) differ by more than 5%, indicating that the electrodes are near opposite edges of the wafer 28. After reaching this point on the wafer 28, an SPV measurement is taken using the previously measured capacitance values. In each cycle, the measurement of each value (reflected light, SPV signal, capacitance) is repeated for 10 milliseconds, and an average value is calculated using the CPU 164.

In one embodiment, the wafer 28 is placed on a grounded turntable (conveyor belt, robotic arm, or other similar device) 178 that is coated with an insulating material and is used to transport the wafer 28 in a down, up, or other orientation such that the sensor surface of the probe head 32 is parallel to the wafer surface. Alternatively, the transfer device is biased using a DC voltage. In one embodiment, the DC bias is selected to be between-1000 and 1000 volts. Although FIG. 1D shows the use of the grounded, insulated turntable 22 to move the wafer 28 under the probe assembly 14, it is possible to provide all of the necessary measurements without grounding the turntable using only the electrodes provided by the sensors 54. Referring to fig. 5, as described above, the SPV signal is received by the center surface photovoltage electrode 204, which center surface photovoltage electrode 204 is connected to the input terminal of an operational amplifier 250 located on the preamplifier circuit board 58. The other input terminal of the operational amplifier 250 is connected to ground and to the output terminal of the operational amplifier 250 through one or more resistors. The back capacitive contact previously provided by the turntable is now provided by three registration electrodes 208 located on the periphery of the sensor, the three registration electrodes 208 being connected to ground 252 instead of to the input terminals of a capacitive (current measuring) preamplifier located on the preamplifier circuit board 58 when measuring SPV.

To measure capacitance, the electrode 208 is alternately switched between ground 252 and the input of a capacitive preamplifier located on the preamplifier circuit board 58. This arrangement enables non-contact measurements to be made using any type of wafer support. Thus, the wafer support does not need to be connected to ground and can be made of an insulating material.

As described above, measuring the surface doping concentration requires the formation of an inversion layer on the wafer surface. In one embodiment, this is accomplished by charging the wafer 28 using a corona generator and then measuring the surface photovoltage on the wafer 28. Specifically, the wafer 28 is first charged to inversion using a corona generator. n-type wafers require negative surface charges and p-type wafers require positive surface charges. In one embodiment, the corona generator comprises a single metal tip, such as tungsten, that is 5mm above the wafer 28 and is biased at 3.5kV for 2-3 seconds. After charging, the wafer 28 is moved under the probe assembly 14 and measurements are taken. After the measurement, the wafer 28 is discharged by moving the wafer 28 under a neutral corona generator or returning the wafer 28 to the original corona generator operating in a neutral discharge mode.

Simple corona generators with metal tips or wires are not capable of controllably charging the wafer surface. Control of charging is important because although a minimum amount of charge is required to induce an inversion layer on the surface of the wafer 28, overcharging may damage the wafer surface and even cause electrical breakdown of an insulating coating formed on the wafer surface. To avoid overcharging the wafer 28, the closed-loop controlled corona charging arrangement disclosed in fig. 6A and 6B controls the charge deposited on the wafer surface, thereby preventing surface damage.

Referring to fig. 6A, the wafer 28 is moved under an ionized air source 260 located about 10mm above the wafer 28, the wafer 28 being located on a grounded insulating turntable 22. A reticulated stainless steel reference electrode 264 is placed at a distance of about 0.5mm to 1mm from the wafer 28. Potential V on reference electrode 264 _el With a user-defined and computer-generated reference voltage V _ref 268 is referred to as a differential potential V _diff The difference is amplified and its polarity is reversed within the corona control module 270. Apply the voltage V _corr To the source of ionized air 260. Thus, the potential V applied to the ionized air source 260 by the power control module 270 _corr Is opposite to the polarity of the differential voltage and is given by the following expression:

V _corr ＝V _ref -V _el 。

controlling the corona charging during the charging process allows not only real-time control but also the use of simpler electronic circuitry. The presence of ions between the ionized air source 260, the reference electrode 264, and the wafer 28 reduces the equivalent impedance in the electronic circuit and allows for the use (in the control module 270) of an amplifier having 10 ⁹ -10 ¹⁰ Ohmic input impedance. When the wafer surface potential is measured not during charging but after the corona is turned off, the input impedance is higher than that of the amplifier used in the previous methodImpedance (10) ¹³ -10 ¹⁵ Ohms) are orders of magnitude lower.

Referring to fig. 6B, the wafer 28 may be discharged by setting the reference voltage 268 to 0, i.e., grounding it. Alternatively, if a separate corona unit is used to charge and discharge the wafer, the discharge corona reference voltage may be permanently connected to ground.

Referring to fig. 7, an alternative method of sensing the surface inversion layer is to bias the sensor with a high voltage. The method entails forming an insulating film 230, such as polyimide, on the inductor center electrode 204 and the positioning electrode 208. FIG. 8 illustrates an alternative method for inducing an inversion layer on the surface of the wafer 28 by voltage biasingThe method is carried out. Fig. 8 shows a schematic of the electronic circuitry including a preamplifier for measuring AC surface photovoltage and a connector to a bias high voltage source for use with the above-described sensor with polyimide coating 230. The insulating coating 230 of the inductor 54 allows a sufficiently high voltage (500-1000V) to be applied to induce a surface inversion layer in a typical wafer used in semiconductor manufacturing. The arrangement of rigid inductor electrode 204 separated from the semiconductor surface by an air gap requires a high degree of flatness of the electrode surface. When a high DC voltage is used, any edge or surface roughness will increase the local electric field and increase the ionization of air, resulting in electrical breakdown. Thus, an electrical connection is established between the electrode and the detection electronics, thereby having minimal impact on surface flatness. Thus, the use of the lateral connector 218 eliminates the need to form a through hole in the inductor and maintains a high flatness of the inductor. The current in the space charge region (shown in perspective) of the wafer 28 produced by illuminating the wafer 28 with the LEDs 64 is shown as an equivalent current source J _h . Also depicted is an equivalent resistor R representing the carrier recombination at the surface of the wafer 28 _R And an equivalent capacitor C representing space charge capacitance _sc 。C _G Represents the capacitance between the wafer 28 and the turntable 22, but C _p Representing the capacitance between sensor electrode 204 and wafer 28. Through a 10 megaohm resistor R _HV A computer controlled high voltage 300 is applied to sensor electrode 204. Inductor electrode 204 is also passed through high voltage capacitor C _HV Connected to an operational amplifier 250 (as described above). Capacitor C _OA (also shown in perspective) represents the input capacitance of the operational amplifier 250. Selection C _HV Is made larger than C _OA About 10 times, so as to calculate IM (Δ V) _s ) And Re (delta V) _s ) C for temporary use _L Close to C _OA . Similarly, calculate IM (δ V) _s ) And Re (delta V) _s ) R used in the process _L Is close to R _HV 。

In addition to the above-described method of forming the inversion layer, the inversion layer may be formed on the surface of the wafer 28 using a chemical treatment method. The method is used for p-type silicon wafersAre particularly useful. Since HF introduces positive surface charges, HF treatment will produce a negative inversion layer on the surface of the p-type silicon wafer. In one embodiment, a mixture of hydrofluoric acid and water (1: 100 HF: H) is used in liquid or vapor form ₂ O) treating the silicon wafer to be tested. The wafer is then placed under the probe assembly 14. In many processes, HFThe process is already part of the manufacturing process, so that only probe assembly 14 needs to be placed behind the HF treatment location.

In another embodiment, SPV is used to measure the electrical properties of the wafer parameters just after implantation (pre-anneal) and the wafer parameters after implantation/anneal (post-anneal), as shown in the flow chart of fig. 10. SPV measures lattice damage in the as-implanted condition and measures the concentration of free carriers in the implanted condition after annealing. Implant dose sensitivity, which is determined by the ratio of the relative percent change in SPV signal to the percent change in implant dose/energy, and a high density measurement plot of 0.5 to 3.0 provide an improved analysis of implant uniformity.

In an exemplary embodiment, a silicon wafer that has been ion implanted or implanted with ions is provided as part of the monitoring process 400. The ion implantation may be performed by using any commonly used species such As boron (B), phosphorus (P), arsenic (As), fluorine (F), argon (Ar), indium (In), or boron difluoride (BF) ₂ ) The dopant is doped 402 into the matrix. Doping may be performed using ultra low energy ions, for example, ions below 10 keV. After ion implantation, the wafer typically has an ion implant dose/energy range. For example, the low dose may be 0.1E11-5E12 ions/cm ² (ii) a The high dose may be 5E12-2E15 ions/cm ² (ii) a The low energy can be 0.1keV to 20keV; and the high energy may be 20keV to 10MeV. Prior to the monitoring process, the wafer just implanted (before annealing) may be monitored or the wafer annealed to measure the free carrier concentration.

In an exemplary embodiment, when measuring a freshly implanted wafer, the wafer may be subjected to an optional hydrogen fluoride wash 414, 416 to remove oxides after the wafer has been subjected to the optional ion implant 402. For example, in the case of low energy/low dose, a hydrogen fluoride wash may optionally be performed. Alternatively, when the wafer is characterized as low energy/high dose or high energy/low dose, a hydrogen fluoride wash may be performed with an oxide applied to the wafer prior to ion implantation. In the exemplary embodiment described above, a corona 418, 420 may then optionally be applied, then the wafer is moved under the probe assembly 14 and measurements taken 422. According to one exemplary embodiment, the corona is applied while the wafer is characterized as low dose/low energy. The application of a corona enables calculation of the surface recombination time, however if no corona is applied to the substrate, the minority and majority lifetimes may be calculated. After the optional application of the corona, the wafer is moved under the probe assembly 14 and measured to analyze damage, such as lattice damage 422. The electrical properties of the as-implanted wafer can be characterized by comparing the measurements to a known standard of common wafer damage.

If the wafer is measured after annealing, after optional ion implantation 402, the wafer is annealed 412 using any standard annealing method, such as Rapid Thermal Processing (RTP) or furnace annealing 412. After annealing, the wafer may optionally be subjected to a hydrogen fluoride wash 414', 416'. According to an exemplary embodiment, an inversion layer 424 may be formed on the wafer surface after an optional hydrogen fluoride wash. For example, the inversion layer 426 may be created by applying a corona of suitable polarity or applying a chemical treatment as described above. After the optional formation of the inversion layer, the wafer is moved under the probe assembly 14 and measurements are taken 422.

In an exemplary embodiment using SPV to measure the electrical properties of the as-implanted (pre-anneal) and implanted/annealed (post-anneal) wafer parameters, a thin thermal oxide layer is grown on the wafer, followed by implantation of species in step 402. An oxide layer can be grown on the wafer in a rapid thermal furnace RTF. For example, the thickness may be 20-80 angstroms and calibrated to ensure a stable surface charge on the wafer.

In another alternative embodiment, the short and varying electron-hole lifetime associated with ion implantation damage (i.e., before annealing) affects the results obtained by standard SPV analysis. When measuring a wafer just implanted (i.e., before annealing), the optimum frequency for implanting a damaged wafer can be calculated by varying the frequency at which the light is modulated. Moreover, the wavelength of the light used for irradiation can be optimized to account for a wide range of implant conditions. Therefore, the wavelength, the light intensity and the light intensity modulation frequency of the light can be changed to optimize the measurement result of the doping impurities. For example, the wavelength of light may be selected to fall particularly within a given range, such as within the infrared or ultraviolet spectral range.

In this embodiment, the modulation frequency of the light intensity is swept over a given frequency range when the wafer is located below the probe. The optimum modulation frequency for implanting a damaged substrate, such as silicon, can be calculated by scanning the modulation frequency at the selected maximum light intensity and light wavelength. Wafers with known dose and damage measurements were used as calibration standards for the substrates tested.

For example, for a given maximum light intensity and wavelength of light, the modulation frequency may be 0.1-100kHz. SPV measurements are taken and compared to measurements of known ion implanted substrates that have been exposed to defined energies, beam currents and tilt angles. Thus, the system can be properly calibrated and used to produce wafers with measured contour maps to control industrial implant processes using standard statistical methods.

As described above, the probe head is capacitively coupled to the wafer surface during measurement. The capacitive coupling of the probe to the wafer limits the frequency roll of the analysis, rather than being controlled by the depletion region capacitance or charged defect capacitance.

Using the method and apparatus, the imaginary part of the SPV signal for any given frequency can be measured. Fig. 11 shows an equivalent circuit model 500 of a substrate typically used for ion implant analysis. The SPV voltage 502 is measured at the wafer surface and various electrical characteristics of the wafer can be calculated. As described above, photocurrent source 514 is swept through a given frequency range. The conductivity of the quasi-neutral region (Go) 504, the capacitance of the quasi-neutral region (Co) 506, the composite capacitance of the space charge region (C1) 508, the composite capacitance of the space charge region (Cd) 510, the composite conductivity of the space charge region (G1) 512, the wafer oxide capacitance (Ci) 516, and the series resistance (Rs) implanted into the defect region 518 can be calculated. Furthermore, by measuring the imaginary part of the signal as a function of the modulation frequency, the maximum value of the decay frequency due to the wafer dependent capacitance can be calculated.

Fig. 12 shows a typical scan frequency curve 600 for implanted silicon. The graph shows two different implantation conditions: mild 604 and deep 602 implants, and a profile of standard 606. For example, the low damage dose implant curve 604 may represent that the ion/cm has been at 5E12 ² A substance such as boron implanted in the wafer. The high damage implant curve 602 may represent that the ion/cm has been at 5E13 ² A substance such as arsenic implanted in the wafer under conditions. The curve moves axially up or down with respect to the SPV608 depending on the species mapped for a given modulation frequency sweep 610, the wavelength of light used, and the maximum intensity of modulated light. Thus, differences in implant materials, maximum intensity of light, and wavelength of light cause the low dose implant 612, high dose implant 618, and standard 614 to move the SPV axis upward. The real part of the SPV measurement enables calculation of the actual light intensity and the imaginary part is used to measure the phase shift.

The decay frequency (ω) and the slope (α) of the curves 602 and 604 may be used as calibration points. The combination of parameters may be used to establish a calibration curve for the implant parameters on the multi-point curve of fig. 13. Figure 13 shows an experimental calibration curve from a frequency sweep curve for freshly implanted silicon.

One advantage of frequency sweep analysis is that the low lifetime associated with implanted silicon can be measured over the entire frequency range. Typically, for ultra-shallow implants less than 5kev, short wavelength (e.g., 0.4 μm wavelength) ultraviolet light gives the highest signal. Blue light is more effective for implants having energies greater than 5keV (e.g., wavelengths of 0.375 μm). Generally, the stronger the light from the light source, the higher the SPV signal implanted into the wafer. Longer wavelength light allows SPV measurements on amorphized surface silicon from severe ion damage. Furthermore, light intensities up to those associated with laser diodes will provide improved signals.

Furthermore, the present apparatus is particularly suitable for use in a sealed chamber environment, such as a reduced pressure chamber, a chamber for a chemically active gas, or a chamber for an inert environment. The entire probe assembly 14 can be positioned within the sealed chamber and connected to electronics passing through the walls of the sealed chamber by a pressure fixture. Alternatively, the probe assembly can be mounted on the sealed chamber wall such that the inductor is positioned within the chamber, but the remainder of the probe assembly is positioned outside of the sealed chamber.

The means of implementing the monitoring method using the AC-SPV method emphasizes the determination of the variation of the measured parameter from different wafers rather than the value of the specific parameter itself. Typically, the electrical parameters of the back side of the wafer cannot be measured without changing the front side of the wafer, and the front side of the wafer must be contacted in order to complete the measurement circuit. Therefore, measurement methods performed on the back side of the wafer are not generally used in process monitoring. The non-contact AC-SPV measurement method allows process monitoring by measuring surface properties on the back and front sides of the wafer. As described above, the probe head may be mounted below, above, or otherwise at the wafer such that the sensor surface is parallel to the back side of the wafer depending on how the wafer transfer system transfers the wafer to the probe head. Also, two probes may be used, one on each side of the wafer, to characterize both the front and back sides of the wafer. As a schematic of such means, fig. 9 shows a comparison of measurement results of surface charges on the front surface having a mirror-like surface finish. Measurements were made on two halves of the same 100mm p-type (100) silicon wafer that was subjected to a wet clean process simultaneously. At various stages of the cleaning process, the surface charge is measured on the front side (polished side) of one half and the surface charge is measured on the back side (unpolished side) of the other half. The results shown in fig. 9 indicate that the surface charges on the front and back surfaces have the same behavior.

In addition to measuring epitaxial and ion implanted silicon, the disclosed apparatus and method can also be used to measure Silicon On Insulator (SOI) materials, strained silicon films, si-Ge films (Si-Ge), and metal contaminants. For example, SPV can be used to measure interface charge in SOI materials.

While preferred embodiments have been shown, those skilled in the art will recognize that many changes may be made thereto without departing from the scope and spirit of the present invention. Accordingly, the invention is not limited except as by the appended claims.

Claims (22)

1. A method of measuring defects of an ion-implanted semiconductor wafer, the method comprising the steps of:

a) Heating the wafer to a processing temperature for a processing time;

b) Transferring the wafer such that the surface thereof is substantially parallel to the surface photovoltage electrodes of the head assembly;

c) Exposing at least a portion of the wafer to light having a wavelength and an intensity;

d) Detecting an optical voltage induced at the surface of the wafer in response to the modulated light intensity using a surface optical voltage electrode; and

e) The electrical properties of the wafer are calculated from the photovoltage induced at the wafer surface.

2. The method of claim 1, further comprising the step of f) modulating the intensity of the light at a frequency.

3. The method of claim 1, wherein the light intensity modulation frequency is from 0.1 to 100kHz.

4. The method of claim 1, further comprising the steps of: the wafer is subjected to a hydrogen fluoride rinse.

5. The method of claim 1, further comprising the steps of: an inversion layer is induced on the surface of the wafer.

6. The method of claim 5, wherein the step of inducing an inversion layer on the surface of the wafer is accomplished by applying a corona to the wafer.

7. The method of claim 5, wherein the step of inducing an inversion layer on the wafer surface is accomplished by chemically treating the wafer.

8. The method of claim 1, wherein the step of calculating the electrical property of the wafer comprises comparing the electrical property to a standard.

9. The method of claim 1, wherein the electrical property comprises net carrier concentration.

10. The method of claim 9, wherein the net carrier concentration is equal to

Where k is the Boltzmann constant, T is the Kelvin temperature, q is the base charge, W _d Is the depletion layer width, and N ^* _D Is the effective defect density.

11. The method of claim 2, further comprising the steps of: repeating steps b to f for a plurality of light intensity modulation frequencies.

12. An apparatus for measuring defects in an ion implanted semiconductor wafer, the apparatus comprising:

a heating element adapted to heat each semiconductor wafer to a specified temperature for a specified time, thereby stabilizing the migration of gap defects;

a head assembly including surface photovoltage electrodes;

a conveyor for conveying the wafer so that the surface of the wafer is substantially parallel to the surface photovoltage electrodes of the head assembly during semiconductor processing;

a light source for generating light having a wavelength and an intensity, the light source being modulated at a plurality of frequency ranges;

a detector for detecting photovoltage induced at the wafer surface in response to the light using the surface photovoltage electrode; and

a processor, electrically connected to the detector, for calculating an electrical property of the wafer from the photovoltage induced at the wafer surface.

13. The apparatus of claim 12, further comprising an grower for growing an oxide layer on the wafer.

14. The apparatus of claim 13, wherein the grower comprises a rapid thermal furnace.

15. The apparatus of claim 12, further comprising a scrubber for performing a hydrogen fluoride scrub of the wafer.

16. The apparatus of claim 12, further comprising a corona generator.

17. The apparatus of claim 12, wherein the processor calculates the electrical property of the wafer by at least comparing the electrical property to a standard.

18. The device of claim 12, wherein the electrical property comprises net carrier concentration.

19. The device of claim 18, wherein the net carrier concentration is equal to

Where k is the Boltzmann constant, T is the Kelvin temperature, q is the base charge, W _d Is depletion layer width, and N ^* _D Is the effective defect density.

20. A method of measuring damage to an ion implanted semiconductor wafer during semiconductor processing, the method comprising the steps of:

a) Growing an oxide layer on the wafer;

b) Performing ion implantation on the wafer, heating the wafer to temperature T ₁ Duration P ₁ So as to be opposite to T ₁ And P ₁ Substantially stabilizing gap defect migration;

c) Transferring the wafer such that a surface of the wafer is substantially parallel to a surface photovoltaic electrode of the head assembly during semiconductor processing;

d) Exposing at least a portion of the wafer to light having a wavelength and an intensity, the intensity of light being modulated at a frequency;

e) Detecting a photovoltage induced at the wafer surface in response to the light using a surface photovoltage electrode;

f) Calculating the electrical properties of the wafer from the photovoltage induced at the wafer surface; and

g) Repeating steps d to f for a plurality of light intensity modulation frequencies.

21. The method of claim 20, wherein the electrical property comprises net carrier concentration.

22. The method of claim 20, wherein the net carrier concentration is equal to

Where k is the Boltzmann constant, T is the Kelvin temperature, q is the base charge, W _d Is the depletion layer width, and N ^* _D Is the effective defect density.