HK1113229B - Electronic package having down-set leads and method - Google Patents

Description

Electronic package with down-set pins and method

Technical Field

The present invention relates generally to electronic devices and, more particularly, to a thin profile and small footprint package and method of assembly.

Background

In the miniaturization of portable electronic products, the market for hand-held consumer products is growing. Driven primarily by the cell phone and digital assistant markets, manufacturers of these devices are challenged by ever shrinking data storage formats and the need for PC-like functionality. This challenge places pressure on surface mount component manufacturers to design their products to control the smallest possible area. Doing so allows portable electronic product designers to introduce additional functionality into the device without increasing the overall size of the product. A leadless package with one or more exposed integrated circuit terminals is a type of packaging structure that provides semiconductor manufacturers with the ability to significantly reduce the size of surface mount devices. Such packages include a quad flat no lead (QEN) type design with exposed solder terminals and DirectFET from International rectifier Corporation^TMAnd (6) packaging.

There are manufacturing problems with current surface mount packages having exposed solder terminals. For example, during solder bonding and/or solder reflow steps, the semiconductor die tends to move, which can affect the overall orientation of the bonding pads (e.g., source, emitter, gate, or base electrode bonding pads). This can make surface mount devices less conducive to alignment when they are attached to the next level of a printed circuit board or assembly.

In addition, typical surface mount package manufacturing methods utilize single cavity molding. This method uses a mold cavity with a runner and gate region of the mold compound, which tends to waste mold compound material during the manufacturing process. Also, single cavity molding methods require the manufacturer to use a leadframe with excess leadframe material that will later be removed and discarded as scrap. Such waste materials increase manufacturing costs and may harm the environment.

Applicant's Kim Hwee Tan et al U.S. patent application 2004/0108580 describes a package structure that uses a semiconductor connected to a single flip-chip bump of a recessed leadframe. Tan further describes a fully packaged structure as well as a structure with an exposed die backside for thermal enhancement. Tan uses a grinding process to remove the encapsulation material to provide an exposed die backside. One advantage of the Tan architecture is that it uses a flip-chip (flip-chip) interconnect scheme. This scheme requires an Under Bump Metallurgy (UBM) and a solder Bump plating process (solder Bump plating), which increases the cost of manufacturing the chip. UBM refers to a multi-layer metal layer that provides an interface between bond pads and solder bumps located on a chip, and is typically composed of three separate layers. In addition, the solder bumps may cause stress problems on the chip and/or package structure, which may lead to quality and reliability issues. In addition, the grinding process of Tan can damage semiconductor chips and/or packages, which can also lead to quality and reliability issues.

Disclosure of Invention

Accordingly, there is a need for an improved electronic package structure and method that seeks to address, among other things, die alignment issues that reduce material waste. In addition, this is an advantageous structure and method that supports the design of multi-chip arrangements, flexible interconnect or routing schemes, and chips with solderable, bumpless, or non-flip-chip top metal structures.

The present invention provides a package structure, comprising: an electronic chip having a first bonding surface with a first electrode and a second bonding surface opposite the first bonding surface, wherein the electronic chip is bumpless; and a first lower conductive pin having a first base portion and a first support, wherein the first support is formed as part of the first base portion, and wherein the first support has a bonded area corresponding to a first electrode area, wherein the bonded area is smaller than a first electrode, and wherein the first support is connected to the first electrode.

The present invention also provides an electronic package structure, comprising: a first lower conductive pin including a first pad portion and a first base portion having a first bump standoff; a second down-set conductive pin including a second pad portion and a second base portion; a first electronic chip having first and second contacts on a first surface, wherein the first contact is connected to the first bump support; and first connecting means connecting the second base portion to the second contact.

The present invention also provides a method of forming an electronic package comprising the steps of: a leadframe having first and second down-set conductive leads is provided, wherein the first and second down-set conductive leads include a base portion, and wherein the base portion of the first down-set conductive lead has a first bump standoff. Bonding an electronic chip to the leadframe, wherein the electronic chip includes a first contact and a second contact, and wherein the first contact is connected to the first bump support; and connecting the second contact to the second base portion.

Drawings

FIG. 1A illustrates a cross-sectional view of a package structure according to the present invention;

FIG. 1B illustrates a cross-sectional view of a package structure according to another embodiment of the invention;

FIG. 2 illustrates a cross-sectional view of the plurality of package structures of FIG. 1A fabricated using a preferred molding process in accordance with the present invention;

FIG. 3 illustrates a cross-sectional view of an alternative package structure embodiment in accordance with the present invention;

fig. 4 illustrates a portion of a lead frame structure and a chip of a package structure according to fig. 1A and 1B;

fig. 5 illustrates a bottom view of the package structure of fig. 1A incorporating the lead frame structure of fig. 4;

fig. 6 illustrates a portion of an alternative lead frame structure and chip in accordance with the present invention;

fig. 7 illustrates a bottom view of a package structure incorporating the lead frame structure and chip of fig. 6;

FIG. 8 illustrates a lead frame structure and chips for a multi-chip package structure in accordance with the present invention;

fig. 9 illustrates a bottom view of a package structure incorporating the lead frame structure and chip of fig. 8;

FIG. 10 illustrates an alternative leadframe structure and chip for a multi-chip package structure in accordance with the present invention;

fig. 11 illustrates a bottom view of a package structure incorporating the lead frame structure and chip of fig. 10;

FIG. 12 illustrates a cross-sectional view of a package structure according to another embodiment of the invention;

fig. 13 illustrates a cross-sectional view of a package structure according to yet another embodiment of the invention.

Detailed Description

For ease of understanding, the elements in the drawings are not necessarily drawn to scale, and like element numbers are appropriate throughout the various drawings. Although the present invention is described with an QEN embodiment having exposed solder terminals, those skilled in the art will recognize that the present invention is also applicable to other package types.

Fig. 1A shows a cross-sectional view of a package structure, a leadless package structure, an under-packaged device, or QEN package structure 10, according to an embodiment of the invention. The package structure 10 includes a lead frame, down-set lead frame or conductive substrate 11 that is stamped and formed from a thin sheet of metal such as copper. Alternatively, the lead frame 11 includes a copper alloy (e.g., TOMAC4, TOMAC5, 2 ZFOC, or CDA194), a copper plated iron/nickel alloy (copper plated alloy 42), plated aluminum, plated plastic, or the like. Plating materials include copper, silver, multi-layer plating such as nickel-palladium, and gold. In one exemplary embodiment, the leadframe 11 is formed of copper having a thickness 13 of about 15 to about 50(15-50) microns.

Lead frame 11 also includes recessed or down set portions or conductive leads 14 and 16. Down set leads 14 and 16 include a foot or pad portion 18 and 19, respectively, for connecting package 10 to a next level of circuit board or assembly. Down set leads 14 and 16 also include intermediate connection or solder tail portions 22 and 23, respectively, and support top, base or chip connection portions 26 and 27, respectively. Sole portion 18 forms an angle 36 with intermediate portion 22. In an exemplary embodiment, the angle 36 is about 90 degrees. Alternatively, angle 36 is greater or less than 90 degrees. In an exemplary embodiment, sole portion 19 has a similar orientation as fillet portion 23. Base portions 26 and 27 include projections, raised standoffs, die attach portions, connecting devices, or posts 31 and 32, respectively. The supports 31 and 32 are used to couple, connect or bond to an electronic or semiconductor chip 34 and are formed using, for example, conventional masking and etching techniques. Other methods of forming the brackets 31 and 32 include stud bumping, electroplating and coining to form the indented features. In addition, wire bond ball formation (wire bond ball formation) and wire shear (wire trim) are used to form the supports 31 and 32.

Semiconductor chip 34 includes power MOSFET devices, bipolar transistors, insulated gate bipolar transistors, silicon controlled rectifiers, diodes, analog or digital integrated circuits, sensors, passive components, or other electronic devices. The semiconductor chip 34 includes a first bonding surface 43 and a second bonding surface or bonding end 44 opposite the first bonding surface. In the illustrated embodiment, semiconductor chip 34 is a power transistor that includes a control electrode or contact 28, and a first or primary current carrying electrode or contact 29 formed on a first bonding surface 43. Each of the brackets 31 and 32 has a bonding area corresponding to the area of the contacts 28 and 29 so that the brackets 31 and 32 may have different sizes or surface areas or shapes to properly mate or connect with the contacts 28 and 29.

In a preferred embodiment, contacts 28 and 29 comprise a solderable metal such as TiNiAg, CrNiAu or the like. Contacts 28 and 29 are connected to supports 31 and 32 using solder die attach (solder die attach) and/or conductive epoxy die attach materials. According to the invention, the supports 31 and 32 provide a smaller or better contact area, as well as a self-centering effect, compared to the flat and larger contact area structures of the prior art. This reduces rotation of the semiconductor chip 34 during the die bonding process, thereby reducing the offset problem.

Semiconductor chip 34 also includes a second current carrying electrode 37, which in this embodiment is formed on the back or bottom surface of semiconductor chip 34. In package 10, current carrying electrode 37 is an exposed terminal adapted to be directly bonded or adhered to a bond pad on a next level component. In a preferred embodiment, current carrying electrode 37 comprises a solderable metal layer such as TiNiAg, CrNiAu or the like that is bonded to the next level of assembly with solder or another die attach layer.

Package 10 also includes an optional molded encapsulation or protective layer 39 that covers at least a portion of semiconductor chip 34 and portions of underlying semiconductor leads 14 and 16. In the embodiment shown, solder bottom portions 18 and 19 have exposed surfaces to couple or connect to the next level of assembly. This can be accomplished, for example, by placing current carrying electrode 37 and portions 18 and 19 of lead frame 11 against the surfaces of the mold cavity during the molding process to prevent mold compound from covering these surfaces. This method is advantageous over the grinding process because it eliminates the additional process steps while avoiding the reliability problems associated therewith.

The encapsulation layer 39 comprises an epoxy mold compound such as the G770 mold compound available from Sumitomo Plastics America of santa clara, california. Alternatively, encapsulation layer 39 comprises an enhanced thermal conductivity mold compound, such as the CEL9000 series mold compound available from Hitachi Chemical of santa clara, california.

Fig. 1B shows a cross-sectional view of an under-packaging structure 20 according to another embodiment of the invention. Package structure 20 is similar to package structure 10 except that encapsulation layer 39 is not used. Package 20 is suitable for very light weight and thin profile applications. After the package 20 is bonded to the next level of assembly, a conformal passivation layer (e.g., an epoxy or urethane coating) may be applied over the package for additional protection.

Fig. 2 shows a cross-sectional view of a plurality 100 of the packages 10 of fig. 1, according to a preferred overmolding process for forming the packages 10. A plurality 100 of packages 10 are formed using an array 111 of down-set leadframes 11 and an overmolding process. In the overmolding process, an array 111 of lead frames 11 is molded with a continuous layer 139 of molding compound and the molded structure is singulated, such as along dashed lines 1001, into individual packages 10 using sawing, dicing or other separation techniques. This method is preferred over single cavity molding because it reduces the use of mold compound material and reduces the amount of lead frame material consumed.

Fig. 3 shows an enlarged cross-sectional view of an underlying package 30 according to another embodiment of the invention. In this embodiment, a conductive plug or plate 41 is connected to the electrode 37, which is used for connection to the next level of assembly. In an exemplary embodiment, the plate 41 comprises copper, a copper alloy, or a material similar to that used for the lead frame 11. In addition, the illustrated undulating or non-planar down-set portion 116 is connected to the contacts 29 of the semiconductor chip 34 and has a plurality of standoffs 32. In an exemplary embodiment, the undulating down-set section 116 includes an undulating middle section 123 and an undulating base section 127. In some applications, undulating down portion 116 is preferred because it places a portion of the down conductive leads near the outer surface of package 30, which helps to enhance or improve the transfer or dissipation of heat generated by the current carrying electrode. In alternative embodiments, only the middle or base portion of the down-set portion 116 is undulating. It should be understood that the undulating downset 116 and/or conductive plate 41 may be used with the package 20 of fig. 1B and the embodiments described below.

Fig. 4 shows a portion of an array 1011 of down-set leadframes 11 according to the present invention after the first semiconductor chip 34 is attached, which is suitable for manufacturing packages 10 and 20. The semiconductor chip 34 is connected to the supports 31 and 32 using the above-described materials. Although not shown, a second or additional semiconductor chip 34 is bonded to the second supports 31 and 32 before the packaging step and/or the separation step. Fig. 5 shows a bottom view of package 10 of fig. 1A after forming optional encapsulation layer 39, and shows pads 18 and 19 and exposed portions of electrodes 37. Alternatively, according to the embodiment shown in fig. 3, the element 37 may be replaced by a surface of the plate 41.

Fig. 6 shows a portion of an alternative embodiment of an underlying package 100 that includes a lead frame 211, the lead frame 211 including underlying conductive leads 14 and 16. In this embodiment, lead frame 211 includes additional down-set portions or conductive leads 214 that include a solder bottom or pad portion 221, an intermediate connection or leg portion 222, and a supporting top, bonding portion, platform portion, or die attach portion 228. Also, fillet portion 222 has a height or length 225 that is less than height or length 25 of fillet portion 23, which allows an adhesive structure, a connecting device, a clip or a strip 241 to be used to connect semiconductor chip 34 to base portion 228, as shown. The strap 241 is connected to the semiconductor chip 34 and the base portion 228 using a material such as solder die attach (solder die attach). The strap 241 comprises a material such as copper, copper alloy, electroplated copper, or the like. In an alternative embodiment, heights 25 and 225 are the same, and a bent strip piece (bent clip) is used to connect semiconductor chip 34 to base portion 228.

In the embodiment of fig. 6, the height 25 is greater than the combined thickness of the supports 31 and 32, the semiconductor chip 34 and the chip 241, so that after molding, the encapsulation layer 39 covers the tape blade 241. Fig. 7 shows a bottom view of the package structure 100A after the optional encapsulation layer 39 is formed, and after the separation step. Bottom-bonding portions 18, 19 and 221 of package 100A include exposed surfaces for connection to the next level of assembly as shown. The embodiment of fig. 6 is preferred if planarization of electrode 37 is an issue.

Fig. 8 illustrates a portion of an underlying multi-chip package 300 in accordance with the present invention. As shown in fig. 4, the lead frame 311 includes the lead frame portion 11 and the semiconductor chip 34 except for the common pad portion 319. The lead frame 311 also includes additional recessed or down-set portions or conductive leads 314 and 316 for supporting the same or different semiconductor chips 334. For example, the semiconductor chip 334 includes diodes, sensors, passive components, integrated circuits, or the like. The down-set conductive leads 316 include a standoff 332 in which a semiconductor chip 334 is bonded, such as with a solder die attach layer. In this embodiment, down-set semiconductor leads 314 are partially down-set, or higher than other base portions, as shown to accommodate chip 341, which connects semiconductor chip 334 to base portion 326. Down-set conductive lead 314 also includes a foot or pad portion 321 for connection to the next level of assembly. Solder tail portion 322 connects solder pad portion 321 to base portion 326. In an alternative embodiment, chip 341 may be omitted and, in addition, the bottom or back surface 336 of semiconductor chip 334 is directly exposed for connection to the next level of assembly. It should be understood that the conductive plate 41 may be used for connection.

Fig. 9 shows a bottom view of an underlying multi-chip package 300 after a molding step to form optional encapsulation layer 39, and after a separation step to show package outline and exemplary locations of foot portions 18, 319, and 321 and electrodes 37.

Fig. 10 shows a portion of an alternative down-set multi-chip package 400 including a lead frame 411 in accordance with the present invention. The embodiment of fig. 10 is similar to that of fig. 9 except that the lead frame includes additional down-set conductive leads 414 that support a conductive chip 441 that connects electrode 37 of semiconductor chip 34 to base portion 426. This is similar to the embodiment described in connection with fig. 6. In this embodiment, down-set conductive leads 414 are partially down-set, or higher than other base portions, to accommodate chip 441. In an alternative embodiment, down-set conductive lead 414 is down-set to the same extent as the other down-set portions, and bent strips are used to connect the electrodes to down-set conductive lead 414. Down-set conductive lead 414 includes a bottom or pad portion 421 for connection to a next level of assembly.

Fig. 11 shows a bottom view of an underlying multi-chip package 400A after a molding step to form package layer 39, and after a separation step to show package outline and exemplary locations of exposed surfaces of pad portions 18, 319, 321, and 421. It should be understood that the size of the pads 18, 19, 319, 321, and 421 shown in fig. 5, 7, and 9 is merely exemplary, and that this size may be increased or decreased depending on design and application constraints.

Fig. 12 shows a cross-sectional view of an under-packaging structure 40 according to yet another embodiment of the invention. Package 40 is similar to packages 10, 30, 100A, 300A, and 400A except that encapsulation layer 139 is thinner to expose an upper, outer, or major surface of base portion 127. This can be accomplished, for example, by holding base portion 127 against the surface of the mold cavity during the molding process to prevent mold compound from covering base portion 127.

In the embodiment shown, the outer surface of the base portion 26 is also exposed, but this is not required. By exposing the outer surface of the base portion 127, heat dissipation is improved. Also, as shown in FIG. 12, base portion 127 is longer than base portion 27 to provide more surface to dissipate heat. Optionally, the heat spreader is directly connected to the base portion 127 with a conductive epoxy. In addition, thermally conductive and electrically insulating layer 63 is used to connect the heat sink to package 40. It should be understood that the embodiment of fig. 12 is applicable to packages 10, 30, 100A, 300A, and 400A, and combinations thereof.

Fig. 13 shows a cross-sectional view of a package structure 500 according to yet another embodiment of the invention. The package structure is similar to package structures 10, 30, 100A, 300A, and 400A, except that in this embodiment, leadframe 511 includes down-set conductive leads 514 having pedestals or platform portions 526 that are spaced from contacts 528 of conductive chip 34. That is, the base portion 526 is formed without a bracket. This allows other connection devices, such as wire bonds 541, to be used to connect the contacts 528 to the base portion 526. Wire bonds 541 are formed using conventional wire bonding techniques. In this embodiment, the contacts 528 comprise a conductive material suitable for wire bonding, such as aluminum, an aluminum alloy, or the like. In alternative embodiments, wire bonds 541 are replaced with tape bonds or tape tabs. It should be understood that the embodiment of fig. 13 is suitable for packaging structures 10, 20, 30, 100A, 300A or combinations thereof.

It is therefore apparent that there has been provided, in accordance with the present invention, a structure and a method of forming an improved electronic package. This package incorporates an underlying lead frame with the chip oriented such that its primary current carrying electrodes are connected to a support on the underlying lead frame. The support reduces chip rotation during solder die attach. In one embodiment, the chip includes control electrodes connected to other supports on the down-set lead frame. In a preferred embodiment, the current carrying electrode comprises a solderable metal. The standoff and solderable metal provide a more reliable and cost-effective package structure than prior art devices that utilize flip-chip and UBM interconnection schemes.

In another embodiment, wire bonds are used to connect the control electrodes to the leadframe. In yet another embodiment, the lead frame includes an underlying conductive lead having an undulating profile to increase heat dissipation. In yet another embodiment, the encapsulation layer is thinned to provide an exposed base portion that improves heat dissipation. The structure according to the invention is also suitable for multi-chip and multi-interconnect configurations. An overmolding process is used in the preferred method of forming the package of the present invention, which reduces the use of mold compound and the amount of lead frame scrap.

While the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these exemplary embodiments.

Claims (26)

1. A package structure, comprising:

an electronic chip having a first bonding surface with a first electrode and a second bonding surface opposite the first bonding surface, wherein the electronic chip is bumpless; and

a first lower conductive pin having a first base portion and a first support, wherein the first support is formed as part of the first base portion, and wherein the first support has a bonded area corresponding to a first electrode area, wherein the bonded area is smaller than a first electrode, and wherein the first support is connected to the first electrode.

2. The package structure of claim 1, further comprising an encapsulation layer covering at least a portion of the first down conductive pin and at least a portion of the electronic chip.

3. The package structure of claim 2, wherein a surface of the first base portion is exposed.

4. The package structure of claim 2, wherein the first down-set conductive pin comprises a first pad portion, and wherein a portion of the first pad portion and the second bonding side are exposed.

5. The encapsulation structure of claim 2, wherein the encapsulation layer comprises an overmolded encapsulation material.

6. The package structure of claim 1, wherein the first electrode comprises a solderable metal.

7. The package structure of claim 1, wherein at least a portion of the first down conductive pin is undulating.

8. The package structure of claim 1, further comprising a conductive plate connected to the second bonding side.

9. The package structure of claim 1, further comprising a second down-set conductive pin, wherein the second down-set conductive pin comprises a second shelf and a second pad portion, and wherein the electronic chip further comprises a second electrode on the first bonding surface, and wherein the second electrode is connected to the second shelf.

10. The package structure of claim 9, further comprising a third down-set conductive pin, wherein the second bonding surface is connected to the third down-set conductive pin with an adhesive structure.

11. The package structure of claim 10 wherein the adhesive structure comprises a tape tab.

12. The package structure of claim 1, further comprising a second down-set conductive pin separate from the electronic chip, and wherein a connecting device connects the second down-set conductive pin to a second electrode on the electronic chip.

13. The package structure of claim 12, wherein the connection device comprises a wire bond.

14. An electronic package structure, comprising:

a first lower conductive pin including a first pad portion and a first base portion having a first bump standoff;

a second down-set conductive pin including a second pad portion and a second base portion;

a first electronic chip having first and second contacts on a first surface, wherein the first contact is connected to the first bump support; and

first connecting means connecting the second base portion to the second contact.

15. The electronic package structure of claim 14, further comprising an encapsulation layer covering at least a portion of the first down conductive pin and at least a portion of the first electronic chip.

16. The electronic package structure of claim 15, wherein a surface of the first base portion is exposed.

17. The electronic package structure of claim 14, wherein the first connector device comprises a second bump standoff formed on the second base portion.

18. The electronic package structure of claim 14, wherein the first connector device comprises a wire bond.

19. The electronic package structure of claim 14, further comprising:

a third down-set conductive pin comprising a third pad portion and a third base portion having a third bump support;

a fourth down-set conductive pin comprising a fourth pad portion and a fourth base portion;

a second electronic chip having a third contact connected to the third bump support; and

a second connecting device connecting the second electronic chip to the fourth down-set conductive pin.

20. The electronic package structure of claim 14, further comprising:

a third down-set conductive pin comprising a third pad portion and a third base portion; and

a second connection device connecting the second surface of the first electronic chip to the third base portion.

21. The electronic package structure of claim 20, wherein the second connector device comprises a tape tab.

22. The electronic package structure of claim 14, wherein a portion of the first down conductive pin is undulating.

23. A method of forming an electronic package comprising the steps of:

providing a lead frame having first and second down-set conductive leads, wherein the first and second down-set conductive leads include a base portion, and wherein the base portion of the first down-set conductive lead has a first raised support

Bonding an electronic chip to the leadframe, wherein the electronic chip includes a first contact and a second contact, and wherein the first contact is connected to the first bump support; and

connecting the second contact to the second base portion.

24. The method of claim 23, further comprising the step of encapsulating at least a portion of the first and second down-set conductive leads and at least a portion of the electronic chip.

25. The method of claim 23, wherein the step of connecting the second contact to the second base portion comprises bonding the second contact to a second raised pedestal formed on the second base portion.

26. The method of claim 23, wherein the step of connecting the second contact to the second base portion comprises connecting the second contact to the second base portion with a wire bond.