HK1112764A - Switch matrix system with plural bus arbitrations per cycle via higher-frequency arbiter - Google Patents

Abstract

An arbiter in a switch matrix system arbitrates multiple bus transaction requests in a single bus frequency clock cycle, by operating at a frequency greater than the bus frequency. This allows for two or more arbitration operations in a single bus frequency clock cycle with one instance of arbitration logic. The arbiter may arbitrate for two or more slave devices, or may arbitrate multiple master device requests directed to the same slave device. The arbiter frequency may be variable, and may be predicted based on, e.g., prior bus activity. If only one bus transaction request is pending, the arbiter frequency may equal the bus frequency. The results of an earlier arbitration decision may be utilized to more intelligently make subsequent arbitration decisions in the same bus frequency clock cycle.

Description

Switch matrix system with multiple bus arbitration per cycle through higher frequency arbiter

Technical Field

The present invention relates generally to the field of electronic data processing, and in particular to a high performance bus arbitration system and method.

Background

Data transfer between functional units is a common operation of computer systems. Transferring programs from disk to memory to processor, sending data from graphics engine to frame buffer to video card, and sending input from keyboard or mouse to processor are all common examples of data transfers within a computer system.

FIG. 1 depicts a simplified diagram of a system bus architecture, generally indicated by the numeral 10. A system bus 12 interconnects the various system units, the system bus 12 being divisible into address channels, data channels, control channels, and the like. A master device, such as the CPU 14 or DMA engine 16, directs data transfers across the bus 12, referred to herein as bus transactions, to or from a slave device, such as the memory 18 and/or the input/output circuits 20. When two or more independent master devices 14, 16 are connected to the bus 12, their access to the bus is controlled by the arbiter 22.

As is known in the art, one or more master devices 14, 16 assert a bus request to the arbiter 22. The arbiter 22 monitors activity on the bus 12 and when the bus 12 becomes available, the arbiter 22 sends a bus grant to one of the requesting masters 14, 16. The granted master 14, 16 may then initiate a transaction on the bus 12, such as a read or write cycle directed to one or more slave devices 18, 20.

While the system bus 10 works well in connecting several master devices 14, 16 with multiple slave devices 18, 20, it imposes the limitation that only one master device 14, 16 can access a slave device 18, 20 at a time. In a high performance processor, it is often the case that two or more master devices 14, 16 may in fact wish to access one or more slave devices 18, 20 independently.

Fig. 2 depicts a high performance data transfer system, generally indicated by reference numeral 30. A switch matrix 32 (also referred to as a crossbar switch) interconnects a plurality of master devices 34 to a plurality of slave devices 36, where in the most general case any master device can access any slave device. For example, FIG. 2 depicts master 1 accessing slave 1, and simultaneously master 2 accessing slave 0. In some implementations, one or more of the slave devices 36 may include two or more address buses, allowing more than one master device 34 to access simultaneously.

For a bus system 30 that includes n master devices 34 and a single slave device 36, only one arbiter is necessary within the switch matrix 32 to arbitrate competing accesses to the slave device 36. For an n x m crossbar system 30 with n master devices 34 and m slave devices 36, one to m arbiters may be implemented. The highest performance will be achieved using m arbiters, each dedicated to one slave device 36. If there are fewer than m arbiters (that is, at least one arbiter performs arbitration for two or more slave devices 36), performance will be degraded because each arbiter can arbitrate for only one slave device 36 at a time or within any given bus cycle. However, implementing many arbiters consumes chip area, complicates routing, and increases power consumption.

Disclosure of Invention

In accordance with one or more embodiments, an arbiter in a bus arbitrates multiple bus transaction requests in a single bus frequency clock cycle by operating at an arbiter frequency that is greater than the bus frequency.

In one embodiment, a system includes a bus operating at a bus frequency. At least one master device is connected to the bus and requests bus transactions. At least one slave device is connected to the bus and engages in bus transactions. The arbiter arbitrates more than one transaction request in a single bus frequency clock cycle by operating at an arbiter frequency that is greater than the bus frequency.

In another embodiment, a method of arbitrating a plurality of bus transaction requests in a bus operating at a bus frequency comprises: operating the arbiter at an arbiter frequency greater than the bus frequency; and arbitrates multiple bus transaction requests in one bus frequency clock cycle.

Drawings

FIG. 1 is a functional block diagram of a prior art computer bus.

Fig. 2 is a functional block diagram of a crossbar bus.

FIG. 3 is a timing diagram of a crossbar bus arbitration cycle.

Detailed Description

Fig. 3 depicts a timing diagram of a representative bus transaction request and arbitration in a crossbar matrix system 30. In this example, the bus operates at a bus frequency of 100MHz with a 10 nanosecond clock cycle, and the two slave devices A and B share a single arbiter. The two slave devices M0, M1 issue requests for bus transactions directed to both slave devices a and B simultaneously in bus cycle 1.

In a system 30 with a conventional arbiter, slave a will arbitrate in bus cycle 2 and slave B in bus cycle 3 as indicated by the dashed lines. The arbiter will issue a request to slave a in bus cycle 3 and a request to slave B in bus cycle 4 as indicated by the dashed lines. The slave devices will acknowledge in bus cycles 4 and 5, respectively, and the master devices M0 and M1 may proceed with the bus transaction as each respective slave acknowledge is received.

In one or more embodiments, multiple arbitration cycles are performed in one bus frequency clock cycle by operating the arbiter at an arbiter frequency greater than the bus frequency. As depicted in the solid line signal of fig. 3, the arbiter performs arbitration for both slave devices a and B in bus cycle 2 by running at an arbiter frequency that is twice the bus frequency (in this embodiment). Thus, the arbiter is able to issue requests to both slave devices a and B in bus cycle 3, and both slave devices a and B may acknowledge in bus cycle 4. Both M0 and M1 may begin bus transactions in bus cycle 5, where bus cycle 5 is a full cycle earlier than above in the case of M1, and depicted in dashed lines in fig. 3, where the arbiter operates at the bus frequency. Similarly, by running the arbiter at 3, 4, or other multiples of the bus frequency, requests directed to three, four, or more slaves may be arbitrated in a single bus frequency clock cycle, allowing individual bus transactions to proceed in parallel.

In these embodiments, a single instance of arbiter may arbitrate multiple bus transaction requests for multiple slaves in parallel, without requiring duplicate instances of arbitration logic. As used herein, a single arbiter instance comprises the logic and configuration information necessary to perform arbitration for one or more bus transaction requests directed to a slave device 36. By operating the arbiter at an arbiter frequency higher than the bus frequency, multiple bus transaction requests may be arbitrated in a single bus frequency clock cycle using only one instance of arbitration logic, rather than duplicating arbitration logic for each slave device 36. This saves silicon area, reduces routing complexity and saves power at the expense of generating and routing at least two clock signals having different frequencies.

In most embodiments, the arbiter frequency will be a multiple of the bus frequency, but not necessarily 2n times (e.g., the arbiter frequency may be 3 or 5 times the bus frequency). This allows a maximum amount of time to be devoted to each arbitration operation. However, the arbiter frequency being an exact multiple of the bus frequency is not limiting of the invention disclosed herein. In general, the arbiter frequency may only be sufficiently greater than the bus frequency to allow arbitration of at least two bus transaction requests in a single bus frequency clock cycle.

The timing diagram of FIG. 3 depicts two master devices M0, M1 simultaneously requesting bus transactions directed to two different slave devices 36 sharing a single present arbiter. The same timing relationship occurs if a single master device 34 simultaneously requests bus transactions directed to two different slave devices 36 that share an arbiter. For example, the master device 34 may direct read transactions to one slave device 36 and write transactions to another slave device. Alternatively, the master device 34 may know that the slave devices 36 have different response latencies, and that simultaneous requests for similar bus transactions will not cause a bus conflict when the transaction occurs.

In another embodiment, two or more master devices 34 may simultaneously request bus transactions directed to the same slave device 36. If the slave device 36 has sufficient address bus capacity, it may be able to engage in two or more bus transactions simultaneously. One example of a high address bus capacity is a shared channel bus architecture. To save silicon area and reduce routing complexity, the address channel functionality of the bus 30 may be merged with the data transfer channel. For example, the address bus may share a channel with the write data bus. If the system has a 32-bit real (hardware) address space and a 128-bit write data bus, multiplexing the address and write data functionality into a single 128-bit bus channel allows up to four separate addresses to be transferred during one address transfer cycle. In this case, up to four master devices 34 (or less than four if one or more master devices 34 issue multiple bus requests) may request bus transactions and issue addresses during the same cycle, with two or more addresses directed to the same slave device 36. If the slave device 36 has the capability, it may accept all requests and engage in multiple simultaneous bus transactions. In this embodiment, a single arbiter may arbitrate multiple bus transaction requests all directed to the same slave device 36 in a single bus frequency clock cycle by operating at an arbiter frequency greater than the bus frequency.

In one or more embodiments, the arbiter frequency may be variable. The arbiter frequency may be equal to the bus frequency when only one bus transaction request is outstanding. In this embodiment, the arbiter performs one arbitration per bus frequency clock cycle, as in conventional arbiters. This saves power over operating the arbiter at a higher frequency than the bus, where operating the arbiter at a higher frequency than the bus does not provide performance benefits.

In one embodiment, a prediction is made of the arbiter frequency. The prediction may be based on recent bus activity, for example. During periods when one or more master devices 34 are issuing multiple bus transaction requests, the arbiter frequency may be increased for the possibility of multiple arbitrations, whether from different master devices 34 to the same slave device 36 or to different slave devices 36 sharing one arbiter. For example, in one embodiment, the number of bus transaction requests pending during the first n bus cycles may be stored and examined to predict the arbitration frequency for one or more subsequent bus cycles. In another embodiment, the fact that multiple pending bus transaction requests may increment a saturation counter, as is well known in processor branch prediction implementations. Extended cycles without multiple pending bus transaction requests may decrement the counter. The MSB of the counter may be used as a prediction of whether a higher arbiter frequency should be used. Those skilled in the art will recognize that various techniques may be used to predict the arbiter frequency.

In one embodiment, the arbiter can take advantage of the serial nature of sequential arbitration to improve the "intelligence" of "subsequent" arbitration by taking into account the results of previous arbitration. For example, if a first arbitration operation grants a master device 34 a write request to a slave device 36, subsequent arbitrations performed during the same bus frequency clock cycle may deny granting another master device 34 a write request to the same slave device 36 (which would otherwise be granted) to prevent write data conflicts from occurring at the slave devices 36.

In one embodiment, the arbiter may include a pending bus status register, such as allocating one bit to each possible combination of read and write transactions from each master device 34 to each slave device 36. Early arbitration decisions made by the arbiter can set the relevant pending bus state bits, and logic in the arbiter can utilize the results of these arbitration decisions (e.g., updated pending bus states) to make subsequent arbitration decisions more intelligently within the same bus frequency clock cycle. This can achieve higher performance (performance improvement beyond multiple arbitrations per bus frequency clock cycle) by optimizing bus traffic and avoiding conflicts and bottlenecks.

By performing multiple bus transaction request arbitration in a single bus frequency clock cycle by running the arbiter at an arbiter frequency higher than the bus frequency, performance can be improved by allowing parallel arbitration without the expense of having multiple instances of arbiter logic. The serial nature of multiple arbitrations allows for more intelligent arbitration decisions because later arbitration operations take as input the operation of the previous arbitration decision. To conserve power, the arbitration frequency may be throttled back to the bus frequency when there are no multiple requests outstanding. To balance power savings during low bus utilization with improved performance during high bus utilization, the arbiter frequency may be predicted.

Although the present invention has been described herein with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications, and other embodiments are possible within the broad scope of the present invention, and accordingly, all variations, modifications and embodiments are to be regarded as being within the scope of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

Claims (17)

1. A system, comprising:

a bus operating at a bus frequency;

at least one master device connected to the bus and requesting bus transactions;

at least one slave device connected to the bus and engaged in bus transactions; and

an arbiter that arbitrates more than one transaction request in a single bus frequency clock cycle by operating at an arbiter frequency that is greater than the bus frequency.

2. The method of claim 1, wherein the arbiter comprises a single instance of arbitration logic.

3. The method of claim 1, wherein the arbiter frequency is a multiple of the bus frequency.

4. The method of claim 1, wherein:

the slave device includes at least two address paths;

two master devices simultaneously requesting bus transactions from the slave devices; and is

The arbiter issues grants to the two masters in a single bus frequency clock cycle.

5. The method of claim 1, wherein:

the master device requesting bus transactions from two slave devices simultaneously; and is

The arbiter issues grants to the master device for the two slave devices in a single bus frequency bus cycle.

6. The method of claim 1, wherein the arbiter frequency is equal to the bus frequency if no more than one bus transaction request is asserted.

7. The method of claim 1, wherein the arbiter frequency is predicted in response to bus transaction request activity.

8. The method of claim 1, wherein the arbiter arbitrates at least first and second bus transaction requests sequentially in a single bus frequency clock cycle, and wherein arbitration of the second request includes a result of arbitration of the first request.

9. The method of claim 8, wherein the arbiter maintains a state of pending bus transactions.

10. A method of arbitrating a plurality of bus transaction requests in a bus operating at a bus frequency, comprising:

operating the arbiter at an arbiter frequency greater than the bus frequency, an

Multiple bus transaction requests are arbitrated in one bus frequency clock cycle.

11. The method of claim 10, wherein the arbiter frequency is a multiple of the bus frequency.

12. The method of claim 11, wherein the arbiter arbitrates bus transaction requests in each arbiter frequency clock cycle.

13. The method of claim 12, wherein the arbiter sequentially in a single bus frequency clock cycle

At least first and second bus transaction requests are arbitrated, and wherein arbitration for the second request includes a result of arbitration for the first request.

14. The method of claim 13, wherein the arbiter maintains a state of pending bus transactions.

15. The method of claim 10, wherein the arbiter frequency is variable.

16. The method of claim 15, wherein the arbiter frequency is predicted based on bus activity.

17. The method of claim 10, wherein the arbiter frequency is equal to the bus frequency if only one bus request is pending.