HK1111517B - Split thin film capacitor for multiple voltages - Google Patents

Description

Split thin film capacitor for multiple voltages

Technical Field

Various embodiments described herein relate to capacitor designs, typically including thin film capacitors for use with electronic devices such as integrated circuits.

Background

Many electronic devices have local instantaneous current requirements that are not always properly supplied by the power supply, resulting in local voltage level shifts and possibly erroneous signal propagation. The use of capacitors in local power filtering applications for electrical and electronic devices is known. However, as the clock cycle rate in electronic devices continues to increase as the devices become smaller, particularly in integrated circuit devices such as microprocessors and memories, the need for tightly coupled capacitors increases. In addition, as electronic devices become smaller, operating voltages need to be reduced in certain portions of the device to keep the electric field below a critical level where device reliability is reduced. One way to reduce the operating voltage while maintaining the performance of an electronic device in the critical reliability portion of the device is to operate with two power supplies having different power supply voltage levels. For example, the internal logic portion of an integrated circuit (i.e., IC) may use transistors of minimum size in order to obtain the fastest possible operating speed, and thus may require a low voltage power supply, while input and output (i.e., I/O) drivers at the periphery of the IC may use larger and more powerful transistors that require a high voltage power supply and that can withstand higher voltage levels than small logic transistors can tolerate without degrading reliability. As a result of the two supply voltage scenario just discussed, there may be a need for two different tightly coupled capacitors associated with the same integrated circuit chip. The use of two different capacitors with different power supply levels may present space issues for electronic devices, for example in IC packages, and thus there is a need for a single capacitor with multi-voltage level capability. There is also a need for a capacitor having two independent power supplies to isolate noise.

Drawings

FIG. 1 is a side view of an illustrative embodiment of the present invention;

FIG. 2 is a top and side view of another exemplary embodiment of the present invention;

FIG. 3 is a top and side view of other exemplary embodiments of the present invention;

FIG. 4 is a side view of a component using an embodiment of the present invention;

FIG. 5 is a block diagram of a system using an embodiment of the present invention.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration the principles of the invention, specific embodiments of a means in which the invention may be best practiced. In the drawings, like numerals describe substantially similar components throughout the various views of the embodiments. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments of the disclosed principles may be utilized and structural and material changes may be made to the embodiments disclosed herein without departing from the spirit and principles of the present invention.

The terms "high" and "low" as used herein for dielectric constants (i.e., high-k and low-k) are relative terms referring to materials having dielectric constants relative to standard dielectric materials such as silicon dioxide and silicon nitride. When the terms "high" and "low" are used herein for voltages, they refer to relative values in the supply voltage values, and the term "ground" refers to the reference voltage supply. The value of the "high" voltage will vary depending on various factors in the electrical system in which embodiments may be implemented, such as the process and dimensions of the integrated circuit found in the electrical system, and other such differences. For example, as ICs get smaller, they become more sensitive to high voltage degradation of the gate oxide of MOSFETs and junction breakdown of bipolar junction transistors, and often lower operating voltages to increase device lifetime.

Referring to fig. 1, a side view of the internal structure of a thin film capacitor is shown having a substrate 100 typically made of a standard or low value dielectric material (i.e., low-k) and having a second dielectric layer 102 on the top surface, the second dielectric layer 102 typically being made of a low-k material to reduce signal crosstalk in many electrical paths and multiple signal lines through the substrate in various directions, such as a straight direction from the top surface to the bottom surface, side conductors connecting different portions of the device utilizing the top, inner and bottom surfaces and creating external electrical contacts to other electrical devices and a printed circuit board (i.e., PCB). A number of wires and vias 104 that form the top plate of a thin film capacitor (i.e., TFC) and connect the top plate to the back side of substrate 100 are shown in cross-section in this illustrative embodiment. Also shown are a number of wires and vias 106 that form and connect the bottom plate of the TFC buried in the second dielectric layer 102 to the back side of the substrate 100. The two capacitor plates 104 and 106 are separated by a high dielectric value (i.e., high-k) dielectric material 108 to form a high value capacitor. Any high-k material may be used for layer 108. Illustrative examples of high-k materials include barium strontium titanate, barium titanate, or strontium titanate, which is useful if dielectric material 100 is a tape cast ceramic. Numerous other high-k dielectric materials are known to those skilled in the art and may be used in the practice of this embodiment as required by the materials and processes used in the particular application.

The illustrative embodiment shown in fig. 1 may be clearly extended to include vertical electrical leads such as 110 to connect portions of the top surface to external electronic devices using contact points on the top or bottom surface, and to connect portions of the TFC at one location on the substrate 100 to other locations. For example, all of the upper capacitor electrode plate portions 104 may be connected together to form one large capacitor by utilizing horizontal electrical conductors that are bottom, top, or buried in the substrate 100 by methods known to those skilled in the art. The joined top plate electrode lines may then be connected to the vertical conductors 110 and thus to an external power source via contact points on the top or bottom surface. Alternatively, the bonded top plate electrode lines may be connected to external electronic devices through connection pads located on the bottom surface of the substrate 100 without the need for the vertical connectors 110. In a similar manner, the buried bottom capacitor plates 106 may be connected together to form a large capacitor by similar means to those described above, and connected to external electronics such as an IC or power supply by connections on the top or bottom surface.

The exemplary embodiment shown in fig. 1 may be extended to include an arrangement in which the structures shown on the top surface of the substrate may also be formed on the bottom surface to provide a capacitor having substantially twice the area and capacity in the same size of the total used area of the electronic device to which the capacitor is attached. It should also be understood that the vertical electrical conductors 110 are not limited to the single row shown around the periphery of the capacitor, but may have multiple rows of vertical connectors and contact points, and may form an area array of connectors to reduce the resistance and inductance of the outgoing and incoming currents. Thus, in the exemplary embodiment shown in fig. 1, each of the upper capacitor plates 104 may be connected to a different voltage supply, while the lower capacitor plates 106 may all be connected to a reference voltage, by means of included electrical conductors such as vertical connectors 110, to provide a reference voltage which may be referred to as a ground voltage. Alternatively, the lower capacitor plate 106 may be connected to a separate reference voltage supply spaced apart from the upper capacitor plate 104 for various reasons such as ground bounce isolation. With this arrangement, a circuit such as an IC may be provided with two different supply voltages, which may be useful when a low voltage level is provided, such as to the internal minimum sized transistor logic of the IC, while a high voltage level is provided to the memory cache or input/output (i.e., I/O) components of the same IC.

In fig. 2, a top view of a thin film capacitor (i.e., TFC) with an upper capacitor plate that is schematically divided into two separate portions is shown at the top of the figure. In this illustrative example, the left side 202 of the capacitor is selected to provide the operating voltage level to the memory cache component of a tightly coupled electronic device, such as an IC mounted directly on top of a TFC. The right side 204 of the illustrative TFC is selected to provide different operating voltage levels to the voltage sensitive logic cores of the IC. Alternatively, the two sides 202 and 204 may separately provide internal IC signals that need to be electrically isolated from each other due to synchronous switching issues or other design reasons.

In the lower detailed side view of fig. 2, the area around the upper capacitor plate spacing is shown. In this illustrative example, the upper capacitor plate is shown as being divided into only two portions, and the lower capacitor plate 208 is shown as a single piece of electrical conductor. The embodiments described herein are obviously not limited to that discussed above with reference to the illustrative example of fig. 1, where the lower capacitor plates are separated. The capacitor is formed on a substrate 210 and the underlying capacitor plate 208 is covered with a high-k dielectric material 206, the dielectric material 206 being shown as continuous in this illustrative example for simplicity. The selection of the dielectric material 206 will depend on the particular application in which the embodiment is used. For example, in the field of low temperature co-fired (co-fired) ceramics, the high k dielectric material may be selected as barium strontium titanate or other similar materials. For simplicity, the high-k dielectric layer 206 is shown as a continuous single layer, but embodiments are not so limited and the high-k dielectric layer may also be broken down into multiple separate portions when most useful for the particular application being implemented.

An illustrative embodiment is shown in fig. 3 with a top view having a region 302 selected to provide a lower power supply voltage level to the smallest sized transistor core logic region of an IC and a region 304 selected to provide a higher, or lower, or different power supply voltage level to the memory cache region of the same IC. In an expanded top view, it is seen that region 302 is arranged in this exemplary embodiment to provide two different lower supply voltage values to different regions of the core area of the IC by virtue of the alternating stripes of capacitor plate conductors above, e.g., stripe 306 having connections to different external power supplies as compared to stripe 308. Because of signal isolation issues, different power supplies may have the same voltage level and be independent of each other, or may provide different voltage levels in response to differences in the operation of the transistors in the respective regions, depending on the specific requirements of the application. The same isolation of power supplies may also occur in the area 304 selected for use by the cache components of the IC. For example, high voltage supply level region 304 may use two different supply voltage levels for cache components and I/O components. I/O components, in the case of what is known as a BiCMOS process, or other I/O type devices, may use bipolar junction transistors as output devices, and thus may require a different power supply level than the cache MOS transistors.

As can be seen in the side view of the illustrative embodiment, the isolated conductor stripes 306 and 308 of the upper capacitor plate 302 are located on a high-k dielectric layer 310, which is shown as a continuous layer in fig. 3 for simplicity. The embodiment should not be limited to the case shown above. The bottom conductor forming lower capacitor plate 312 is shown separated into individual conductor stripes in this illustrative embodiment, each associated with a conductor stripe of upper capacitor plate 302, although an uninterrupted lower capacitor plate with an additional reference voltage supply (e.g., ground) may be a preferred approach in a number of specific applications. The underlying capacitor plate conductor 312 is formed on a substrate 314, as previously disclosed in connection with the description of fig. 1 and 2, the substrate 314 may also have a via conductor, an internal horizontal conductor, and/or another capacitor structure located on the bottom of the substrate 314, as just described.

With this arrangement, the cache area of the IC may be provided with a high supply voltage level capacitor 304, while portions 306 and 308 of the low supply voltage capacitor area 302 are used to provide two different low voltage supply levels to portions of the internal core logic area. By varying the relative size of the stripes 306 to the stripes 308, the amount of capacitance provided to different portions of the lower portion 302 can be easily adjusted to the requirements of a particular application.

An alternative method of controlling the amount of capacitance provided to different portions of the low voltage power supply area 302 or the high voltage power supply area 304 of an IC is shown in the side view at the bottom of fig. 3, which shows an exemplary embodiment with two different high-k dielectric layers 310 and 311. The amount of capacitance provided to different parts of the IC can still be controlled by varying the relative areas of the conductor stripes 306 and 308 as previously described, but with this schematic arrangement, the thickness of the two high-k dielectric layers can also be varied, as shown in the figure, where layer 311 is shown thinner than the other high-k dielectric layer 310, or the material used as the high-k dielectric can be different for the two layers, or a combination of the two approaches can be used as appropriate for the particular application in which the embodiment is implemented.

In addition to the features already discussed, the stacked capacitor arrangement, substrate 314 of the exemplary embodiment shown in fig. 3 may have a vertical via connector, an inner conductor, and a two-sided top and bottom formed capacitor structure as previously discussed with respect to fig. 1 and 2 and with respect to the side-by-side stripe embodiment.

In fig. 4, an illustrative embodiment of a TFC used in a direct mount IC manner is shown. The TFC capacitor 402 is shown with an organic substrate 404 that may be a multilayer printed circuit board and having a capacitor 406 formed on the top and a capacitor 408 formed on the bottom. The capacitor may also be embedded in the substrate. The top and bottom capacitors may be connected in various ways, for example they may be completely isolated from each other and fit into different parts of the mounted IC412, or they may be connected to each other to substantially double the available capacitance, or any combination of connections as required by the particular application to which the TFC is applied.

The bottom surface of the TFC capacitor 402 has a plurality of connection pads that may be connected to external contacts. For example, the illustrative embodiment shows an area array of pins 410 for connecting to a through-hole printed circuit board. Alternative connections may include gull-wing leads for surface mount applications, ball grid arrays, or connector pins such as the full grid socket (i.e., FGS) shown in the figures.

The top surface of the TFC capacitor 402 in this exemplary embodiment has an area array of connection pads that are arranged to receive and solder the packaged IC412 using an array of solder balls 414. Alternative connection methods may include flip-chip mounting of unpackaged silicon chips using plated solder or gold pads, or surface mounting of IC packages with ceramic leads with attached heat sinks.

With this arrangement, the IC412 has short electrical connections from various portions of the TFC 402 to any desired number of different power or reference supply voltage sources. The TFC 402 may also be advantageously used to provide a means for attaching the IC412 to an electronic device using electrical connection pins 410. This arrangement may have the benefit of allowing for more complete testing of the IC412 before assembly in a complete electronic device due to the proper placement of the capacitance required for full speed IC testing.

Fig. 5 is a block diagram of an article 502 according to various embodiments, such as a communication network, a computer, a memory system, a magnetic or optical disk, some other information storage device, and/or any type of electronic device or system. The article 502 may include a processor 504 coupled to a machine-accessible medium such as a memory 506 that stores relevant information (e.g., computer program instructions 508, and/or other data), and an input/output drive 510 connected to an external electrical or electronic device through various means such as a bus or cable 512, which when accessed, causes the machine to perform actions such as calculating an answer to a mathematical question. Various components of the article 502, such as the processor 504, may have transient current problems that benefit from using the present embodiment to mitigate and moderate current variations using tightly coupled capacitors. As an illustrative example, processor 504 may be advantageously packaged in a ceramic package directly on top of the TFC, as previously discussed and illustrated in fig. 4. The present embodiments may be applied to any component part of the article 502 of the processor 504.

As another illustrative example, the article 502 may be a system of communication network elements such as those attached to other network elements (not explicitly shown) via a bus cable 512. The communication network may include a plurality of coupled network elements interconnected by a bus, such as cable 512 as shown. The network elements may include dipole antennas, unidirectional antennas, or other forms of wireless interconnection capabilities in lieu of or in addition to the wired cables 512. Among the various elements present in an exemplary communication network, there may be electronic circuitry that benefits from the exemplary embodiments using the TFCs described above. Electronic circuitry in a communication network that may benefit from the described tightly coupled TFC may include a local microprocessor 504, and an external line driver such as an input/output driver 510 shown in the figure to transmit signals along a cable 512. This embodiment may be advantageous for any individual component of the illustrated system, depending on the particular application or use of the system.

As another illustrative example, the article of manufacture 502 may alternatively be a computer system having multiple elements including a computing element 504, such as a microprocessor, a memory element 506 storing program code 508, a communication element, and an input/output drive element 510, and may be connected to other computer systems via a bus or cable 512 or by a wireless connection (not shown). One or more of these elements may benefit from using the above-described TFC, in particular the I/O driver 510, and/or the computational element 504, both of which may have transient current issues that tightly coupled TFCs may improve. Depending on the use, this embodiment may be advantageous for any individual component in the system. In a number of other examples where capacitors are used, the present embodiment is also useful with more than one, or any number of, such capacitors used in each of the elements, including such elements as charge pumps, filters, radio frequency applications, and differential AC couplers.

The accompanying drawings that form a part hereof show by way of illustration, and not of limitation, specific embodiments in which the disclosed subject matter may be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments may be utilized or derived therefrom, such that structural and logical substitutions and changes may be made without departing from the spirit of the disclosure. This detailed description, therefore, is not to be taken in a limiting sense, but rather is to be accorded the spirit of various embodiments only as defined by the appended claims and all equivalents thereof.

Embodiments of the inventive subject matter may be referred to herein, individually or collectively, by the term "invention" merely for convenience and without intending to voluntarily limit the spirit of this application to any single invention or inventive concept if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, it should be appreciated that any arrangement calculated to achieve the same purpose may be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.

An abstract is needed that will allow the reader to quickly ascertain the nature of the technical disclosure, and which will provide an abstract that will comply with 37c.f.r. § 1.72 (b). It is submitted with the understanding that it will not be used to interpret or limit the spirit of the meaning of the claims. In addition, in the foregoing detailed description, various features are seen as being grouped together in a single embodiment for the purpose of streamlining the disclosure and enhancing clarity. This method of disclosure is not to be interpreted as reflecting an intention that the claimed embodiments require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims (10)

1. A method of forming a thin film capacitor, comprising:

forming a substrate (314);

patterning a first plurality of electrodes (308) on a top surface of a substrate;

forming a pattern of a first dielectric material (311) on the first plurality of electrodes;

forming a pattern of a second plurality of electrodes (312) on the first dielectric material;

forming a pattern of a second dielectric material (310) on the second plurality of electrodes;

forming a plurality of vertical via connectors in the first and second dielectric materials, the plurality of vertical via connectors passing through gaps in the second plurality of electrodes; and

patterning a third plurality of electrodes (306) on the second dielectric material,

wherein the first plurality of electrodes and the third plurality of electrodes constitute one capacitor plate of a thin film capacitor and are respectively connected to different power supplies, and wherein the second plurality of electrodes constitute another capacitor plate of the thin film capacitor and are connected to a reference voltage source.

2. The method of claim 1 wherein the first dielectric material comprises one or more materials selected from the group consisting of barium strontium titanate, barium titanate, strontium titanate, and mixtures thereof.

3. The method of claim 1, the substrate further comprising one or more materials selected from the group consisting of single crystal silicon, polycrystalline silicon, glass, single crystal oxide, metal foil, tape cast ceramic, polymer, and mixtures thereof.

4. A method as claimed in claim 3, further providing the substrate material with a plurality of conductive vias arranged to conduct electrical signals from the top of the substrate to the bottom of the substrate.

5. The method of claim 4, further comprising forming a capacitor on the bottom surface of the substrate.

6. The method of claim 1, further providing a first power supply voltage to the first plurality of electrodes;

providing a ground voltage to the second plurality of electrodes; and

a second power supply voltage is provided to the third plurality of electrodes.

7. The method of claim 1, further providing a plurality of contact locations to the top surfaces of the third plurality of electrodes, each of the plurality of contact locations being electrically connected to a selected portion of one of the first, second, and third plurality of electrodes and arranged to be electrically connected to a selected one of a plurality of inverted mounting pads on the integrated circuit.

8. The method of claim 1, further providing the substrate with a plurality of electrical contact pins arranged to connect the first, second and third pluralities of electrodes to an external circuit.

9. The method of claim 8, wherein the electrical contact pins comprise an area array of electrical connectors, wherein one or more of the electrical connectors are selected from the group consisting of pins, solder bumps, and wires.

10. The method of claim 8, wherein the electrical contact pins comprise a peripheral array having at least one row.