HK1111244A - Memory access control apparatus and method, and communication apparatus - Google Patents

Description

Memory access control device and method, and communication device

CROSS-REFERENCE TO RELATED APPLICATIONS

The present invention comprises the subject matter of Japanese patent application JP2006-201505 filed to the patent office on 25.7.2006, the entire contents of which are incorporated herein by reference.

Technical Field

The present invention relates to a memory access control device and method, and a communication device, and more particularly, to a memory access control device and method that facilitate improvement of security of data in a memory, and a communication device.

Background

For example, in PCT japanese translation patent publication No. 2003-500786, proposals have been made to allocate physical addresses actually accessed to a memory by scrambling logical addresses designated to be accessed by a processor (e.g., a Central Processing Unit (CPU) or the like), thereby making it difficult to analyze or tamper data in the memory.

Disclosure of Invention

In recent years, unauthorized data interception and tampering have become more ingenious, and there is a strong demand for enhancing the security of data in a memory in addition to the technology described in PCT japanese translation patent publication No. 2003-500786.

It is desirable to be able to easily enhance the security of data in memory.

According to a first embodiment of the present invention, there is provided a memory access control device including the following elements: scrambling key generation means for generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo-random numbers; and assigning means for scrambling the logical addresses using the scrambling key, thereby assigning the physical addresses to the logical addresses.

The scramble key generation apparatus can generate a scramble key in which a fixed value is a bit stream including only 1.

The memory access control device may further comprise random number generation means for generating a random number or a pseudo random number.

The random number generating means may generate Gold sequence pseudo random numbers.

In the case where the generated random number or the generated pseudo random number is equal to a predetermined value, the random number generation means may generate a new random number or a new pseudo random number.

According to a first embodiment of the present invention, there is provided a memory access control method including the steps of: generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo random numbers; and scrambling the logical addresses using the scrambling key, thereby assigning physical addresses to the logical addresses.

According to a second embodiment of the present invention, there is provided a communication apparatus including the following elements: scrambling key generation means for generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo-random numbers; and assigning means for scrambling the logical address using the scrambling key to assign a physical address to the logical address, the physical address being used to store data read from the device having the contactless integrated circuit card function.

According to the first embodiment of the present invention, a binary scrambling key including predetermined low-order bits that are fixed values, in which the value of the least significant bit is 1 and the remaining bits are a random number or a pseudo random number, is generated, and a physical address is allocated to a logical address by scrambling the logical address using the scrambling key.

According to a second embodiment of the present invention, a binary scrambling key including predetermined low-order bits that are fixed values is generated, wherein the value of the least significant bit is 1 and the remaining bits are a random number or a pseudo-random number; and scrambling the logical address by using the scrambling key, thereby assigning a physical address to the logical address, the physical address being used for storing data read from the device having the contactless integrated circuit card function.

According to the first or second embodiment of the present invention, data in the memory becomes difficult to analyze or tamper with. According to the first or second embodiment of the present invention, the security of data in the memory can be easily improved.

Drawings

FIG. 1 is a block diagram of a reader/writer according to an embodiment of the present invention;

FIG. 2 is a block diagram showing a functional structure of the control module shown in FIG. 1;

fig. 3 is a block diagram illustrating a functional structure of the random number output unit shown in fig. 2;

FIG. 4 is a block diagram showing a detailed functional structure of the bus scrambler shown in FIG. 2;

FIG. 5 is a diagram depicting a sequence of values in an internal register of the scramble key buffer shown in FIG. 2;

FIG. 6 is a flowchart describing a scramble key generation process performed by the reader/writer shown in FIG. 1;

FIG. 7 is a flowchart describing a memory access control process performed by the reader/writer shown in FIG. 1;

fig. 8 is a block diagram showing a functional structure of the random number output unit shown in fig. 2 according to the second embodiment of the present invention; and

fig. 9 is a flowchart describing a scramble key generation process performed by the reader/writer shown in fig. 1 in the case where the reader/writer has the random number output unit shown in fig. 8.

Detailed Description

Before describing embodiments of the present invention, the correspondence between the features of the claims and the specific elements disclosed in the embodiments of the present invention described with reference to the specification or the drawings is described below. The purpose of this description is to ensure that embodiments supporting the claimed invention are described in the specification or drawings. Therefore, even if an element in the following embodiments is not described in the specification or the drawings with reference to a specific feature of the present invention, it does not necessarily mean that the element is not related to the feature in the claims. Conversely, even if an element is described herein as relating to a particular feature in a claim, this does not necessarily mean that the element does not relate to other features of the claim.

According to a first embodiment of the present invention, there is provided a memory access control device (e.g., the bus scrambler 43 shown in fig. 2) including the following elements: scrambling key generation means (for example, a scrambling key buffer 61 shown in fig. 2) for generating a binary scrambling key including predetermined low-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are a random number or a pseudo-random number; and an assigning means (for example, a memory 33 shown in fig. 2) for assigning the physical address to the logical address by scrambling the logical address using the scrambling key.

The memory access control device according to the first embodiment of the present invention may further include random number generation means (for example, the random number generator 101 shown in fig. 3) for generating a random number or a pseudo-random number as a scrambling key.

According to a first embodiment of the present invention, there is provided a memory access control method including the steps of: generating a binary scrambling key including predetermined lower-order bits that are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are a random number or pseudo-random number (e.g., step S2 shown in fig. 6 or step S105 shown in fig. 9); and scrambling the logical addresses using the scrambling key, thereby assigning physical addresses to the logical addresses (e.g., step S38 or S41 shown in fig. 7).

According to a second embodiment of the present invention, there is provided a communication apparatus (for example, a reader/writer 1 shown in fig. 1) for communicating with an apparatus (for example, an IC card 2 shown in fig. 1) having a noncontact integrated circuit card function, including the following elements: scrambling key generation means (for example, a scrambling key buffer 61 shown in fig. 2) for generating a binary scrambling key including predetermined low-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are a random number or a pseudo-random number; and assigning means (for example, an address bus scrambling circuit 52 shown in fig. 2) for scrambling the logical addresses using the scrambling key, thereby assigning physical addresses, which are used for storing data read from the device having the contactless integrated circuit card function, to the logical addresses.

Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram of a reader/writer according to an embodiment of the present invention. The reader/writer 1 according to the embodiment of the present invention includes an antenna 11, a Radio Frequency (RF) driving board 12, and a control module 13.

The RF driving board 12 performs short-range communication based on electromagnetic induction with the contactless Integrated Circuit (IC) card 2 using a single-frequency carrier via the antenna 11. The frequency of the carrier wave used by the RF drive plate 12 may be, for example, 13.56MHz in the industrial, scientific and medical (ISM) frequency band. The close range communication refers to communication in which devices can communicate with each other when the distance between the devices is within several tens of centimeters, and it also includes communication in which (housings of) the devices contact each other.

The control module 13 executes processing for implementing a service using the IC card 2. The control module 13 reads/writes data used in the service from/to the IC card 2 through the antenna 11 and the RF driving board 12 as necessary. The control module 13 is capable of performing parallel processing that provides a plurality of service types. That is, one reader/writer 1 can provide various services using a non-contact IC card, such as an electronic money service, a prepaid card service, and a ticket card service of various traffic types.

Fig. 2 is a block diagram showing a functional structure of the control module 13 shown in fig. 1. The control module 13 includes a CPU31, a memory access controller 32, a memory 33, and a reset circuit 34. The memory access controller 32 includes a scramble key change instruction unit 41, a random number output unit 42, and a bus scrambler 43. The bus scrambler 43 includes a scrambling key holder 51 and an address bus scrambling circuit 52. The scramble key holder 51 includes a scramble key buffer 61 and an internal memory 62.

The CPU31 and the address bus scrambling circuit 52 are connected to each other via an address bus 35 provided therebetween, and the bus bandwidth of the address bus 35 is n bits. The address bus scrambling circuit 52 and the memory 33 are connected to each other with the address bus 36 interposed therebetween, and the bus bandwidth of the address bus 36 is n bits as well. The CPU31 and the memory 33 are connected to each other by a data bus 37 provided therebetween, and the bus bandwidth of the data bus 37 is m bits.

The CPU31 executes a predetermined program to execute processing for implementing services using the IC card 2. The CPU31 is capable of executing programs associated with services in parallel with each other. In other words, the CPU31 is capable of performing parallel processing to provide a variety of services.

The CPU31 reads/writes data used in various services from/to the memory 33. When writing data to the memory 33, the CPU31 supplies a logical address signal indicating a logical address of a logical data write position to the address bus scrambling circuit 52 via the address bus 35, and supplies a write signal including data to be written and an instruction to write data to the memory 33 via the data bus 37. When reading data from the memory 33, the CPU31 supplies a logical address signal indicating a logical address of a logical data read position to the bus scrambling circuit 52 via the address bus 35, and supplies a read signal indicating a data read instruction to the memory 33 via the data bus 37.

The memory access controller 32 controls access of the CPU31 to the memory 33.

Among the various elements included in the memory access controller 32, the scramble key change instruction unit 41 includes, for example, a button, a switch, or the like. In order to change the scramble key stored in the scramble key holder 51, for example, the user inputs an instruction to change the scramble key via the scramble key change instruction unit 41.

When a signal indicating an instruction to change the scramble key is supplied from the scramble key change instruction unit 41 to the random number output unit 42, the random number output unit 42 generates a pseudo random number including a bit stream of n-p bits, and outputs the generated pseudo random number as the scramble key to the scramble key buffer 61.

The bus scrambler 43 performs a process of converting a logical address represented by a logical address signal supplied from the CPU31 into a physical address for actually accessing the memory 33.

Among the respective elements included in the bus scrambler 43, the scrambling key holder 51 generates a scrambling key using a pseudo random number supplied from the random number output unit 42, and holds the generated scrambling key. More specifically, the scramble key buffer 61 of the scramble key holder 51 generates a scramble key using the pseudo random number supplied from the random number output unit 42, and holds the generated scramble key. Meanwhile, the scramble key buffer 61 supplies the generated scramble key and stores it in the internal memory 62. The internal memory 62 is a nonvolatile memory such as a flash memory, or a Random Access Memory (RAM) supported by a battery or the like. The internal memory 62 continuously holds the scramble key even in the case where the power of the control module 13 is turned off. When the control module 13 is turned on from the off state, the scramble key buffer 61 reads out the scramble key stored in the internal memory 62 and stores the scramble key. Then, the scramble key buffer 61 supplies a reset instruction signal to the reset circuit 34 during a period from the start of the control module 13 to the completion of the reading of the scramble key from the internal memory 62.

The address bus scrambling circuit 52 scrambles the logical address indicated by the logical address signal supplied from the CPU31 using the scrambling key held in the scrambling key buffer 61, thereby converting the logical address into a physical address for actually accessing the memory 33. In other words, the address bus scrambling circuit 52 scrambles the input logical addresses, thereby assigning physical addresses to the logical addresses. The address bus scrambling circuit 52 supplies physical address signals representing the converted physical addresses to the memory 33 via the address bus 36.

The memory 33 is a nonvolatile memory such as a flash memory, an electrically erasable programmable read-only memory (EEPROM), a Hard Disk Drive (HDD), a magnetoresistive ram (mram), a ferroelectric ram (feram), or an Ovonic unified memory (Ovonic unified memory). In the case where a write signal is supplied from the CPU31 to the memory 33, the data contained in the write signal is written to a physical address on the memory 33, which address is represented by a physical address signal supplied from the address bus scrambling circuit 52. In the case where a read signal is supplied from the CPU31 to the memory 33, data is read from a physical address on the memory (the address being indicated by a physical address signal supplied from the address bus scrambling circuit 52), and the read data is supplied to the CPU31 via the data bus 37.

When the reset instruction signal is supplied from the scramble key buffer 61, the reset circuit 34 supplies a reset signal to the CPU31, thereby initializing the state of the CPU 31.

Fig. 3 is a block diagram showing a functional structure of the random number output unit 42. The random number output unit 42 includes a random number generator 101 and a switch 102.

The random number generator 101 includes a Linear Feedback Shift Register (LFSR) random number generator 111 having an L1 bit shift register, an LFSR random number generator 112 having an L2 bit shift register, and an exclusive or (EXOR) circuit 113.

The LFSR random number generators 111 and 112 are based on the existing LFSR principle in which an exclusive or of values of predetermined bits of a shift register is input as a feedback value to the shift register. The random number generator 101 generates a Gold sequence (Gold-sequence) pseudo random number by computing an exclusive or of two different maximum length sequence (M-sequence) pseudo random numbers generated by the LFSR random number generators 111 and 112, respectively, bit by bit using an exclusive or circuit 113. The number of LFSR random number generators 111 and 112 included in the random number generator 101 is not limited to two. The random number generator 101 may have three or more LFSR random number generators.

The switch 102 is turned on in response to input of a signal indicating an instruction to change the scramble key from the scramble key change instruction unit 41. A bit stream representing the Gold sequence pseudo random number generated by the random number generator 101 is output to the scramble key buffer 61 via the switch 102.

Fig. 4 is a block diagram showing a detailed functional structure of the bus scrambler 43.

The scramble key buffer 61 comprises an n-bit shift register with serial and parallel inputs and parallel outputs. As shown in FIG. 5, among the internal registers of the scramble key buffer 61, the low-order p bits (K1K)_pBits) are fixed values, and the pseudo random number supplied as a serial signal from the random number output unit 42 is set to the remaining high-order n-p bits (K)_p+1d～K_nA bit). That is, the scramble key buffer 61 generates and holds a predetermined low-order p bits as a fixed value and a binary scramble key of the remaining n-p bits as a pseudo random number. The Least Significant Bit (LSB) of the p bits having a fixed value is always set to 1. That is, the LSB of the scramble key is always set to 1.

The address bus scrambling circuit 52 calculates, bit by bit, A1-A represented by logical address signals including those supplied from the CPU31 via the address bus 35 by the exclusive OR circuits 151-1 to 151-n_nThe n-bit logical address of the bit and the logical address including K1-K stored in the scramble key buffer 61_nXOR of the n-position of the bits to convert the logical address to include SA 1-SA_nThe n-bit physical address of the bit. The address bus scrambling circuit 52 supplies a physical address signal indicating the converted physical address to the memory 33 via the address bus 36.

The processing performed by the reader/writer 1 will be described below with reference to fig. 6 and 7.

Referring to the flowchart shown in fig. 6, the scramble key generation process performed by the reader/writer 1 will be described. This process starts when the user inputs an instruction to change the scramble key through the scramble key change instruction unit 41 with the reader/writer 1 turned on.

In step S1, the random number output unit 42 outputs a pseudo-random number. More specifically, the scramble key change instruction unit 41 supplies a signal indicating an instruction to change the scramble key to the switch 102, thereby turning on the switch 102. The random number generator 101 always generates a pseudo random number in the case where the power of the reader/writer 1 is turned on. By turning on the switch 102, the random number generator 101 starts outputting a pseudo random number to the scramble key buffer 61 via the switch 102. In the case where the random number generator 101 outputs a pseudo random number of n-p bits, the switch 102 is turned off.

In step S2, the bus scrambler 43 sets the scrambling key, and the scrambling key generation process ends. Specifically, the scramble key buffer 61 sets a pseudo random number of a bit stream including n-p bits supplied from the random number output unit 42 to high-order n-p bits of the internal register. Thus, an n-position scramble key including p fixed values of lower order bits and n-p pseudo random numbers of higher order bits is generated. The scramble key buffer 61 holds the generated scramble key in an internal register, and supplies and stores the scramble key in the internal memory 62. That is, the scramble key is backed up in the internal memory 62.

Thus, it is possible to set a scramble key, which has a different value and is difficult to predict, to each control module 13. This scramble key setting processing is performed, for example, before shipment of the reader/writer 1 from the factory.

Next, with reference to the flowchart of fig. 7, a memory access control process performed by the reader/writer 1 is described. The process starts, for example, with the reader/writer 1 turned on.

In step S31, in the case where the reader/writer 1 is turned on and the control module 13 is turned on, the scramble key buffer 61 starts to supply a reset instruction signal to the reset circuit 34.

In step S32, the reset circuit 34 starts to supply a reset signal to the CPU31, thereby resetting the CPU 31. Thus, the state of the CPU31 is initialized.

In step S33, the scramble key buffer 61 reads the scramble key held in the internal register 62. The scramble key buffer 61 stores the read scramble key in an internal register.

In step S34, the scramble key buffer 61 stops supplying the reset instruction signal to the reset circuit 34. Accordingly, the reset circuit 34 stops supplying the reset signal to the CPU 31. The CPU31 starts executing the program.

In step S35, the CPU31 determines whether to write data. In a case where the next processing in the program executed by the CPU31 does not involve writing data, the CPU31 determines not to write data, and the flow advances to step S36.

In step S36, the CPU31 determines whether to read data. In a case where the next processing in the program executed by the CPU31 does not involve reading data, the CPU31 determines not to read data, and the flow returns to step S35.

The processing in steps S35 and S36 is repeated until it is determined that data is written in step S35 or read in step S36.

In a case where the next process in the program executed by the CPU31 involves writing data in step S35, the CPU31 determines to write data, and the flow proceeds to step S37.

In step S37, the CPU31 gives an instruction to write data. More specifically, the CPU31 supplies a logical address signal indicating a logical address of a logical data write position to the address bus scrambling circuit 52 via the address bus 35, and supplies a write signal including data to be written and an instruction indicating write data to the memory 33 via the data bus 37.

In step S38, the address bus scramble circuit 52 converts the logical address into a physical address. Specifically, the address bus scramble circuit 52 scrambles the logical addresses by calculating the exclusive or of the logical addresses indicated by the logical address signals and the scramble key held in the scramble key buffer 61 bit by bit, thereby converting the logical addresses into physical addresses. The address bus scrambling circuit 52 supplies physical address signals representing the converted physical addresses to the memory 33 via the address bus 36.

In step S39, the memory 33 writes data. Specifically, the memory 33 writes data contained in the write signal supplied from the CPU31 to a physical address on the memory 33, the address being indicated by the physical address signal. Thus, even in the case where the CPU31 gives an instruction to write data to consecutive logical addresses, the data is actually written to a randomly arranged position on the memory 33. Thus, it is difficult to analyze or tamper with the data stored in the memory 33.

When the consecutive lower-order bits of the scramble key are zero, the logical address lower-order bits corresponding to the consecutive zero-order bits are assigned without being converted into physical addresses. Therefore, in a range where the lower order bits are not converted on the memory 33, data is arranged in the same sequence as the logical addresses. For example, when three consecutive low-order bits of the scramble key are zero, the three low-order bits of the logical address are assigned without being converted into the physical address, and data is arranged in the same sequence as the logical address in a range in which the low-order bits are not converted in the memory 33. Thus, the data is more likely to be analyzed. In contrast, as described above, the LSB of the scramble key held in the scramble key buffer 61 is fixed to 1, and thus the LSB of the logical address is always scrambled. Thus, on the memory, data is prevented from being arranged in the same sequence as the logical addresses, and the data can be made more difficult to analyze more reliably.

By setting the fixed value of the scrambling key to a bit stream including only 1, the data stream can be reliably scrambled and arranged in a more detailed manner, so that the data becomes more difficult to analyze.

After that, the flow returns to step S35, and the processing at and below step S35 is executed.

In step S36, in a case where the next processing in the program executed by the CPU31 involves reading data, the CPU31 determines the read data, and the flow proceeds to step S40.

In step S40, the CPU31 gives an instruction to read data. Specifically, the CPU31 supplies a logical address signal indicating a logical address of a logical data read position to the address bus scrambling circuit 52 via the address bus 35, and supplies a read signal indicating a data read instruction to the memory 33 via the data bus 37.

In step S41, as in the processing in step S38 described above, the logical address is converted into a physical address, and a physical address signal representing the converted physical address is supplied from the address bus scrambling circuit 52 to the memory 33 via the address bus 36.

In step S42, the memory 33 reads data. Specifically, the memory 33 reads data stored at a physical address indicated by the physical address signal and supplies the read data to the CPU31 via the data bus 37.

After that, the flow returns to step S35, and the processing at and below step S35 is executed.

As described above, different scramble keys can be easily set for different control modules 13. Even in the case where the scramble key set to one control module 13 is analyzed, it is possible to prevent the data stored in the memory 33 of the other control module 13 from being analyzed or tampered with using the scramble key. Therefore, damage due to data leakage or tampering can be kept to a minimum.

The existing techniques can be employed in performing the pseudo random number generation method and the address scrambling method. The security of the data in the memory 33 can be easily improved since no new complex circuitry is required and the user only has to perform the additional step of entering an instruction to change the scrambling key.

As described above, data is prevented from being arranged in the same sequence as the logical addresses in the memory 33, and thus the data can be made more difficult to analyze more reliably.

Referring to fig. 8 and 9, a random number output unit 42 according to a second embodiment of the present invention is described below.

Fig. 8 is a block diagram showing a functional structure of the random number output unit 42 according to the second embodiment. The random number output unit 42 shown in fig. 8 includes a random number generator 101, a bit stream checker 201, a switch 202, a random number storage unit 203 including an n-p bit shift register, and a switch 204. In fig. 8, parts corresponding to those of fig. 3 are denoted by the same reference numerals, and description of parts performing the same processing is omitted to avoid redundancy.

The bitstream checker 201 obtains a signal indicating an instruction to change the scramble key from the scramble key change instruction unit 41. When a signal indicating an instruction to change the scramble key is supplied from the scramble key change instruction unit 41, the bitstream checker 201 turns on the switch 202. Accordingly, a bit stream representing the Gold sequence pseudo random number generated by the random number generator 101 is supplied from the random number generator 101 to the random number storage unit 203 via the switch 202, and is stored in the random number storage unit 203.

The bit stream checker 201 checks whether the pseudo random number stored in the random number storage unit 203 coincides with any predetermined disable value. In the case where the pseudo random number stored in the random number storage unit 203 coincides with a disable value, the bit stream checker 201 turns on the switch 202 and outputs a pseudo random number including a predetermined number of bits from the random number output unit 101 to the random number storage unit 203, thereby changing the value of the pseudo random number stored in the random number storage unit 203. In the case where the pseudo random number stored in the random number storage unit 203 does not coincide with any disable value, the bit stream checker 201 turns on the switch 204. Thus, the pseudo random number including the n-p bit stream stored in the random number storage unit 203 is output to the scramble key buffer 61 via the switch 204. That is, in the case where the pseudo random number generated by the random number generator 101 is equal to a predetermined disable value, the bit stream checker 201 controls the random number generator 101 to generate a new random number, and outputs this random value different from the disable value to the scramble key buffer 61.

Next, with reference to the flowchart of fig. 9, a scramble key generation process executed by the read/write apparatus 1, which is different from the flowchart of fig. 6, in the case where the random number output unit 42 shown in fig. 8 is provided in the reader/writer 1 will be described. This process starts when the user inputs an instruction to change the scramble key through the scramble key change instruction unit 41, for example, with the power of the reader/writer 1 turned on.

In step S101, the random number output unit 42 generates a pseudo random number. Specifically, the scramble key change instruction unit 41 supplies a signal indicating an instruction to change the scramble key to the bit stream checker 201. The bitstream checker 201 turns on the switch 202. The random number generator 101 constantly generates a pseudo random number when the power of the reader/writer 1 is turned on. By turning on the switch 202, the random number generator 101 starts outputting a pseudo random number to the random number storage unit 203 via the switch 202. In the case where the random number generator 101 outputs a pseudo random number of n-p bits, the bit stream checker 201 turns off the switch 202.

In step S102, the bitstream checker 201 determines whether the pseudo random number is a disable value. For example, values that may be more easily predicted than other values, such as a bitstream that includes the same consecutive values (e.g., 111.. 111), or a bitstream having alternating different values (e.g., 0101.. 0101 or 1010.. 1010), are preset by the user in bitstream checker 201 as values that are prohibited from being used as scrambling keys. In the case where a value obtained by removing the low-order fixed value of the scramble key from each of these disable values coincides with the pseudo random number stored in the random number storage unit 203, the bit stream checker 201 determines that the pseudo random number is a disable value, and the flow proceeds to step S103.

In step S103, the bitstream checker 201 generates a new pseudo random number. Specifically, the bit stream checker 201 turns on the switch 202 and outputs a pseudo random number including a predetermined number of bits from the random number generator 101 to the random number storage unit 203. The random number storage unit 203 shifts the stored bit stream up by the number of bits of the newly input pseudo random number and adds the input pseudo random number to the end of the bit stream. That is, a new pseudo random number generated by the random number generator 101 is stored in the random number storage unit 203.

After that, the flow returns to step S102. The processing in steps S102 and S103 is repeated until it is determined in step S102 that the pseudo random number is not a disable value.

In the case where it is determined in step S102 that the pseudo random number is not the disable value, the processing proceeds to step S104.

In step S104, the random number output unit 42 outputs a pseudo random number. Specifically, the bitstream checker 201 turns on the switch 204. Thus, the pseudo random number stored in the random number storage unit 203 is output to the scramble key buffer 61 via the switch 204.

In step S105, the scramble key is set, and the scramble key generation process ends, as in the above-described process in step S2 shown in fig. 6.

Since it is avoided in the above-described manner that an easily predictable value is set as the scramble key, it is difficult to analyze or tamper with the data stored in the memory 33, thereby enhancing the security of the data in the memory 33. Furthermore, by changing the scrambling key when, for example, the memory 33 is replaced or initialized, the scrambling key becomes more difficult to analyze.

In the above description, the case where a Gold sequence pseudo-random number is used as a scrambling key has been described. However, the random number or pseudo-random number used as the scramble key is not limited to the above example. For example, an M-sequence pseudo random number generated by using only one LFSR or a physical random number using thermal noise may be used.

The method of scrambling addresses is not limited to the above example. Other methods using a scrambling key set by a random number or a pseudo-random number may also be employed.

In the above description, the IC card 2 is described as a communication partner of the reader/writer 1. Needless to say, the reader/writer 1 can communicate with a device having a noncontact IC card function, such as a mobile phone, a Personal Digital Assistant (PDA), a timepiece, and a computer having a noncontact IC card function.

The memory access controller 32 shown in fig. 2 can also be applied to other devices that read/write data from/to a memory, in addition to a reader/writer.

In the random number output unit 42 shown in fig. 8, in addition to the prohibition of outputting an easily predictable value as a scramble key described above, a value that is prohibited from being output may be arbitrarily set according to the application.

Although the case where the memory 33 shown in fig. 2 is a nonvolatile memory is described above, it is needless to say that the memory access controller 32 may be used to control a volatile memory.

The user may be allowed to set a value other than the LSB of the fixed value of the scramble key.

Further, the user may be allowed to set a variable value other than the fixed value of the scramble key.

It should be understood by those skilled in the art that various modifications, combinations, self-combinations and alterations can be made to the present invention based on design requirements and other factors within the scope of the appended claims or their equivalents.

Claims (9)

1. A memory access control device, comprising:

scrambling key generation means for generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo-random numbers; and

an assigning means for scrambling a logical address using the scrambling key to assign a physical address to the logical address.

2. The memory access control device according to claim 1, wherein the scramble key generation device generates the scramble key of which the fixed value is a bit stream including only 1.

3. The memory access control device of claim 1, further comprising a random number generation device for generating the random number or the pseudo random number.

4. A memory access control device according to claim 3, wherein the random number generation means generates a Gold sequence pseudo random number.

5. The memory access control device according to claim 3, wherein the random number generation means generates a new random number or a new pseudo random number in a case where the generated random number or the generated pseudo random number is equal to a predetermined value.

6. A memory access control method, comprising the steps of:

generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo random numbers; and scrambling the logical address using the scrambling key, thereby assigning a physical address to the logical address.

7. A communication apparatus for communicating with an apparatus having a contactless integrated circuit card function, comprising:

scrambling key generation means for generating a binary scrambling key including predetermined lower-order bits which are fixed values, wherein the value of the least significant bit is 1 and the remaining bits are random numbers or pseudo-random numbers; and

and assigning means for scrambling a logical address using the scrambling key to assign a physical address to the logical address, the physical address being used to store data read from the apparatus having a contactless integrated circuit card function.

8. A memory access control device, comprising:

a scrambling key generator configured to generate a binary scrambling key including predetermined lower-order bits that are fixed values, wherein a value of a least significant bit is 1 and remaining bits are a random number or a pseudo-random number; and

an allocation unit configured to scramble a logical address using the scrambling key, thereby allocating a physical address to the logical address.

9. A communication apparatus for communicating with an apparatus having a contactless integrated circuit card function, comprising:

a scrambling key generator configured to generate a binary scrambling key including predetermined lower-order bits that are fixed values, wherein a value of a least significant bit is 1 and remaining bits are a random number or a pseudo-random number; and

an assigning unit configured to scramble a logical address using the scramble key, thereby assigning a physical address to the logical address, the physical address being used to store data read from the device having a contactless integrated circuit card function.