HK1110971B - Multimedia card interface method, computer program product and apparatus - Google Patents

Description

Multimedia card interface method, computer program product and apparatus

Technical Field

Exemplary embodiments of the present invention relate generally to removable memory modules containing memory devices and, more particularly, to interfaces to removable memory modules such as, but not limited to, removable memory modules known as multi-media cards (MMCs) and removable memory modules known as Secure Digital (SD) memory cards.

Background

In removable memory modules, such as MMC, busy signaling is defined, for example, in connection with data programming. The busy signal is output from the MMC to the host device and in this case is used to indicate "the buffer is ready for the next data". The erase command also uses a busy signal, but in this case indicates "erase busy". The use of busy signals is inflexible as there is usually only one busy signal line in order to save on pin count.

The current definition of a busy signal in MMC association (MMCA) systems is based on the fact that: the software layer of the host device is typically implemented in such a way that data is transferred in blocks, e.g. in 16 k-bit blocks. It is therefore feasible to use a so-called multi-block write command, since one data block transferred over the MMC interface is only a fraction of the host device block size (typically an MMC block is 512 bytes). Since the meaning of the busy signal is currently "buffer ready" in terms of data transfer, the host can transfer multiple 512 byte data blocks to the MMC without polling the status of the buffer.

However, as currently specified, the problem encountered is that the host must begin polling the "program ready" status signal after the last block (e.g., the last 512 bytes of the 16 kbyte total blocks) has been transferred, which becomes relevant at this point since there are no new blocks to transfer. Requiring the host to poll the program ready status signal is an inefficient use of host processing capacity.

Disclosure of Invention

The above and other problems are overcome, and other advantages are realized, in accordance with the exemplary embodiments of this invention.

In a first aspect thereof, the present invention provides a method for interfacing a first unit to a second unit over a bus comprising signal lines. The method comprises the following steps: driving first information from a first cell to a second cell through a signal line; driving a signal line from a second cell to cause a state change; interpreting a change of state of the signal line as having a first meaning at the first unit, and driving second information from the first unit to the signal line in response; driving the signal line from the second unit to cause the state change again; and interpreting, at the first unit, a change in state of the signal line, which occurs after the second information is driven to the signal line, as having a second meaning different from the first meaning.

In a second aspect thereof, the present invention provides a computer program product embodied in a computer-readable medium and comprising program instructions for performing an operation of interfacing a first unit to a second unit through a bus comprising signal lines. These operations include: driving first information from a first cell to a second cell through a signal line; driving a signal line from a second cell to cause a state change; interpreting a change of state of the signal line as having a first meaning at the first unit, and driving second information from the first unit to the signal line in response; driving the signal line from the second unit to cause the state change again; and interpreting, at the first unit, a change in state of the signal line, which occurs after the second information is driven to the signal line, as having a second meaning different from the first meaning.

In a third aspect thereof, the present invention provides an apparatus for interfacing a first unit to a second unit over a bus comprising signal lines. The apparatus in this embodiment comprises a driver at the first unit coupled to the signal line and a receiver at the first unit coupled to the signal line. The driver is operable to drive first information and then second information from the first unit to the second unit through the signal line, and the receiver is operable to receive a change in state of the signal line driven from the second unit after the second unit receives the first information and after the second information. The controller at the first unit is operable to interpret a change of state of the signal line as having a first meaning after driving the first information from the first unit to the second unit through the signal line and a second meaning different from the first meaning after driving the second information from the first unit to the second unit through the signal line. The first unit may comprise a host and the second unit may comprise a memory card.

In a fourth aspect thereof, the present invention provides an apparatus for interfacing a first unit to a second unit through a bus including signal lines. The apparatus in this embodiment comprises a driver at the first unit coupled to the signal line and a receiver at the first unit coupled to the signal line. The receiver is operable to receive first information and then second information from the second unit through the signal line, and the driver is operable to drive a change of state of the signal line to the second unit after receiving the first information and after receiving the second information. The controller at the first unit causes the change in state of the signal line to have a first meaning after receiving the first information from the second unit through the signal line and a second meaning different from the first meaning after receiving the second information from the second unit through the signal line. The first unit may comprise a memory card and the second unit may comprise a host.

In yet another of its aspects, the present invention provides a method for transferring data from a first unit to a second unit over a bus. The method comprises the following steps: initiating n block data transfers, wherein n > 1; for the first n-1 data blocks transferred from the first unit to the second unit, controlling the status signal generated by the second unit to become a buffer busy/ready status signal after each of the n-1 data blocks, thereby informing the first unit when the first unit can transfer the next data block; and for the nth data block transferred from the first unit to the second unit, controlling the state signal to become a program busy/ready state signal after the nth data block, thereby informing the first unit that the second unit terminates the internal programming if there is the internal programming.

In a further aspect thereof, the present invention provides a computer program product embodied in a computer-readable medium and comprising program instructions for performing an operation of transferring data from a first unit to a second unit over a bus. These operations include: initiating n block data transfers, wherein n > 1; for the first n-1 data blocks transferred from the first unit to the second unit, controlling the status signal generated by the second unit to become a buffer busy/ready status signal after each of the n-1 data blocks, thereby informing the first unit when the first unit can transfer the next data block; and for the first data block transferred from the first unit to the second unit, controlling the state signal to become a program busy/ready state signal after the nth data block, thereby informing the first unit that the second unit terminates the internal programming if there is the internal programming.

In yet another of its aspects, the present invention provides an apparatus for transferring data from a first unit to a second unit over a bus. The apparatus includes a controller to initiate a transfer of n blocks of data, where n > 1. For the first n-1 data blocks transferred from the first unit to the second unit, the second unit controls the status signal to become a buffer busy/ready status signal after each of the n-1 data blocks, thereby informing the first unit when the first unit can transfer the next data block; and for the nth data block transferred from the first unit to the second unit, the second unit controls the state signal to become a program busy/ready state signal after the nth data block, thereby informing the first unit that the second unit terminates the internal programming if there is the internal programming.

According to another mode of the invention, embodiments of the invention include a method, computer program product and apparatus to transfer data from a first unit to a second unit over a bus. The method comprises the following steps: initiating n block data transfers, wherein n > 1; for the first n-1 data blocks transferred from the first unit to the second unit, controlling the status signal generated by the second unit to become a buffer busy/ready status signal after each of the n-1 data blocks, thereby informing the first unit when the first unit can transfer the next data block; and after the nth data block transferred from the first unit to the second unit, transmitting a stop transmission command to the second unit and controlling the status signal to become a program busy/ready status signal, thereby informing the first unit that the second unit terminates the internal programming if there is the internal programming.

Drawings

The foregoing and other aspects of exemplary embodiments of the present invention will become more apparent upon reading the following detailed description in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram showing a first unit coupled to a second unit by a bus; and

fig. 2 is an exemplary waveform diagram illustrating the operation of the present invention.

Detailed Description

Fig. 1 shows a first unit, such as a host 1, connected to a second unit, such as a memory card 2 (e.g. MMC), via a bus 3 comprising a busy signal 4 associated with a data line 5. Also shown are a Command (CMD) line 6 and a Clock (CLK) line 7, through which CMD line 6 host 1 issues commands to card 2. In general, bus 3 may be compatible with a bus as defined by "The MultiMediaCard, System Specification, Version 3.31, MMCA Technical Committee", 2003, except as modified to provide a multipurpose or multi-mode busy signal 4 according to embodiments of The present invention. It should be recognized, however, that embodiments of the present invention should not be construed as limited to use with MMC-compatible cards, interfaces, and buses only.

The host 1 may be a cellular phone or a digital camera or a PC or any suitable device that can accommodate the use of a memory card 2. Assume that host 1 includes a driver 1A and a receiver 1B coupled to data signal line 5 and a control logic 1C coupled to driver 1A and receiver 1B and operable in accordance with the teachings of the present invention. Assume that memory card 2 includes a driver 2A and a receiver 2B coupled to data signal lines 5 and control logic 2C coupled to driver 2A and receiver 2B and operable in accordance with the teachings of the present invention.

Exemplary embodiments of the present invention provide for changing the meaning of busy signal 4 during command execution. In the case of MMC data transfer operation this means that for the first data block sent, the busy signal 4 is used and interpreted by the host 1 as currently defined (i.e. "buffer busy/ready"), but for the last data block, the busy signal 4 is interpreted as "programmed busy/ready". It should be noted that during data transfer there may be ongoing data programming within MMC 2. Thus, the "program busy/ready" status signal is used to inform the host 1 when the internal programming of the memory card 2 is completed.

By using an exemplary embodiment of the present invention, the host 1 is not required to poll the MMC 2's internal "program busy/ready" status signal, thereby saving host Interface (IF) resources. Host 1 may instead continue to use a more efficient busy signal based interrupt-driven mode of operation for the entire data transfer. Furthermore, the use of embodiments of the present invention means that fewer software timers (such as the software timers used to time polling operations) are required, thereby simplifying implementation. The use of embodiments of the present invention also means that performance enhancement can be achieved; backward and forward compatibility becomes possible; and parallel activity implementation usage becomes possible in an efficient manner.

Two exemplary modes of operation are now described. It should be appreciated that more than these two modes of operation can be achieved through the use of embodiments of the present invention.

The first mode of operation is referred to as multi-block writing. For MMC compatible operation, the command sequence is as follows:

CMD16(Set_Block_Length)；

CMD23(Set _ Block _ Count); from this information, MMC2 may determine which data block is the last block; and

CMD24(Write _ Block): a plurality of data blocks are written.

This command sequence is then followed by sending the data block on data line 5 to MMC 2. Between each data block there is busy signalling on the data line 5. Busy in this case means "buffer busy/ready". Once the busy signal is deasserted (goes high), host 1 may send the next data block to MMC 2. As described above, during data transfer, there may be ongoing data programming within MMC 2. According to an aspect of the invention, after MMC2 receives the last data block, it changes the meaning of busy signal 4 to "program busy/ready". This means that the host 1 does not need to start polling the programming state of MMC2 but may instead continue to wait also for a busy interrupt in this access phase. However, the occurrence of a busy interrupt is interpreted by host 1 as the occurrence of a "program ready" status indication.

The second mode of operation is referred to as open ended multi-block writing. For MMC compatible operation, the command sequence is as follows:

CMD16(Set_Block_Length)；

CMD25(Write_Multiple_Block)；

sending the data block on the data line 5; and

CMD12(Stop _ Transmission); from this information, MMC2 knows that the last data block has been sent.

Busy signalling is present on the data line 5 between each data block. Busy in this case means "buffer busy/ready". Once the busy signal is deasserted, host 1 may send the next data block to MMC 2. During the data transfer there may be ongoing data programming within MMC 2. According to an aspect of the invention, after MMC2 receives the stop command (CMD 12), it sets the busy signal again, but the meaning of busy signal 4 in this case is again "program busy/ready".

It can be noted that: there may be several time slots during which CMD12 may be sent to MMC2, and these may affect the meaning and interpretation of busy signal 4.

Fig. 2 is a waveform diagram illustrating an operation mode in which CMD23(Set _ Block _ Count) and CMD25(Write _ Multiple _ Block) are sent on the CMD signal line 6, and the diagram illustrates that the data line 5 transfers the first and last data blocks and indicates one of "buffer busy/ready" and "program busy/ready" using the dual busy signal 4 driven by the card 2.

As an alternative embodiment, separate busy lines may be used for different types of status indications (e.g., for buffer status and program status in this case). However, this approach would require more physical pins and would not be backward compatible.

In contrast to the previous use of busy signal 4, according to aspects of the present invention, the meaning of busy signal 4 is changed within the same command (e.g., multi-block write) and between transferred blocks of data.

Within the scope of the exemplary embodiments of the present invention, host 1 programs MMC2 to select the operating mode for busy signaling. For example, MMC2 may default to regular use of busy signaling at power-on reset, but may then be programmed by host 1 to operate with multi-mode use of busy signaling (e.g., buffer busy/ready and programmed busy/ready). Alternatively, the power-up mode of operation may be defined as multi-mode use of busy signaling, while host 1 may then program MMC2 to utilize conventional busy/ready signaling.

In one aspect of the invention, embodiments of the invention provide a memory card 2 comprising a bus interface for coupling to a host 1 through a bus 3 comprising data lines 5. The bus interface comprises a driver 2A coupled to the data signal line and a receiver 2B also coupled to the data signal line 5. The receiver 2B is operable to receive first information from the host 1 through the data signal line 5. The driver 2A is operable to drive a change of state of the data signal line 5 (as a transition of the busy signal 4) to the host 1. The memory card 2 also includes control logic or controller 2C coupled to the driver 2A and the receiver 2B and operable to cause a change in state of the data signal line 5 to have a first meaning (e.g., "buffer busy/ready") after receiving first information from the host 1 over the data signal line 5 and a second meaning (e.g., "program busy/ready") after receiving second information from the host 1 over the data signal line 5.

The bus 3 further comprises a command signal line 6, and the controller 2C is responsive to at least one command received from the host 1 via the command signal line 6 to cause the state of the data signal line 5 to change to have a first meaning after receiving first information from the host 1 via the data signal line 5 and a second meaning after receiving second information from the host 1 via the data signal line 5.

The controller 2C may respond to programming received from the host 1 to determine the meaning of the change in state of the data signal line 5 as follows: has a first meaning after receiving first information from the host through the data signal line and a second meaning after receiving second information from the host through the data signal line, or has a first meaning after receiving first information from the host 1 through the data signal line 5 and also has a first meaning after receiving second information from the host 1 through the data signal line 5.

The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the best method and apparatus presently contemplated by the inventors for carrying out the invention. However, various modifications and changes may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims.

As just a few examples of alternative embodiments, one skilled in the art may attempt to use other similar or equivalent signaling protocols and module types. In addition, busy signal 4 may be made to assume more than two meanings during a single data transfer command. As an example, when three data blocks are transferred, the busy signal 4 may have a first meaning after the first data block transfer, a second meaning after the second data block transfer, and a third meaning after the third data block transfer. In this regard, the busy signal may be used to indicate a plurality of different states during execution of the multi-phase command. For example, assume a multi-phase erase command is used in which one or more addresses to be erased are sent on the command line, and in which busy signal 4 indicates that more one or more addresses may be sent after receiving one or more first addresses, and busy signal 4 indicates an erase state after sending one or more last addresses to be erased.

However, all such and similar modifications of the teachings of this invention will still fall within the scope of the embodiments of this invention.

Furthermore, some of the features of the exemplary embodiments of this invention could be used to advantage without the corresponding use of other features. Accordingly, the foregoing description should be considered as merely illustrative of the principles, teachings and embodiments of this invention, and not in limitation thereof.

Claims (21)

1. A method for interfacing a first unit to a second unit through a bus comprising signal lines, comprising:

driving first information from the first cell to the second cell through the signal line;

driving the signal line from the second cell to cause a state change;

the first unit interpreting the change of state of the signal line as having a first meaning and in response driving second information from the first unit to the signal line;

driving the signal line from the second unit to cause a state change again; and

interpreting the re-caused state change of the signal line that occurs after the first unit drives the second information to the signal line as having a second meaning different from the first meaning.

2. An apparatus for performing an operation of interfacing a first unit to a second unit through a bus including signal lines, the apparatus comprising:

means for driving first information from the first cell to the second cell through the signal line;

means for driving the signal line from the second cell to cause a state change;

means for causing the first unit to interpret the change of state of the signal line as having a first meaning and in response to drive second information from the first unit to the signal line;

means for driving the signal line from the second unit to cause the state change again; and

means for interpreting the re-caused state change of the signal line that occurs after the first unit drives the second information to the signal line as having a second meaning that is different from the first meaning.

3. An apparatus for interfacing a first unit to a second unit through a bus including signal lines, the apparatus comprising:

a driver coupled to the signal line at the first cell, the driver operable to drive first information and then second information from the first cell to the second cell through the signal line;

a receiver coupled to the signal line at the first unit, the receiver operable to receive a change of state of the signal line driven from the second unit after the second unit receives the first information and receives the second information; and

a controller to interpret the change of state of the signal line at the first cell as having a first meaning after the first information is driven from the first cell to the second cell through the signal line and a second meaning different from the first meaning after the second information is driven from the first cell to the second cell through the signal line.

4. The apparatus of claim 3, wherein the first unit comprises a host, and wherein the second unit comprises a memory card.

5. An apparatus for interfacing a first unit to a second unit through a bus comprising signal lines, the apparatus comprising:

a driver coupled to the signal line at the first cell, the driver operable to drive a change of state of the signal line to the second cell after receiving first information and after receiving second information;

a receiver coupled to the signal line at the first unit, the receiver operable to receive first information and then second information from the second unit over the signal line; and

a controller at the first unit to cause the change in state of the signal line to have a first meaning after receiving first information from the second unit through the signal line and a second meaning different from the first meaning after receiving second information from the second unit through the signal line.

6. The apparatus of claim 5, wherein the first unit comprises a memory card, and wherein the second unit comprises a host.

7. A method for transferring data from a first unit to a second unit over a bus, comprising:

initiating n block data transfers, wherein n > 1;

for the first n-1 data blocks transferred from the first unit to the second unit, controlling the status signal generated by the second unit to be a buffer busy/ready status signal after each of the first n-1 data blocks is transferred, thereby informing the first unit when the first unit can transfer the next data block; and

for an nth data block transferred from the first unit to the second unit, controlling the status signal to become a program busy/ready status signal after the nth data block is transferred, thereby informing the first unit that the second unit has terminated the internal programming if there is the internal programming.

8. The method of claim 7, wherein the first unit comprises a host, and wherein the second unit comprises a memory module.

9. The method of claim 7, wherein the first unit comprises a cellular telephone, and wherein the second unit comprises a memory card.

10. The method of claim 7, wherein the first unit receives the status signal transmitted after each of the n data blocks in an interrupt-driven mode of operation.

11. An apparatus for performing an operation of transferring data from a first unit to a second unit over a bus, the apparatus comprising:

means for initiating a transfer of n blocks of data, wherein n > 1;

means for controlling, for the first n-1 data blocks transferred from the first unit to the second unit, the status signal generated by the second unit to become a buffer busy/ready status signal after each of the first n-1 data blocks is transferred, thereby informing the first unit when the first unit can transfer the next data block; and

means for controlling the status signal to become a programming busy/ready status signal after the transfer of the nth data block for the nth data block transferred from the first unit to the second unit, thereby informing the first unit that the second unit has terminated the internal programming if there is the internal programming.

12. The apparatus of claim 11, wherein the first unit comprises a host, and wherein the second unit comprises a memory module.

13. The apparatus of claim 11, wherein the first unit comprises a cellular telephone, and wherein the second unit comprises a memory card.

14. The apparatus of claim 11, wherein the first unit receives the status signal transmitted after each of the n data blocks in an interrupt-driven mode of operation.

15. An apparatus for transferring data from a first unit to a second unit over a bus, comprising a controller to initiate a transfer of n blocks of data, where n >1, wherein for the first n-1 blocks of data transferred from the first unit to the second unit, the second unit controls a status signal to become a buffer busy/ready status signal after each of the first n-1 blocks of data are transferred, thereby informing the first unit when the first unit can transfer the next block of data; and for the nth data block transferred from the first unit to the second unit, the second unit controls the status signal to become a programming busy/ready status signal after the nth data block is transferred, thereby informing the first unit that the second unit has terminated the internal programming if there is the internal programming.

16. The apparatus of claim 15, wherein the first unit comprises a host, and wherein the second unit comprises a memory module.

17. The apparatus of claim 15, wherein the first unit comprises a cellular telephone, and wherein the second unit comprises a memory card.

18. The apparatus of claim 15, wherein the first unit receives the status signal transmitted after each of the n data blocks in an interrupt-driven mode of operation.

19. A memory card including a bus interface for coupling to a host through a bus including data signal lines, the memory card comprising:

a driver coupled to the data signal line and operative to drive a change of state of the data signal line to the host;

a receiver coupled to the data signal line and operative to receive first information from the host through the data signal line; and

a controller coupled to the driver and the receiver and operable to cause the change in state of the data signal line to have a first meaning after receiving the first information from the host over the data signal line and a second meaning different from the first meaning after receiving second information from the host over the data signal line.

20. The memory card of claim 19, wherein the bus further comprises command data lines, and wherein the controller is responsive to at least one command received from the host over the command signal lines such that the change in state of the data signal lines has the first meaning after receiving the first information from the host over the data signal lines and the second meaning after receiving the second information from the host over the data signal lines.

21. The memory card of claim 19, wherein the controller is responsive to programming received from the host to determine the meaning of the change in state of the data signal line as follows: having the first meaning after receiving the first information from the host through the data signal line and having the second meaning after receiving the second information from the host through the data signal line; or the first meaning after receiving the first information from the host through the data signal line and the first meaning after receiving the second information from the host through the data signal line.