HK1110700A

HK1110700A - Capacitors with high energy storage density and low esr

Info

Publication number: HK1110700A
Application number: HK08105098.2A
Authority: HK
Inventors: 奥弗‧斯内; 阿纳‧斯内
Original assignee: 桑德夫技术有限公司
Priority date: 2004-07-23
Filing date: 2005-07-20
Publication date: 2008-07-18

Description

Capacitor with high energy storage density and low equivalent series resistance

Technical Field

The present invention relates to the field of electronic components, and more particularly to an apparatus and method for constructing capacitors having high capacitance and high energy storage density, as well as low equivalent resistance.

Background

Capacitor devices have a variety of applications in the electrical, electronic and microelectronic fields. A number of different useful embodiments of capacitors have been successfully implemented and commercially applied. Capacitor characteristics such as capacitance density, operating voltage, energy storage density, Equivalent Series Resistance (ESR), heat resistance, and life span are continuously improved. Currently, significant efforts to reduce the cost and size of capacitors have significantly pushed the technology of automated production methods and achieved a satisfactory commercial state for most applications.

Capacitors can be used for energy storage, among which the benefits are fast response, compatibility of high voltages, and extended charge/discharge cyclingLife span (compared to battery). Electrolytic capacitors are more suitable for energy storage and other electrical energy applications, wherein a high capacitance density is obtained by combining the advantages of a large area anode and a corresponding high dielectric constant insulating layer with the contact characteristics of a liquid or solid electrolytic cathode. The technology of electrolytic capacitors is well known in the art and a wide variety of useful devices are currently available and commercially available in the marketplace. One particularly useful structure, aluminum electrolytic capacitors, employs as the anode a large area etched aluminum foil having an area increasing factor of substantially x 25 to x 100, and Al grown by anodic oxidation₂O₃The layer is employed as a dielectric layer. The cathode employs an additional aluminum foil and the contact between the cathode and the dielectric layer is generally accomplished by using an electrolytic solution.

The efficient incorporation of aluminum electrolytic capacitors into compact devices generally involves winding strips of anode/dielectric foil and cathode foil, separated by paper strips or other films suitable for electrolytic impregnation into a compact cylindrical shape, which are then impregnated with a suitable electrolytic solution to facilitate cathode contact.

Aluminum electrolytic capacitors are most commonly used in industry, with advantageously high capacitance density, relatively high voltage compatibility, and extremely low cost. However, the relatively short lifetime (on the order of only a few thousand hours at 85 ℃), relatively high and often degraded ESR, high leakage currents, polarity, and limited temperature range are just some of the undesirable features that have limited the application of aluminum electrolytic capacitors and tantalum electrolytic capacitors as energy storage devices or circuit components in high performance and high reliability electronic devices. Recent improvements in basic electrolytic capacitor technology have successfully employed solid polymer electrolyte solution contacts to increase the life span and useful temperature range with advantageously lower ESR. Clearly, the weak connection of aluminum capacitor technology relates to the electrolytic properties of the contacts.

Electrolytic capacitors have been generally very useful for achieving high capacitance densities, and they have failed to achieve satisfactorily long life, high voltage compatibility, extended temperature range, and low ESR. In contrast, the technology of film capacitors generally employs metallized polymer films in electrostatic capacitors to achieve very suitable high voltage compatibility, longer life, Alternating Current (AC) compatibility, and improved high temperature resistance. Thin film capacitors are economically mass produced by coating both sides of a polymer film with thin metal films, generally using physical vapor deposition techniques. Compact film capacitors are completed by winding strips of metallized polymer film into a roll. Alternatively, multilayer laminates of metallized polymer films have been achieved to have significantly reduced ESR for the entire capacitor. These film capacitors have advantages in terms of high voltage and AC performance, but are so far limited to relatively low capacitance densities. Additionally, the predominantly implemented polymer dielectric films are inherently limited to temperature ranges below 120 ℃, which means lower reliability in high power applications.

The high capacitance density of electrolytic capacitors is primarily due to the initial substrate having its relatively high capacitance area. Additionally, anodically polarized Al in aluminum electrolytic capacitors₂O₃Or anodically polarized Ta in Ta electrolytic capacitors₂O₅Has a dielectric constant of ∈ accordingly_rAbout 8 and e_r25 far exceeding epsilon for suitable polymer films_rA normal dielectric constant of 2. The capacitance follows the following equation:

img id="idf0001" file="A20058003190600141.GIF" wi="257" he="38" img-content="drawing" img-format="GIF"/

wherein epsilon₀Is the vacuum permittivity,. epsilon_rIs the relative permittivity of the dielectric material, a is the effective area of the capacitor, and d is the thickness of the dielectric layer. In fact, the thickness of the dielectric layer is determined by the specification of the voltage that can be reliably applied to the capacitor without causing catastrophic breakdown or degradation over the lifetime of the capacitor. E.g. d ═ V/E_DBIn which E_DBIs the dielectric breakdown field of the dielectric layer. In practice, capacitors are typically scaled down to ensure extended life, and dielectric thicknesses are typically extended by a factor of x 1.5 to x 2.

Fig. 1 shows a schematic layout structure of an aluminum electrolytic capacitor. Thus, the capacitor 100 is made by winding the laminate of the foils 150 into a compact roll having a cylindrical shape. The foil is cut into longer strips prior to the winding process. Foil stack 150 includes an anodic aluminum foil 102 having an etched large area surface 103; and Al formed by anodic oxidation processing₂O₃A dielectric layer 104. The cathode aluminum foil 106 includes Al₂O₃Generally substantially thinner than the thickness of the dielectric layer 104. The surface of the cathode foil 106 is modified by etching, typically to a much smaller extent than the area enhancement 103 of the anode foil 102. A paper foil 110 is inserted between the anode foil and the cathode foil before winding the capacitor. After winding, the foil 110 is saturated with the electrolytic solution and cathode contacts are formed by the electrolytic solution penetrating into gaps 112 and 114 between the foil 110 and the anode 102 and the foil 110 and the cathode 106, respectively. Clearly, the capacitor ESR is related to the consistency of the electrolytic solution in the gaps 112 and 114. A capacitor generally comprises an equivalent circuit of two capacitors connected in series, with the larger capacitor formed on the anode and the smaller capacitor formed on the cathode. These capacitors are primarily suitable for Direct Current (DC) applications, where the voltage polarity is kept approximately positive at the anode.

Electrolytic capacitors generally exhibit continuous degradation of ESR corresponding to degradation of the electrolytic cathode contact. Subsequent production yield improvements depend on further anodizing the electrolytic solution of the dielectric defect to repair the locally cracked and thinned dielectric site by anodic oxidation growth at the local defect. This growth is enhanced at the defect due to the significantly high local current.

Capacitors having capacitance values roughly in the range of 0.01 to 1 muf are employed in large numbers on conventional PC boards (PCBs) to form useful electrical and electronic circuits, and thus occupy a significant portion of the PCB area. Additionally, the cost involved in the assembly of discrete capacitors on a PCB, and sometimes yield reductions and failures involving hundreds of solder joints, are significant. Finally, performance limitations related to capacitors with respect to PCB contact resistance and inductance are sometimes difficult to overcome. Accordingly, the electronics industry has been working on integrating capacitors into capacitor arrays, and more recently into the layout structure of practical PCBs. The complete integration of the capacitors into the PCB may advantageously reduce the area occupied by the capacitors while further reducing the size of the electronic device. Significant cost and weight reduction is an additional advantage. Additionally, performance limitations related to contact resistance and inductance are also expected to be greatly reduced by this integration.

However, the disadvantageous aspects of the integrated capacitor are clearly and clearly a need for higher levels of PCB customization, and a potential PCB yield reduction involving defective capacitors. Whereas customization is not foreseen to give the problem of inevitable changes of PCBs to full customization, the industry is looking for integration techniques that are compatible with current PCB manufacturing techniques and are quickly and easily configurable as needed to continually upgrade and improve customized electronic products, sometimes for just a few months. Thus, the integrated capacitor yield must be as close to 100% as possible, and/or sometimes some capacitor redundancy is required to support lower cost PCB production and reduce the insurmountable cost of PCB inspection.

There is a need for a capacitor with improved energy retention density that has both higher capacitance density and high voltage compatibility while maintaining a lower ESR. These capacitors should preferably have an extended lifetime over an extended temperature range. Additionally, there is a need for improved formation and extended life of high capacitance capacitors and increased specific capacitance per unit volume and weight. There is also a need for such a method that enables the integration of capacitors into the layout structure of PC boards without significantly altering current production techniques, while maintaining the ability of existing PC board production lines to quickly and efficiently customize their products. In particular, low cost capacitor device layout structures and associated production methods are desired.

Disclosure of Invention

Atomic Layer Deposition (ALD) has emerged as a possible deposition method in integrated circuit thin film applications. Up to now have not been considered for macroscopic applications, such as electrolytic capacitors. ALD has until now been considered a too slow process to produce fifty micron thick films generally associated with these applications. ALD is a cyclic process that is implemented by dividing a conventional CVD process into an iterative sequence of self-terminating process steps. An ALD cycle includes multiple (at least two) chemical dosing steps in which active chemicals are delivered independently into a process chamber. Each dosing step is typically followed by an inert gas purge step that eliminates the active chemistry from the process space before introducing the next precursor. In this approach, ALD is applied (lay down) films, one atomic layer after the other. Thus, to produce fifty micron films, using this technique has been considered quite laborious and too slow for commercial purposes.

However, ALD also provides robust and atomic-level control of film thickness and properties without the need for in-situ detection. It deposits a continuous and uniform film on any three-dimensional surface structure, penetrating the narrowest and deep grooves, channels and cavities. Thus, ALD films have unique pinhole free (pinhole free) and low stress characteristics, which may reflect their suitability for high-throughput production of large-area devices.

In recent years, there has been a clear trend toward the use of Atomic Layer Deposition (ALD) films in semiconductor production. In the next decade, the critical dimensions of integrated circuits are scaled down to only 10 to 25 atomic layers. Therefore, atomic layer level control of film thickness and properties is necessary. ALD grown films in a unique layer-by-layer manner allows conformal and uniform growth to challenge the difficult substrate topology with atomic-level control and is currently the only well-known film deposition technique that has proven to meet this pressing need. Thus, ALD remains a key to the future of IC processes and many other technologies.

In an ALD process, the deposition thickness per cycle is precisely and repeatedly indicated by a self-saturating mechanism. Deposition is the result of a chemical reaction between the reactive molecular precursor and the substrate. Like CVD, elements comprising films are delivered as molecular precursors. The net reaction (net reaction) must deposit a pure desired film and reduce the "extra" atoms that make up the molecular precursor. In the case of CVD, molecular precursors are fed simultaneously into the CVD reactor. The substrate is maintained at a temperature optimized to promote chemical reactions between the molecular precursors while efficiently absorbing the byproducts (so that the byproducts are not incorporated into the film). Thus, this reaction is performed to deposit a desired pure film. Table 1 summarizes the major differences between ALD processing and CVD processing.

Table 1.1: comparison between ALD and CVD

	CVD、PVD	ALD
	CVD、PVD	ALD	Growth mode	Continuous	Step-by-step layer by layer

Growth rate	Variable	The growth of each step is accurately controlled
Growth rate	Variable	The growth of each step is accurately controlled	Thickness control	Speed x time	Is determined with a selected number of steps
Initiation of growth	Nucleation and grain growth	Continuous film	Thickness control	Speed x time	Is determined with a selected number of steps
Initiation of growth	Nucleation and grain growth	Continuous film	Film characteristics	Pinhole, compressive stress	Pinhole free, negligible stress
Shape retention property	Change and are difficult to maintain	100% and for the most complex 3D structures	Film characteristics	Pinhole, compressive stress	Pinhole free, negligible stress

ALD provides many advantages over many other conventional techniques and is best suited for some applications dealing with thin film deposition. The ALD film can be grown exclusively continuously on the substrate, preventing inferior discontinuous transition caused by nucleation. As a result, ALD films are pinhole free and grow virtually stress free. All other deposition techniques initiate film growth by nucleation. Nucleation is the result of local bonding between the substrate and the growing film. In the case of CVD, for example, molecular precursors are attached to a surface primarily through CVD reactions between reactive precursors on the surface. Nucleation is followed by grain growth. After the grains eventually terminate the composite continuous film, the thickness may be on the order of 5nm to 10nm in the case of CVD, and even thicker in the case of Physical Vapor Deposition (PVD). Films initiated by nucleation exhibit significant compressive stress and abundant pinholes that extend beyond the junction depth. Pinholes and compressive stress are associated with non-ideal grain boundaries and generally reflect that CVD and PVD films are not suitable for passivation and encapsulation applications at layer thicknesses of less than 500 nm.

The ALD film may be grown continuously to any thickness if the surface of the substrate is fabricated to be reactive to one ALD precursor. In this case, the ALD film may be grown continuously layer by layer from the interface all the way. The ability to initialize the surface and grow layer by layer starting from the first layer enablesALD films are continuous, low stress, and pinhole free; this is thus a desirable choice for devices with substrates having a high capacitance area, where reliability and yield mainly depend on the number and density of defects. For example, ALD dielectric films were developed for DRAM capacitor applications where they were demonstrated to have over 10000cm²The area of real area of (a) is increased to maintain near 100% throughput for ultra thin films in the-5 nm range. Additionally, Al₂O₃Dielectric films are predominantly preferred over PVD films in the magnetic data storage industry where magnetic sensors are produced with practical 100% throughput using ALD. Finally, ALD films for device packaging applications have shown significant device reliability improvements, representing pinhole-free encapsulation on large-size flat planar devices, as well as other devices. As a result, very thin encapsulation films can be achieved by ALD, which has a minimal negative impact on device performance. For example, IC devices may be packaged at the wafer level with minimal impact on performance or subsequent packaging process flows.

Because of their superior low defectivity and conformality, ALD films are well suited for the deposition of dielectric and conductive films for high energy and capacitance applications.

It is an object of the present invention to provide a method of manufacturing a capacitor having improved capacitance and energy density while maintaining a low ESR. It is another object of the present invention to improve the device layout structure of an electrolytic capacitor and form an electrostatic capacitor device layout structure by replacing an electrolyte with a highly conformal conductive film, thus constituting an electrostatic capacitor mainly employing an electrolytic capacitor manufacturing technique. Yet another object of the present invention is to improve the temperature resistance and life time of high capacitance and high energy density capacitors. It is another object of the present invention to provide a capacitor device layout structure and associated method of manufacture that is compatible with Alternating Current (AC). It is another object of the present invention to provide a capacitor that can be integrated into a PC board.

In one aspect of the invention, capacitor yield is improved by employing a method and apparatus for repairing defects in a capacitor dielectric layer. In another aspect of the invention, capacitor yield is further improved by adopting local, low dielectric, breakdown point "self-healing".

In another aspect of the invention, the Equivalent Series Resistance (ESR) of the high capacitance and high energy density capacitor is significantly reduced by significantly reducing the contact resistance with both the anode and cathode.

The present invention achieves a high capacitance area anode substrate that is commonly used in the manufacture of electrolytic capacitors along with the formation of high quality dielectric and conductive films to produce electrostatic capacitors with significantly improved capacitance density, lifetime, and temperature resistance. Advantageously, the present invention proposes a layout structure and a manufacturing method that realize a capacitor with high capacitance density and high energy density with extremely low ESR. Additionally, the present invention relates to a feasible solution for capacitor-PCB integration.

A method for repairing defects in a capacitor dielectric layer includes ALD deposition into the defects, applying an ALD film to at least a portion of the dielectric layer, and biasing the dielectric layer in an oxidized state. Additionally, the entire capacitor foil stack is biased to substantially remove the conductive contact film from the weak spot by means of local heat generation and evaporation and/or oxidation of the contact layer from the weak spot.

In one aspect of the invention, a capacitor comprises a capacitor foil. The capacitor foil comprises a metal foil. The metal foil is chemically etched to obtain a high capacitance area. The capacitor foil further comprises a conformal and substantially uniform dielectric layer grown over the metal foil; and a substantially uniform and conformal conductive layer grown over the dielectric layer. In another aspect of the invention, the capacitor preferably includes an additional metal foil that preferably forms a substantial electrical contact with a portion of the conformal conductive film. In another aspect of the invention, at least a portion of the conformal conductive film is grown, preferably by ALD. In another aspect of the invention, the capacitor foil preferably includes an additional conductive layer, which is preferably in substantial electrical contact with the conformal conductive film. Preferably, the capacitor further comprises an additional metal foil, and the additional metal foil preferably makes substantial electrical contact with a portion of the additional conformal conductive film. In another aspect of the invention, the capacitor foils are preferably formed as strips, the additional metal foils are preferably formed as strips, and the strips preferably have substantially the same width and length; and the strips of capacitor foil and the additional strips of metal foil are preferably wound to form a significantly compact capacitor core shape. In a further aspect of the invention, the electrical contacts are preferably formed on a flat face of the condenser core. The electrical contact preferably comprises a first insulating portion attached to an edge of said additional metal foil on a first of said planar faces; preferably a first electrical contact formed on said first face in contact with an edge of said metal foil; a second insulating portion attached to an edge of the metal foil on a second one of the flat faces; and preferably a second electrical contact formed on said second face in contact with an edge of said additional metal foil. In a further aspect of the invention, the electrical contacts are preferably formed on planar faces of the condenser core, preferably comprising a first insulating portion attached to an edge of the additional conductive layer on a first one of the planar faces; preferably a first electrical contact formed on said first face in contact with an edge of said metal foil; a second insulating portion attached to an edge of the metal foil on a second one of the flat faces; and preferably a second electrical contact formed on said second face in contact with an edge of said additional conductive layer. In another preferred aspect of the invention, the capacitor foil is preferably formed as a strip and is preferably wound to form a substantially compact capacitor core shape. In another aspect of the invention, the capacitor preferably comprises a capacitor core laminate comprising a first metal foil and a repeatable laminate. The repeatable laminate preferably comprises a selected number of foil pairs and each foil pair preferably comprises said capacitor foil and an additional metal foil. In another aspect of the invention, the capacitor preferably comprises a capacitor core laminate of capacitor foils. Further, the capacitor core stack is preferably cut into capacitor core parts, and the electrical contacts are preferably formed on two parallel sides of the capacitor core parts. These electrical contacts preferably comprise a first insulating portion attached to an edge of said additional metal foil on a first of said two parallel sides; a first electrical contact formed on the first side in contact with an edge of the metal foil; a second insulating part attached to an edge of the metal foil on a second side of the two parallel sides; and a second electrical contact formed on the second side in contact with an edge of the additional metal foil. In another preferred modification of the present invention, the capacitor core stack is preferably cut into capacitor core parts, and the electrical contacts are preferably formed on two parallel sides of the capacitor core parts. The electrical contact preferably comprises a first insulating portion attached to an edge of the additional conductive layer on a first of the two parallel sides; preferably a first electrical contact is formed on the first side in contact with an edge of the metal foil; a second insulating part attached to an edge of the metal foil on a second side of the two parallel sides; and preferably a second electrical contact formed on the second side in contact with an edge of the additional conductive layer. In a preferred aspect of the invention, at least a portion of the dielectric layer is preferably formed by ALD. In another preferred aspect of the present invention, at least a portion of the dielectric layer is preferably formed by anodic oxidation. In another preferred variant of the invention, a part of the dielectric layer is preferably formed by anodization, a part of the dielectric layer is preferably formed by ALD, and the thickness of the ALD part is preferably selected to increase the breakdown voltage of the dielectric layer significantly. In a preferred aspect of the invention, the capacitor foil is preferably electrically biased, wherein the electrical biasing preferably comprises applying an electrical potential between the metal foil and the conformal conductive film, and the electrical potential is preferably selected to increase the breakdown voltage of the dielectric layer without significantly reducing the capacitance of the capacitor foil. In another aspect of the invention, the capacitor foil is preferably electrically biased, wherein the electrically biasing preferably comprises applying an electrical potential between the metal foil and the conformal conductive film, and the electrical potential is preferably selected to reduce leakage current through the dielectric layer without significantly reducing the capacitance of the capacitor foil. In another preferred aspect of the invention, the dielectric layer is preferably electrically biased, wherein said electrically biasing preferably comprises applying an electrical potential between the metal foil and an electrolyte, said electrolyte preferably providing electrical contact with the dielectric layer, and the electrical potential is preferably selected to increase the breakdown voltage of the dielectric layer without significantly increasing the thickness of the dielectric layer. In another aspect of the invention, a preferred application of the capacitor foil is mounted to a PCB, and the PCB comprises electrical contact pads. Mounting preferably includes substantially achieving low ESR electrical contact with the electrical contact pads, and the capacitor foil is then preferably scored to define the capacitor. The defined capacitor preferably comprises a selected capacitance, and the selected capacitance is preferably determined by the unit capacitance of the capacitor foil and the area of the defined capacitor. Preferably, the integrated capacitor is embedded in the layer structure of the PCB. A preferred material for the metal foil according to an aspect of the present invention comprises aluminum. A preferred material for the dielectric layer according to another aspect of the present invention comprises alumina. A preferred material for the conformal conductive film comprises titanium nitride. In a preferred aspect of the invention, the high-capacitance area region of the metal foil includes an area increasing region greater than 10 x. In another preferred aspect of the present invention, the capacitor foil preferably includes high capacitance area regions on both sides, and the dielectric layer is preferably grown on both sides of the metal foil, and the conformal conductive film is preferably grown on the dielectric layer on both sides of the capacitor foil.

The present invention also provides a capacitor manufacturing method comprising applying a metal foil of a high capacitance area, subsequently oxidizing the entire area of the foil of the high capacitance area, and conformally growing a conductive film on the dielectric film to manufacture a capacitor foil. Preferably, the method further comprises winding the capacitor foil into a capacitor core, and the capacitor core has two faces, electrically contacting an edge of the high capacitance area metal foil on a first face and electrically contacting an edge of the conductive film on a second face. In a preferred modification of the present invention, the capacitor manufacturing method further comprises laminating the capacitor foils into a capacitor core laminate, cutting the capacitor core laminate into capacitor core pieces, selecting two parallel side portions on the capacitor core pieces, electrically contacting an edge of the metal foil of the high capacitance area on a first side portion, and electrically contacting an edge of the conductive film on a second side portion.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate preferred embodiments of the invention and together with the description, serve to explain the principles of the invention. In the drawings:

fig. 1 schematically shows a prior art layout structure of an aluminum electrolytic capacitor;

FIG. 2 schematically illustrates a layout structure of a high energy storage density capacitor according to the present invention;

FIGS. 3a and 3b schematically illustrate the mechanism of defect repair according to the present invention, wherein ALD dielectric film deposition is achieved to adhere to dielectric films grown by anodic oxidation;

FIGS. 4a and 4b show cross-sectional SEM images of structures according to the present invention that are seamlessly filled with ALD films;

FIGS. 5a to 5e schematically show structures according to the present invention filled with ALD gaps;

FIGS. 6a and 6b schematically illustrate the layout of a high energy storage density capacitor according to the present invention using a thicker cathode film or a thicker deposited cover film with less ESR;

FIGS. 7a and 7b schematically illustrate a layout of a high energy storage density capacitor according to the present invention utilizing an offset anode foil to reduce ESR after winding of the cathode foil with the anode dielectric contact foil;

figures 8a to 8d schematically illustrate the manufacture of low resistance contacts to an anode and a cathode according to the invention;

FIG. 9 schematically shows a cross-sectional view of a completed capacitor according to the present invention;

10a to 10c schematically illustrate the manufacture of low resistance contacts to an anode and a cathode according to the invention;

FIG. 11 schematically illustrates a multilayer stacked capacitor layout structure according to the present invention;

figure 12 schematically illustrates a multilayer stacked capacitor layout structure according to the present invention;

FIG. 13 schematically illustrates a layout of a distributed capacitor made from a single layer of stacked capacitor foils in accordance with the present invention;

fig. 14 schematically illustrates a layout structure of a PCB-integrated capacitor according to the present invention; and is

Fig. 15a and 15b schematically show a high energy storage capacitor according to the invention.

Detailed Description

A. Area increased electrostatic capacitor

A key aspect of the present invention is the fabrication of macroscopic electronic devices such as macroscopic capacitors utilizing conformal layers that are deposited utilizing Atomic Layer Deposition (ALD). These devices may be used as distributed electronic components, components of hybrid circuits, counterparts to integrated circuit boards, and other applications. In the present specification, "macroscopic" means that the size of a single electronic component such as a single capacitor is 200 micrometers or more. Preferably, the individual electronic components are 2000 microns or larger.

In an exemplary preferred embodiment of the invention, an etched aluminum foil is applied as the starting substrate. Commercially available etched aluminum foils are mass produced for use as electrolytic capacitor anodes as is well known in the art. These foils can, for example, be from 25 μm to 250 μm with a specific area increase up to x 100. Fig. 2 shows a capacitor 200 comprising an etched aluminum foil 202, a dielectric layer 204, and a contact layer 206 forming an electrical contact 210 to a cathode aluminum foil 208. Various etched aluminum foils can be applied as the anode 202 with an area increase ranging from x 25 to x 100. Such high capacitance area substrates are characterized by a finely etched structure that is most suitable for use with relatively thin dielectric layers 204, ranging from 10nm to 200 nm; and thus, the substrate is suitable for low voltage capacitor applications ranging from 5V to 100V. A lower area increase is suitable for thicker dielectric films ranging from 0.2 μm to 2 μm (and even thicker) and correspondingly for higher voltage capacitor applications ranging from 100V to 1000V.

The characteristic area increase of the foil 202 is chosen to best suit the characteristics of the capacitor. For example, foil 202 is implemented by using a conventional aluminum foil having a thickness of 50 μm and an area increase of 40, wherein the aluminum foil generally has a uniform etched pattern of 10 μm to 25 μm protruding into the foil from both sides. Such etched structures comprise deep holes, having a width in the range between 2 μm and 4 μm, penetrating substantially vertically from the surface of the foil. The density of the foil 202 is reduced to 1.5 grams/cm by etching³. The dielectric layer 204 is preferably formed by anodization, as is well known in the art. Other suitable methods of forming the dielectric layer 204 with improved throughput are described below, including highly conformal film growth using Atomic Layer Deposition (ALD) or a combination of anodization and supplemental ALD grown films. The contact layer 206 is formed using ALD to produce a conformal electrode that adheres to the dielectric layer 204. As described above, ALD is best suited for highly conformal high quality film deposition onto substrates with high capacitance areas. For example, a 50nm TiN film having a resistivity of 300 μ Ω cm is suitable. Alternatively, a laminate of 5nm TiN and 45nm W was achieved with a resistivity of 10 μ Ω cm to improve ESR through better contact resistance.

The capacitor 200 is formed by cutting a strip 250 from a foil 202 (now wrapped with layers 204 and 206) with an unetched capacitor stageAluminum foil sheet 208 is wound together to form a layered, generally cylindrical shape. Foil 208 generally has a thickness of 5 μm and a grain/cm of 2.7³The density of (c). Such a layered structure is shown in schematic cross-sectional view in the insertion region in fig. 2. The contact between foil 208 and layer 206 generally comprises only a portion of region 210. A portion of the region 212 corresponding to the porous extension in the etched hole does not directly contact the foil 208. However, the contact resistance in the hole is relatively small as described below.

In one particular embodiment of FIG. 2, a 2cm by 500cm strip of foil 202 is applied to 1 μm of dielectric Al₂O₃Layer 204. Area increase includes x 40 increased surface area and use of both sides of the foil to create-80000 cm²The actual area of (a). The capacitor has a capacitance of C-566 μ F and is suitable for 500V applications when a 50% de-rating is used. Alternatively, a 10V capacitor is formed with a 100 x incremental foil 202 and a 20nm thick dielectric layer 204. For the area increase of both sides of the foil 202 and for the applicability, a strip of 2mm x 10cm area has 400cm²The actual area of (a). The capacitor has a capacitance of C-140 muF, which is for-0.025 cm³Is significant in terms of the smaller volume (-3 mm diameter when wound on a teflon rod of 1/16 "outer diameter) and weight (-0.02 gram). Thus, a capacitance density of 7000 μ F/gram was obtained.

B. Yield increasing method

Electrolytic aluminum capacitors generally fail after the capacitor ESR degrades beyond a useful range. Dielectric failure is generally prevented by a self-healing mechanism due to the electrochemical formation of a dielectric layer that thickens at a weak point. The weak point can be described as a locally thin dielectric region that is involved in imperfections in the anodization process. For example, fig. 3a schematically illustrates a local thin spot 222 formed in the dielectric layer 220. Cracks or other defects such as 222 are unavoidable in the anodizing process due to significant expansion of the aluminum after oxidation (greater than x 1.4 at room temperature) and the factors generated in the anodizing processLong Al₂O₃On an aluminum substrate with Al₂O₃At the interface between the layers and at the Al already formed₂O₃Grow downward, thus significantly pressing the Al that has been formed₂O₃. The locally thin spots tend to dielectric breakdown at a significantly lower voltage than a completely thick area of layer 220. Thus, when the electrolytic capacitor is subjected to a full rated voltage, the local thin point breaks down and emits a relatively high current, which is localized at the breakdown point. The current draws additional anodic oxidation, which is caused by the thick local Al₂O₃Approximately "repairing" these points. The repair process stops when the dielectric breakdown transitions to "off," i.e., when the dielectric thickness at that point reaches the appropriate thickness. This useful mechanism of "aging" is a key advantage of electrolytic capacitor technology, allowing capacitors of greater capacitance to be produced in high yields. However, this "self-correcting" mechanism depends on the electrolyte supplying the oxidation process with oxygen.

In the electrostatic capacitor layout structure disclosed in the present invention, the electrolytic solution is replaced by the solid conductive film 206 (fig. 2), and the final capacitor does not have the "self-correcting" characteristic. However, utilizing an anodization technique to form the dielectric layer 204 is still desirable in most cases. Thus, the embodiment shown in FIG. 3b employs anodized Al₂O₃Layer 220 and ALD Al₂O₃A stack of layers 224 to provide defect repair by conformally filling ALD film 226 into local thin spots 222 during formation of layers 224. When the width of the local defect is less than half the thickness of layer 224, the ALD technique is demonstrated to seamlessly fill structure 222 up to the total thickness of the combined layers 220+224, as shown in fig. 3 b.

Figure 4 shows an SEM image of a 400nm thick ALD film 22+24+26 deposited on a complex device structure (figure 4 a). The device layout structure prior to deposition includes cracks 18 and 20, and trench structure 12, which is substantially narrower than 2 x 400 nm. Fig. 4b shows the layout structure of fig. 4a more clearly. In FIG. 4b, the ALD film is also divided into three "layers" to illustrate the continuous growth and filling of structure 12. Note that the continuous and seamless filling of structures 18 and 20, undesired cracks during the metallization process, respectively, involves some delamination of metal structures 4 and 6. Also note that structure 12 (although not a defect but a set structure) is completely and seamlessly filled with ALD film. Also, ALD films have precisely 400nm thickness in all regions that do not correspond to structures narrower than 800nm, where a fully conformal film does not control to completely fill the structure. It is clearly clear that at the structure 16 it is only slightly wider than 800nm and, thus, is preferably conformally coated rather than enclosed.

As shown in fig. 4, when the thickness of the layers 22+24+26 exceeds the width of a crack or half of a structure such as the region 12, the structure (or defect) is completely filled and the thickness of the ALD layer above the crack minus the depth of the crack is equal to the thickness of the layers 22+24+26 over the entire region. This seamless gap-fill characteristic contributes to the layer-by-layer growth mechanism of ALD and is further illustrated in fig. 5.

In fig. 5a, a recess 67 has been formed in the layer 66. As shown in fig. 5b, an initial layer of dielectric film 70 is grown by ALD adhesion over the entire surface area of the device profile. The employment of ALD causes the layer of dielectric film 70 to completely cover the surface area of the already existing structure including the recess 67. The thickness of the dielectric film 70 is increased by successive depositions of additional layers of dielectric film. As schematically shown in fig. 5c, the dielectric film 70' is grown to a thickness slightly smaller than the width of the recess 67. It should be clear to those skilled in the art that the layer-by-layer deposition of the dielectric film 70 'is schematically illustrated in the figures by the dashed line separating the dielectric film 70' into a layered structure. However, it is also clear that due to the conformal nature of ALD films, in practice, the dielectric film 70 'forms a single seamless, conformal film, regardless of the number of discrete layers of dielectric material deposited to form the dielectric film 70'.

As shown in fig. 5d, the dielectric film 70 "is finally grown to a thickness that seamlessly closes the recess 67. Thus, it should be apparent that the thickness of the dielectric film 70 "is grown to be approximately equal to one-half the width of the recess, or approximately equal to one-half the thickness of the device layer 66, to form the plug 72. Thus, a closed portion is formed between the corresponding portions of the dielectric film 70 ″ covering each side of the recess. The position of the closure is shown by arrow 82. Subsequent layers of dielectric material may be further deposited on the surface of the dielectric film 70 ". After the recess 67 has been filled, each such continuous layer will be conformally deposited to form an additional thickness over the entire area of the already present dielectric film 70 *, as shown in fig. 5 e.

Since the local defects are relatively small, a relatively thin cladding layer 224 (fig. 3b) is necessary to "repair" the anodized layer 220. For example, a layer 224 having a thickness ranging from 10nm to 50nm is suitable for most applications. Thus, the 500V capacitor with a dielectric thickness of 1 μm given in the above example is made substantially of anodized Al₂O₃Dielectric layer made of ALD Al₂O₃The thin coating of the film is complementary. Anodization and ALD Al of 950nm to 990nm and 5nm to 10nm are recommended accordingly₂O₃And (4) combining the layers. In contrast, in the above example, for a 10V capacitor with only 20nm dielectric film, it is appropriate to finish the entire dielectric film with ALD.

In certain applications, it is preferable to employ ALD films to form the entire dielectric layer even for high voltage capacitors. These include making capacitors on substrates made of materials other than aluminum (e.g. etched nickel foil, compressed powder substrates), or with materials such as Ta₂O₅、HfO₂、ZrO₂、TiO₂And combinations of these layers, and aluminum oxide or silicon oxide in the form of alloy and/or nanolayers as are well known in the art of ALD technology. For example, capacitors for very high temperature applications utilize Al₂O₃The ALD film is formed attached to a nickel foil to realize a dielectric layer. In another example, 1: 3 Al₂O₃∶Ta₂O₅The ALD alloy layer is formed on an etched aluminum foil substrate, advantageously in combination with epsilon_rA high dielectric constant of 16 and a high dielectric strength of 7MV/cm so thatHigher capacitance x voltage density. Alloy and nanolayer techniques, well known in the art of ALD technology, have also proven that films of very low defect density can be made from materials that are otherwise considered inferior. For example, TiO₂And Ta₂O₅The 1: 1 alloying treatment is suitable for producing high-quality amorphous dielectric layers having an epsilon_rBreakdown voltages of 32 and > 5MV/cm, giving a voltage exceeding Al₂O₃X 2 increased capacitance density of the dielectric.

The advantages of low cost anodization, defect reduction, and increased capacitance density can be achieved by anodizing, e.g., 50nm, of Al when implemented on aluminum foil sheets having an area increase of 75 to x₂O₃Layers and coatings such as TiO₂/Ta₂O₅100nm, with an advantageous 50V credit and a capacitance density of 1600 μ F/gram, with the advantages of Al for 100nm₂O₃Only 760 muF/gram of equivalent capacitors of the dielectric body.

In another preferred embodiment of the present invention, anodized Al₂O₃Defects in the layer are repaired by an electrolytic aging process. Thus, an anodized foil such as 202+204 in fig. 2 is sandwiched between two electrolytic paper foils, and a metal plate serves as the cathode. A contact is formed to the foil 202 to serve as an anode. The laminate is immersed in an electrolytic solution to form a (rechargeable) flat electrolytic capacitor having two sides and a DC voltage is applied to complete the "aging" process, as is well known in the art of electrolytic capacitor production, which is done just after the dielectric "forming (anodization)" step and not after the completed capacitor. After "defect repair", the foils 202+204 are cleaned to remove the electrolyte.

Similar to self-healing of metallized thin film capacitors, the relatively thin electrode film is locally heated at the point of the defect by a highly localized current to locally evaporate the metal electrode and the point of weakness and thus isolate the point of weakness from the capacitor. Thus, the membrane 202 (fig. 2) comprising layers 204 and 206 is sandwiched between two larger plates, where the plates are grounded and serve as cathodes. After the foil 202 is electrically connected to the DC power supply, the thin layer 206 may be locally heated at the defect failure point due to the high current and locally reduce or oxidize the layer 206 at the weak point to provide "self-healing".

C. Low ESR capacitor

The main object of the present invention is to obtain a low Equivalent Series Resistance (ESR) capacitor. Layer 206 (fig. 2) embodiments with thin layers of ALD TiN or other conductive ALD films are more suitable for achieving low contact resistance in increased area structures. In general, a 50nm layer with only 60 Ω/□ TiN ALD film is sufficient to provide lower contact resistance in structures with large areas of 0.5 μm to 4 μm width and up to 20 μm depth. For example, an ESR of 1 μ Ω was applied to 10cm of the full layer stack 202+204+206²An area capacitor having a structure in which the area is increased to 40 or more and etched to a depth of 20 μm or less. Likewise, the 5/45nm TiN/W stack 206 will contribute an ESR of only 0.13 μ Ω per capacitor as described above. Therefore, the contact layer does not significantly affect the ESR. An embodiment of reducing the contact resistance of the entire capacitor is schematically shown in fig. 6a and 6 b. Fig. 6a shows a conformal conductive film 406 formed in capacitor layout structure 400 attached to dielectric layer 404. The film 406 forms a contact 420 with the foil 408 across the area of the foil 408. To improve the contact 420, the raw oxygen is preferably removed from the foil 408 before being wound with the foil 402 (stack 404+406 with the layers thereon). For example, aluminum foil 408 is etched in a dilute phosphoric acid solution. Optionally, in low temperature capacitor applications, a layer of conductive epoxy or glue (not shown) is interposed between the foil 408 and the layer 406. A further reduced contact 420 resistance enables a thin conductive non-oxide layer (not shown) on the foil 406, for example evaporated gold, preferably with a thickness in the range from 20nm to 50 nm. The modified contact 420 is preferably also obtained by coating the topside surface of layer 406 with a thin non-oxide film (not shown), such as gold, without exposing the environment, to substantially prevent contact damage due to the topside surface of layer 406Is degraded by oxidation. Optionally, materials such as ruthenium (Ru) deposited on the foil 408 and/or film 406 reduce contact resistance with their conductive oxides, namely RuO₂It can be formed on the surface of Ru without significantly increasing ESR. The layer implemented to reduce the resistance of the contact 420 need not follow the high capacitance area points, since the contact 420 is formed only at the surface facing the top side. Therefore, conventional Physical Vapor Deposition (PVD) techniques are suitable.

Although the capacitor layout structure described with reference to fig. 6a is suitable for low ESR applications, further improvements are obtained by taking a thick cap film in contact with layer 406. This embodiment further reduces the series resistance of the non-contact portion involving the region 424. Fig. 6b shows an embodiment 450. Film 458 is preferably formed attached to contact layer 406 'without environmental exposure to prevent oxidation of the surface of layer 406'. Layer 458 is formed, for example, by sputtering 0.5 μm to 1 μm of aluminum, as is well known in the art. Although this technique achieves a substantially higher contact area via the partial region 424 ', it need not substantially penetrate into a deeper, high capacitance area structure such as 422'. In some embodiments, the film 458 completely replaces the foil 408 (fig. 6 a). In most common applications, the relatively thin film 458 is implemented with or without a supplemental, non-oxide film on top to improve contact with the foil 408 (not shown). In another example, film 406' includes a metal such as copper or ruthenium as a seed layer for electroplating film 458 of copper or nickel. In this case, advanced electroplating techniques, well known to those skilled in the art of semiconductor and other device processing, are employed to substantially refill structure 422' and further reduce the ESR. In another embodiment, film 406' is implemented using ALD of TiN or TiN/W, while the seed layer for electroplating is implemented using sputtering or evaporation, preferably without exposing the environment. In this case, the seed copper, nickel or Ru film need not follow the entire structure of structure 422'. The plating film 458 forms contacts that extend into the structure 422' to such an extent that the seed layer can penetrate into the high aspect ratio structure. However, the PVD-seed/plating methods described herein are suitable for obtaining low ESR, which is suitable for extremely low ESR applications, such as high peak power storage capacitors. An electroless plating process is also suitable for attaching the conductive seed layer to form layer 458.

In an additional preferred embodiment of the present invention, layer 458 is deposited as continuous contact layer 406' using an ALD process. Layer 458 may be made of substantially the same material as layer 406' or a significantly different material. In another embodiment, layer 458 is deposited using a suitable CVD process and a suitable conductive material, such as tungsten (W). Layer 458 is preferably deposited without environmental exposure after deposition of layer 406'. In another preferred embodiment, the capacitor for relatively low temperature applications is made with a layer (not shown) of conductive epoxy or glue in place of layer 458. In this embodiment, a conductive material of suitable viscosity is applied to adhere to layer 406', as is well known in the art. Such application is accomplished, for example, by spraying, dipping, or rolling, and is preferably applied in a variety of applications with suitably low viscosity to adhere to layer 406' to establish a low resistance contact, preferably followed by application of higher viscosity to establish thicker layer 458.

After the manufacturing process, the capacitor film stack, including the base foil 402 (fig. 6b), the dielectric layer 404, the contact layer 406, and the conductive layer 458, is slit into strips of suitable length and width, having the desired capacitance. The foil is then rolled into a substantially compact shape to produce a compact and robust capacitor. Optionally, the strips of the capacitor film laminate 252 (fig. 7a) are wound with the strips 208' to produce a compact and robust capacitor with a significantly lower ESR structure. The film stack 252 may or may not include the layer 458. Preferably, the capacitor 200 'is fabricated with the strips 252 and 208' slightly offset, as schematically shown in fig. 7a and in a more detailed cross-sectional view in fig. 7 b. This process of offset winding produces gaps 254 and edges 256 on the lower 251 and upper 253 sides of the cylindrical capacitor, respectively. As schematically shown in the cross-sectional view in fig. 7b, the capacitor comprises alternating foils 202 ', dielectric layers 204', contact layers 206 ', and foils 208'. Optionally, the capacitor further comprises a layer 458 (not shown) as described above with reference to fig. 6 b.

After winding, underside 251 is etched to substantially remove layer 206 "(fig. 8a) from the exposed areas in gap 254'. Preferably, layer 206 "is over-etched to form recess 260. Alternatively, if layer 458 is applied as described above with reference to FIG. 6b, layer 458 is also etched from gap 254' and is preferably recessed (not shown) using an over-etch technique well known in the semiconductor and other device processing arts. Preferably, layer 206 "and layer 458 are etched in solution using a suitably selected etching technique known to those skilled in the art. For example, EDTA-H₂O₂-NH₄OH was used to selectively etch TiN without affecting Al₂O₃A dielectric layer 204 "or many other dielectric materials employed on the layer 204" attached to the aluminum foil 202 ". In another example, tungsten in layer 458 can be selectively etched using a hydrogen peroxide solution without significantly etching TiN, Al₂O₃Or aluminum, as is well known in the art. The technique of wet etching provides a number of different and suitably selective etching methods suitable for forming the processing stage 200 "(fig. 8a), showing a cross-sectional view of only the various layers. In process step 200 ", only the lower side 251 'of the capacitor is exposed to the etching medium, while the upper side 253' is prevented from contacting the etching medium. Preferably, the wound capacitor is partially immersed in the etching medium to keep the face 253' unexposed. Alternatively, the face 253' may be protected in a fixture or by a removable film, and the entire capacitor may be exposed to the etching medium.

In process step 200 * shown in fig. 8b, the capacitor is clad with a thick insulating layer. Fig. 8b shows corresponding portions 262 and 264 of the insulating layer on the bottom side 251 'and the top side 253' of the capacitor, respectively. However, the insulating layer preferably covers the entire capacitor. Preferably, the layers 262-264 are applied in a variety of applications using a dipping or spraying method, with a low viscosity solution being first applied to substantially penetrate into the gaps 254 'and recesses 260 and adhere to the edges 256' of the foil 208 ", followed by a higher viscosity solution to produce a substantially thicker layer, and followed by a suitable baking and/or curing of the layer, as is well known in the art. Layers 262-264 are selected to accommodate capacitor performance specifications and particularly suitable temperature ranges. For example, various epoxy materials are suitable for lower temperature ranges up to 100 ℃, while polyimide films are suitable for capacitors having temperature specification ranges up to 350 ℃ (e.g., Photoneece ® PWDC-1000 from Dow Corning). The higher temperature range is employed by coating materials such as BCESQ or other equivalent spin-on glass materials, where the temperature range is extended to-500 ℃. Alternatively, CVD or PE-CVD deposition layers 262-264, which are well known in the art, may be utilized to preferably fabricate capacitors having an extended temperature range in excess of 500 deg.C (care should be taken in this case to ensure that other structural materials are suitable for the higher temperature range. While layers 262-264 should preferably substantially penetrate into gap 254 'and adhere to edge 256', need not be preferably conformal, and may include voids at recesses 260 and other hard-to-reach corners without affecting capacitor reliability and yield. An insulating layer 262 and 264 is applied to insulate the edges of the foils 202 "and 208" from the contact layers formed at the top side 253 'and the bottom side 251', respectively, during a subsequent manufacturing step 200 * "as described below with reference to fig. 8 d.

In a subsequent process step 200 *' shown in fig. 8c, the capacitor faces 251 "and 253" are polished and then cleaned of debris, as is well known in the art. Bottom side 251 "is polished to remove a portion of insulating layer 262 and a portion of foil 202" leaving insulating inserts 266 between dielectric layer edges 204 * and simultaneously exposing edges 202 * of foil 202 ". Thus, the bottom of the foil 208 "and the layer 206" are encapsulated by the combination of the dielectric layer 204 * and the insert 266. Likewise, top side 253 "is polished to remove a portion of insulating layer 264 and a portion of foil 208", leaving insulating inserts 268 between edges 208 * of foil 208 ", and exposing edges 208 * of foil 208". Thus, the top of the foil 202 "is sealed by the insert 268. Similar polishing and debris removal techniques are successfully and cost-effectively applied to the fabrication of semiconductor interconnect layouts known in the semiconductor manufacturing art. Preferably, capacitor polishing and subsequent debris removal is applied to a large number of capacitors, which are preferably clamped together to form a large, 300mm diameter area, which allows the use of readily available polishing equipment commonly used in semiconductor manufacturing. Such an apparatus is generally suitable for "dry-in-dry-out" processing of wafers, wherein the entire polishing and cleaning is done automatically and repeatedly. Additionally, Chemical Mechanical Polishing (CMP) methods known in the art are used to improve the throughput of the process step 200 *' by substantially matching the erosion rates of the different materials being polished. The process step 200 *' preferably completes the polishing to obtain flat faces 251 "and 253" that are suitable for making electrical contact. However, other techniques, such as etchback (etchback), may be used by those skilled in the art to produce faces 251 "and 253".

In a subsequent processing step 200 * "(fig. 8d), electrical contacts 270 and 272 are formed attached to bottom side 251" and top side 253 ", respectively. The contact layers 270 and 272 are connected to substantially the entire edge of the foil 202 * 'and the entire edge of the foil 208 *', respectively, in order to significantly reduce the ESR. Contact layers 270 and 272 may be formed using a variety of different techniques known in the art. For example, conductive epoxy is used to fabricate capacitors for low temperature applications. Various brazing alloys and brazing techniques are suitable for fabricating the contact layers 270 and 272 while forming capacitors suitable for high temperature applications. The swaging technique, and the use of conductive epoxy, cement, and glue are also suitable for forming low resistance contacts with the exposed edges of foils 202 * 'and 208 *'. The layout structure of the preferred embodiment shown in fig. 8d achieves a very low ESR by contacting substantially the entire edges of foils 202 * ' and 208 * ' at bottom side 251 * and top side 253 *, respectively, while maintaining a high yield and high reliability if foils 208 * ' and 202 * ' are sealed at bottom side 251 * and top side 253 *, respectively, with interposer 266 ' and dielectric layer 204 * ', respectively, and interposer 268 ', respectively. This combination of parallel contact and substantially hermetic insulation is critical to the performance, yield and reliability of capacitors fabricated in accordance with the present invention.

In other processes, the capacitor is completed by connecting the contact pads and encapsulating the capacitor with a protective sleeve, as is well known in the art. For example, fig. 9 shows a schematic cross-sectional view of a completed capacitor, wherein the capacitor includes contact pads 274 and 276, which are in contact with contact layers 270 'and 272', respectively; and also includes a sheath 278.

In an additional embodiment, as described above with reference to fig. 6b, the capacitor layout does not include the foil 208' (fig. 7a) and the improved low ESR contact is obtained with a thicker contact layer 458 (fig. 6 b). Thus, the capacitor is formed by winding only one foil, wherein the foil (cross-sectional view of FIG. 10 a) includes the base foil 602, the dielectric layer 604, the contact layer 606, and the thicker contact layer 458'. Preferably, the layer 458' is made of a different material than the foil 602 to facilitate useful etch selectivity. In a subsequent processing step 600 shown in fig. 10a, layers 606 and 458' are selectively etched at bottom side 651 to form gaps 654 and undercuts 660. The top side 653 is then subjected to a selective etching process 600', which is shown in fig. 10b, to selectively etch the foil 602 and form a gap 686. In subsequent processing steps, the capacitor is sealed and polished, similar to the processing steps described above with reference to fig. 8b and 8c, to form the layout structure 600 "shown in fig. 10 c. Thus, the capacitor is prepared for low ESR contact formation by sealing the layer 458 'and the foil 602 with the inserts 666 and 668 at the capacitor bottom side 651 and the capacitor top side 653, respectively, and exposing the corresponding edges 688 and 690 of the foil 602 and the layer 458' at the bottom side 651 and the top side 653, respectively. In subsequent processing, the entire contact layer and pad and capacitor are fabricated in a similar manner to the process described above with reference to fig. 8d and 9.

Alternative capacitor layout structures and associated fabrication techniques utilize multilayer stacking techniques. The multilayer lamination technique is particularly suitable for manufacturing capacitors having a relatively small capacitance. For example, FIG. 11 shows a cross-sectional view of a multilayer stack formed from multiple stacked layers of foil 702, dielectric layer 704, contact layer 706, and thicker layer 758. For example, five layers are stacked to produce 354 μ F/cm for 10V applications (with 50% derate)²High capacitance area density using a 50 μm thick foil 702 etched to obtain a 100 x area increase; 20nm thick Al₂O₃A dielectric layer 704 on both sides; a 50nm thick TiN contact layer 706 on both sides; and 100nm tungsten layers 758 on both sides, having a total thickness of 0.25 mm. After the lamination process, the capacitor is cut into small area parts, for example 1.4 x 2mm capacitors, having a capacitance of 10 muf and an ESR of 0.02 to 0.03 omega. Having-70 μ FV/cm³The exemplary capacitor (after encapsulation) is about a 10-fold improvement over the prior art obtained with tantalum electrolytic capacitors. Such improvements are particularly advantageous given the leading significantly better performance, lifetime and temperature durability of the inherent electrostatic capacitors. Preferably a multilayer stack is prepared on a larger capacitance area foil and in turn cut into smaller sized capacitors. After dicing, the debris is removed from the edges using suitable cleaning techniques such as ultrasonically enhanced etching, as is well known in the semiconductor and other device processing arts. In subsequent processing steps, which are substantially similar to the processing steps described above with reference to fig. 10a to 10c, 8b and 8d, a capacitor layout structure 700 schematically shown in fig. 11 is formed. Thus, the capacitor is prepared for low ESR contact formation by sealing the layer 758 and foil 702 with inserts 766 and 768 at the capacitor first and second faces 751 and 753, respectively, and exposing the corresponding edges 788 and 790 of the foil 702 and layer 758, respectively, at the first and second faces 751 and 753, respectively, and then forming first and second contact layers 792 and 794, respectively. In subsequent processing, the entire contact pad and capacitor are fabricated similar to the process layout structure described above with reference to fig. 9And (4) obtaining.

Optionally, a multi-layer lamination technique is also applied to the additional foil 708 to further reduce the ESR as shown in fig. 12. In the particular implementation 700 'of fig. 12, the capacitor does not include a contact improving layer 758 between the foil 708 and the contact layer 706'. However, these layers and the additional oxidation inhibiting layer are suitable for this embodiment according to the above description. The multilayer lamination technique is particularly suitable for manufacturing capacitors having a relatively small capacitance. In the example of fig. 12, a cross-sectional view of a multilayer stack is shown, made up of a foil 702 ', a dielectric layer 704 ', a contact layer 706 ', and a foil 708, laminated together a plurality of times. For example, five layers are stacked to produce 354 μ F/cm for 10V applications (with 50% derate)²The capacitance area density of (a) using a 50 μm thick foil 702' that is etched to obtain a 100 x area increase; 20nm thick Al₂O₃A dielectric layer 704' on both sides; a 50nm thick TiN contact layer 706' on both sides; and 5.8 μm aluminum foil 708 on both sides, having a total thickness of 0.31 mm. After the lamination process, the capacitor is cut into small area parts, such as 1.4X 2mm capacitors, with a capacitance of 10 μ F (55 μ F/cm)³) And 10^-4ESR of Ω. After such dicing, debris is removed from the edges using suitable cleaning techniques such as ultrasonically enhanced etching, as is well known in the art of semiconductor and other device processing. In a subsequent processing step, which is substantially similar to the processing step described above with reference to fig. 8a to 8d, a capacitor layout structure 700' schematically shown in fig. 12 is formed. Thus, the capacitor is prepared for low ESR contact formation by respectively sealing the foil 708 'and the foil 702' with the inserts 766 'and 768' at the capacitor first face 751 'and the capacitor second face 753', respectively, exposing the corresponding edges 788 'and 790' of the foil 702 'and the foil 708', respectively, at the first face 751 'and the second face 753', respectively, and then forming the first contact layer 792 'and the second contact layer 794', respectively. In subsequent processing, the entire contact pad and capacitor are fabricated similar to the process layout described above with reference to fig. 9, and the capacitorThe final dimensions were 1.6X 2.2X 0.5mm X mm.

An optional multilayer lamination technique is implemented by adapting the process described with reference to fig. 8a, wherein layer 706 'is not etched to be removed from gap region 766'. Of course, laser engraving is used to remove the narrow street of the layer 706 ' so that the edge of the layer contacts the first contact layer 792 ', but is electrically isolated from the remainder of the layer 706 ' that is substantially outside the demetallized street. Laser engraving used in the production of metallized film capacitors of laminated layers is well known in the art and is described in U.S. patent No.5055965 to Charles c.

Various other techniques may be used to fabricate low ESR capacitors with parallel connection structures based on techniques known in the art of macro-capacitor technology or other potentially cost-effective techniques. For example, tailored manufacturing processes are employed to make smaller capacitors with a single layer stack. For example, fig. 13 shows an embodiment of a small macro-capacitor 800 comprising a 25 μm thick aluminum foil 802 that is etched on one side to obtain a 100 area increase; 20nm thick Al₂O₃A dielectric layer 804 attached to the etched side 803 of the foil 802 by oxidation, ALD or by oxidation after ALD; a 5nm thick TiN contact layer 806, which serves as an adhesion/barrier layer for copper metallization; a 0.5 μm thick copper layer 858 deposited by first depositing ALD seed (10nm) followed by electroplating; and a 2 μm thick piece of copper foil 808 brazed to the copper layer 858 with a brazing alloy 852. In this figure, the fine cross-hatching at 803 shows the etch penetration into the surface. Conformal Al with TiN and copper₂O₃The greater porosity on the etched surface 803 in combination with the conformal ALD deposition produces an increased capacitance, not shown, and not to scale in the figure. Optionally, 2.5 μm copper (858+808) is electroplated throughout the thickness, while reducing the need for braze alloy 852. Optionally, layer 808 is deposited using sputtering techniques while reducing the need for braze alloy 852. Thin layers 840 and 842 of gold, approximately 50nm thick, are also evaporated accordinglyOn the bottom side of foil 802 and on the top side of foil 808 to improve subsequent solder connections of the completed capacitor. Thus, a 10V compatible capacitor (50% de-rating) is formed with 35 μ F/cm²Capacitance and-10^-4ESR of. omega./. mu.F. For example, a capacitor having an ESR of 5.6. mu.F and 0.0005. omega. was obtained using an area of 4X 4mm X mm. These capacitors are then brazed or soldered onto ribbon leads 845 using, for example, brazing alloy 846, and further encapsulated with protective sleeve 847, as shown in fig. 13, to produce discrete (shown) or ganged (not shown) surface mount capacitors. Optionally, a foil laminate comprising layers (from bottom to top) 840, 802, 804, 806, 858, 808, 842 is integrated into a multilayer PC board as described below to advantageously obtain-100 μ FV/cm with a thickness of only-30 μm³A specific capacitance.

D. Integration with PC boards

The capacitor foil in the embodiment described above with reference to fig. 13 is particularly suitable for integration into a Printed Circuit Board (PCB). For example, an embodiment of a portion 900 of a PCB is illustrated with reference to fig. 14. The capacitor is fabricated as described above attached to a 25 μm aluminum foil 902 etched on one side 903. A dielectric layer 904 is grown, for example, by ALD or a combination of anodization and ALD, attached to the etched side 903 to a thickness of 20nm suitable for 10V applications (50% de-rating). For example, contact layer 906 is grown 10nm of TiN by ALD. An additional layer 958 is grown attached to layer 906 to obtain a low contact ESR, for example, by a combination of seed ALD and electroplating to grow 0.5 μm copper. Both the bottom of foil 902 and the top of layer 958 are coated with PVD gold 940 and 942, respectively, preferably to a thickness of 20 to 50 nm. This laminated foil 950 is utilized by the PCB manufacturer to integrate the capacitors into the layout structure of the PCB.

For example, in the embodiment shown in fig. 14, a metallized Kapton film is employed to construct a multilayer PCB, as is well known to those skilled in the art. A Kapton film 952 is formed with the layout of conductors and additional capacitor contact pads 951 as is known in the art and schematically illustrated by reference numeral 947 in fig. 14. Thereafter, foil 950 is laminated and soldered, brazed, or adhesively attached with a conductive material to Kapton foil 952 having patterned conductors 947 and 951. At this point, the foil 950 is patterned as is known in the art and etched to adhere to the pads 951 to form the desired capacitors. The value of the capacitor is selected by selecting the area of the capacitor. Subsequent debris removal is accomplished after patterning, as is well known in the art. Then, a capacitor having a thickness of-26 μm is soldered, brazed, or adhered with a conductive adhesive to the pad 948 prepared on the bottom of the Kapton foil 954. Fig. 14 does not accurately show the thickness values of the different layers. If the significantly smaller thickness of the-26 μm capacitor is compared to the final thickness of the PCB in the range of 500 μm, the gap between the capacitors is left empty in a preferred embodiment. In another preferred embodiment of the invention (not shown), the gap is for example filled with a polyimide perfluorocopolymer (polyimide of perfluor-polymer) material. After the Kapton foils 952 and 954 are laminated with other foils including the PCB, the capacitor is fully embedded in the PCB, exhibiting a significant area savings and correspondingly lower contact ESR from the pads 951 and 948 to the capacitor electrodes 902 and 906. The method for integrating the foil 950 is suitable for PCB manufacturing technology and is easily suitable for customized PCBs by the pattern of the pads 951 and 948 and the scribed pattern of the foil 950. Typically (although not necessarily) one contact to the capacitor, e.g. 948, is a continuous ground plane that covers a major area of the relevant Kapton foil (e.g. 954). In scoring the foil stack 950 into a particular pattern, a multiple etching step process is performed to properly etch the various layers comprising the stack.

E. High energy storage density capacitor device

The object of the invention is to produce a high energy storage capacitor. Advantageously, capacitors suitable for high voltages are manufactured attached to an aluminium foil with a smaller area increasing foil. For example. A50 μm foil with etched x 40 area increase can be used by ALD or positive etching as described above1.0 μm thick Al grown on both sides of the foil by combination of polar oxidation and ALD₂O₃A dielectric layer. Reduced by 50%, these dielectric films are suitable for the manufacture of 500V capacitors. A low ESR contact is established, for example, by achieving a 50nm TiN contact layer deposited by ALD followed by a 0.5 μm copper deposit by a combination of a 10nm seed ALD layer and electroplating and utilizing a commercially available 5.8 μm thick aluminum foil 208 (fig. 2). Therefore, the capacitance per unit area was 0.56. mu.F/cm². The thickness of the laminate was 56 μm and the weight per unit area was 0.01gram/cm². A capacitor having 400 muf was formed by winding a 1cm wide strip. The total area of the strip was 714cm²(ii) a Thus, the length of the strip is 714 cm. The final capacitor had a cylindrical shape of 176 windings, a 2.3cm diameter wound film and 3.4 μ Ω ESR, and a weight of 6.7 grams, comprised 2 x 0.5mm thick copper contact pads 270 'and 272' (fig. 9), wound on a stainless steel thin-walled steel capillary tube having an outer diameter of 0.3125cm (1/8 inches), and further as shown in example 1000 in fig. 15 a. In fig. 15a, the wound capacitor foil 1010 is shown prior to assembly with contact plates 1020 and 1030. Four capacitors are used to make the embodiment 1050 shown in figure 15 b. The capacitors are assembled in series by soldering or brazing the plates 1020 and 1030 together, and then the contact pads 1035 and 1036 are added. Finally, protective sleeve 1040 is manufactured. The stacked capacitor device with a capacitance of 100 μ F can operate at 2KV and has an ESR of 13.6 μ Ω. Protective and electrically insulating sleeve 1040 increases the diameter of the completed capacitor to 2.5cm and the total length to 4.6cm and the weight by 8 grams. Thus, the complete capacitor weighs 35 grams and has 22.6cm³The volume of (a). The energy storage capacity is shown as E ═ CV²An energy density of 200 joules or 5.7 joules/gram. The capacitor internal charging time τ ═ RC is 1.4nsec, and is suitable for very high peak currents. For example, the capacitor holds a load of 0.2 joules when fully charged at 2 KV; and is adapted to discharge 50% of the charged load in-1 nsec, providing a current of-100000000A for a short circuit. These characteristics are combined with longer life and higher temperature durabilityRepresents a significant improvement over the prior art.

The description and examples of preferred embodiments further illustrate the principles of the invention and are not meant to limit the scope of the invention to any particular method or apparatus. All suitable modifications, embodiments and equivalents are included within the scope of the invention as defined in the summary of the invention and the claims.

Claims

1. A capacitor (200, 400, 700 ') comprising a chemically etched metal foil (202, 402, 702'), wherein the capacitor comprises:

a conformal and substantially uniform dielectric layer (204, 404, 704') grown attached to the metal foil; and

a substantially uniform and conformal conductive film (206, 406, 706') grown over the dielectric layer.

2. The capacitor of claim 1, further comprising an additional metal foil (208, 408, 708) in substantial electrical contact with a corresponding portion of the conformal conductive film.

3. The capacitor of claim 1, wherein at least a portion of the conformal conductive film is grown by ALD.

4. The capacitor of claim 1, further comprising an additional conductive layer (458, 758) substantially in electrical contact with said conformal conductive film.

5. The capacitor of claim 4, further comprising an additional metal foil in substantial electrical contact with a portion of the additional conductive film.

6. The capacitor of claim 2, further comprising:

a strip (250) of said capacitor foil;

a strip of said additional metal foil having substantially the same width and length as said capacitor foil; and is

The strips of capacitor foil and the strips of additional metal foil are wound to form a substantially compact capacitor core shape.

7. The capacitor of claim 5, further comprising:

a strip of said capacitor foil;

8. A capacitor according to claim 4, further comprising a strip of said capacitor foil wound to form a substantially compact capacitor core shape.

9. The capacitor of claim 2, further comprising:

a capacitor core laminate comprising:

a first metal foil; and

a repeatable laminate;

the repeatable laminate includes a selected number of foil pairs, and the foil pairs comprise:

the capacitor foil; and

said additional metal foil.

10. The capacitor of claim 5, further comprising:

a capacitor core laminate comprising:

a first metal foil, and

a repeatable laminate;

the repeatable laminate includes a selected number of foil pairs; and the pair of foils comprises:

the capacitor foil; and

said additional metal foil.

11. The capacitor of claim 4, further comprising:

a capacitor core laminate comprising a repeatable laminate; and said repeatable laminate includes a selected number of said capacitor foils.

12. A capacitor according to claim 6, characterized in that electrical contacts are formed on a flat face of the capacitor core and that the electrical contacts comprise:

a first insulating portion attached to an edge of the additional metal foil on a first one of the planar faces;

a first electrical contact formed on the first face in contact with an edge of the metal foil;

a second insulating portion attached to an edge of the metal foil on a second one of the flat faces; and

a second electrical contact is formed on the second side in contact with an edge of the additional metal foil.

13. The capacitor of claim 7 wherein electrical contacts are formed on a planar face of said capacitor core and said electrical contacts comprise:

14. The capacitor of claim 8 wherein electrical contacts are formed on a planar face of said capacitor core and said electrical contacts comprise:

a first insulating portion attached to an edge of the additional conductive layer on a first one of the planar faces;

forming a second electrical contact on the second face in contact with an edge of the additional conductive layer.

15. The capacitor of claim 9 wherein said capacitor core laminate is cut into capacitor core pieces; and electrical contacts are formed on two parallel sides of the capacitor core member; and is

The electrical contact includes:

a first insulating portion attached to an edge of the additional metal foil on a first of the two parallel sides;

a first electrical contact formed on the first side in contact with an edge of the metal foil;

a second insulating part attached to an edge of the metal foil on a second side of the two parallel sides; and

16. The capacitor of claim 10 wherein said capacitor core laminate is cut into capacitor core pieces; and electrical contacts are formed on two parallel sides of the capacitor core member; and is

The electrical contact includes:

17. The capacitor of claim 11 wherein said capacitor core laminate is cut into capacitor core pieces; and electrical contacts are formed on two parallel sides of the capacitor core member; and is

The electrical contact includes:

a first insulating portion attached to an edge of the additional conductive layer on a first of the two parallel sides;

forming a second electrical contact on the second side in contact with an edge of the additional conductive layer.

18. The capacitor of claim 1, wherein at least a portion of the dielectric layer is formed by ALD.

19. The capacitor of claim 1 wherein at least a portion of the dielectric layer is formed by anodization.

20. The capacitor of claim 18 wherein a portion of the dielectric layer is formed by anodic oxidation; a portion of the dielectric layer is formed by ALD; and the thickness of the ALD portion is selected to substantially increase the breakdown voltage of the dielectric layer.

21. A capacitor according to claim 1, wherein the capacitor foil is electrically biased, and wherein the electrical biasing comprises:

applying an electrical potential between the metal foil and the conformal conductive film;

the potential is selected to increase a breakdown voltage of the dielectric layer; and is

The capacitance of the capacitor is substantially maintained.

22. A capacitor according to claim 1, wherein the capacitor foil is electrically biased, and wherein the electrical biasing comprises:

the potential is selected to reduce leakage current through the dielectric layer; and is

The capacitance of the capacitor is substantially maintained.

23. The capacitor of claim 1, wherein the dielectric layer is electrically biased, and wherein the electrical biasing comprises:

applying an electrical potential between the metal foil and an electrolyte;

the electrolyte provides electrical contact to the dielectric layer;

The thickness of the dielectric layer does not increase significantly.

24. A capacitor according to claim 1, wherein the capacitor foil is mounted on a PCB; and the PCB includes:

an electrical contact pad;

the mounting includes substantially enabling low ESR electrical contact with the electrical contact pad;

the capacitor foil is scribed to define a capacitor;

the defined capacitor comprises a selected capacitance; and is

The selected capacitance is determined by the capacitance per unit area of the capacitor foil and the area of the defined capacitor.

25. A capacitor according to claim 4, wherein said capacitor foil is mounted on a PCB; and the PCB includes electrical contact pads;

the capacitor foil is scribed to define a capacitor;

the defined capacitor comprises a selected capacitance; and is

26. The capacitor of claim 1, wherein said metal foil comprises aluminum.

27. The capacitor of claim 1 wherein said dielectric layer comprises aluminum oxide.

28. The capacitor of claim 1, wherein said conformal conductive film comprises titanium nitride.

29. The capacitor of claim 1 wherein the large area region comprises an area increase region greater than x 10 times.

30. The capacitor of claim 1, wherein said capacitor foil comprises:

a large area region on both sides;

the dielectric layer is grown on both sides of the metal foil; and is

The conformal conductive film is grown on the dielectric layer on both sides of the capacitor foil.

31. A method of manufacturing a capacitor comprising providing a conductive foil having an irregular surface to increase its area and oxidizing the surface area of the conductive foil to form a dielectric film, the method comprising:

conformally growing a conductive film on the dielectric film to form a capacitor foil; and is

Completing the capacitor to include the capacitor foil.

32. The method of claim 31 wherein said capacitor foil is wound into a capacitor core having two faces; electrically contacting an edge of the metal foil of the large area region on the first side; and electrically contacting an edge of the conductive film on the second face.

33. The method of manufacturing a capacitor of claim 31, comprising:

laminating said capacitor foil layers into a capacitor core laminate;

cutting the capacitor core stack into capacitor core pieces;

selecting two parallel sides on the capacitor core piece;

electrically contacting an edge of a metal foil of the large area region on the first side; and is

Electrically contacting an edge of the conductive film on the second side.

34. A method of fabricating a macroscopic capacitor comprising providing a substrate having a large surface area, said method comprising the steps of:

forming a conformal layer of dielectric or electrical conductor on the substrate by atomic layer deposition; and is

Completing the macro-capacitor to include the conformal layer.

35. The method of claim 34, wherein the forming step comprises forming a dielectric material.

36. The method of claim 34, wherein the dielectric material is selected from the group consisting of: al (Al)₂O₃Silicon oxide, Ta₂O₅、HfO₂、ZrO₂、TiO₂And their groupAnd (6) mixing.

37. The method of claim 34, wherein the forming step comprises forming a conductor.

38. The method of claim 37, wherein the conductor is selected from the group consisting of TiN, copper, tungsten, ruthenium, and combinations thereof.

39. The method of claim 34, wherein the completing step comprises completing a portion of a discrete electrical component, a hybrid electrical component, or a printed circuit board.