HK1110452A - A variable power adaptive transmitter - Google Patents

Description

Variable power adaptive transmitter

Technical Field

The present invention relates to communication systems, and more particularly to transmitters in network interfaces and other devices.

Background

Referring now to fig. 1, an exemplary network 10 is shown that includes one or more wireless network devices 20-1, 20-2, …, and 20-X (collectively wireless network devices 20) and/or one or more wired network devices 24-1, 24-2, …, and 24-Y (collectively wired network devices 24). The wireless network device 20 wirelessly exchanges data packets with the access point 30. The wired network device 24 exchanges data packets with the router 40 over a cable, fiber or other medium. The access point 30 is also in communication with a router 40. The mountain drive 40, in turn, communicates with a broadband modem 44, which broadband modem 44 communicates with a service provider 48. The service provider 48 in turn provides access to a distributed communications network 50, such as the internet.

Referring now to fig. 2, an exemplary wireless network device 20 is shown. The wireless network device 20 generally includes a host 58 and a wireless network interface 60. The wireless network interface 60 generally includes a wireless physical layer device (PHY)62, the wireless physical layer device 62 including a transceiver 64, the transceiver 64 including a transmitter 66 and a receiver 68. The wireless network interface 60 also includes a Media Access Controller (MAC)70 and/or other components (not shown).

Referring now to fig. 3, an exemplary wired network device 24 is shown. The wired network device 24 generally includes a host 78 and a wired network interface 80. The wired network interface 80 generally includes a wired physical layer device (PHY)82, the wired physical layer device 82 including a transceiver 84, the transceiver 84 including a transmitter 86 and a receiver 88. The wired network interface 80 also includes a Media Access Controller (MAC)90 and/or other components (not shown).

As described above, during use, transmitters 66 and 86 receive data to be transmitted on respective media. The power supply voltage of the network interface may place some limitations on the dynamic range of the transmitters 66 and 86 relative to the reference voltage used to power the transmitters.

Referring now to fig. 4 and 5, the transmitters 66 and 86 of fig. 2 and 3 are generally capable of receiving at + V_sand-V_sThe power supply voltage swings between. In this case，V_sLess than or equal to V_ddThe power supply voltage of (1). However, clipping may occur when the amplitude of the transmitter signal to be output by the transmitter 100 is higher than the voltage swing of the supply voltage, e.g., at 110 and 112 in fig. 5. Increasing the supply voltage will reduce clipping. However, increasing the supply voltage will also increase the power consumption of the device.

Disclosure of Invention

A circuit includes a delay module that receives a digital transmit signal and generates a delayed transmit signal. The first digital-to-analog converter converts the delayed transmit signal to an analog transmit signal. The analog output circuit amplifies the analog transmission signal. The envelope generation module generates an envelope signal based on amplitude information related to the digital transmit signal. The power supply adjustment module supplies a reference supply voltage when the envelope signal is less than a threshold and boosts a bias voltage of the amplifier above the reference supply voltage when the envelope signal is greater than the threshold.

In other features, the second digital to analog converter converts the envelope signal to an analog envelope signal. The first digital-to-analog converter has a higher resolution than the second number of converters. A third digital to analog converter receives the envelope signal and selectively increases the bias current for the amplifier. The bias current increases when the envelope signal exceeds a threshold value. The wireless network interface conforms to at least one of IEEE standards 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.

A circuit includes an analog output module that receives a bias signal and a control signal. The delay module receives the first signal and generates a delayed first signal. The control module receives the delayed first signal and generates a control signal based on the delayed first signal. The envelope generation module receives a second signal including amplitude information related to the first signal and generates an envelope signal that selectively increases the bias signal supplied to the analog output module when the envelope signal exceeds a predetermined threshold and before the analog output module receives a corresponding portion of the first signal.

In other features, the first signal comprises a digitally modulated carrier signal. The rectifier module rectifies the digital modulated carrier signal and outputs the rectified modulated carrier signal to the envelope generation module. The digital-to-analog converter converts the envelope signal to an analog envelope signal. The rise time of the envelope signal is slower than the fastest rise time of the first signal. The analog output module includes a power amplifier. The control module includes a transmitter module.

In other features, the switch is connected to a first reference voltage and is controlled by the envelope generation module. The capacitor is connected with the output of the envelope generation module and the switch. The inductor is connected with the analog output module and the capacitor. The matching network is in communication with the analog output module. The antenna is in communication with the matching network. The envelope generation module receives a first signal and generates an envelope signal based on the first signal. The delay circuit delays the modulated carrier signal. The up-converter up-converts the delayed modulated carrier signal.

A circuit includes an analog output device for receiving a bias signal and a control signal. The delay device receives the first signal and generates a delayed first signal. The control device receives the delayed first signal and generates a control signal based on the delayed first signal. Envelope generating means receives a second signal comprising amplitude information relating to the first signal and generates an envelope signal which selectively increases the bias signal supplied to the analogue output means when the envelope signal exceeds a predetermined threshold and before the analogue output means receives a corresponding portion of the first signal.

In other features, the first signal comprises a digitally modulated carrier signal. The rectifier device rectifies the digital modulation carrier signal and outputs the rectified digital modulation carrier signal to the envelope generating device. The digital-to-analog conversion means converts the envelope signal into an analog envelope signal. The rise time of the envelope signal is slower than the fastest rise time of the first signal. The analog output means comprises power amplifying means for amplifying. The control means comprises transmitting means for transmitting. The switching means for switching are connected to the first reference voltage and controlled by the envelope generating means. The capacitance means provides a capacitance and is connected to the output of the envelope generating means and the switching means. The inductive means provides inductance and is connected to the capacitive means and the analogue output means.

In other features, the matching network means for matching is connected to the analog output means. The antenna is connected with the matching network device. The envelope generating means receives the first signal and generates an envelope signal based on the first signal. The delay means delays the modulated carrier signal. And the up-conversion device up-converts the delayed modulated carrier signal.

A method, comprising: receiving a bias signal and a control signal at an analog output module; receiving and delaying a first signal; generating a control signal based on the delayed first signal; receiving a second signal comprising amplitude information related to the first signal; and generating an envelope signal based on the second signal, the envelope signal selectively increasing the bias signal supplied to the analog output module when the envelope signal exceeds a predetermined threshold and before the analog output module receives the corresponding portion of the first signal.

In other features, the first signal comprises a digitally modulated carrier signal. The method includes rectifying the digitally modulated carrier signal and outputting the rectified digitally modulated carrier signal to an envelope generation module. The method comprises converting the envelope signal to an analog envelope signal. The rise time of the envelope signal is slower than the fastest rise time of the first signal. The method also includes generating an envelope signal based on the first signal. The method also includes delaying the modulated carrier signal and upconverting the delayed modulated carrier signal.

Further areas of applicability of the present invention will become apparent from the message description provided hereinafter. It should be understood that the detailed description and specific examples, while indicating the preferred embodiment of the invention, are intended for purposes of illustration only and are not intended to limit the scope of the invention.

Drawings

The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:

fig. 1 is a functional block diagram of an exemplary wireless network in accordance with the prior art;

FIG. 2 is a functional block diagram of the exemplary wireless network device of FIG. 1;

FIG. 3 is a functional block diagram of the exemplary wired network device of FIG. 1;

FIG. 4 is a functional block diagram of a transmitter powered by a voltage source according to the prior art;

FIG. 5 is an exemplary waveform of a wireless signal transmitted by the transmitter of FIG. 4;

FIGS. 6A and 6B are functional block diagrams of an exemplary adaptive transmitter according to the present invention;

FIG. 7A is an exemplary functional block diagram and circuit diagram of a power supply adjustment module;

FIG. 7B is an exemplary functional block diagram and circuit diagram of an asymmetric supply adjustment module;

FIG. 7C is an exemplary functional block diagram and circuit diagram of a symmetric supply adjustment module;

FIG. 8A shows a symmetric boost waveform;

fig. 8B shows the slower signal rise time of the envelope signal;

FIG. 8C shows an asymmetric boost waveform;

FIG. 9 is an exemplary functional block diagram of an exemplary RF amplifier with boosting;

FIG. 10A is a functional block diagram and circuit diagram of another exemplary adaptive transmitter;

FIG. 10B shows a rectified boost waveform;

FIG. 11A is an exemplary implementation of the present invention in a network access storage module;

FIG. 11B is an exemplary implementation of the present invention in a digital versatile disc drive;

FIG. 11C is an exemplary implementation of the present invention in a high definition television;

FIG. 11D is an exemplary implementation of the present invention in a wireless local area network device associated with a vehicle;

FIG. 11E is an exemplary implementation of the present invention in a cellular telephone;

FIG. 11F is an exemplary implementation of the present invention in a set top box; and

FIG. 11G is an exemplary implementation of the present invention in a media player.

Detailed Description

The following description is merely exemplary in nature and is in no way intended to limit the disclosure, application, or uses. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. The phrase "A, B and at least one of C" as used herein should be interpreted to mean a logic (a or B or C) using a non-exclusive (non-exclusive) logical or. It should be understood that steps within a method may be performed in a different order without altering the principles of the present invention.

Referring now to fig. 6A and 6B, adaptive transmitters 150-1 and 150-2 (collectively adaptive transmitters 150) in accordance with the present invention are shown. Components of the adaptive transmitter 150Receive reference voltage V_s. Unlike conventional systems, the reference voltage V_sCan be temporarily greater than the supply voltage V_dd. Thus, some components within the transmitter may be temporarily driven higher than the supply voltage V_ddTo avoid clipping and to increase the dynamic range while maintaining relatively low power consumption.

In fig. 6A, the adaptive transmitter 150-1 includes a Digital Signal Processor (DSP)152, and the digital signal processor 152 outputs a transmission signal to be transmitted. The delay module 154 delays the transmit signal by a predetermined delay time and/or a variable delay time that may be adjusted. The digital-to-analog converter 158 converts the delayed transmit signal to an analog transmit signal. The analog transmission signal is output to an analog output circuit such as an amplifier 162, and the amplifier 162 amplifies the analog transmission signal. Although one amplifier is shown, any analog output circuit requiring a bias voltage may be used.

The boost module 164 receives the transmit signal (or amplitude information related to the transmit signal) and selectively increases the voltage V supplied to the amplifier and/or any other analog output circuit when the analog transmit signal exceeds the level of the power supply voltage or any other threshold_sAbove, for example, the supply voltage level V_ddThe threshold value of (2). In contrast to a causal system, the boosting of the voltage of the amplifier 162 occurs before the amplifier 162 receives a corresponding transmit signal that exceeds a threshold. Thus, clipping can be avoided, unlike in a causal system where clipping can be reduced but cannot be avoided. The envelope signal may also have a rise time that is slower than the fastest rise time of the transmit signal.

The boost module 164 includes an envelope module 170, a digital-to-analog converter 172, and a power supply adjustment module 174. The transmit signal may be output to the envelope module 170. The envelope module 170 generates an envelope signal based on the transmit signal. The envelope signal tracks the positive and/or negative peaks of the transmitted signal with a lower bandwidth. The envelope signal is output to a digital-to-analog converter 172, and the digital-to-analog converter 172 converts the envelope signal into an analog signal. The analog signal from the digital-to-analog converter 172 is output to the power supply adjustment module 174. The supply adjustment module 174 generates a variable supply voltage or bias voltage for the amplifier 162.

The supply adjustment module 174 supplies V when the envelope signal is less than the threshold signal_s＝V_dd. The supply adjustment module 174 temporarily sets V when the envelope signal is greater than the threshold signal_sIs boosted to V_ddThe above. Step-up voltage V_BoostAllowing the amplifier in the transmitter to track the transmit signal without clipping the transmit signal. The delay provided by the delay block 154 allows the supply adjust block 174 to generate the supply voltage V_sIs boosted to V_ddThe additional voltages required above. The digital-to-analog converter 158 may have a higher resolution and/or bandwidth than the digital-to-analog converter 172.

It will be appreciated that the envelope signal generator need not receive the same signals as the delay block 154 and D/a converter 158 shown in fig. 6A. For example, the digital signal processor 152 may output amplitude information related to the digital signal to the envelope signal generator and the transmit signal (including additional information) to the delay module 154 and the D/a converter 158. Other types of signals may also be used.

Referring now to fig. 7A-7C and 8A-8C, an exemplary power supply adjustment module 174 is shown that includes a switch S_BoostAnd a boost capacitor C_BoostA boost capacitor C_BoostThe boosted voltage is received from the digital-to-analog converter 172. When the envelope signal is less than the threshold signal, the switch S_BoostOff, supply adjustment module 174 supplies V_s＝V_dd. When the envelope signal is greater than the threshold signal, the switch S_BoostTurn on, supply the power adjustment module 174 to supply V_s＝V_dd+V_Boost. Stored in a capacitor C_BoostWill provide bias voltages and/or currents to amplifiers and/or other analog output circuits. In fig. 8A, the boost voltage temporarily boosts the supplied voltage (V)_s) Increase to V_ddAnd to reduce or prevent clipping of the transmitter signal.

In FIG. 7B, the digital letterThe signal is output to a positive envelope generation module 176 and a negative envelope generation module 177 which generate a positive envelope signal and a negative envelope signal, respectively. The outputs of the positive envelope generation module 176 and the negative envelope generation module 177 are input to digital-to-analog converters (DACs) 178 and 179, respectively. The outputs of DACs 178 and 179 are coupled to a positive boost capacitor C, respectively_boost+And a negative boost capacitor C_boost-And (4) connecting. Switches 181-1 and 181-2 are operated as described above to selectively use V_ddOr a boost voltage biases amplifier 180.

In fig. 7C, the digital signal is supplied to a rectifier 182 (or absolute value circuit) that rectifies the signal. If an absolute value circuit is used, the absolute value circuit may selectively change the sign bit to provide an absolute value. The envelope module outputs the positive and negative envelope signals to DACs 184 and 185, respectively. The outputs of DACs 184 and 185, respectively, are coupled to positive boost capacitor C_boost+And a negative boost capacitor C_boost-And (4) connecting. Switches 186-1 and 186-2 are operated as described above to selectively use V_ddOr a boost voltage biases amplifier 187.

The circuit in fig. 7B produces the symmetric boost waveform shown in fig. 8A. In fig. 8A and 8B, the transmitter signal 190 has a higher bandwidth than the envelope signal 192. The envelope signal 192 predicts the transmitter signal 190. In other words, the envelope signal 192 does not merely follow the increase in the transmitter signal 190 as is the case with the conventional peak envelope detector signal shown generally at 188. Conversely, the envelope signal 192 begins to increase when an increase in the transmitter signal 190 is predicted and may have a higher amplitude than a conventional peak envelope detector signal. Furthermore, the bandwidth of the envelope signal 192 is lower than the bandwidth of the transmitter signal 190. In other words, the rise time of the envelope signal 192 is greater than the fastest rise time of the transmitter signal 190. Stated another way, the tilt 197 of the envelope signal in fig. 8A will be less than the tilt 196 of the corresponding (and delayed) portion of the transmitter signal 190. Using an envelope signal with a faster response or step response (such as the response shown at 199 in fig. 8B) may cause high frequency noise.

In fig. 8C, an asymmetric waveform is shown that can be produced by the circuit in fig. 7C. The boost generated is different for the positive and negative portions of the signal. Therefore, the positive and negative bias voltages for the differential amplifier may also be different.

Referring now to fig. 9, an adaptive transmitter 200 may be implemented in an RF amplifier for a wireless transmitter. The components of the adaptive transmitter 200 receive a supply voltage V_dd. However, some components within the transmitter may be temporarily driven above the supply voltage V_dd. The digital transmit modulator 202 outputs the transmit signal to the delay module 154 and the rectifier 201 (or absolute value module), and the rectifier 201 outputs the rectified digital signal to the envelope module 170. The digital-to-analog converter 158 converts the delayed transmit signal to an analog transmit signal. The analog transmit signal is output to an upconverter 204, which upconverts the signal. The up-converted signal is output to an amplifier 162 that amplifies the signal.

The envelope module 170 generates an envelope signal based on the transmit signal and/or the threshold signal. The envelope signal is output to a digital-to-analog converter 172, and the digital-to-analog converter 172 converts the envelope signal into an analog signal. The analog signal from the digital-to-analog converter 172 is output to the power supply adjustment module 174. The supply adjustment module 174 generates a variable supply voltage for the amplifier 162.

The supply adjustment module 174 supplies V when the envelope signal is less than the threshold signal_s＝V_dd. The supply adjustment module 174 temporarily sets V when the envelope signal is greater than the threshold signal_sIs boosted to V_ddThe above. The delay provided by the delay block 154 allows the supply adjust block 174 to generate the supply voltage V_sIs boosted to V_ddThe additional voltages required above. The digital to analog converter 208 also receives the envelope signal and generates an RF bias current. The bias current selectively biases the amplifier 162. The bias current may be provided at the same time as the boost voltage is provided and/or the bias current may continuously provide an adaptive bias current to the amplifier 162. The bias adjustment module 210 adjusts the RF bias flowing to the amplifier based on the envelope signalThe current is applied.

Suitable applications include wireless network devices and wired network devices. The network device may be VDSL or VDSL2 compatible. The wireless network device may be compliant with IEEE standards 802.11, 802.11a, 802.11b, 802.11G, 802.11h, 802.11n, 802.16, and 802.20 and/or with bluetooth and cellular phones, such as standards compliant with GSM 4G.

Referring now to fig. 10A-10B, the transmitter circuit 240 includes a Digital Signal Processor (DSP)242, the digital signal processor 242 generating a first signal containing amplitude information and a modulated carrier signal. The rectifier 244 (or absolute value circuit) rectifies the signal and outputs the signal to the envelope generator module 246, the envelope generator module 246 generating the envelope signal as described above. DAC250 converts the envelope signal to an analog envelope signal and applies the analog envelope signal to capacitor C_BoostUp generating a boost voltage V_Boost. The envelope generator module 246 also generates a control signal that selectively opens and closes a switch 258, the switch 258 connected to V_dd. The switch is operated as described above.

The delay module 255 receives the modulated carrier signal and generates a delayed modulated carrier signal. The upconverter module 256 upconverts the delayed signal. The transmitter 257 generates a control signal for the control terminal of the power amplifier 264 based on the delayed modulated carrier signal. The inductor 260 may be connected to the boost capacitor C_BoostAnd a first terminal of the power amplifier 264. A matching network 266 is coupled to the first end and an antenna 268. In fig. 10B, the digital transmit signal is rectified (e.g., at 300) and an analog envelope signal is generated, as shown. The bias voltage of the amplifier is increased to V as required_ddIn order to prevent clipping.

Referring now to fig. 11A-11G, various exemplary implementations of the present invention are shown. Referring now to FIG. 11A, the present invention may be implemented in a network access storage module (NAS)901 that includes a hard disk drive 900. The present invention may be implemented and/or implemented in a wireless network interface module, which is generally identified at 904 in fig. 11A. In some implementations, signal processing and/or control circuitry 902 and/or other circuitry (not shown) in HDD 900 may process data, communicate with module 904, encode and/or encrypt, perform calculations, and/or format data for output to magnetic storage media 906 and/or for receipt from magnetic storage media 906.

The HDD 900 may communicate with another networked device (not shown), such as a computer, a mobile computing device such as a personal digital assistant, a cellular telephone, a media player or MP3 player, and/or the like, and/or other devices, via one or more wired links 908 and/or modules 904. The HDD 900 may be connected to memory 909, which memory 909 is, for example, Random Access Memory (RAM), low latency nonvolatile memory such as flash memory, Read Only Memory (ROM), and/or other suitable electronic data storage. The HDD 900 may also include a power module 903.

Referring now to FIG. 11B, the present invention may be implemented in a Digital Versatile Disk (DVD) drive 910. The present invention may be implemented and/or implemented in a wireless network interface module, identified generally at 911 in fig. 11B. Signal processing and/or control circuit 912 and/or other circuits (not shown) in DVD drive 910 may process data, perform coding and/or encryption, perform calculations, and/or format data read from and/or written to optical storage medium 916. In some implementations, the signal processing and/or control circuit 912 and/or other circuits (not shown) in the DVD drive 910 may also perform other functions, such as encoding and/or decoding and/or any other signal processing functions related to a DVD drive.

The DVD drive 910 may communicate with an output device (not shown), such as a computer, television, or other device, via one or more wired links 917 and/or via a wireless link through the module 911. The DVD drive 910 may communicate with a mass data storage device 918 that stores data in a nonvolatile manner. The mass data storage device 918 may include a Hard Disk Drive (HDD). The HDD may have the configuration shown in fig. 11A. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The DVD drive 910 may be connected to memory 919, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The DVD drive 910 may also include a power supply 913.

Referring now to fig. 11C, the present invention may be implemented in a High Definition Television (HDTV) 920. The present invention can implement either or both signal processing and/or control circuitry, which is generally identified at 922 in fig. 11C, and a wireless network interface module 929, and/or can implement the present invention in either or both signal processing and/or control circuitry and a wireless network interface module 929.

HDTV 920 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 926. In some implementations, signal processing circuit and/or control circuit 922 and/or other circuits (not shown) of HDTV 920 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

HDTV 920 may communicate with mass data storage 927 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in fig. 11A, and/or at least one DVD may have the configuration shown in fig. 11B. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The HDTV 920 may be connected to memory 928 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The HDTV 920 may also include a power supply 923.

Referring now to fig. 11D, the present invention may implement the wireless network interface module 948 of the vehicle 930 and/or may implement the present invention in the wireless network interface module 948 of the vehicle 930. A power transmission (powertrain) control system 932 receives input from one or more sensors, such as temperature sensors, pressure sensors, rotation sensors, airflow sensors, and/or any other suitable sensors, and/or generates one or more output control signals, such as engine operating parameters, transmission operating parameters, and/or other control signals.

The control system 940 may similarly receive signals from input sensors 942 and/or output control signals to one or more output devices 944. In some implementations, the control system 940 may be part of an anti-lock braking system (ABS), a navigation system, an telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc, or the like. Other implementations are also contemplated.

The powertrain control system 932 may communicate with a mass data storage device 946 that stores data in a nonvolatile manner. The mass data storage device 946 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 11A and/or at least one DVD may have the configuration shown in fig. 11B. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The powertrain control system 932 may be connected to memory 947, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage device 947. Vehicle 930 may also include a power supply 933.

Referring now to FIG. 11E, the present invention can be implemented in a cellular telephone 950 that can include a cellular antenna 951. The present invention can implement the wireless network interface module 968 and/or the present invention can be implemented in the wireless network interface module 968. In some implementations, the cellular telephone 950 includes a microphone 956, an audio output device 958 such as a speaker and/or audio output jack, a display 960, and/or an input device 962 such as a keyboard, pointing device, voice actuation device, and/or other input devices. The signal processing and/or control circuits 952 and/or other circuits (not shown) in the cellular telephone 950 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular phone 950 may communicate with mass data storage 964 that stores data in a nonvolatile manner, such as optical and/or magnetic storage devices, e.g., hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 11A and/or at least one DVD may have the configuration shown in fig. 11B. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The cellular phone 950 may be connected to memory 966, the memory 966 being, for example, RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. Cellular telephone 950 may also include a power supply 953.

Referring now to fig. 11F, the present invention may be implemented in a set top box 980. The present invention may be implemented in the network interface module 996 and/or the present invention may be implemented in the network interface module 996. Set top box 980 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 988 such as a television and/or monitor and/or other video and/or audio output devices. The source may be connected to the set top box 980 via the network interface module 996. Signal processing and/or control circuits 984 and/or other circuits (not shown) of set top box 980 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box 980 may communicate with a mass data storage device 990 that stores data in a nonvolatile manner. The mass data storage device 990 may comprise an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 11A and/or at least one DVD may have the configuration shown in fig. 11B. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The set top box 980 may be connected to memory 994, the memory 994 being, for example, RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The set top box 980 may also include a power supply 983.

Referring now to FIG. 11G, the present invention can be implemented in a media player 1000. The present invention may implement the wireless network interface 1016 and/or may be implemented in the wireless network interface 1016. In some implementations, the media player 1000 includes a display 1007 and/or a user input device 1008 such as a keyboard, touch pad (touch pad), or the like. In some implementations, the media player 1000 may use a Graphical User Interface (GUI) that typically uses menus, drop down menus, icons and/or a point-and-click interface via the display 1007 and/or user input device 1008. The media player 1000 also includes an audio output device 1009 such as a speaker and/or audio output jack. The signal processing and/or control circuits 1004 and/or other circuits (not shown) of the media player 1000 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player 1000 may communicate with a mass data storage 1010 that stores data, such as compressed audio and/or video content, in a non-volatile manner. In some implementations, the compressed audio files include files compliant with the MP3 format or other suitable compressed audio and/or video formats. The mass data storage device may comprise an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 11A and/or at least one DVD may have the configuration shown in fig. 11B. The HDD may be a compact HDD that includes one or more platters having a diameter of less than about 1.8 ". The media player 1000 may be connected to memory 1014, such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player 1000 may also include a power supply 1013. Implementations other than those described above are also contemplated.

Although amplifier 162 is shown, any analog output circuit requiring a bias voltage and/or current may be used. The present invention saves power by generally reducing the required supply voltage and selectively increasing the supply voltage as needed. Thus, the dynamic range of the circuit is improved without significantly increasing power consumption.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

This application claims priority from U.S. provisional application No.60/773,033 filed on 14.2006 and U.S. provisional application No.60/763,041 filed on 27.2006. The disclosures of the above applications are hereby incorporated by reference in their entirety.

Claims (20)

1. A circuit, comprising:

a delay module for receiving the digital transmit signal and generating a delayed transmit signal;

the first digital-to-analog converter is used for converting the delayed transmitting signal into an analog transmitting signal;

an analog output circuit for receiving the analog transmit signal;

an envelope generation module for generating an envelope signal based on amplitude information related to the digital transmit signal; and

a power supply adjustment module to supply a reference supply voltage when the envelope signal is less than a threshold, and boost the bias voltage of the analog output circuit above the reference supply voltage when the envelope signal is greater than the threshold.

2. The circuit of claim 1, further comprising a second digital-to-analog converter that converts the envelope signal to an analog envelope signal, wherein the first digital-to-analog converter has a higher resolution than the second digital converter.

3. The circuit of claim 2, further comprising a third digital-to-analog converter that receives the envelope signal and generates a third signal and selectively increases a bias current for the analog output circuit based on the third signal.

4. The circuit of claim 3, wherein the bias current increases when the envelope signal exceeds the threshold.

5. A wired network interface comprising the circuit of claim 1.

6. A wireless network interface comprising the circuit of claim 1.

7. The wireless network interface of claim 6, wherein the wireless network interface conforms to at least one of IEEE standards 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.

8. The circuit of claim 1, wherein the envelope generation module receives the digital transmit signal and generates the envelope signal based on the digital transmit signal.

9. The circuit of claim 1, wherein a rise time of the envelope signal is slower than a fastest rise time of the analog transmit signal.

10. The circuit of claim 1, wherein the threshold is substantially equal to a level of a reference supply voltage of the circuit.

11. A circuit, comprising:

a delay module for receiving the digital transmit signal and generating a delayed transmit signal;

the first digital-to-analog converter is used for converting the delayed transmitting signal into an analog transmitting signal;

an analog output circuit for receiving the analog transmit signal;

a power supply boost module to sample a signal including amplitude information of the digital transmit signal and to selectively boost a reference voltage supplied to the analog output circuit based on a difference between the sampled signal and a threshold before the analog output circuit receives a corresponding portion of the analog transmit signal.

12. The circuit of claim 11, wherein the supply boost module comprises:

an envelope generation module that generates an envelope signal;

a second digital-to-analog converter converting the envelope signal into an analog envelope signal; and

a power supply adjustment module that supplies a reference supply voltage when the envelope signal is less than the threshold, and boosts the bias voltage of the analog output circuit above the reference supply voltage when the envelope signal exceeds the threshold.

13. The circuit of claim 12, wherein the first digital-to-analog converter has a higher resolution than the second digital-to-analog converter.

14. The circuit of claim 12, further comprising a third digital-to-analog converter that receives the envelope signal and generates a bias current for the analog output circuit.

15. The circuit of claim 14, wherein the bias current increases when the envelope signal exceeds the threshold.

16. A wired network interface comprising the circuit of claim 12.

17. A wireless network interface comprising the circuitry of claim 12.

18. The wireless network interface of claim 17, wherein the wireless network interface conforms to at least one of IEEE standards 802.11, 802.11a, 802.11b, 802.11g, 802.11h, 802.11n, 802.16, and 802.20.

19. The circuit of claim 12, wherein the envelope generation module receives the digital transmit signal and generates the envelope signal based on the digital transmit signal.

20. The circuit of claim 12, wherein the rise time of the envelope signal is slower than the fastest rise time of the analog transmit signal.