HK1109988B - Single or multi-layer printed circuit board with improved via design - Google Patents

Description

Single or multilayer printed circuit board with improved via design

(Cross-reference to related applications)

This application is the partial continuation Of U.S. patent application No.10/227768, entitled "Single Or Multi-Layer Printed Circuit Board With processed Or extended Board toilet Tabs And Method Of Manufacture Thereof", filed on 26.2002, which is incorporated herein by reference, And U.S. patent application No.10/184387, entitled "Process creating Vias For Circuit Assemblies", filed on 27.2002, 6.2002, which is incorporated herein by reference.

Background

Currently, printed circuit boards are manufactured as part of larger panels. Although most commonly used printed circuit boards are manufactured in a rectangular shape of a standard size, the respective printed circuit boards may be configured in an arbitrary shape. When the manufacture of the printed circuit board is completed, it is cut and separated from the larger panel mainly by machine cutting or routing process (routing process) cutting a channel along the printed circuit board. In some designs, the channel along the printed circuit board does not completely surround the perimeter of the printed circuit board. Instead, tabs (tab) are left at several locations along the perimeter of the printed circuit board to secure it to the larger panel before the board is singulated from the larger panel by breaking the tabs (single). Generally, the metal plates in the printed circuit board do not extend to the edge where they would be cut by wire selection. In this way, no exposed conductive metal is left on the edges of the printed circuit board.

The existing methods of cutting printed circuit boards from larger panels are unsatisfactory for high density boards because the limited dimensional stability of the printed circuit boards does not allow one high density pattern to be aligned next on a larger panel. Cutting lines made along the perimeter of the printed circuit board further weaken the panel material, thereby exacerbating misalignment of one pattern to the next.

Electronic systems assembled on conventional printed circuit boards rely on thermal conduction from the heat dissipating integrated circuit to the printed circuit board to remove some of the heat from the integrated circuit. For an intermediate heat range of up to about 2 watts per chip, conduction to the printed circuit board is sufficient to cool the integrated circuit without the need for a bulky and expensive heat sink. However, in high performance systems, as the density of the system and the percentage of substrate covered by the integrated circuit increases, the efficiency of the thermal path that transfers heat to the printed circuit board decreases. At the point where the density of the system is substantially increased, the printed circuit board is no longer effective as a heat sink for the integrated circuit. However, as system density increases, the need for effective thermal conduction from the integrated circuit to the substrate and then from the substrate to the environment becomes more important. As the trend toward higher system densities and greater integrated circuit coverage progresses, means for cooling the substrate are required in order to maintain the integrated circuits on the substrate at a safe operating temperature.

In addition to heat conduction, high performance systems increasingly require low impedance power and ground voltage supplies to run integrated circuits at higher clock speeds. Generally, the AC impedance of the power and ground power supply is reduced by using a low impedance bypass capacitor connected to the power and ground planes. On conventional printed circuit boards, capacitors are connected to the power and ground planes through vias that extend through some thickness of the board, thereby increasing the impedance of the junction and degrading the performance of the system. As switching speeds increase, the problem of making a low impedance connection between the bypass capacitor and the power and ground planes becomes more important.

It is therefore desirable to overcome the above and other problems by providing a printed circuit board having one or more printed circuit board layers, each of which has a conductive layer extending to an edge thereof and substantially, but not completely, covered by an insulating material. The edges of the conductive layer that are not covered by the insulating material may be on the perimeter (or edge) of the printed circuit board layer or on the edges of tabs used to couple the board with the disposable portion of the larger panel that the board is formed in manufacture. The exposed edges of the conductive layer are exposed upon individually separating the printed circuit board layer from the respective tabs connected thereto, or upon breaking the tabs during individually separating the printed circuit board from the free-standing portion of the larger panel. In one embodiment, the broken end of one or more tabs terminates in a groove in the perimeter of the printed circuit board. In a second embodiment, the broken end of the one or more tabs extends outwardly from the perimeter of the printed circuit board.

The conductive surface may be formed of a metal that may be suitable for both conducting heat from and providing power or grounding to electrical components disposed on one or both surfaces of a printed circuit board or printed circuit board layer. Tabs extending outwardly from the edge of the printed circuit board of the second embodiment can be coupled with the mechanical and/or electrical fixture to provide a path for heat flow from the printed circuit board to the externally coupled mechanical fixture and/or to provide electrical power to the conductive layer of the printed circuit board.

Each printed circuit board layer may include one or more land-free (landless) vias or vias extending all or part of the way therethrough. Each bumpless via or via is configured as desired to facilitate deposition (deposition) of a conductive material therein, patterning and etching of the conductive material, and via or via formation without conductive bumps at each exposed end thereof.

Disclosure of Invention

The present invention is a multilayer printed circuit board formed of a plurality of Printed Circuit Boards (PCBs) laminated together. Each PCB comprises: a conductive plate coated with an insulating top layer covering one surface of the conductive plate, an insulating bottom layer covering the other surface of the conductive plate, and an insulating edge layer covering an edge of the conductive plate; and a circuit pattern defined on an outwardly facing surface of at least one of the top and bottom layers. The insulating interlayer is sandwiched between a top layer of a first PCB of the plurality of PCBs and a bottom layer of a second PCB of the plurality of PCBs.

The insulating edge layer may include at least one opening exposing at least a portion of an edge of the conductive plate.

At least one electrical conductor, such as but not limited to a conductive post, may electrically connect the circuit patterns on the first and second PCBs via the insulating interlayer.

The circuit pattern of one of the PCBs may comprise at least one electrical conductor on a top layer of the one PCB and at least one electrical conductor on a bottom layer of the one PCB. A through hole or via may extend through one PCB. The vias may have conductive inner surfaces extending therethrough that electrically connect one electrical conductor on a top layer of one PCB with one electrical conductor on a bottom layer of one PCB. The conductive inner surface may be electrically separated from the conductive plate by an insulating via layer.

The inner surface of the through-hole may converge from a position adjacent to a top layer of a PCB to a position intermediate the top and bottom layers of a PCB and diverge from a position intermediate the top and bottom layers of a PCB to a position adjacent to a bottom layer of a PCB.

In cross section, one side of the inner surface of the through-hole may have an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer. In cross section, opposite sides of the inner surface of the through-hole may have a generally hyperbolic profile.

The circuit pattern of one of the PCBs may include a plurality of electrical conductors on a top layer of the one PCB and a plurality of electrical conductors on a bottom layer of the one PCB. A through hole or via may extend through one PCB. The via may have a plurality of via conductors extending therethrough. The respective via conductors may be electrically isolated from each other by a via layer disposed between the conductive plate and the plurality of via conductors. Each via conductor may be electrically connected to at least one electrical conductor on a top layer of one PCB and/or at least one electrical conductor on a bottom layer of one PCB.

The inner surface of the through-hole may converge from a position adjacent to a top layer of a PCB to a position intermediate the top and bottom layers of a PCB and diverge from a position intermediate the top and bottom layers of a PCB to a position adjacent to a bottom layer of a PCB.

In cross section, one side of the inner surface of each via conductor or of an insulating via layer disposed between a pair of via conductors may have an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer. Specifically, a section of one side of the inner surface of the via conductor or one side of the inner surface of the insulating via layer may have a profile in the shape of a side (side) which is generally hyperbolic.

The present invention is also a method of forming a multilayer circuit board, the method comprising: (a) providing a plurality of circuit boards, each PCB comprising a conductive plate conformally coated with an insulating material; (b) forming a first circuit on one of the circuit boards; (c) forming a second circuit on the other of the circuit boards; and (d) laminating a plurality of PCBs together such that the insulating interlayer is disposed between one circuit board and another circuit board, and such that the first and second circuits are electrically connected via the insulating interlayer.

Each circuit may include at least one conductor. The conformally coated insulating material may include at least one opening exposing at least a portion of an edge of the conductive plate. At least a portion of the edge of the conductive plate may be on a tab extending from the circuit board within or outside the perimeter of the circuit board.

The method may include conformally coating through-holes or vias in conductive plates of a circuit board with an insulating material. At least one via conductor can be formed on at least a portion of the conformally coated insulating material in the via. One via conductor may be electrically connected with at least one conductor of a first circuit formed on one side of the first circuit board and/or with at least one conductor of a circuit formed on the other side of one circuit board.

The method may further include forming a plurality of electrically isolated via conductors on the conformally coated insulating material in the vias. Each via conductor may be electrically connected to at least one conductor of the first circuit formed on one side of the first circuit board and/or at least one conductor of the first circuit formed on the other side of the first circuit board.

The inner surface of the through-hole may converge from a position adjacent to the top surface of one circuit board to a position intermediate the top and bottom surfaces of one circuit board and may diverge from a position intermediate the top and bottom surfaces of one circuit board to a position adjacent to the bottom surface of one circuit board.

In cross section, one side of the inner surface of the through-hole may have an arcuate profile from a position intermediate the top and bottom surfaces to a position adjacent the top surface or a position adjacent the bottom surface. Specifically, the cross section on one side of the inner surface of the through-hole may have a profile generally in the shape of one side of a hyperbola.

The present invention is also a circuit board including a conductive plate coated with an insulating top layer covering one surface of the conductive plate, an insulating bottom layer covering the other surface of the conductive plate, and an insulating edge layer covering an edge of the conductive plate. The top layer of the circuit board may contain electrical conductors and the bottom layer of the circuit board may contain electrical conductors. The through hole or via may extend through the circuit board. The vias may include via conductors extending therethrough that electrically connect the electrical conductors on the top layer and the electrical conductors on the bottom layer. The via conductors may be electrically isolated from the conductive plate by an insulating via layer.

The insulating edge layer may include at least one opening exposing at least a portion of an edge of the conductive plate.

The inner surface of the via may converge from a position adjacent the top layer of the circuit board to a position intermediate the top and bottom layers of the circuit board and may diverge from a position intermediate the top and bottom layers of the circuit board to a position adjacent the bottom layer of the circuit board.

In cross section, one side of the inner surface of the through-hole may have an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer. In particular, in section, the opposite sides of the inner surface of the through-hole may have a profile generally in the shape of a hyperbola.

The top layer of the circuit board may contain a plurality of electrical conductors and the bottom layer of the circuit board may contain a plurality of electrical conductors. The via may include a plurality of via conductors extending therethrough. The via conductors may be electrically isolated from each other. Each via conductor can be electrically connected to at least one electrical conductor on the top layer and/or at least one electrical conductor on the bottom layer.

The inner surface of the via may converge from a position adjacent the top layer of the circuit board to a position intermediate the top and bottom layers of the circuit board and may diverge from a position intermediate the top and bottom layers of the circuit board to a position adjacent the bottom layer of the circuit board.

In cross section, one side of the inner surface of the through-hole may have an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer. Specifically, one side of the cross section of the inner surface of the through-hole may have a profile generally in the shape of one side of a hyperbola.

Finally, the present invention is a method of forming a circuit board, the method comprising: (a) providing a circuit board having a through hole or via therethrough; (b) conformally coating the conductive plate including the inner surface of the through-hole with an insulating material; (c) forming a conductor on one side of the conformally coated conductive plate; (d) forming another conductor on the other side of the conformally coated conductive plate; (e) a via conductor is formed on the insulating material in the via, the via conductor electrically connecting the conductor of one side of the conformally coated conductive sheet and the conductor of the other side of the conformally coated conductive sheet.

Step (c) may comprise forming a plurality of conductors on one side of the conformal coated conductive sheet. Step (d) may include forming a plurality of conductors on the other side of the conformal coated conductive plate. Step (e) may comprise forming a plurality of via conductors on the insulating material in the vias. The via conductors may be electrically isolated from each other. Each via conductor may be electrically connected with at least one conductor of one side of the conformally coated electrically conductive sheet and at least one conductor of the other side of the conformally coated electrically conductive sheet.

The conformally coated insulating material may include at least one opening exposing at least a portion of an edge of the conductive plate. At least a portion of the edge of the electrical conductor may be on a tab extending from the circuit board within or outside the perimeter of the circuit board.

The inner surface of the through-hole may converge from a position adjacent one side of the conformally coated electrically conductive sheet to a position intermediate one side and the other side of the conformally coated electrically conductive sheet, and may diverge from the position intermediate one side and the other side of the conformally coated electrically conductive sheet to a position adjacent the other side of the conformally coated electrically conductive sheet.

In cross section, one side of the inner surface of the through-hole may have an arcuate profile from a position intermediate the one side and the other side to a position adjacent the one side or a position adjacent the other side. In particular, one side of the cross-section may have a profile in the shape of a side of a generally hyperbolic curve.

Drawings

FIG. 1 is a cut-away perspective view of a printed circuit board layer having a perforated conductive surface surrounded by an insulating material according to the present invention;

FIG. 2 is a cross-sectional perspective view of a portion of a printed circuit board layer of the type shown in FIG. 1, including a circuit pattern formed on an outwardly facing surface thereof;

FIGS. 3 and 4 are plan views of a panel having different circuit board layers formed therefrom in accordance with the present invention;

FIG. 5 is a plan view of the panel shown in FIGS. 3 and 4 laminated together with their circuit board layers aligned with each other;

FIG. 6 is an isolated plan view of the panels of FIGS. 3 and 4 utilizing tabs for connecting their circuit board layers with the disposable part of the panel;

fig. 7 is an isolated plan view showing the tab shown in fig. 6 after severing in response to application of a severing force applied thereto;

FIG. 8 is a view taken along line VIII-VIII in FIG. 7;

FIGS. 9 and 10 are plan views of panels containing printed circuit board layers according to the present invention;

FIG. 11 is a plan view of the panel shown in FIGS. 9 and 10 laminated together with their circuit board layers aligned with each other;

FIG. 12 is a plan view of the laminated printed circuit board layers shown in FIG. 11, separated individually from the free access portion of their respective panels;

FIG. 13 is a cross-section taken along line XIII-XIII in FIG. 12;

fig. 14 is a plan view of the single, separate, stacked circuit board layer shown in fig. 12 with some of the tabs coupled with the mounting fixture and some of the tabs coupled with the electrical fixture;

FIG. 15 is a cross-sectional side view of the laminated printed circuit board layers of FIG. 12 including an optional insulating interlayer disposed therebetween and having exemplary conductors disposed therethrough for electrically connecting the circuit patterns on the respective printed circuit board layers;

fig. 16 is a plan view of an isolated cross-section of a printed circuit board layer containing bumpless vias (or vias) having a single via conductor therein in accordance with the present invention;

FIG. 17 is a cross-section taken along line XVII-XVII in FIG. 16;

fig. 18 is a plan view of a printed circuit board layer containing bumpless vias (or vias) having a plurality of via conductors therein in accordance with the present invention;

fig. 19 is a section taken along line XIX-XIX in fig. 18.

Detailed Description

Referring to fig. 1, a printed circuit board layer 2 includes a conductive plate or foil 4. The plate 4 may be formed of copper foil, iron-nickel alloy, or a combination thereof. The plate 4 may be a perforated plate as shown in fig. 1, or may be a solid plate. To prevent failure of the adhesive bond used to adhere an integrated circuit or packaged integrated circuit (not shown) to printed circuit board layer 2, it is desirable that plate 4 have a coefficient of thermal expansion comparable to that of the silicon material from which integrated circuits are typically made. Describing the plate 4 as perforated means that the plate 4 is a mesh plate having a plurality of through holes or passages 6 spaced at regular intervals.

An electrically insulating coating 8 is formed around the plate 4. The coating 8 may be formed around the plate 4 in any manner known in the art, such as conformal coating. Specifically, the coating 8 forms an insulating top layer 10 covering the top surface 12 of the plate 4, an insulating bottom layer 14 covering the bottom surface 16 of the plate 4, and an insulating edge layer 18 covering the edges 20 of the plate 4. When the plate 4 is coated with the coating 8, the inner surface of each through-hole or passage 6 is also coated with the coating 8. Thus, no part of the plate 4 is not coated with the coating 8.

With reference to fig. 2 and with continuing reference to fig. 1, printed circuit board layer 2 formed in the manner described above may have conductive patterns formed on the outward facing surface of top layer 10 and/or the outward facing surface of bottom layer 14 by conventional processes. In particular, one or more photolithographic techniques and one or more metallization techniques may be utilized to form conductive patterns on the outward facing surface of the top layer 10 and/or the outward facing surface of the bottom layer 14. The conductive pattern may comprise an uncoated via or via 6-1, a plated blind via or via 6-2 and/or a plated via or via 6-3. Additional details regarding the formation of printed circuit board layers 2 and the formation of conductive patterns comprising one or more types of Vias or Vias 6 on top layer 10 and/or bottom layer 14 may be found in U.S. patent application serial No.10/184387 entitled "Process For Creating Vias For circuits structures," filed on 2002, 6, 27, which is assigned to the same assignee as the present application and is incorporated by reference.

The preparation of one or more printed circuit board layers 2 in the form of a panel and the assembly of a plurality of printed circuit board layers for forming a multilayer printed circuit board assembly will now be described.

Referring to fig. 3, one or more first Printed Circuit Board (PCB) layers 30 are fabricated as part of a panel 32. Each first PCB layer 30 is surrounded by a free run 34 of the panel 32. In accordance with the present invention, each first PCB layer 30 is coupled to the free access portion 34 of the panel 32 by one or more tabs 36.

The general steps of preparing the panel 32 into the form shown in fig. 3 will now be described. First, the first conductive plate such as the conductive plate 4 of the size of the panel 32 is provided. The plate may be a solid plate or a perforated plate depending on the application. Cut lines or slots 38 are then formed in the conductive plates by pattern etching or mechanical cutting or routing to define the perimeter of the respective first PCB layers 30 of panel 32. These slots 38 are interrupted by tabs 36 that hold the respective first PCB layer 30 to the free run 34 during processing.

An electrically insulative coating such as coating 8 is then deposited over the conductive plates forming panel 32 in such a manner that the top, bottom and edges of the conductive plates associated with each first PCB layer 30 that are exposed during the formation of slots 38 are covered thereby. If the conductive plate is a perforated plate, the electrically insulating coating also covers the inner surface of the respective through-hole or passage. Additionally, the top and bottom surfaces and edges of each tab 36 defined during formation of the slot 38 may also be covered by an electrically insulative coating. The top and bottom surfaces and edges of the discretionary portion 34 defined during formation of the slot 38 may also be covered with an electrically insulating coating. But this is not required. However, generally all edges, surfaces of the conductive plates of the panel 32 and the inner surfaces of the respective through holes where vias are provided are covered by an electrically insulating coating.

Photolithographic processing techniques and metallization techniques described in the above-identified U.S. patent applications, which are well known in the art and incorporated herein by reference, are then utilized to define a circuit pattern 40 on one or both of the exposed surfaces of the electrically insulative coating deposited over the portions of the conductive plates associated with the respective first PCB layers 30.

If each first PCB layer 30 is ready for use after circuit pattern 40 is formed thereon, each first PCB layer 30 may be singulated from panel 32 by applying a breaking force to each tab 36 connecting each first PCB layer 30 and discretionary portion 34. However, if desired, an electrically insulating coating (not shown) and one or more additional layers of circuit patterns (not shown) may be formed over the circuit patterns 40 so that the various layers of the circuit patterns are interconnected in the desired manner by utilizing conventional processes. Each first PCB layer 30 may then be singulated from panel 32 by applying a breaking force to each tab 36 connecting each first PCB layer 30 and discretionary portion 34. If a breaking force is applied to each tab 36 on the perimeter (or edge) of first PCB layer 30, i.e., on the boundary between tab 36 and first PCB layer 30, a portion of the edge of first PCB layer 30 connecting the tabs is exposed. Specifically, separating each tab 36 from first PCB layer 30 on the perimeter of first PCB layer 30 exposes a portion of the edge of the conductive plate of first PCB layer 30 to which tab 36 was previously connected.

Alternatively, each first PCB layer 30 of panel 32 may be laminated to a second PCB layer 42 of panel 44 shown in fig. 4. The panel 44 includes one or more second PCB layers 42 connected to a free-standing portion 46 of the panel 44 by tabs 48, the tabs 48 being defined during formation of slots 50 in a conductive plate of the panel 44 in the same manner as described above with respect to the formation of the slots 38 in the panel 32.

An electrically insulative coating is deposited over the conductive plates forming the panel 44 in a manner such that the top, bottom and edges of the conductive plates associated with each second PCB layer 42 that are exposed during formation of the slots 50 are covered. If the conductive plate is perforated, the electrically insulating coating also covers the inner surface of the respective through-hole or via. Additionally, the top, bottom, and edges of each tab 48 defined during formation of the slot 50 may also be covered by an electrically insulating coating. The top, bottom and edges of the discretionary portion 46 defined during formation of the slot 50 may also be covered with an electrically insulating coating. But this is not essential. In general, however, all edges, surfaces of the conductive plates of the panel 44 and the inner surfaces of the respective vias where provided are covered by an electrically insulating coating.

Each second PCB layer 42 has a circuit pattern 52 formed on one or both exposed surfaces of an electrically insulative coating deposited on a portion of the conductive plate associated with each second PCB layer 42. If desired, each second PCB layer 42 may include an electrically insulative coating formed over circuit pattern 52 and one or more additional layers of circuit patterns such that the various layers of circuit patterns are interconnected in a desired manner by utilizing conventional processes.

Referring to fig. 5, with continued reference to fig. 3 and 4, panels 32 and 44 may be laminated together in a manner known in the art such that each first PCB layer 30 is aligned with a corresponding second PCB layer 42 to form a multi-layer PCB assembly 60. Suitable techniques known in the art may be utilized to form one or more electrical connections between circuit pattern 40 and circuit pattern 52. For simplicity of explanation, the formation of one or more electrical connections between the circuit pattern 40 and the circuit pattern 52 will not be described herein.

As shown in fig. 5, tabs 36 of panel 32 do not overlap tabs 48 of panel 44 when panels 32 and 44 are laminated together. In this manner, PCB layers 30 and 42 forming each multi-layer PCB assembly 60 may be individually separated from their free-dominated portions 34 and 46, respectively, independently of each other. However, if desired, one or more tabs 36 and 48 may be aligned with each other when panels 32 and 44 are stacked.

Individual second PCB layers 42 may be singulated from panel 44 by applying a breaking force to individual tabs 48 connecting individual second PCB layers 42 and discretionary portion 46. The breaking force applied to each tab 48 may be applied to the perimeter (or edge) of the corresponding second PCB layer 42, i.e., the boundary between tab 48 and second PCB layer 42, thereby exposing a portion of the edge of second PCB layer 42, particularly the edge of the conductive plate of second PCB layer 42 that previously joined tab 48.

Referring to fig. 6 and 7, with continued reference to fig. 3-5, instead of breaking one or more tabs 36 and 48 on the perimeter (or edge) of the respective first and second PCB layers 30 and 42, respectively, one or more of the tabs 36 and 48 are configured to break its ends in the middle to facilitate individual separation of the respective PCB layers 30 and 42 from the respective free-dominated portions 34 and 46. If desired, the location at which each such tab 36 and 48 is configured to be broken may be received within a recess of the corresponding PCB layer, such that no portion of the tab remaining secured to the PCB layer extends beyond the perimeter of the PCB layer after breaking. Each such tab 36 and 48 will now be described with reference to the exemplary tab 36 of the panel 32. It should be understood that each tab 48 of panel 44 is similar to each tab 36 of panel 32 and, therefore, the following description of exemplary tabs 36 applies to each tab 48.

As shown in fig. 6, an exemplary tab 36 extends between first PCB layer 30 and discretionary portion 34. To facilitate breaking, exemplary tab 36 includes a narrowed portion 62 along its length, also known as a Charpy notch. The narrowed portion 62 enables the exemplary tab 36 to break at a well-defined location, whereby the exemplary tab 36 is divided into a first portion 64 that remains attached to the first PCB layer 30 and a second portion 66 that remains attached to the discretionary portion 34.

The ends of slot 38 on opposite sides of exemplary tab 36 define a recess 68 within a perimeter 70 of first PCB layer 30. For the purposes of this description, perimeter 70 of first PCB layer 30 includes an outer edge 72 of first PCB layer 30 and an imaginary extension 74 that spans outer edge 72 of each groove 68. As shown, narrowed portion 62 of each tab 36 is within perimeter 70 of first PCB layer 30. Thus, when the exemplary tab 36 is separated into the first portion 64 and the second portion 66, the tip 76 of each first portion 64 terminates within the groove 68.

With reference to fig. 8 and with continuing reference to all previous figures, since the first PCB layer 30 and the exemplary tab 36 comprise a conductive plate 78, such as plate 4 of fig. 1, coated with an electrically insulative coating 80, such as coating 8 of fig. 1, breaking the exemplary tab 36 exposes a smaller portion 82 of the edge of the conductive plate 78 and the surrounding electrically insulative coating 80. Since only the top end 76 of the first portion 64 of the exemplary tab 36 includes a smaller portion 82 of the conductive plate 78 that is exposed, substantially all of the edges of the conductive plate 78 are covered by the electrically insulating coating 80, and in particular the insulating edge layer of the electrically insulating coating 80. Thus, inadvertent electrical contact with the edges of the conductive plate 78 covered with the insulating edge layer of the electrically insulating coating 80 can be avoided.

The conductive plates of first PCB layer 30 and second PCB layer 42 may be utilized to carry heat away from electrical components disposed on one or both surfaces thereof. Additionally, the electrically conductive plates of PCB layers 30 and 42 of each multilayer PCB assembly 60 may be utilized to provide electrical power and ground to electrical components disposed on the outwardly facing surface of multilayer PCB assembly 60. This is accomplished by connecting the power supply lines of each integrated circuit disposed on the multi-layer PCB assembly 60 to the conductive pads of one PCB layer 30 and 42 and connecting the ground lines of each integrated circuit to the conductive pads of the other PCB layer 30 and 42. The conductive plates of each PCB layer 30 and 42 may then be connected by suitable fastening means to a suitable one of the power and ground terminals of the external power source via a smaller portion 82 of the edge of the conductive plate exposed on the first portion 64 of the one or more tabs 36.

Referring to fig. 9, first PCB layer 90 may be fabricated in the same manner as first PCB layer 30 discussed above with respect to fig. 3. One or more tabs 92 may extend outwardly from perimeter 94 of first PCB layer 90 and connect it to a free access portion 96 of a panel 98 that also contains first PCB layer 90 and tabs 92. First PCB layer 90 and tabs 92 may be formed from conductive plates coated with an electrically insulating coating from the top, bottom, and edges in a manner similar to PCB layers 30 and 42 and tabs 36 and 48, respectively. However, the electrically insulative coating may be omitted from one or more tabs 92, or may be removed from one or more tabs 92 after deposition. One or more of tabs 92 may each include a mounting hole 100, and such mounting holes 100 may be used to couple tab 92 to mounting hardware or an external circuit, such as a power supply.

The circuit pattern 101 may be formed on one or both exposed surfaces of the first PCB layer 90 by using photolithographic processing techniques and metallization techniques well known in the art. Once first PCB layer 90 has circuit pattern 101 formed on one or both exposed surfaces thereof, first PCB layer 90 and individual tabs 92 may be individually separated from panel 98, particularly free access portion 96, and utilized as is. However, if desired, an electrically insulating coating and one or more additional layers of circuit patterns may be formed over the circuit pattern 101 such that the various layers of the circuit pattern are interconnected in a desired manner by utilizing conventional processes. First PCB layer 90 and respective tabs 92 may then be singulated from panel 98.

Referring to fig. 10 and 11, if desired, panel 98 may be laminated to layer panel 106 in a manner well known in the art such that first PCB layer 90 is laminated to second PCB layer 102 aligned with panel 106 to form a multi-layer PCB assembly 104 best shown in fig. 11-13. Second PCB layer 102 is a portion of panel 106 that includes tabs 108 and a discretionary portion 110. One or more tabs 108 may each include mounting holes 112 that may be used to couple tab 108 with appropriate mechanical hardware or circuitry. Second PCB layer 102 and tabs 108 may be formed from electrically conductive plates coated with an electrically insulative coating in a manner similar to PCB layers 30 and 42 and tabs 36 and 48, respectively. However, the electrically insulative coating may be omitted from each tab 108 or may be removed from each tab 108 after deposition.

The circuit pattern 114 may be formed on one or both surfaces of the second PCB layer 102 by using photolithographic processing techniques and metallization techniques known in the art. Suitable techniques known in the art may be utilized to form one or more electrical connections between circuit pattern 101 and circuit pattern 114.

Then, with reference to fig. 12 and with continuing reference to fig. 11, a breaking force may be applied to each tab 92 and 108 to singulate first and second PCB layers 90 and 102, and thus singulate multi-layer PCB assembly 104, from discretionary portions 96 and 110. To facilitate the application of a breaking force to the respective tabs 92 and 108, the tabs 92 and 108 may be positioned on the first and second PCB layers 90 and 102 such that they do not overlap each other. As shown, all of the individual tabs 92 and all of the individual tabs 108 are retained with the first and second PCB layers 90 and 102, respectively. Thus, the breaking force applied to each tab 92 and each tab 108 causes them to break away from free dominant portions 96 and 110, respectively. To cleanly break each tab 92 and 108 from discretionary portions 96 and 110, a break line or score line may be formed on the boundary of each tab 92 and 108 and each discretionary portion 96 and 110 to weaken the mechanical connection therebetween. A suitable breaking force may be applied to each tab 92 and 108 by a mechanical press having a ram with a suitably shaped tip for causing a breaking force to be applied to the tab, particularly the score line.

Alternatively, a breaking force may be applied to each tab 92 and 108 on the perimeter (or edge) of first and second PCB layers 90 and 102, respectively, i.e., on the boundary between each tab 90 and 92 and first and second PCB layers 90 and 102. Upon application of such a breaking force, portions of the edges of first and second PCB layers 90 and 102 that connect tabs 92 and 108, respectively, are exposed. Specifically, separating each tab 92 and 108 from first and second PCB layers 90 and 102 on the perimeter of first and second PCB layers 90 and 102, respectively, exposes portions of the edges of the conductive plates of first and second PCB layers 90 and 102 that previously joined the tabs 92 and 108.

With reference to fig. 13 and with continuing reference to fig. 11 and 12, assuming a breaking force is applied to each tab 92 and each tab 108 causing them to break away from free-dominated portions 96 and 110, respectively, at an appropriate time, one or more electrical components 120, such as, but not limited to, a packaged integrated circuit, an unpackaged flip-chip integrated circuit, a resistor, a capacitor, and/or an inductor, may be coupled with appropriate points of circuit pattern 101 and/or circuit pattern 114 of multilayer PCB assembly 104 in a manner known in the art. Also, as shown in fig. 14, one or more tabs 92 and/or 108 may be coupled with a mounting fixture 122 or an electrical fixture such as a power source 124. Since each tab 92 is part of a conductive plate 130 associated with first PCB layer 90 and since each tab 108 is part of a conductive plate 132 associated with second PCB layer 102, connecting one or more tabs 92 to one terminal of power supply 124 and one or more tabs 108 to the other terminal of power supply 124 will therefore apply a bias to conductive plates 130 and 132. Providing electrical power to the conductive plates 130 and 132 in this manner simplifies the supply of electrical power to individual electrical components, such as the electrical components 120, coupled to one or both outward facing surfaces of the multi-layer PCB assembly 104.

In addition, other electrical components, such as one or more capacitors 134, may be connected between adjacent pairs of tabs 92 and 108. The inclusion of one or more capacitors 134 between adjacent pairs of tabs 92 and 108 reduces the need to mount filter capacitors on one or both of the outwardly facing surfaces of multilayer PCB assembly 104 to provide electrical filtering (electrical filtering) of the electrical components disposed thereon.

Similar to the top end of exemplary tab 36, top end 136 of each tab 92 and top end 137 of each tab 108 comprise exposed edges of conductive plates 130 and 132, respectively. In addition, to facilitate connection of electrical components therebetween, such as capacitor 134, all or a portion of the top and/or bottom surfaces of conductive plates 130 and 132 associated with an adjacent pair of tabs 92 and 108, respectively, may be exposed.

As shown in fig. 13, multi-layer PCB assembly 104 includes one surface of the electrically insulative coating of first PCB layer 90 laminated directly to one surface of the electrically insulative coating of second PCB layer 102. However, if desired, an insulating interlayer 140 may be provided between the first and second PCB layers 90 and 102 as shown in fig. 15. In particular, one surface of the first PCB layer 90 may be laminated onto one surface of the insulating interlayer 140, and the other surface of the insulating interlayer 140 may be laminated onto one surface of the second PCB layer 102.

One or more conductors 142, such as smaller conductive posts, may extend through the insulating interlayer 140 for connecting one or more points of the circuit pattern 101 on the first PCB layer 90 to one or more points of the circuit pattern 114 on the second PCB layer 102. Since conductors such as conductor 142 are well known in the art, details regarding the use of such conductors will not be described herein.

Although the use of the insulating interlayer 140 has been described with respect to the first and second PCB layers 90 and 102, it should be understood that an insulating interlayer, such as the insulating interlayer 140, may be utilized with the multi-layer PCB assembly 60 shown in fig. 5 in the same manner as the insulating interlayer 140 is utilized with the multi-layer PCB assembly 104 shown in fig. 15. In particular, one surface of each instance of first PCB layer 30 may be laminated to a surface of an insulating interlayer, such as insulating interlayer 140, and another surface of the insulating interlayer may be laminated to one surface of an instance of second PCB layer 42 to form an embodiment of multi-layer PCB assembly 60 that includes an insulating interlayer between first and second PCB layers 30 and 42.

In FIGS. 3-5 and 9-12, each PCB layer 30, 42, 90 and 102 is shown as including one or more conventional plated through holes (or vias) therethrough. Each such conventional plated through-hole (or via) includes a so-called "land" L (see, e.g., fig. 2) around its periphery at each end where it terminates on the exposed surface of the printed circuit board layer. The use of lands L surrounding the respective ends of plated through holes (or vias) terminating on the exposed surface of the printed circuit board layer enables the conductive material in the vias to be electrically connected to conductors such as conductive traces or wires on the surface of the printed circuit board in a manner well known in the art. One problem with using lands L that surround the respective ends of plated through holes (or vias) that terminate on the exposed surface of the printed circuit board layer is that the additional conductive material used to form the lands L provides more opportunity for electrical shorts (electrical short) to be formed with adjacent wires or lands L during the mounting of electrical components on the printed circuit board layer. Also, the use of the lands L reduces the available density of conductor lines and lands on the printed circuit board layer. Specifically, the printed circuit board layer is manufactured according to rules regarding minimum spacing between edges of adjacent conductors, such as lands L and wires. Thus, eliminating lands L around each exposed end of a via or via causes adjacent structures, such as adjacent lands L or adjacent wires, to be moved closer than a non-land via or via that does not violate the minimum spacing rule. It is therefore desirable to eliminate the use of lands L surrounding each exposed end of a via or via.

A method of forming a printed circuit board layer 2 having a bumpless through hole or via will now be described with reference back to fig. 1. As described above with respect to fig. 1, the printed circuit board layer 2 includes a conductive plate or foil 4 formed of copper foil, iron-nickel alloy, or a combination thereof. In one desired embodiment, the conductive plate 4 is formed of invar. The plate 4 may have one or more through holes or vias 6 that extend through the plate 4.

With reference to fig. 16 and 17 and with continuing reference to fig. 1, the board 4 containing the individual through-holes 6 is optionally conformally coated with a copper layer 144. It is desirable that copper layer 144 be electrodeposited onto board 4. This should not be construed as limiting the invention.

The use of a copper layer 144 is particularly advantageous when the board 4 is formed of a material other than copper, in order to avoid a mismatch between the coefficient of thermal expansion of the material forming the board 4 and the coefficient of thermal expansion of the material deposited on the copper layer 144 or the electrical components mounted to the printed circuit board layer 2.

The plate 4 or copper layer 144 (if present) is then conformally coated with the insulating material forming the coating 8. The insulating material desired to form coating 8 is initially electrodeposited onto plate 4 or copper layer 144 (if present). Electrodeposition of the insulating material results in a substantially uniform layer that conforms to the surface or edges of the copper layer 144 or the board 4 (if present). It has been observed that this substantially uniform layer of electrodeposited insulating material has an undesirably relatively rough surface on which to form a circuit pattern, such as circuit pattern 146. Thus, after the insulating material is electrodeposited, the PCB layer 2 is heated to a high temperature sufficient to cause the insulating material to melt in whole or in part. Once melted, the insulating material deposited onto the opposite surface of the board 4 or copper layer 144 (if present) flows and flattens out, thereby becoming sufficiently flat to provide a suitably smooth and uniform surface for forming the circuit pattern 146 thereon upon cooling. Melting the insulating material also enables it to flow along the edges of the respective through-hole 6. More specifically, melting the insulating material causes the shape of the insulating material in the through-hole 6 to change from its conformally coated shape (shown in phantom) to the shape shown in cross-section in fig. 17. When recooled to a solid, the insulating material in each through-hole 6 maintains substantially the same shape as that shown in fig. 17.

Upon cooling, the insulating material forms a coating 8. The coating layer 8 comprises: an insulating top layer 10 covering the top surface 12 of the plate 4 or the top surface 148 of the copper layer 144 (if present); an insulating underlayer 14 covering the bottom surface 16 of the plate 4 or the bottom surface 150 of the copper layer 144 (if present); an insulating edge layer 18 covering an edge 20 of the plate 4 (best shown in FIG. 1); and an insulating via layer 152 covering an inner surface 154 of the plate 4 or an inner surface 156 of the copper layer 144 (if present) for each via 6.

It can be seen that once the coating 8, and in particular the insulating via layer 152, is formed, the surface of the insulating via layer 152 converges from a position adjacent the top layer 10 to a position intermediate the top layer 10 and the bottom layer 14 and diverges from a position intermediate the top layer 10 and the bottom layer 14 to a position adjacent the bottom layer 14.

As shown in the cross-section of via 6 in fig. 17, one side of insulating via layer 152 has an arcuate profile from a position intermediate top layer 10 and bottom layer 14 to a position adjacent top layer 10 or bottom layer 14. Also, as shown in the cross-section of the via 6 in fig. 17, the opposite side of the insulating via layer 152 has a generally hyperbolic-shaped profile.

Once the coating 8 is formed, an electrodeposited copper layer, for example, is formed over the coating 8, i.e., over the top layer 10, the bottom layer 14, the insulating edge layer 18, and the respective insulating via layers 152. Since the insulating via layer 152 has the form shown in fig. 17, the electrodeposited copper on coating 8 conforms to the arcuate surface of insulating via layer 152. In other words, the copper electrodeposited over the coating 8 conformally coats the arcuate surfaces of the coating 8, and in particular the insulating via layer 152.

The electrodeposited copper on the coating 8 may then be patterned and etched in a manner well known in the art to define a circuit pattern 146 thereon. The exemplary circuit pattern 146 includes conductive traces 158-164 on the top layer 10, conductive traces 166 and 168 on the bottom surface 14, and one or more via conductors 170 on the surface of each insulating via layer 152. As shown in fig. 17, the via conductor 170 has a substantially uniform thickness.

The opposite side of the inner surface of the via conductor 170 has a minimum diameter D1. The arcuate surface of the insulating via layer 152 enables electrical connections to be established between the via conductors 170 and the conductive traces 160, 162, 166 and 168 without the need for the lands L shown in dashed lines in fig. 16.

With reference to fig. 18 and 19 and with continuing reference to fig. 1, 16 and 17, how it is desired that the via 6 not comprise a single via conductor 170, but rather a plurality of electrically isolated via conductors 170-1, 170-2, etc. formed on the insulating via layer 152. Various via conductors 170-1, 170-2, etc. may be used to connect the conductive traces defined on the top layer 10 to the conductive traces defined on the bottom layer 14. For example, via conductor 170-1 may be used to electrically connect conductive trace 160 and conductive trace 166 of coating 8 disposed on top layer 10 and bottom layer 14, respectively. Similarly, via conductors 170-2 may be used to electrically connect conductive traces 162 and 168 of coating 8 disposed on top layer 10 and bottom layer 14, respectively.

The ability to form a plurality of electrically isolated via conductors 170 on the insulating via layer 152 is facilitated by the arcuate shape of the insulating via layer 152, and thus by the arcuate shape of the copper electrodeposited on the insulating via layer 152. Specifically, the arcuate shape of the copper electrodeposited on the insulating via layer 152 enables a photoresist to be deposited thereon and then patterned and etched in a manner well known in the art. The uncured photoresist and the copper underlying the uncured photoresist are then removed by means well known in the art, such as chemical etching, to define a plurality of via conductors 170-1, 170-2, etc. in the vias 6. The hardened photoresist may then be removed by means well known in the art.

As best shown in fig. 18, removing portions of the copper electrodeposited on the insulating via layer 152 to define a plurality of via conductors 170 in the vias 6 results in vias 6 having a minimum diameter D1 between the opposing surfaces of the via conductors 170. Conversely, the opposite surface of the insulating via layer 152 where the electrodeposited copper has been removed will have a second diameter D2 that is greater than the diameter D1.

The photoresist used to define the plurality of via conductors 170 in the vias 6 is desirably an electrodeposited photoresist that conformally coats the electrodeposited copper on the insulating via layer 152 of the vias 6. Suitable exemplary electrodepositable photoresists are disclosed in U.S. patent nos. 6560053 to Kahle, II, et al, 5733479 to Kahle, II, et al, 5721088 to Martin, et al, and 6100008 to mcmurdi, which are incorporated herein by reference.

The combination of electrodeposited photoresist on the arcuate surfaces of electrodeposited copper on the insulating via layer 152 of the via 6 facilitates exposing the photoresist to appropriate hardening radiation in order to define a plurality of electrically isolated via conductors 170 on the insulating via layer 152. In contrast, the vertical surfaces of existing vias limit or prevent uniform exposure of the photoresist in the via to the hardening radiation, particularly to collimated light that may be used to define one or more conductive traces or any other portion of the circuit pattern on the top layer 10 and the bottom layer 14 of the coating 8.

Two or more of the printed circuit board layers 2 described above with respect to fig. 16-19 may be used to form a multi-layer printed circuit board assembly, such as the multi-layer PCB assembly 60 or 104, with or without an insulating interlayer 140 sandwiched between two or more adjacent printed circuit board layers 2. Similar to printed circuit board layers 40, 52, 90 and 102, printed circuit board layer 2 shown in fig. 16-19 may be connected to the disposable portion of the panel by one or more tabs, such as tabs 36, 48, 92 or 108, and may be singulated from the panel in any of the manners described above with respect to printed circuit board layers 40, 52, 90 and 102.

It can be seen that the present invention provides a printed circuit board having one or more printed circuit board layers, each printed circuit board layer having a conductive surface extending to the edge of the printed circuit board while being substantially, but not completely, covered by an insulating material. The edges of the conductive layer not covered by the insulating material are positioned on the edges or tabs of the circuit board layer that are used to couple the circuit board layer to the disposable portion of the larger panel that forms the printed circuit board layer during the manufacturing process. Upon individually separating the printed circuit board layers from the free-standing portion of the panel, the exposed edges of the conductive layers are exposed.

The conductive layers of each circuit board layer serve a dual purpose: removing heat from, and providing electrical power or ground to, electrical components disposed on one or both surfaces of a printed circuit board or printed circuit board layer.

The present invention also provides a printed circuit board layer having one or more bumpless vias therethrough. It is desirable that, in cross section, one side of the inner surface of each through-hole has an arcuate profile from a position intermediate its ends to a position adjacent one end thereof or a position adjacent the other end thereof. In one desirable embodiment, in cross-section, opposite sides of the inner surface of the through-hole have a generally hyperbolic profile. Since the inner surface of one side of each via has an arcuate profile in cross-section, each via may contain a single via conductor extending therethrough or a plurality of electrically isolated via conductors extending therethrough. The ability to form a large number of electrically isolated via conductors in a single via enables a reduction in the number of vias through the circuit board required to pass signals between opposing surfaces or layers thereof. Thus, the use of bumpless through holes or vias according to the present invention can reduce the number of through holes or vias required in a printed circuit board in order to pass signals between opposite surfaces of the printed circuit board.

The invention has been described with reference to the preferred embodiments. Obvious modifications and alterations will occur to others upon reading and understanding the preceding detailed description. For example, multi-layer PCB assembly 60 is described as being formed by laminating PCB layers 30 and 42 together with or without an insulating layer, such as insulating interlayer 140, laminated between PCB layers 30 and 42. However, the circuit patterns of each pair of adjacent PCB layers may be electrically connected in a desired manner, with or without an insulating layer such as the insulating interlayer 140 being laminated between one or more adjacent pairs of PCB layers, forming a multi-layer PCB assembly from three or more PCB layers laminated together. Also, electrical components such as capacitors 134 are depicted as being connected to tabs 92 and 108 of adjacent PCB layers 90 and 102 of multilayer PCB assembly 104. However, the electrical components may be connected between tabs of adjacent or non-adjacent PCB layers of a multi-layer PCB assembly having three or more PCB layers. It is intended that the invention be construed as including all such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

Claims (32)

1. A multilayer circuit board comprising:

a plurality of circuit boards, each circuit board comprising: a conductive plate coated with an insulating top layer covering one surface of the conductive plate, an insulating bottom layer covering the other surface of the conductive plate, and an insulating edge layer covering an edge of the conductive plate; and a circuit pattern defined on an outwardly facing surface of at least one of the top and bottom layers; and

an insulating interlayer sandwiched between the top layer of a first circuit board of the plurality of circuit boards and the bottom layer of a second circuit board of the plurality of circuit boards.

2. The circuit board of claim 1, wherein the insulating edge layer comprises at least one opening exposing at least a portion of an edge of the conductive plate.

3. The circuit board of claim 1, further comprising at least one electrical conductor electrically connecting the circuit patterns on the first and second circuit boards via the insulating interlayer.

4. The circuit board of claim 1, wherein,

the circuit pattern of one of the circuit boards comprises at least one electrical conductor on a top layer of the one circuit board and at least one electrical conductor on a bottom layer of the one circuit board; and is

A via or via extends through the one circuit board, the via having a conductive inner surface extending therethrough that electrically connects one electrical conductor on the top layer of the one circuit board and one electrical conductor on the bottom layer of the one circuit board, the conductive inner surface being electrically isolated from the conductive plate by an insulating via layer.

5. The circuit board of claim 4, wherein the inner surface of the via converges from a position adjacent the top layer of the one circuit board to a position intermediate the top and bottom layers of the one circuit board and diverges from a position intermediate the top and bottom layers of the one circuit board to a position adjacent the bottom layer of the one circuit board.

6. The circuit board of claim 5, wherein, in cross section, an inner surface of one side of the through-hole has an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer.

7. The circuit board of claim 6, wherein, in cross-section, opposite sides of the inner surface of the through-hole have a generally hyperbolic shaped profile.

8. The circuit board of claim 1, wherein,

the circuit pattern of one of the circuit boards comprises a plurality of electrical conductors on a top layer of the one circuit board and a plurality of electrical conductors on a bottom layer of the one circuit board; and is

A through-hole or via extends through the one circuit board, the through-hole having a plurality of through-hole conductors extending therethrough, each through-hole conductor being electrically isolated from each other, each through-hole conductor being electrically connected to at least one electrical conductor on the top or bottom layer of the one circuit board.

9. The circuit board of claim 8, wherein the inner surface of the via converges from a position adjacent the top layer of the one circuit board to a position intermediate the top and bottom layers of the one circuit board and diverges from a position intermediate the top and bottom layers of the one circuit board to a position adjacent the bottom layer of the one circuit board.

10. The circuit board of claim 9, wherein, in cross section, one of the via conductors or a side of the insulating via layer disposed between a pair of the via conductors has an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer.

11. The circuit board of claim 10, wherein a cross-section of one side of one of the via conductors or the insulating via layer disposed between a pair of the via conductors has a profile generally in the shape of one side of a hyperbola.

12. A method of forming a multilayer circuit board comprising:

(a) providing a plurality of circuit boards, each circuit board comprising a conductive plate conformally coated with an insulating material;

(b) forming a first circuit on one of the circuit boards;

(c) forming a second circuit on the other of the circuit boards; and

(d) a plurality of circuit boards are laminated together such that an insulating interlayer is provided between the one circuit board and the other circuit board, and such that the first and second circuits are electrically connected via conductors in the insulating interlayer.

13. The method of claim 12, wherein each circuit comprises at least one conductor.

14. The method of claim 12, wherein the conformally coated insulating material comprises at least one opening exposing at least a portion of an edge of the conductive plate.

15. The method of claim 14, wherein one opening is on a tab extending from the circuit board within or outside a perimeter of the circuit board.

16. The method of claim 12, further comprising:

conformally coating the through-holes or vias of the conductive plates of the one circuit board with an insulating material; and

at least one via conductor is formed on at least a portion of the insulating material in the via such that the one via conductor is electrically connected to at least one conductor of the first circuit formed on one side of the first circuit board and to at least one conductor of one circuit formed on the other side of the one circuit board.

17. The method of claim 16, further comprising forming a plurality of electrically isolated via conductors on the insulating material in the vias such that each via conductor is electrically connected to at least one conductor of the first circuit formed on one side or the other of the first circuit board.

18. The method of claim 17, wherein the inner surface of the via converges from a position adjacent the top surface of the one circuit board to a position intermediate the top and bottom surfaces of the one circuit board and diverges from a position intermediate the top and bottom surfaces of the one circuit board to a position adjacent the bottom surface of the one circuit board.

19. The method of claim 18, wherein, in cross section, a side of the via has an arcuate profile from a position intermediate the top and bottom surfaces to a position adjacent the top surface or a position adjacent the bottom surface.

20. The method of claim 19, wherein a cross-section of one side of the through-hole has a profile generally in the shape of one side of a hyperbola.

21. A circuit board, comprising:

a conductive plate coated with an insulating top layer covering one surface of the conductive plate, an insulating bottom layer covering the other surface of the conductive plate, and an insulating edge layer covering an edge of the conductive plate;

electrical conductors on a top layer of the circuit board and electrical conductors on a bottom layer of the circuit board; and

a through-hole or via through the circuit board, the through-hole having a through-hole conductor extending therethrough electrically connecting the electrical conductor on the top layer and the electrical conductor on the bottom layer, the through-hole conductor being electrically isolated from the conductive board by an insulating via layer, wherein an inner surface of the through-hole converges from a position adjacent the top layer of the circuit board to a position intermediate the top and bottom layers of the circuit board and diverges from a position intermediate the top and bottom layers of the circuit board to a position adjacent the bottom layer of the circuit board.

22. The circuit board of claim 21, wherein the insulating edge layer comprises at least one opening exposing at least a portion of an edge of the conductive plate.

23. The circuit board of claim 21, wherein, in cross section, a side of the inner surface of the via has an arcuate profile from a position intermediate the top layer and the bottom layer to a position adjacent the top layer or a position adjacent the bottom layer.

24. The circuit board of claim 23, wherein, in cross-section, opposite sides of the inner surface of the via have a profile that is generally hyperbolic in shape.

25. The circuit board of claim 21, further comprising a plurality of electrical conductors on a top layer of the circuit board and a plurality of electrical conductors on a bottom layer of the circuit board, wherein,

the via includes a plurality of via conductors extending therethrough;

the via conductors are electrically isolated from each other; and is

Each via conductor is electrically connected to at least one electrical conductor on the top layer and at least one electrical conductor on the bottom layer.

26. A method of forming a circuit board, comprising:

(a) providing a circuit board having a through hole or via therethrough;

(b) conformally coating the conductive plate including the inner surface of the through-hole with an insulating material;

(c) forming a conductor on one side of the conformally coated conductive plate;

(d) forming another conductor on the other side of the conformally coated conductive plate;

(e) a via conductor is formed on the insulating material in the via, the via conductor electrically connecting the conductor of one side of the conformally coated conductive sheet and the conductor of the other side of the conformally coated conductive sheet.

27. The method according to claim 26, wherein,

step (c) comprises forming a plurality of conductors on one side of a conformal coated conductive plate;

step (d) comprises forming a plurality of conductors on the other side of the conformal coated conductive plate;

step (e) comprises forming a plurality of via conductors on the insulating material in the vias;

the via conductors are electrically isolated from each other; and is

Each via conductor is electrically connected to at least one conductor of one side of the conformally coated electrically conductive sheet and at least one conductor of the other side of the conformally coated electrically conductive sheet.

28. The method of claim 27, wherein the conformally coated insulating material comprises at least one opening exposing at least a portion of an edge of the conductive plate.

29. The method of claim 28, wherein at least a portion of the edge of the electrical conductor is on a tab extending from the circuit board within or outside the perimeter of the circuit board.

30. The circuit board of claim 26, wherein the inner surface of the through-hole converges from a position adjacent one side of the conformally coated electrically conductive sheet to a position intermediate the one side and the other side of the conformally coated electrically conductive sheet and diverges from the position intermediate the one side and the other side of the conformally coated electrically conductive sheet to a position adjacent the other side of the conformally coated electrically conductive sheet.

31. The circuit board of claim 30, wherein, in cross section, one side of the inner surface of the through-hole has an arcuate profile from a position intermediate the one side and the other side to a position adjacent the one side or a position adjacent the other side.

32. The circuit board of claim 31, wherein a cross-section of one side of the inner surface of the via has a profile generally in the shape of one side of a hyperbola.