HK1109678B - Methods and apparatuses for providing stacked-die devices - Google Patents

Description

Method and apparatus for providing stacked-die devices

Technical Field

Embodiments of the invention relate generally to the field of integrated circuit devices and, more particularly, to methods and apparatus for stacking dies to fabricate stacked-die devices.

Background

If the chips can be packed more densely on the surface of the silicon circuit board, the size and cost of the module can be reduced and the performance of the system improved. One possible approach to maximizing packing density involves placing chips one on top of another to form a three-dimensional stack, which is referred to as a stacked chip device or a stacked die device. Over the past years, there has been some interest in stacking chips where possible. Such chip stacking schemes include stacking multiple reduced size chips for wire bonding, or stacking multiple chips of the same size using spacers or using corner cutting techniques or using a "T-cut" die as the upper die. Problems arise when the trend moves from 2 to 4 stacked die in typical devices today to 6 to 8 and more stacked die in the near future to stacking more die.

For example, for a reduced-size die solution, the point is eventually reached where the upper die size is invalid. For corner cut or T-cut die solutions, there is a limit on the size difference between the lower die and the upper die in the stack (i.e., excessive overhang is more difficult to handle and results in a stacked die device that is less stable).

Furthermore, each of these schemes presents the problem of increased yield loss. As the number of stacked die increases, yield loss increases. The stacked die devices are not fully inspected until they are completed. Temperature sensing and other tolerance sensing may be done on individual dies at the die, pre-stack level, but such sensing does not represent the overall functionality of the stacked-die device. Particularly when one of the stacked dies implements a logic processor device, rapid detection before all electrical connections of the entire device are completed is unreliable.

To address the issue of stack limitations and yield loss, the concept of sub-packaging of stacked dies has been introduced. In such a scheme, a plurality of sub-packages, each including stacked-die devices, are produced and tested. Upon successful testing, two or more sub-packages are stacked and electrically connected to form a stacked-die device.

Fig. 1 illustrates a stacked-die device including stacked sub-packages according to the prior art. The stacked-die device 100 shown in fig. 1 includes three sub-packages 105a, 105b, and 105c, which may be stacked-die packages, such as packages 105b and 105 c. The package 105a includes a substrate 110a with conductive balls 120 (e.g., a Ball Grid Array (BGA)) formed on a bottom surface 111 of the substrate 110 a. The conductive balls 120 are used to electrically connect the substrate 110a to a motherboard (not shown). The die 130a is disposed on the upper surface 112 of the substrate 110 a.

Package 105b includes a stacked-die device having a die 130c stacked atop die 130 b. Package 105c includes a stacked-die device having dies 130d through 130f stacked one on top of the other as shown. All of the dies 130a, 130b and 130c and 130d to 130f are electrically connected to the respective substrates 110a to 110c or to each other with wire bonds 140. The wire bonds 140 for each sub-package are typically covered with a molding compound 145 for protection before stacking the sub-packages. The sub-packages are electrically interconnected with interconnects 150, which interconnects 150 may be copper joints between the sub-packages.

The stacked-die device 100 addresses some of the disadvantages of stacking limitations and yield loss, but it also has disadvantages. For example, copper inserts that form the connection joints between sub-packages require additional space. In other words, the interconnects 150 between the sub-packages must be slightly removed from the wire bonds 140 so that they are not covered by the molding compound 145. This increases the size of the stacked-die device. The formation of copper inserts also requires additional processes (e.g., drilling) which increases cost and virtually limits the construction of each package to standard shapes and sizes. Fig. 1A is a top view of a sub-package for the stacked-die device 100 described above with reference to fig. 1. As shown in fig. 1A, a copper interposer 150 for connecting sub-packages has a carrier 155. The carrier is outside the area on the substrate 110a where the wire bonds 140 may be placed. For a given size, the die 130a, the substrate 110a, and thus the sub-package 105a need to be large enough to accommodate the carrier 155.

Disclosure of Invention

According to an aspect of the present invention, there is provided an apparatus comprising: a substrate having a top surface and a bottom surface; a set of one or more dies attached to the top surface of the substrate, the one or more dies extending a first distance above the top surface; one or more interconnects formed on the top surface of the substrate, the one or more interconnects extending a second distance above the top surface; and an encapsulant disposed on the top surface of the substrate and extending a third distance above the top surface, the third distance being greater than the first distance and less than the second distance such that the one or more dies are encapsulated and portions of the one or more interconnects are exposed, the interconnects comprising metal balls.

In accordance with another aspect of the present invention, there is provided a system comprising: a first sub-package; and a second sub-package stacked on top of and electrically connected to the first sub-package, each of the first sub-package and the second sub-package including a substrate having one or more dies attached to a top surface thereof and one or more interconnections formed on the top surface thereof, and an encapsulant disposed on the top surface of the substrate such that the one or more dies are encapsulated and an upper portion of each of the one or more interconnections is exposed, the interconnections including metal balls.

According to yet another aspect of the present invention, there is provided a method comprising: forming one or more interconnects on a top surface of a substrate, the one or more interconnects extending a first distance above the top surface of the substrate; attaching a set of one or more dies to a top surface of a substrate, the one or more dies extending a second distance above the top surface; the encapsulant is applied over the top surface of the substrate and the one or more interconnects such that the encapsulant extends a third distance over the top surface, the third distance being less than the first distance and greater than the second distance.

Drawings

The invention may best be understood by referring to the following description and accompanying drawings that are used to illustrate embodiments of the invention. The figures are as follows:

FIG. 1 illustrates a stacked-die device including stacked sub-packages according to the prior art;

FIG. 1A is a top view of a sub-package for a stacked-die device according to the prior art;

FIG. 2 illustrates top and side views of a substrate for a sub-package according to one embodiment of the present invention;

3A-3D illustrate a process for producing a sub-package according to one embodiment of the invention;

FIG. 4 illustrates a process for encapsulating the die of a sub-package while exposing an upper portion of the sub-package interconnects according to one embodiment of the invention; and

fig. 5 illustrates a stacked-die device including stacked sub-packages according to one embodiment of the invention.

Detailed Description

Numerous specific details are set forth in the following description. However, it is understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the understanding of this description.

Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, inventive aspects lie in less than all features of a single disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

Fig. 2 illustrates top and side views of a substrate for a sub-package according to one embodiment of the invention. The substrate 210 has interconnects 240 and sub-package interconnects 250, which may be, for example, conductive metal balls, that may be used to electrically connect one sub-package to another sub-package thereon in a stacked sub-package configuration. The sub-package interconnects 250 may be similar to BGA typically used on the bottom side of a die for surface mount packaging. According to one embodiment of the invention, the sub-package interconnections are formed on the top side (die side) of the substrate. The sub-package interconnections 250 are discontinuous and thus wire bonding may be achieved near and between the sub-package interconnections 250. For one embodiment, the wire bonds may be formed until the sub-package interconnects are to be placed before forming the sub-package interconnects 250 that provide interconnection between the sub-packages. The sub-package interconnects are electrically connected to the die 230 through interconnects 240. The bottom side of the substrate may have conventional BGA or metal pads for electrically connecting to the sub-package below.

Fig. 3A to 3D illustrate a process for producing a sub-package according to one embodiment of the present invention. As shown in fig. 3A, substrate 310 is a conventional substrate having features for die attachment and wire bonding or flip chip attachment. The bottom surface 311 of the substrate 310 has conductive metal balls 320, as described above with reference to fig. 1. The substrate 310 has sub-package interconnections 350 formed on the top surface 312. The sub-package interconnections 350 are attached to metal pads (not shown) formed near the periphery of the substrate 310. The sub-package interconnections 350 may be conductive metal balls, which may be formed of solder, which may be a lead/tin alloy. In alternative embodiments, the sub-package interconnections 350 may be made of copper or other suitable conductive metal. For such embodiments, the sub-package interconnects 350 may be attached using a process similar to conventional BGA ball attach methods.

For one embodiment of the invention, the integrated circuit chip (die) is attached to the substrate 310 after the sub-package interconnections 350 are formed on the top surface 312 of the substrate 310. According to one embodiment of the invention, a die may implement multiple types of memory devices or logic processor devices. The die, which may be one die or a plurality of dies in a stacked configuration, are attached to the substrate 310 and to each other using conventional die attachment methods and materials. As shown in fig. 3B, the die 330a is attached to the top surface 312 of the substrate 310 and the die 330B is stacked atop the die 330a and attached to the die 330 a. Each of the dies may be electrically connected to the substrate and to each other using conventional methods (e.g., wire bonding or flip chip attachment). The sub-package interconnects 350 extend a greater distance above the top surface 312 than the die stack.

As shown in fig. 3C, the attached die or stack of dies is then encapsulated to protect the die and, if there are associated wires (e.g., wire bonds), also the associated wires, while leaving the upper portions 351 of the sub-package interconnects 350 exposed. The encapsulant extends above the upper surface 312 above the die stack but is not as high as the sub-package interconnects 350. For one embodiment of the present invention, the encapsulant 345 is a thermoset material such as an epoxy or polymer resin, which may include varying amounts (e.g., from 0 to 80 weight percent) of silica or other inorganic particulates to modify CTE, modulus, or viscosity. For one embodiment of the present invention, such a thermoset material may include a fluxing agent to provide fluxing capability during subsequent reflow. For one embodiment of the present invention, the encapsulation of the die stack is achieved by a stencil printing process, as shown in fig. 3C, which will be described in more detail below.

As shown in fig. 3D, the encapsulant 345 may surround the entire sub-package interconnections 350. The sub-package interconnects 350 may remain encapsulated, where the sub-package is the top-most sub-package of the stacked sub-package devices. In the case where the sub-package interconnections are to be used to electrically connect the sub-package to another sub-package above it in a stacked sub-package configuration, the upper portions of the sub-package interconnections 350 may be exposed by known methods, such as by grinding or laser drilling.

A sub-package to be stacked on top of another sub-package may not include conductive metal balls, such as a BGA, but may include pads 321 corresponding to the sub-package interconnects of the sub-package on which they are stacked.

Seal for a motor vehicle

For one embodiment of the invention, encapsulation of the die of the sub-package is achieved using a stencil printing process. The high coverage of the encapsulant is controlled by optimizing the stencil printing process and material selection for improved processability, sealing performance, and thermodynamic properties. Fig. 4 illustrates a process for encapsulating the die of a sub-package while exposing an upper portion of the sub-package interconnects according to one embodiment of the invention. The process 400 shown in fig. 4 begins with operation 405, where a template is provided and placed on a substrate. The stencil may be a thin nickel plate that is patterned to cover some of the upper portions of each of the sub-package interconnections.

A stencil-printable encapsulant is provided at operation 410. Typical sealants are non-stencilable, but may be made stencilable by reducing their viscosity, for example by adding a solvent to the sealant.

At operation 415, a stencil-printable encapsulant is applied to encapsulate the die. The amount of encapsulant is controlled such that the die (e.g., die stack) and associated wires are completely encapsulated while the upper portion of each of the sub-package interconnects remains exposed. The lower portion of the sub-package interconnections is also sealed. In practice, some of the encapsulant may remain on the upper portions of the sub-package interconnects, but a low viscosity encapsulant helps to reduce the amount of such encapsulant.

At operation 420, the substrate is subjected to an elevated temperature to remove the solvent (i.e., evaporate some or all of the solvent added in operation 410). For one embodiment of the present invention, the substrate is subjected to a temperature of about 100 degrees Celsius for about 2 hours. The temperature and time for such an evaporation process may be modified depending on the amount of solvent to be evaporated. The solvent that assists the stencil printing process is removed as much as possible prior to reflow to reduce voids that may form during curing/reflow if the solvent is not removed. Removal of the solvent increases the viscosity of the applied sealant. For one embodiment of the present invention, after baking, the encapsulant is cured (cross-linked) during a subsequent reflow process, which is described more fully below. For one embodiment of the invention, such curing is accomplished simultaneously with solder reflow. For one embodiment of the invention, the curing kinetics of the sealant are specifically designed to reduce interference with joint formation.

Refluxing

Two or more sub-packages are interconnected to form a stacked sub-package device according to one embodiment of the invention. The sub-packages are stacked on top of one another such that the pads or conductive metal balls on the bottom side of the topmost sub-package correspond to the exposed sub-package interconnects of the sub-package below the next in the stack. A reflow process or other conventional surface mount process is then performed to create interconnections between the sub-packages. During reflow, the viscosity of the encapsulant is reduced by the elevated temperature. There is a wetting force between the pads of the upper sub-package and the sub-package interconnections of the lower sub-package, causing any encapsulant material remaining on the surfaces of the sub-package interconnections to drain away allowing for the proper formation of interconnections between the sub-packages.

Fig. 5 illustrates a stacked-die device including stacked sub-packages according to one embodiment of the invention. The stacked-die device 500 shown in fig. 5 includes three sub-packages 505a, 505b, and 505c, which may be stacked-die sub-packages manufactured according to embodiments of the present invention. The sub-package 505a includes a substrate 510a with conductive balls 520. Sub-package 505a has dies 530a and 530b encapsulated with encapsulant 545 a. The upper portions 551a of the sub-package interconnects 550a are exposed and form interconnections with the pads 521b formed on the bottom surface of the sub-package 505 b. Sub-package 505b has dies 530c and 530d attached to substrate 510b, which are encapsulated with encapsulant 545 b. The upper portions 551b of the sub-package interconnects 550b are exposed and form interconnections with the pads 521c formed on the bottom surface of the sub-package 505 c. Sub-package 505c has dies 530e and 530f attached to substrate 510c, which are encapsulated with encapsulant 545 c. The entire sub-package interconnect 550c is also encapsulated. The stacked-die device 500 is also typical, as are each of the stacked sub-packages of the stacked-die device 500. The stacked-die device may have any reasonable number of stacked sub-packages and each sub-package may have one die or any number of stacked dies.

General matters

Embodiments of the present invention provide methods and apparatus for producing stacked-die devices having a stacked sub-package configuration. Various embodiments of the invention have been described as including particular features or processes. The features or processes may be modified for alternative embodiments of the invention. For example, although the sub-package interconnections are generally described as conductive metal balls, it may be any suitable material or shape in accordance with alternative embodiments of the present invention.

Embodiments of the invention have been described as a process having various operations. Such operations are exemplary and may be described in their most basic form, but operations may be added to, deleted from, or modified in processes according to various embodiments without departing from the basic scope of the invention. For example, in the process 400 described above with reference to fig. 4, the operation of covering the sub-package interconnections may be omitted. For such a process, the upper portion of the sub-package interconnects may be exposed by dragging a squeegee across the surface to which the encapsulant is applied to expose the sub-package interconnects. For such embodiments, the limited encapsulant material remaining on the surface of the sub-package interconnects will flow down the surface during reflow due to the increased viscosity of the encapsulant and wetting between the sub-package interconnects and the corresponding pads of the connected sub-packages. Thus, any residual sealant does not interfere with the formation of the proper interconnections.

According to one embodiment of the invention, a no-flow underfill material may be applied prior to reflow for better joint formation and thermal energy dissipation. In an alternative embodiment of the invention, the underfill material may be applied after the sub-packages have been attached.

While the invention has been described in terms of several embodiments, those skilled in the art will recognize that the invention is not limited to the embodiments described, but can be practiced with modification and alteration within the spirit and scope of the appended claims. The description is thus to be regarded as illustrative instead of limiting.

Claims (29)

1. An apparatus, comprising:

a substrate having a top surface and a bottom surface;

a set of one or more dies attached to the top surface of the substrate, the one or more dies extending a first distance above the top surface;

one or more interconnects formed on the top surface of the substrate, the one or more interconnects extending a second distance above the top surface; and

an encapsulant disposed on the top surface of the substrate and extending a third distance above the top surface, the third distance being greater than the first distance and less than the second distance such that the one or more dies are encapsulated and portions of the one or more interconnects are exposed, wherein the interconnects comprise metal balls.

2. The apparatus of claim 1, wherein one or more dies are attached to each other in a stacked die configuration and an uppermost portion of an uppermost die extends a first distance above the top surface.

3. The apparatus of claim 1, wherein one or more of the dies has an associated conductive line that extends a fourth distance above the top surface, the fourth distance being less than the first distance such that the associated conductive line is encapsulated.

4. The device of claim 1, wherein the sealant is a thermoset material.

5. The apparatus of claim 1, further comprising:

a second substrate having a top surface and a bottom surface, the second substrate having a second set of one or more dies attached to the top surface of the second substrate, and one or more conductive regions formed on the bottom surface of the second substrate, each conductive region electrically coupled to a respective one of the one or more interconnects formed on the top surface of the substrate.

6. The device of claim 4, wherein the thermoset material is an epoxy.

7. The apparatus of claim 3, wherein the associated wires of one or more dies comprise wire bonds.

8. The apparatus of claim 1, wherein one or more of the dies has a logical processor device implemented thereon.

9. A system, comprising:

a first sub-package; and

a second sub-package stacked on top of and electrically connected to the first sub-package, each of the first sub-package and the second sub-package including a substrate having one or more dies attached to a top surface thereof and one or more interconnects formed on the top surface thereof, and an encapsulant disposed on the top surface of the substrate such that the one or more dies are encapsulated and an upper portion of each of the one or more interconnects is exposed, the interconnects including metal balls.

10. The system of claim 9, wherein the substrate of the second sub-package has one or more conductive regions formed on a bottom surface, each conductive region electrically coupled to a respective one of the one or more interconnects formed on the top surface of the substrate of the first sub-package.

11. The system of claim 10, further comprising:

one or more additional sub-packages successively stacked atop the second sub-package, each additional sub-package comprising a substrate having one or more dies attached to a top surface thereof and one or more interconnects formed on the top surface thereof; and an encapsulant disposed on the top surface of the substrate such that the one or more dies are encapsulated and an upper portion of each of the one or more interconnects is exposed; and one or more conductive regions formed on the bottom surface, each conductive region electrically coupled to a respective one of the one or more interconnects formed on the top surface of the substrate of the immediately preceding sub-package.

12. The system of claim 9, wherein one or more dies are attached to each other in a stacked die configuration.

13. The system of claim 9, wherein one or more of the dies has associated leads that are completely encapsulated by the encapsulant.

14. The system of claim 13, wherein the associated wires of one or more of the dies comprise wire bonds.

15. The system of claim 9, wherein the sealant is a thermoset material.

16. The system of claim 15, wherein the thermoset material is an epoxy.

17. The system of claim 9, wherein one or more dies implement a logical processor device.

18. A method, comprising:

forming one or more interconnects on a top surface of a substrate, the one or more interconnects extending a first distance above the top surface of the substrate;

attaching a set of one or more dies to a top surface of a substrate, the one or more dies extending a second distance above the top surface;

the encapsulant is applied over the top surface of the substrate and the one or more interconnects such that the encapsulant extends a third distance over the top surface, the third distance being less than the first distance and greater than the second distance.

19. The method of claim 18, further comprising:

a template is placed on the substrate prior to applying the encapsulant, the template having a pattern corresponding to one or more interconnects formed on a top surface of the substrate such that the template reduces an amount of the encapsulant formed on any of the one or more interconnects that extend a first distance greater than a second distance above a top surface of the substrate.

20. The method of claim 19, wherein the sealant is a thermoset material.

21. The method of claim 20, wherein the thermosetting material is an epoxy.

22. The method of claim 21, further comprising:

the viscosity of the thermal epoxy is reduced before it is applied to the top surface of the substrate.

23. The method of claim 22, wherein reducing the tack of the thermal epoxy comprises adding a solvent thereto.

24. The method of claim 18, further comprising:

stacking a second substrate, the second substrate having a top surface and a bottom surface atop the substrate, the second substrate having a second set of one or more dies attached to the top surface of the second substrate, and one or more conductive regions formed on the bottom surface of the second substrate, each conductive region corresponding to an interconnection of one or more interconnects formed on the top surface of the substrate.

25. The method of claim 24, further comprising:

a reflow process is performed such that an electrical connection is formed between each of the interconnects formed on the top surface of the substrate and each of the corresponding conductive regions formed on the bottom surface of the second substrate.

26. The method of claim 18, further comprising:

a squeegee is applied over the encapsulant to reduce an amount of encapsulant formed on any of the one or more interconnects that extend a distance greater than the second distance over the top surface of the substrate.

27. The method of claim 18, wherein one or more of the dies has associated leads that are completely encapsulated by the encapsulant.

28. The method of claim 27, wherein the associated wires of one or more dies comprise wire bonds.

29. The method of claim 18, wherein one or more dies implement a logical processor device.