HK1109510B - Xo-buffer robust to interference - Google Patents

Description

Anti-interference XO buffer

Technical Field

The present invention relates to methods and apparatus for suppressing interference in RF circuits, and more particularly to circuit and wiring techniques for distributing oscillator reference signals while suppressing unwanted spurious signals.

Background

Integrated radio receivers do not easily implement Radio Frequency (RF) synthesizers that are interference resistant and have fast settling times. Interference immunity requires that all frequencies be synchronized. This typically requires that the frequency synthesizer reference frequency be equal to the RF channel spacing and that the reference oscillator frequency, typically generated by a crystal oscillator, be an integer multiple of the channel spacing. This configuration is virtually free of spurious components since all frequencies are harmonically related. However, the settling time of a synthesizer having such a reference frequency and channel spacing relationship may be undesirably long because the settling time is proportional to the inverse of the channel spacing (i.e., the reference frequency).

Because of these conflicting requirements, which are exacerbated by the need to support frequency generation for various standards with uncorrelated channel spacing, fractional-N synthesizers are commonly used. fractional-N synthesizers are prone to generate interfering components when the radio carrier frequency generated is close to, but not equal to, an integer multiple of the synthesizer reference frequency. Thus, parasitics at an offset equal to the difference between the carrier and the reference harmonic will accompany the carrier. See Jan-Wim Eikenbrook and Sven Mattisson, "Frequency Synthesis for Integrated transceivers," capturer Part III, page 339-: Mixed-Signal Design; PLLs and synthesizers, Kluwer Academic Publishers, 2000. Suppressing these parasitic components is very difficult and time consuming, often requiring many Application Specific Integrated Circuit (ASIC) iterations, which increases the complexity and cost associated with these devices.

A fractional-N synthesizer typically takes a reference frequency from an on-chip or off-chip crystal oscillator (XO) which is provided to a phase frequency detector through one or more buffers. These buffers are required to ensure a sufficiently low noise level by increasing the crystal signal power and making the reference zero crossings as short as possible (e.g. a steep square wave). Modern radio transceivers (i.e., transmitter plus receiver) are often constructed as integrated circuits (e.g., ASICs), including one or more on-chip RF oscillators. However, RF oscillators are a source of unwanted signal and power supply leakage, which introduce performance-degrading interference not only in the associated circuitry but also in adjacent circuitry. One source of interference from an on-chip RF oscillator is the inductance of the oscillator's LC tank, which is tuned to a particular frequency based on an applied control voltage (e.g., by controlling the voltage of a varactor diode to change the capacitance of the LC tank).

Fig. 1 illustrates the interference situation that occurs with respect to a conventional fractional-N Phase Locked Loop (PLL) frequency synthesizer. As shown in fig. 1, a crystal oscillator (XO)110 generates a reference signal 112, which is input to a buffer 114. The reference signal is preferably a sinusoidal signal, having a frequency of f_xo(or more commonly f)_refTo represent the frequency of any type of reference signal). The buffer 114 may be a limiter, which is at the frequency f_refGenerating a deformation phi of an XO reference frequency signal_R116 and has a steep zero-crossing characteristic. The reference signal output from the XO buffer is input to the Phase Frequency Detector (PFD)118 along with the phase and frequency of the output of the frequency divider 132. The output of the PFD is a pulse, which is compared to a reference frequency signal phi_R116 and the output of divider 132. The output of the phase detector 118 is applied to a charge pump (not shown) and then filtered by a low pass filter 122. The output of the loop filter 122 is then applied to a Voltage Controlled Oscillator (VCO) 126. Output signal phi of VCO 126₀128 are provided to the input of a frequency divider 132. The frequency divider receives a control signal provided to control input 134.

As a result of this feedback arrangement, the VCO 126 outputs a signal φ_RFrequency f of_OIs driven equal to the reference signal frequency multiplied by the division factor of divider 132. Thus, the frequency of the VCO 126 can be controlled by controlling the division factor by the control input 134 of the frequency divider 132.

The divider 132 dynamically adds or subtracts some integer (i.e., N M, where N and M are integers) to the VCO output signal phi in proportion to N and N_RFrequency f of_OA frequency division is performed which results in an average frequency division ratio N plus a fraction K/F (K and F are integers). K/F is the duty cycle for determining the fractional value, where F is the circuitIs the fractional modulus of (e.g., 8 means 1/8 fractional resolution), K is the fractional channel of work. The signal φ at the output of the VCO 126 by applying K and F values associated with a particular desired frequency to the divider control input 134₀Can be set to a frequency f_O＝f_ref(N+K/F)。

As shown by the dashed paths in fig. 1, inductive coupling from the VCO inductor may enter the crystal oscillator bond wires (not shown), the reference frequency signal path 112 along path 140, the PFD input paths 116 and 136 along paths 142 and 144, and the power supply rail (not shown), respectively. The power supply is also disturbed by the VCO current, which causes a voltage drop between VCC, ground, and the substrate. Unwanted low frequency mixing products are produced when the VCO frequency leaks into either of the PFD inputs.

The PFD input of the frequency synthesizer is typically connected to a latch. For example, edge triggered latches are widely used in PFDs of fractional-N synthesizers. The basic construction of this type of PFD includes a pair of edge-triggered, resettable D-flip-flops with the D input set to a logic 1. The clock inputs of the D-flip-flops receive a signal having a reference frequency and a signal having a frequency of a Voltage Controlled Oscillator (VCO) divided by a value set in the frequency divider, respectively. The Q output of the D-flip-flop is input to an AND (AND) gate, which when high outputs a reset signal to both D-flip-flops. The state of the Q output of the D-flip flop produces "UP" and "DOWN" pulses, respectively, of a duration corresponding to whether the frequency of the reference frequency leads or lags the frequency of the divided VCO signal. The output of the PFD is used to control a charge pump in a known manner, the output signal of which is low-pass filtered and applied to the input of the VCO. More detailed descriptions of edge-triggered PFDs are available in T.H. Lee, "The Design of CMOS Radio-Frequency Integrated Circuits" (Design of CMOS Radio Frequency Integrated Circuits), Cambridge University Press, Cambridge, 1998, and B.Razavi, "RE Microelectronics" (RE Microelectronics), Prentice-Hall, Upper saddleRiver, 1998.

The latches of the edge triggered PFD are wideband. Timing jitter appears in the VCO control voltage generated by the PFD when the VCO signal leaks to the clock of any latch. Jitter on the VCO control voltage will cause the VCO to mix with the closest harmonic of the reference signal. When the difference between the two is sufficiently small, two unwanted in-band spurious tones may appear on either side of the VCO output frequency.

The interference situation shown in fig. 1 can be modeled as shown in fig. 2 without losing its generality. In fig. 2, the XO-buffer 114 of fig. 1 is modeled as a differential pair 210 including transistors Q1 and Q2. The collector of each transistor Q1 and Q2 is connected to a load resistor R_OThe emitters of the transistors Q1 and Q2 are commonly connected to a constant current source 212. The input of the phase frequency detector 118 is also shown as a differential pair 220 comprising transistors Q3 and Q4, their collectors connected to a load resistor R and their emitters connected in common to a constant current source 222. Load resistor R of differential pair 210_OAnd the load resistor R of the phase frequency detector input 220 is connected to V_CCThe supply voltage rail 226. Input reference frequency signal v from XO source_xoThe buffer input to the bases of transistors Q1 and Q2 of differential pair 210 is applied (along path 112 from XO 110 in fig. 1).

Various documents are known. For example, EP1349268a2 describes a large gain range, high linearity, low noise MOS VGS with noise suppression based on differential design. Entitled "15 Gbit/s high-gain amplifier buffered using Si-bipolar production technology" (15 Gbit/s high gain limiting amplifier constructed using silicon bipolar production technology),et al, Electronic Letters, Vol.30, No.18, describes a limiting amplifier with two separate output buffers. JP9162731 describes providing a low output impedance logic circuit to the end points of a transmission line.

Returning to fig. 1, the output signal produced by the XO-buffer is passed alongThe path 116 is provided to the input of a phase frequency detector 118. Along this path, the interference caused by VCO leakage is modeled in fig. 2 with two interfering components 230 and 232. The first interference component 230 has a voltage v_ccxIs connected in series with V between the XO-buffer 210 and the input of the PFD 220_CCIn the circuit. The second interference component 232 is used for generating an induced interference voltage v_xIs shown as a three-winding transformer 232 connected in series in the path from the output of the XO-buffer to the input of the PFD. When these interference components 230 and 232 are applied to the input signal v of the PFD input 220_iWill be compared with the output signal v generated by the XO-buffer_bDifferent.

The problems caused by VCO leakage are currently overcome by employing balanced signal paths in combination with circuits with high common mode rejection and power supply rejection ratios (CMRR and RSRR, respectively). Balanced wiring schemes are effective in some respects because they result in most of the interference entering the signal path being common mode, with only a small imbalance term disturbing the reference signal, either due to some wiring asymmetry or limited CMRR. Such schemes typically suppress interference in the signal path by 20 to 40 dB. Interference into the power supply rail will similarly be suppressed by a high PSRR, typically of the same order as the CMRR. However, with increasing degrees of integration, the on-chip distance becomes smaller and smaller. Meanwhile, as the on-chip inductor is not changed in proportion to other circuit technologies, the relative spacing between the inductor and the conducting wire is also smaller, and the inductive coupling interference is further worsened. For example, the spurious level at the GSM frequency synthesizer output must be more than 44dB below the carrier biased at 400kHz, assuming a loop filter attenuation at this bias of 23dB, which corresponds to a reference frequency spurious of-88 dBc below the DCS band with a 13MHz crystal reference signal. Even with today's wiring and circuit technology, it becomes increasingly difficult to achieve these spurious frequency levels. Therefore, there is a need in the art for a more robust reference frequency allocation scheme.

Disclosure of Invention

It should be emphasized that the term "comprises/comprising" when used in this specification is taken to specify the presence of stated features, integers, steps or components; the use of these terms does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.

According to one aspect of the invention, a reference frequency allocation apparatus comprises an oscillator for generating a reference frequency signal, and buffer means having an input connected to an output signal path of the oscillator. The buffer arrangement includes at least one component spatially separated from other components of the buffer to increase the output impedance seen from the buffer. The rewiring of the buffer component locations causes the buffer output impedance to suppress unwanted spurious components generated by the leakage of the RF signal into the signal path.

According to another aspect of the invention, a method of suppressing unwanted signals along an RF signal path to an input circuit includes providing sub-components of a buffer limiter arrangement in first and second regions of a substrate, and routing the RF signal path from an output of the buffer arrangement to the input circuit provided in the second region of the circuit layout. By providing the buffer limiter sub-assembly in the second region, the buffer limiter output impedance and the input impedance of the input circuit become mismatched, thereby suppressing interference introduced on the signal path between the buffer limiter output and the input circuit input.

Another aspect of the invention relates to a phase-locked loop (PLL) circuit that includes a buffer limiter having an input for receiving a reference frequency signal and an output for outputting a buffered reference frequency signal. A first low pass filter is connected in the signal path between the buffer and the first input of the phase frequency detector. A second low pass filter is applied to the output of the phase frequency detector to produce a filtered phase detector output. In turn, the voltage controlled oscillator generates an output signal whose frequency depends on the filtered phase detector output. The output signal is received by a frequency divider, which produces a divided signal. In a PLL, the physical layout of the first filter and the components of the buffer results in the output impedance of the buffer being greater than the impedance of the first input of the phase frequency detector.

Another aspect of the invention relates to a method for suppressing unwanted signals along a radio frequency-RF-signal path to an input circuit, comprising the steps of: providing a sub-assembly (Q) of buffers in first and second regions of a substrate₁，Q₂，R_O) (ii) a Routing RF signal paths from outputs of the buffer to input circuits disposed in a second region of the substrate in which a buffer subassembly (R) is disposed_O) Causes the output impedance of the buffer and the input impedance of the input circuit to become mismatched and thereby suppresses interference introduced into the RF signal path between the buffer output and the input circuit input; low pass filtering an RF signal path near the input circuit; and providing a plurality of low pass filters and a plurality of buffers in the RF signal path between the output of the buffers and the input of the input circuit, wherein each of said buffers is continuously connected to one of said low pass filters.

Another aspect of the invention relates to a phase-locked loop circuit for suppressing unwanted signals, comprising: a buffer having an input for receiving a reference frequency signal and an output for outputting a buffered reference frequency signal; a phase frequency detector having first and second inputs; a first low pass filter connected in the radio frequency-RF-signal path between the buffer and the first input of the phase frequency detector; a second low pass filter acting on the output of the phase detector to produce a filtered phase detector output; a voltage controlled oscillator for generating an output signal having a frequency dependent on the filtered phase detector output; a frequency divider for receiving the output signal and generating a frequency divided signal; characterized in that the physical layout of the first low-pass filter and the sub-components of the buffer results in an output impedance of the buffer being greater than an impedance of the first input of the phase frequency detector to suppress interference present on the RF signal path, wherein the buffer further comprises a differential output connected to the first input of the phase frequency detector, wherein at least one component of the first low-pass filter is connected across the differential output.

Additional aspects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The aspects and advantages of the invention will be realized and attained by the systems and methods particularly pointed out in the written description and claims hereof as well as the appended drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings:

fig. 1 is a schematic diagram of a phase-locked loop (PLL) circuit showing a VCO leakage path.

Fig. 2 is a circuit model showing the effect of interference due to leakage from RF components.

Fig. 3 is a circuit model showing the parasitic components of fig. 1 and 2 as circuit elements.

Fig. 4 shows a part of a PLL circuit in which the load resistors are rearranged according to an exemplary embodiment of the present invention.

Fig. 5 is a block diagram of an exemplary PLL RF circuit including a filter provided before a phase frequency detector according to an exemplary embodiment of the present invention.

Fig. 6a to 6c are circuit diagrams illustrating PLL circuit components in which a low-pass filter is provided before a phase frequency detector according to an exemplary embodiment of the present invention.

Fig. 7 is a block diagram showing a low pass filter and buffer circuit arranged in cascade along a reference frequency signal path.

Detailed Description

These and other aspects of the invention will now be described in detail, with reference to exemplary embodiments thereof as illustrated in the accompanying drawings.

To achieve a solution to the above-described interference pickup problem, a simplified model shown in fig. 3 is used to analyze the interference source shown in fig. 2. For reasons of generality, all signals are assumed to be unbalanced, but since the PSRR and CMRR are cancelled by the appropriate amount, the results are easily extended to the balanced case (i.e. symmetrical or almost symmetrical). Therefore, only the unbalanced signal representation is used in the following.

As shown in fig. 3, i_bAnd v_bRespectively representing buffer output current and voltage, v_iRepresenting the input voltage of a Phase Frequency Detector (PFD). Induced signal interference in figure 3 using voltage source v_xCurrent source i for simulating, capacitive (conductive) signal crosstalk_xTo indicate. Voltage source v for power supply interference_ccxExpressed as R for the buffer output impedance and the PFD input impedance, respectively_OAnd r_iTo indicate. Can be shown as

Here, the frequency dependence is omitted for simplicity. Typical buffers are designed to have a low output impedance (i.e., R)_O＜＜r_i) So equation (1) can be simplified as follows:

v_i1≈[(i_b+i_x)·Ro+(v_x+v_ccx)](2)

this strategy reveals that the effect of capacitive crosstalk can be determined by selecting i_bTo minimize i_xBecomes unimportant. In addition, it is apparent that a larger spacing of circuit components results in v_xAnd v_ccxRatio of i to i_b·R_OMuch smaller. However, current and future demands for increased circuit density make such spacing increasingly difficult, if not impossible, to achieve. Therefore, it is necessary to provide inhibition v_xAnd v_ccxOther ways of the above.

The present invention deals with the interference caused by RC leakage by varying the impedance levels at the buffer output and the PFD input in a first exemplary manner. For example, let R_O＞＞r_iResulting in:

where i is_xIs omitted because it does not play a greater role than in equation (2). From equation (3), it can be seen that_xAnd v_ccxCaused drynessThe disturbance will be in the ratio R_O/r_iBut is suppressed. By generating impedance mismatch via high buffer output impedance, the buffer is made to have a low impedance mismatch_xAnd v_ccxThe resulting interference will be more robust.

FIG. 4 illustrates increasing the buffer output impedance relative to the phase detector input impedance to obtain a high ratio R_O/r_iExemplary manner of (a). As shown in fig. 4, the snubber load resistor R_OIs provided physically closer to the input of the phase detector input 420 than the buffer unit 410. Providing buffer load resistor R closer to the PFD input_OIncreases the buffer output resistance and decreases the input resistance of the PFD, thus suppressing the output resistance from v as can be seen from equation (3)_xAnd v_ccxResulting in interference.

For example, RF ASICs typically have an R of approximately 500mv/1mA or 500 Ω resistance_O. Corresponding normal input resistance r_i≈β/g_mOr about 2.5k omega at 1 mA. (the inputs of the buffer and phase detector usually operate at similar current levels for noise reasons.) when the resistor is moved to the input side of the PFD, the input resistance of the PFD becomes r_i≈R_OOr 500 Ω and is here denoted by r_oThe buffer output impedance is represented by the initial voltage V of transistors Q3 and Q4_AAnd (4) giving. Initial voltage V in general_ACan be at a collector current (I) of 1mA_C) It was 25V. This translates into a buffer output resistance r_o≈V_A/I_COr 25k Ω, yield excellent v_xAnd v_ccxInterference suppression 25000/500 or 40 dB.

Simple rearrangement of the load resistor R in case a disturbance is already present in the signal path from the reference signal source_OIt will not be sufficient to suppress the parasitic components caused by the interference. For example, interference on the reference signal path can cause PLL spurious tones in two ways: (1) subsampling (i.e., folding) of unwanted audio in the PFD or (2) in the reference signal and buffer signal paths (before the PFD input)) Inter-modulation between interfering tones. Therefore, there is a need for alternative or additional ways to suppress the interference components caused by subsampling and intermodulation.

According to the invention, the suppression of these tones is achieved in a second way, in which the reference frequency signal is cleaned by filtering. In the subsequent analysis, it is assumed that the interference is caused by interfering audio. However, the concepts discussed below are equally valid for noise, bearing in mind that an increased noise floor or noise "hump" will be observed, rather than the clear PLL spurs associated with interfering audio.

The phase noise caused by the sub-sampling of the RF at the PFD input is roughly proportional to the ratio of the slew rates (slew rates) of the reference and interferer signals at the PFD input (when the interferer signal is much smaller than the reference signal). In order to reduce phase noise, it is known to place a limiting buffer at the front end of the reference path to maximise the reference signal slew rate, whilst limiting any effect of interference picked up behind the buffer. However, once the interferer enters the signal path, simply adding a limiter will not change the slew rate ratio. In this case, a low pass filter may be introduced to suppress the interference while minimizing the effect of the reference signal.

Fig. 5 is a block diagram of a fractional-N phase locked loop circuit in which a low pass filter is used to suppress spurious tones caused by interference in the signal path of a reference frequency signal, according to an exemplary embodiment of the present invention. The PLL shown may be used in a transmit circuit of a communication device, such as a mobile phone, for example. For example, similar circuitry may be used in the receive circuitry of such devices.

Having a frequency f_refIs provided to the input of a buffer 520 which limits the amplitude and outputs a square wave signal with steep zero crossings. The output of the buffer is provided to a Low Pass Filter (LPF)530 that filters the reference signal and provides a filtered signal to a first input of a Phase Frequency Detector (PFD) 540. Although only one buffer 520 is shown in figure 5,it is understood that multiple buffer stages and LPFs may be present in the path between the low pass filter 530 and the PFD 540. The output of the PFD540 is filtered in a loop filter 550 and passed to a Voltage Controlled Oscillator (VCO)560, which provides an output signal at a VCO output 570. The output of VCO 560 is also provided to divider 580 where it is divided by a divide ratio. The divided output of divider 580 is provided along path 590 to a second input of PFD 540.

After the first buffer (i.e., limiter) 520, the output will be close to a square wave in waveform. Thus, the effect of the low pass filter 530 on the signal zero crossing slew rate can be estimated by evaluating the peak slew rate of the filter output when a step input is received. The maximum slew rate will be a reasonable approximation of the slew rate at the zero crossing.

The filter output response can be calculated in the laplace domain as follows:

v_o(s)＝v_i(s)·H(s)，

where v is_i(s) and H(s) are the filter input signal and the transfer function, respectively, in the s-plane. Nominal output slew rate due to stepped input (i.e., v)_i(s) is as follows

Assuming an on-chip passive filter, all poles are real, and for simplicity and without loss of generality, it can be assumed that all poles coincide. The transfer function of such an n-pole filter can be expressed as:

where a is the filter pole angular frequency, H₀Is the low frequency gain. (see, for example, John J.Dt' Azzo and Connstatinine H.Houpis, Linear Control System Analysis and Design-conventional and modern), McGraw-Hill, 1981.) the nominal output voltage (i.e., a 1 and H₀1) the time derivative is equal to the impulse response of the filter, e.g. the derivative operator is summed with the input signal,

the peak slew rate is approximately equal to the zero-crossing slew rate, which may be approximatelyFor n ≦ 10, the error is less than 35%.

Nominal filter slew rateProportional to the inverse of the filter order. Thus, the off-nominal slew rate will be proportional to the filter pole frequency divided by its order (i.e., a/n). Furthermore, the filter attenuates high frequency and (s/a)ⁿ＝(ω_RF/a)ⁿIs in direct proportion. Since the decay increases faster with n than with the slew rate, we take the maximum value of n and the minimum value of a in order to maximize the slew rate decay result. However, due to noise constraints, the slew rate cannot be reduced and one has to select a filter pole frequency that is much higher than the frequency that can result in maximum slew rate attenuation. The pole frequency (i.e., a/2/π) is typically selected to be the crystal oscillator reference frequency f, which is often 13 or 26MHz_oxMultiplication by a preceding, usually 10^mZero crossing gain results, where m is the number of limiters. In practice, the limiter (rather than the filter) will limit the bandwidth, for example when m exceeds 3. In this case, since the attenuation is small (i.e., ω_RFA), the filter can be omitted or the filter bandwidth can be set similar to the limiter bandwidth. However, as shown below, the filter is preferably placed after the first limiter, in which case m is 1.

Fig. 6a to 6c show an exemplary implementation of a low pass filter between the buffered reference frequency signal and the phase frequency detector input. It will be appreciated that the circuitry shown may be part of a PLL, such as a PLL of a frequency synthesizer, a modulator or some other RF circuit. The circuit portions shown in fig. 6a to 6c are explained above with respect to similarly labeled elements in fig. 4. For example, the functions of current source 612/622, transistors Q1 through Q4, and simulated conduction and induced disturbance 630/632 of fig. 6a through 6c correspond to current source 412/422, transistors Q1 through Q4, and simulated conduction and induced disturbance 430/432, respectively, described above with respect to fig. 4.

Fig. 6a shows a buffer 610 and a PFD input 620 of a PLL in which a two-pole low-pass filter is added to the signal path before the PFD input. The bipolar point low-pass filter of fig. 6a is a single-ended configuration comprising two values C₁Two values of C₂And is connected to signal groundResistor of potential (shown as value R)₀/2). Other filter topologies, such as active RC or LRC filters, may also be used, but are preferably at least second order, have low input impedance, and are placed close to the PFD input. The low pass filter thus arranged increases the impedance mismatch between the stages and thus reduces the picked up induced interference in addition to suppressing high frequency interference and noise.

By providing one or more pairs of capacitors and resistors in a differential configuration (e.g., by bridging these components across signal lines), some chip space can be saved, but at the expense of CMRR. For example, FIG. 6b shows an example of the invention where the filter buffer paths have two poles, one single ended and one differential. Fig. 6c shows an exemplary filter buffer path with 3 filter poles, two of which are differential and one of which is single ended.

The limiting buffer has a saturating transfer function. The transfer function is highly nonlinear and stabilizes the output signal amplitude (and PLL loop gain) while improving the zero-crossing slew rate. When a sinusoidal signal from an oscillator (e.g. a crystal oscillator (XO)) is generated having an angular frequency ω_xoOf (c) and a small RF interference through such a limiter, both signal components are subject to harmonic and intermodulation tone generation. In the vicinity of RF audio, the dominant component decays quickly to the harmonic spectrum and odd-order intermodulation products of the square-wave-like crystal oscillator signal. These two signal components can be represented as:

here, v_xo1Is the amplitude of the underlying audio frequency or frequencies,and:

here, v_rf0Is the amplitude of the fundamental RF interference audio.

After one limiter stage, the RF intermodulation products decay fast enough not to cause any low-frequency spurious components close to the reference signal fundamental frequency. However, the situation may be different after the second limiter stage (i.e. when the signal passes through two cascaded limiters). In this case, the amplitude of the intermodulation tones near the RF interference does not attenuate much with distance from the RF fundamental tone, as is the case with only one pair of successively connected limiters. The effect of this spectral broadening is when the RF carrier is selected to be an odd multiple of the oscillator frequency fxo (e.g., 71 · f)_xo+Δ_f) The appearance of intermodulation tone frequency is very goodClose to the crystal oscillator fundamental frequency f_xo＝(ω_xoAnd/2 pi). When the RF carrier is close to f_xoIs an even multiple of (e.g., 72 · f)_xo+Δ_f) There are similar spectral results, except that there are odd order intermodulation tones between the crystal oscillator harmonics. In either case, removing the intermodulation tones through filtering would be difficult due to the need for the filter to have a high Q value. Such a filter may be a complex active filter or RLC filter, both variants being prone to pick up interference due to large area and/or mutual inductance with the RF carrier line.

The mechanism of the broadening of the intermodulation spectrum is: after the first limiter, the limiter is no longer fed with two sinusoidal signals. The second limiter will receive as input the sum of the two signals described in equations 4 and 5. Currently, there are not only odd-order intermodulation products of the two fundamental frequencies, but also all combinations of fundamental frequencies plus harmonics and sidebands, resulting in a fairly flat intermodulation spectrum around the RF fundamental frequency. The only way to filter out the high order intermodulation products is to suppress the RF components between the first and second limiters. When there are multiple points of entry of RF interference, a filter will be provided between the limiters along with these points of entry.

Fig. 7 is a block diagram of a signal path including a cascaded low pass filter and buffer in accordance with the present invention. The signal path begins with the XO and buffer frequency signal distribution apparatus 710. Although device 710 is shown with an XO reference frequency signal source, the concept of cascading extends to a typical RF-type oscillator circuit or other signal source susceptible to interference from RF leakage. The device 710 output has a reference frequency f_xoIs provided to the input of low pass filter 720. Along this path is the entry point for RF interference Int 1. The low pass filter 720 increases the mid-stage impedance mismatch and filters out the high order intermodulation products introduced by the interference Int 1. The filtered output of filter 720 is provided to the input of buffer limiter 730. Additional buffers may be provided in series with buffer 730 if no interference problems exist in the signal path after buffer 730.

Fig. 7 shows an example after a further disturbance Int2 is introduced to the output of buffer 730. Similar to low pass filter 720 and buffer 730, the low pass filter cleans up the signal and adds to the impedance mismatch of the next stage. The above arrangement is repeated for any number of interference points along the signal path, if necessary. For example, fig. 7 shows the signal path after the entry of interference Int3 into buffer 750, followed by additional cascaded low pass filter 740 and buffer 750. As can be seen, virtually any number of buffer and filter combinations can be used to suppress interference and minimize its effect on the signal.

The foregoing inferences largely ignore frequency dependent effects in the derivation, but these can be readily inferred by those skilled in the art. The invention has been described with reference to specific embodiments. However, it will be apparent to those skilled in the art that the present invention may be embodied in other specific forms than the preferred embodiments described above. This is done without departing from the spirit of the invention.

For example, although the previous embodiments describe bipolar based circuits, the same principles can be applied to other technologies, such as CMOS. Although the embodiments described above refer to a path in the crystal oscillator signal path of a PLL, the use of these techniques is not limited to such a path and can be applied to other sensitive paths as well. In particular, the PFD feedback path has the same sensitivity in common with its input. For example, referring to fig. 5, the present invention can be used to suppress the ingress of spurious components along path 590. The proposed principle can also be used for such signal paths, depending on the wiring distance. In addition, the present invention is not limited to use in PLL circuits, but can be used in other RF circuits that require a reference frequency signal. For example, the invention can be used to suppress spurious components in mixer circuits, waveform generators, and other circuits where suppression of unwanted spurious components is desirable.

By rewiring some of the buffer components, substantial suppression of inductance and power induced interference components can be achieved. An inhibition ratio of about 40dB can be expected without affecting the normal operation of the buffer chain. By additionally adding filtering, further suppression can be achieved and/or generation of intermodulation products can be avoided. The cost in chip active area is substantially 0 when no filter is used, and is small when a filter is used. The additional interference margin will significantly reduce the parasitics and may save one or more ASIC reflow clips (respin). The invention is applicable to both balanced and single-ended signals.

It will be apparent to those skilled in the art that various changes and modifications can be made in the reference frequency allocation method and arrangement of the present invention without departing from the spirit and scope thereof. Thus, it is intended that the present invention cover the modifications of this invention provided they come within the scope of the appended claims and their equivalents.

Claims (10)

1. A method for suppressing unwanted signals along a radio frequency, RF, signal path to an input circuit, characterized by the steps of:

providing a sub-assembly (Q) of buffers in first and second regions of a substrate₁，Q₂，R_o)；

Routing RF signal paths from outputs of the buffer to input circuits disposed in a second region of the substrate in which a buffer subassembly (R) is disposed_O) Causes the output impedance of the buffer and the input impedance of the input circuit to becomeMismatch and thereby suppress interference introduced into the RF signal path between the buffer output and the input circuit input;

low pass filtering an RF signal path near the input circuit; and

a plurality of low pass filters and a plurality of buffers are disposed in the RF signal path between the output of the buffers and the input of the input circuit, wherein each of the buffers is continuously connected to one of the low pass filters.

2. The method of claim 1, wherein the buffer is a slicer.

3. A phase locked loop circuit for suppressing unwanted signals, comprising:

a buffer (520) having an input for receiving a reference frequency signal and an output for outputting a buffered reference frequency signal;

a phase frequency detector (540) having first and second inputs;

a first low pass filter (530) connected in the radio frequency, RF, signal path between the buffer and the first input of the phase frequency detector;

a second low pass filter (550) acting on the output of the phase detector to produce a filtered phase detector output;

a voltage controlled oscillator (560) for generating an output signal having a frequency dependent on the filtered phase detector output;

a frequency divider (580) for receiving the output signal and generating a divided signal;

characterized in that the physical layout of the first low-pass filter and the sub-components of the buffer results in the output impedance of the buffer being greater than the impedance of the first input of the phase frequency detector, to suppress interference present in the RF signal path,

wherein the buffer further comprises a differential output connected to a first input of the phase frequency detector,

wherein at least one component of the first low pass filter is connected across the differential output.

4. The phase locked loop circuit of claim 3 wherein the buffer is a limiter.

5. A phase locked loop circuit as claimed in claim 3, wherein at least one component of the first low pass filter is connected to ground.

6. A phase locked loop circuit as claimed in claim 3, comprising a second buffer coupled to the output of the first low pass filter.

7. The phase locked loop circuit of claim 3 wherein the first low pass filter includes at least two poles.

8. The phase locked loop circuit of claim 7 wherein the first low pass filter includes more than two poles.

9. The phase locked loop circuit of claim 3 wherein the phase frequency divider is a fractional-N divider.

10. A phase locked loop circuit as claimed in claim 3, wherein the oscillator means comprises a crystal oscillator.