HK1109492B - Directed auto-refresh synchronization - Google Patents

Abstract

In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.

Description

Guided auto-refresh synchronization

Technical Field

The present invention relates generally to the field of memories, and in particular, to a system and method for synchronizing bank addresses between a controller and a memory in a directed auto-refresh mode.

Background

This application claims priority based on U.S. provisional application No. 60/640,100, filed on day 28, 12/2004.

Microprocessors, digital signal processors, and other controllers perform computational tasks in a multitude of applications, including

Including embedded applications such as portable electronic devices. There is a tendency that: in each generation of products, such devices have an ever expanding set of features and enhanced functionality, including increased memory and more computationally powerful processors. Another trend in portable electronic devices is the ever shrinking form factor. The primary impact of this trend is the ever-decreasing size of batteries used to power controllers, memory, and other electronic devices in the device, making power efficiency an increasingly important design goal. Thus, improvements to the controller and/or memory that increase execution speed and reduce power consumption are desirable, particularly for portable electronic device processors.

As is well known in the art, Dynamic Random Access Memory (DRAM) is the most cost effective of solid state or electronic data storage technologies. DRAM stores binary data by charging or discharging individually addressable capacitive circuits. To achieve higher bit density and thus lower cost per bit, the circuitry to hold this charge indefinitely is omitted in DRAM technology. Thus, the charge dissipates due to leakage current. In order to preserve the state of data stored in a DRAM, the capacitive circuit storing the bit value must be periodically charged or "refreshed".

DRAM arrays are typically implemented as horizontal, rectangular, two-dimensional arrays comprising a plurality of rows and columns. Data bits are accessed by providing a row address and Row Address Strobe (RAS) control signal followed by a column address and Column Address Strobe (CAS). Once a given row is accessed or "opened," a large number of bit positions may be stored by incrementing the column address. Thus, especially for longer sequential data accesses, the delay in providing the row address and RAS signals may be amortized over many column accesses. This feature is further exploited by Fast Page Mode (FPM) and Extended Data Output (EDO) DRAM technologies, as is known in the art. When higher density DRAMs are packaged into multiple modules, another organization technique will divide the memory segments into separately addressable banks. In a representative implementation, memory addresses may be mapped to DRAMs, as shown below:

the lower level bits may include a byte selection field where the memory module provides data spanning several bytes in a single access. The second most significant bit is the column address, which allows rapid access to data within the same row. Above the row address is a bank select bit that independently addresses one of a plurality of DRAM banks (in this example, four banks). The row address includes more significant bits. Those skilled in the art will recognize that memory addresses may be mapped to memory in a variety of ways; accordingly, the above mapping is illustrative only and not limiting.

Conventional DRAMs are explicitly refreshed under the direction of a controller. The controller places a row address to be refreshed on the address bus and asserts a RAS signal to refresh each memory storage location in the row. During a refresh cycle, all memory access operations are interrupted (i.e., no read or write operations occur during the refresh cycle). A refresh counter in the controller provides a refresh row address and increments the counter after each refresh cycle. All rows in the DRAM array may be refreshed sequentially. This is known in the art as a burst refresh and must be performed once within the total required refresh time of the memory array. Alternatively, the controller may implement distributed refresh, where refresh cycles for successive rows are interspersed between memory access cycles. The average allowable delay between distributed refresh cycles is the total required refresh time of the memory array divided by the number of rows.

With the advent of CAS-before-RAS refresh (CBR refresh), the controller does not need to calculate and supply row addresses for refresh cycles. Memory modules that support CBR refresh include an internal row counter that is incremented upon receiving each CBR refresh cycle. The controller does not know which row is being refreshed at any given time; the controller is only required to issue CBR refresh cycles for the required period of time. CBR refresh is an example of what is broadly referred to herein as auto-refresh, where the controller directs the memory to issue a refresh cycle, but it does not know the particular row address being refreshed. In modern synchronous dram (sdram) implementations, auto-refresh cycles are typically performed in response to RAS and CAS signals being asserted simultaneously.

One disadvantage of conventional auto-refresh techniques (and additionally, in conventional refreshes, where the refresh row address is supplied by the controller if the banks are not independently refreshed) is that the controller is forced to close all DRAM rows for memory access operations (i.e., read and write accesses) before issuing the auto-refresh command. This may adversely affect processor performance by delaying data accesses and/or instruction fetches.

In the case of independently refreshing the banks, one solution is for the controller to explicitly handle the refresh process by providing the row address and bank selection information for each refresh command. In this case, the controller may direct the refresh cycle to one DRAM bank while performing data access operations on the remaining banks. Advanced controllers can organize their memory operations to take advantage of this capability, improving performance.

However, a drawback of this approach is that the controller cannot take advantage of the self-refresh mode provided by many modern memory implementations, which have particular applicability to portable electronic devices. In the self-refresh mode, data is held in the DRAM array during periods of inactivity and with minimal power consumption, and no data access is allowed. That is, during the self-refresh mode, data cannot be written to or read from the DRAM array. DRAM with self-refresh mode enables many circuits, including controllers, to enter an inactive or "sleep" mode to conserve battery power.

During self-refresh, memory mode cycles through the DRAM array, performing the minimum refresh activity necessary to maintain data. To accomplish this, the memory module maintains an internal row/bank address counter that the controller cannot access. Upon exiting the self-refresh mode, the controller does not know which row was last refreshed in the self-refresh mode, and therefore cannot continue with an explicit refresh operation unless it first performs a burst refresh on each row in turn.

Disclosure of Invention

In directed auto-refresh (DARF) mode, a refresh command is issued by the controller and refresh row and bank addresses are maintained inside the memory module. The controller and memory are synchronized with respect to the bank address by providing for initializing a bank address counter internal to the memory to a first predetermined value upon entering DARF mode. The memory performs a refresh cycle for the addressed bank upon receiving a refresh command, and increments the bank address counter in a predetermined order after the refresh cycle. The controller tracks the bank addresses, and if the memory access operation is directed to a bank that is not refreshed, the controller may issue one or more memory access operations during execution of the refresh command. During the self-refresh mode, lost synchronization is reestablished upon exiting the existing self-refresh mode by specifying that the bank address counter assume the second predetermined value. The second predetermined value may be fixed or may be n +1, where n is the value of the bank address counter when the self-refresh mode is initiated.

One embodiment relates to a method of synchronizing a refresh bank address with a refresh bank address counter in a memory module by a controller. The memory module is commanded to enter a directed auto-refresh mode. A directed auto-refresh cycle is issued to the memory, the auto-refresh cycle beginning at a first predetermined bank address.

Another embodiment relates to a method of refreshing a plurality of memory banks by a memory module. A synchronization command is accepted from the controller. A bank refresh counter is set to a predetermined bank address in response to the synchronization command.

Another embodiment relates to an electronic device. The electronic device includes a controller operable to read and write data to the memory module, and further operable to place the memory module in a directed auto-refresh mode and issue a directed auto-refresh command. The electronic device includes a memory module having at least two DRAM banks, each bank being independently addressable for performing refresh cycles. The memory module may operate in a directed auto-refresh mode to perform a refresh cycle for one bank in response to a command from the controller and a memory access cycle on a different bank during the refresh operation. A bank address counter in the memory module is operable to assume a first predetermined value when the memory module enters a directed auto-refresh mode.

Drawings

FIG. 1 is a functional block diagram of a controller and a memory module.

FIG. 2 is a timeline depicting refresh operations and values of bank address counters in various modes.

FIG. 3 is a flow chart of a DRAM refresh method.

Detailed Description

FIG. 1 depicts a representative computer system 10 that includes a controller 12 and a memory module 14. The controller 12 may comprise a microprocessor, digital signal processor, high level state machine implemented in an FPGA or ASIC, or other controller. The memory module 14 may comprise a single DRAM chip, a multi-chip module, a SIMM or DIMM array of DRAM modules, or the like. In the depicted embodiment, the memory module 14 includes four DRAM banks 16 and a refresh circuit 18, the refresh circuit 18 including a bank address counter 20 and a row address counter 21. The refresh circuit 18 performs a refresh cycle on the DRAM bank 16 upon receiving a refresh command from the controller 12 in the directed auto-refresh mode, or autonomously during the self-refresh mode. In addition, the refresh circuit may support other refresh modes known in the art. The memory module 14 also includes row and column address latches, sense amplifiers, bus drivers, and various other circuits (not shown) that are common to DRAM memories and well known in the art.

In the embodiment depicted in FIG. 1, the controller 12 includes memory control circuitry 22 operable to perform read and write operations to the memory module 14. Thus, FIG. 1 depicts common address, data, and control signal (e.g., RAS, CAS, and WE) connections between the memory control circuitry 22 in the controller 12 and the memory modules 14. These control signals are merely representative and not exhaustive, and do not include many of the various control signals that may interface controller 12 and memory 14 in any given implementation.

The memory control circuitry 22 additionally generates a refresh signal (depicted as an RFSH signal) to the memory module 14 in at least one mode. The signal RFSH is representative only; in any given implementation, memory control circuitry 22 may issue auto-refresh commands via other control signals. The memory control circuitry 22 also includes a bank address counter 23 that can mirror the value of the bank address register 20 in the memory module 14 during directed auto-refresh mode.

The controller 12 additionally includes an Extended Mode Register (EMR) 24. Such a register may include a plurality of mode bits and other configuration information as necessary or desired in any given implementation. In one embodiment, the EMR24 includes a directed auto-refresh (DARF) bit 26. The EMR24 additionally includes a self-refresh (SR) bit 28. The controller 12 may include a variety of additional circuits, registers, and other components (not shown) as is well known in the art.

According to one embodiment, the memory module 14 enters a directed auto-refresh mode in response to the controller 12 setting the DARF bit 26 in the EMR 24. When the DARF bit 26 is set, the memory bank address counter 20 is set to a predetermined value and the controller bank address counter 23 is set to the same value. Typically, the bank address counter 20 may be set to zero. However, those skilled in the art will recognize that the bank address may be set to any predetermined value, so long as the controller 12 is aware of the predetermined value utilized.

When incremented after each directed auto-refresh cycle, the bank address counter 20 will cycle through the bank addresses in a predetermined order. In the preferred embodiment, the bank address counter 20 cycles through a binary count (e.g., 0,1, … … m-1 for m banks). However, those skilled in the art will readily recognize that the bank address counter 20 may cycle through the bank address bits in any order, so long as the controller 12 is aware of the particular order utilized so that the bank address register 23 may use the same order.

In one illustrative embodiment, during directed auto-refresh mode, the memory module 14, upon receiving a refresh command from the controller 12, will perform a refresh operation on the row and bank address bits in the respective counters 21, 20. The bank address counter 20 will then increment by one following the refresh operation. When the bank address counter 20 has cycled through the full sequence (i.e., a refresh cycle has been issued to each bank for a given row address), the row address counter 21 is incremented by one.

The controller 12 maintains the bank address counter 23 to mirror the bank address counter 20 and increments the bank address counter 23 when an auto-refresh command is issued to the memory module 14. Because the controller 12 and the memory module 14 are initialized to the same predetermined bank address, and the bank addresses are incremented by the same amount substantially simultaneously (after each auto-refresh command) and in the same order, the controller 12 and the memory module 14 are synchronized with respect to the bank addresses in directed auto-refresh mode.

This synchronization allows the controller 12, which knows that the bank 16 is being refreshed when issuing a refresh command, to continue performing read and write accesses to any DRAM bank 16 other than the bank 16 being refreshed. It should be noted that the controller 12 does not need to know the refresh row address. During refresh operations, all rows must be closed only in the bank 16 being refreshed; the controller 12 may read or write to any address in any other bank 16. Thus, the controller 12 may "hide" directed auto-refresh cycles by scheduling memory accesses so that directed auto-refresh cycles do not affect memory access performance.

FIG. 2 depicts a timeline diagram of refresh behavior between the controller 12 and the memory module 14. The actions and states of the controller 12 are depicted below the timeline. The refresh cycle is depicted as a "tick" above the timeline, and the value of the bank address counter 20 is depicted above the timeline. At the leftmost point (the beginning of the time of interest), the controller 12 is reset. This may correspond to an initial power-up, a software reset, or the like. If the controller 12 wishes to enter directed auto-refresh mode and obtain maximum memory access performance, the controller 12 sets the DARF bit 26. This places the memory module 14 in directed auto-refresh mode and forces the bank address counter 20 to a predetermined value, such as zero in the embodiment depicted in FIG. 2.

The controller 12 may then continue to perform memory access operations on the memory module 14, periodically issuing directed auto-refresh commands at periodic points along the timeline, as indicated by the arrows of FIG. 2. The time during which all DRAM banks 16 within a given row must be refreshed is indicated in FIG. 2 as t_REF. Accordingly, the controller 12 may separate the directed auto-refresh command for each bank into an average value t_REFAnd/4, as indicated in the figure. Upon receiving each bootstrapOn an auto-refresh command, the memory module 14 performs a refresh on the bank addressed by the bank address counter 20, and then increments the bank address counter 20. The row address 21 is incremented as the bank address counter 20 cycles through the full sequence (0, 1, 2, 3 in the depicted embodiment). The controller increments the bank address counter 23 upon issuing each directed auto-refresh command. Thus, the memory controller 22 is aware of the bank address counter 20 value and can perform read and write operations to the memory module 14 by directing memory accesses to DRAM banks 16 other than the bank 16 currently being refreshed concurrently with the directed auto-refresh behavior.

In accordance with one or more embodiments of the present disclosure, the controller 12 may utilize a self-refresh mode of the memory module 14. Specifically, the controller 12 may direct the memory module 14 to enter a self-refresh mode, for example, by setting the SR bit 28 in the EMR 24. The use of the SR bit 28 to direct the memory module 14 into or out of self-refresh mode is merely representative; those skilled in the art will recognize that the controller 12 may communicate the self-refresh mode to the memory module in a variety of ways other than setting the SR bit 28. For example, a common technique to direct SDRAM into self-refresh mode is to hold the Chip Select (CS), RAS, CAS and clock enable (CKE) control signals low at the same time; self-refresh is exited when CKE returns high.

During directed auto-refresh mode, the memory module 14 maintains the row and bank addresses to be refreshed, but leaves the refresh timing to the controller 12. Thus, when the memory module 14 receives a command to enter self-refresh mode, it does not know the elapsed time since the last directed auto-refresh cycle. Thus, according to one embodiment, the refresh circuitry 18 of the memory module 14 must perform a refresh cycle immediately upon entering the self-refresh mode. As used herein, the word "immediately" means in relation to t_REFAnd/4 is a short predetermined time period. The refresh cycle may be directed to the currently addressed bank, or the memory module 14 may refresh all DRAM banks simultaneously upon entering self-refresh mode.

In and outDuring the refresh mode, the memory module 14 continues to perform refresh cycles necessary to maintain the data in the DRAM bank 16. In general, the timing of self-refresh mode refresh cycles is temperature dependent, and the time between refresh cycles may exceed t_REF/4. The controller 12 has no visibility into the refresh behavior, does not know the number or timing of refresh cycles, and cannot track the contents of the bank address counter 20. That is, the controller 12 and the memory module 14 become desynchronized with respect to the bank address when the memory module 14 is in the self-refresh mode.

To re-establish synchronization upon exiting self-refresh mode, the bank address counter 20 must contain a predetermined value so that the bank address counter 23 can be set to the same value. Additionally, because the controller 12 does not know when the last internal refresh cycle occurred during the self-refresh mode, the refresh circuit 18 immediately issues at least one refresh cycle upon detecting a command to exit the self-refresh mode (e.g., upon the controller 12 clearing the SR bit 28 in the illustrated embodiment). This ensures that the controller 12 has t_REF4 to issue another directed auto-refresh command without risk of losing data.

In one embodiment, upon detecting a command to exit self-refresh mode, the refresh circuitry 18 performs a refresh cycle on the currently addressed bank and increments the bank address counter 20. If the contents of the bank address counter 20 then do not match the self-refresh exit predetermined value, the bank address counter 20 is incremented by the sequence and refresh cycle it performs on the addressed bank until its contents match the self-refresh exit predetermined value. Once the value of the bank address counter 20 is set to the self-refresh exit predetermined value (and the bank address counter 23 is set accordingly), the controller 12 and the memory module 14 have re-established bank address synchronization. The controller 12 may then continue to issue directed auto-refresh commands while performing memory access operations on banks other than the bank being refreshed.

In another embodiment, rather than performing sequential bank refresh cycles until the bank address counter 20 reaches the self-refresh exit predetermined value, the memory module 14 may refresh all banks simultaneously and set the bank address counter 20 to the self-refresh exit predetermined value. This approach may reduce the latency in exiting self-refresh mode until the memory module 14 is ready to accept and fulfill memory access requests from the controller 12, particularly for a large number of banks (e.g., eight or more).

There are at least two possibilities for self-refresh exit from a predetermined bank address. In one embodiment, the bank address 20 is always set to a predetermined value, such as zero, upon exiting the self-refresh mode. However, those skilled in the art will readily recognize that the bank address counter 20 may be set to any predetermined value, so long as the controller 12 is aware of the value being utilized so that the bank address counter 23 may be set to the same value.

In another embodiment, the self-refresh exit predetermined bank address is the contents of the bank address counter 20 when entering the self-refresh mode. That is, if the last bank refreshed in directed auto-refresh mode before self-refresh mode is n, then the self-refresh exit predetermined bank address is n + 1. In this embodiment, the bank address counter 23 need not be reset or otherwise set to a predetermined value, but rather the controller 12 may continue to issue directed auto-refresh commands as if synchronization had never been interrupted in self-refresh mode.

FIG. 3 depicts a flow diagram of a method of refreshing a memory in accordance with one or more embodiments. The memory 14 checks for directed auto-refresh mode, such as by checking the DARF bit 26 (block 50). If the memory 14 is not placed in the directed auto-refresh mode, it performs a conventional refresh cycle (block 52). These can occur in the following modes: a conventional refresh mode, in which controller 12 supplies refresh row addresses; or a conventional auto-refresh mode in which the memory module 14 maintains a row address. In any case, the memory module 14 may be commanded to directed auto-refresh mode (block 50) at any time (although there is a risk of losing data in the case of conventional refresh mode because there is no row address synchronization between the controller 12 and the memory 14).

Upon detecting a command to enter directed auto-refresh mode (block 50), the memory module 14 sets the bank address counter 20 to a first predetermined bank address (e.g., zero) (block 54). The memory module 14 then performs directed auto-refresh cycles on the DRAM banks 16 as commanded by the controller 12. After each refresh cycle, the memory module 14 increments the bank address counter 20 in a predetermined order (block 56). This allows the controller 12 to track the value of the bank address counter 20 by similarly incrementing the bank address counter 23.

The controller 12 may command the memory module 14 to enter a self-refresh mode (block 58). If the memory module 14 is placed in self-refresh mode, it immediately performs a refresh cycle (block 60) because it does not know the delay since the last directed auto-refresh cycle. The memory module 14 will then perform the DRAM refresh cycle necessary to maintain the state of the data in the memory. No memory access cycles (e.g., read or write) are performed in the self-refresh mode.

Upon being commanded out of self-refresh mode (block 64), the memory module 14 must perform at least one refresh cycle (block 66). This ensures that the controller 12 (which does not know the timing of the last refresh cycle performed in self-refresh mode) must not wait until t after commanding the memory module 14 to leave self-refresh mode_REFThe next directed auto-refresh is issued at/4. The memory module 14 will then perform additional refresh cycles, if necessary, incrementing the bank address counter 20 to leave a second predetermined value in the bank address counter 20 (block 68). This is necessary for synchronization with the controller 12, which controller 12 will also have a second predetermined value in the bank address counter 23. The controller 12 then synchronizes with the memory module 14 with respect to the refresh bank address and may continue to issue directed auto-refresh cycles while performing memory access cycles on the DRAM banks 16 other than the bank being refreshed.

Although the present invention has been described with respect to particular features, aspects and embodiments thereof, it will be apparent that numerous variations, modifications, and other embodiments are possible within the broad scope of the present invention, and accordingly, all variations, modifications and embodiments are to be regarded as being within the scope of the invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, and all changes coming within the meaning and equivalency range of the appended claims are intended to be embraced therein.

Claims (15)

1. A method of refreshing a plurality of memory banks by a memory module, comprising:

receiving a synchronization command from a controller; and

a bank refresh counter is set to a predetermined bank address in response to the synchronization command.

Upon receiving a directed auto-refresh command from the controller, refreshing the addressed memory bank and incrementing the bank refresh counter in a predetermined order; and is

Setting the bank refresh counter to a second predetermined bank address upon exiting the self-refresh mode;

wherein setting the bank refresh counter to a second predetermined bank address comprises:

performing a continuous refresh operation and incrementing the bank refresh counter until the contents of the bank refresh counter match the second predetermined bank address to set the bank refresh counter to the second predetermined bank address; or

All banks are refreshed simultaneously and the bank refresh counter is set to the second predetermined bank address.

2. The method of claim 1, further comprising incrementing a row address counter when the bank refresh counter cycles through all of the plurality of memory banks.

3. The method of claim 1, further comprising performing both the refresh and the access operations upon receiving a directed auto-refresh command from the controller for one of the plurality of memory banks and a memory access request for another one of the plurality of memory banks.

4. The method of claim 1, further comprising entering a self-refresh mode in response to a self-refresh command received from the controller, and refreshing the memory bank without receiving a refresh command from the controller at a rate sufficient to retain data.

5. The method of claim 4, wherein the memory bank addressed by the bank address counter is refreshed immediately upon receipt of the self-refresh command.

6. The method of claim 4, wherein upon receipt of the self-refresh command, all of the memory banks are refreshed simultaneously immediately.

7. The method of claim 1, wherein the second predetermined bank address is fixed.

8. The method of claim 1, wherein the second predetermined bank address is equal to the first predetermined bank address.

9. The method of claim 1, wherein the second predetermined bank address is n +1, where n is a bank address corresponding to a last directed auto-refresh cycle received from the controller prior to the self-refresh mode.

10. An electronic device, comprising:

a controller operable to read and write data to a memory module, and further operable to place the memory module in a directed auto-refresh mode and issue directed auto-refresh commands, the controller maintaining a refresh bank address at the controller equal to a bank address counter at the memory module throughout the directed auto-refresh mode, the controller further operable to place the memory module in a self-refresh mode and to remove the memory module from a self-refresh mode, the bank address counter operable to assume a second predetermined value upon exiting self-refresh mode;

a memory module having at least two DRAM banks, each bank being independently addressable for performing a refresh cycle, the memory module being operable in a directed auto-refresh mode to perform a refresh cycle for one bank in response to a command from the controller and to perform a memory access cycle on a different bank while performing the refresh cycle; and

a bank address counter located in the memory module and operable to assume a first predetermined value when the memory module enters a directed auto-refresh mode;

and wherein

The memory module is operable to perform successive refresh cycles on the DRAM bank and increment the bank address counter upon exiting self-refresh mode until the contents of the bank refresh counter match the second predetermined bank address to set the bank address counter to the second predetermined value; or

The memory module is operable to refresh all DRAM banks simultaneously and set the bank address to the second predetermined value upon exiting self-refresh mode.

11. The electronic device of claim 10, wherein the bank address counter is further operable to increment in a predetermined order after each directed auto-refresh cycle.

12. The electronic device of claim 10, wherein the memory module immediately performs a refresh cycle for a DRAM bank upon entering a self-refresh mode.

13. The electronic device of claim 10, wherein the second predetermined value is fixed.

14. The electronic device of claim 10, wherein the second predetermined bank address is equal to the first predetermined bank address.

15. The electronic device of claim 10, wherein the second predetermined value is n +1, where n is a bank address corresponding to a last directed auto-refresh cycle issued by the controller prior to the self-refresh mode.