HK1108973B - Substrate with multi-layer interconnection structure and method of manufacturing the same - Google Patents

Description

Carrier plate comprising multilayer interconnection structure and manufacturing, recycling and application methods thereof

[ technical field ] A method for producing a semiconductor device

The present invention relates to a carrier including a multi-layered interconnect structure, a method for manufacturing and recycling the same, a method for packaging the same, and a method for manufacturing a multi-layered interconnect device, and more particularly, to a carrier including a multi-layered interconnect structure, in which a portion of the multi-layered interconnect structure is substantially attached to the carrier, a method for manufacturing the same, a method for recycling the same, a method for packaging the same, and a method for manufacturing a multi-layered interconnect device.

[ background of the invention ]

With the progress of the semiconductor manufacturing process, the line width, line spacing and size of the chip are smaller and smaller, the transmission speed required by the chip is higher and the output power is higher, so the packaging technology for electrically connecting the chip to the outside is also higher and higher, the number of wires is higher and the wire spacing is denser, therefore, the chip packaging technology is gradually changed from the pin insertion type to the surface adhesion type, the connection type of the wire bonding wire of the wire frame is gradually changed to the mode of using the bump, and the circuit board is gradually changed from the PCB hard board and the FPC (flexible printed circuit) board to the IC substrate.

Generally, a six-layer BT PCB is hard and cannot be bent because it weighs about 4 g and has a thickness of about 1mm, while a flexible PCB can only be used to fabricate 2-layer interconnects when the thickness is about 50 μm, and on the other hand, an IC substrate can be used to fabricate 6-layer interconnects when the thickness is about 50 μm, and the total weight is about 0.21 g, so the flexibility and thinness of the IC substrate are the best. In addition, in the interconnect density, the minimum through hole size of the PCB hard board and the flexible printed circuit board is required to be 50 μm, the minimum through hole pad size is required to be 100 μm, and the minimum line width and line spacing is required to be 25 μm, while in contrast, the minimum through hole size of the IC substrate is required to be 20 μm, the minimum through hole pad size is required to be 25 μm, and the minimum line width and line spacing is required to be 20 μm, so that the interconnect density of the IC substrate can be greatly increased.

As the size of the circuit board is reduced, the requirement for the precision of the circuit board is also increased, and the manufacturing process of the circuit board is faced with new challenges, especially how to increase the circuit density in the manufacturing process is very important, and the key to increase the circuit density is the dimensional stability of the circuit board in the manufacturing process. One conventional solution is to fabricate the IC substrate on a rigid carrier, so as to increase the dimensional stability of the IC substrate during the fabrication process due to the better dimensional stability of the carrier, but how to separate the IC substrate from the carrier after the fabrication of the IC substrate is completed is a major issue of such techniques.

In U.S. Pat. No. 4812191, a method for fabricating a multilayer interconnection structure by sacrificial carrier fabrication is disclosed, in which a multilayer interconnection structure is fabricated on a carrier, the thermal expansion coefficient of the carrier is smaller than that of the multilayer interconnection structure, and then the carrier is hardened to generate sufficient tension between the carrier and the multilayer interconnection structure during the temperature raising and lowering processes, and then the multilayer interconnection structure is separated from the carrier by a supporting device adsorbed on the multilayer interconnection structure and acid etching.

In U.S. Pat. No. 5258236, a method for separating a carrier from a multi-layer interconnect structure by laser lift-off is disclosed, as shown in fig. 1, in which after a polymer layer 2, a metal layer 3 and a multi-layer interconnect structure 4 are sequentially formed on a transparent carrier 1, laser ultraviolet light is irradiated on the polymer layer 2 through the transparent carrier 1 to decompose the polymer layer 2, so that the transparent carrier 1 can be separated from other structures.

However, the separation method of the above-mentioned conventional techniques is complicated and complicated, so how to provide a method and structure that can simultaneously manufacture an IC substrate with high dimensional precision and make the separation of the IC substrate from the carrier board simple and low-cost is still sought after in the circuit board manufacturing process.

[ summary of the invention ]

The present invention provides a carrier board including a multilayer interconnection structure and a method for manufacturing the same, wherein the separation of the multilayer interconnection structure from the carrier board is simple, fast and low-cost; the invention further provides a packaging method using the carrier plate comprising the multilayer interconnection structure and a method for recycling the carrier plate comprising the multilayer interconnection structure.

The present invention provides a carrier including a multilayer interconnection structure, comprising: a carrier plate; and a multilayer interconnection structure located on the carrier, wherein the multilayer interconnection structure is substantially attached to the carrier only in a partial region. Wherein the partial area can be in the peripheral area of the carrier plate, distributed in a point shape, or distributed in a grid shape, etc.

The present invention provides a method for manufacturing a carrier board including a multilayer interconnection structure, comprising: providing a carrier plate; and forming a multi-layer interconnection structure on the carrier plate, wherein the multi-layer interconnection structure is substantially attached to the carrier plate only in a partial area. Wherein the partial area can be in the peripheral area of the carrier plate, distributed in a point shape, or distributed in a grid shape, etc.

The invention further provides a packaging method of electronic components, which uses the carrier plate comprising the multilayer interconnection structure, and the packaging method comprises the following steps: electrically connecting at least one electronic component to the carrier plate comprising the multilayer interconnection structure; sealing the electronic element with glue; and cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection device packaged with the electronic element from the carrier plate. The electronic elements are sealed on the electronic elements only in a specific area of the carrier plate of the multilayer interconnection structure without the electronic elements, so that no sealing compound is arranged on the residual area, and the flexibility of the multilayer interconnection device with the electronic elements is maintained.

The present invention further provides a method for packaging an electronic device, using the carrier plate comprising a multilayer interconnection structure, the method comprising: cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection structure from the carrier; electrically connecting at least one electronic component to the multilayer interconnection device; and encapsulating the electronic element. The electronic elements are encapsulated on the plurality of electronic elements only on the specific area of the multilayer interconnection device without the plurality of electronic elements, so that the rest area is not encapsulated, thereby maintaining the flexibility of the multilayer interconnection device encapsulated with the electronic elements.

The present invention further provides a recycling method for recycling the carrier board including the multilayer interconnection structure, which includes providing a carrier board including a multilayer interconnection structure, and removing the multilayer interconnection structure from the carrier board. Wherein a portion of the multilayer interconnection structure is cut off, the removing step can be performed by using a mixed solution of sulfuric acid and hydrogen peroxide to remove the multilayer interconnection structure from the carrier, polishing to remove the multilayer interconnection structure from the carrier, or tearing to remove the multilayer interconnection structure from the carrier.

The present invention further provides a method for manufacturing a multilayer interconnection device, comprising: providing a carrier plate; forming a multi-layer interconnect structure on the carrier, wherein the multi-layer interconnect structure is substantially attached to the carrier only in a partial region; and cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection device from the carrier. Wherein the partial area can be in the peripheral area of the carrier plate, distributed in a point shape, or distributed in a grid shape, etc.

Compared with the prior art that the multi-layer interconnection structure and the carrier plate need to be separated by complicated methods such as solvent and laser, the invention can manufacture the multi-layer interconnection device simply, quickly and at low cost.

[ description of the drawings ]

FIG. 1 shows a conventional method for separating a carrier and a multi-layer interconnect structure by laser lift-off;

FIGS. 2A and 2B are top and cross-sectional views of a carrier including a multilayer interconnect structure according to the present invention;

FIGS. 3A-3D illustrate a method of electrically connecting electronic devices and completing a package using a carrier board with a multilayer interconnect structure according to the present invention;

FIGS. 4A-4D illustrate another method of electrically connecting electronic devices and completing a package using a carrier comprising a multilayer interconnect structure according to the present invention;

FIG. 5 shows the carrier board including the multi-layer interconnection structure remaining after the package process of the present invention;

FIG. 6 shows a grid-like selected area attachment area according to the present invention;

fig. 7 shows that the selected area attachment areas according to the invention are point-shaped.

[ detailed description ] embodiments

Preferred embodiments of the present invention will now be described with reference to the drawings, wherein reference numerals are used to indicate the various elements for ease of illustration and understanding. It is noted that the embodiments of the present invention described are intended to be illustrative only and not limiting, unless such limitations are specifically indicated to be present in the embodiments.

Fig. 2A and 2B are top and cross-sectional views illustrating a carrier board including a multilayer interconnection structure according to the present invention. The multilayer interconnection structure of the present embodiment is a double-sided substrate, i.e. the front side and the back side are both electrically connected to the outside, in the double-sided substrate, the front side of the substrate is electrically connected to the back side of the substrate, but the multilayer interconnection structure may be other interconnection methods, such as multi-point interconnection or other various situations, and the number of layers of the multilayer interconnection structure is not limited, and may be changed appropriately according to various applications.

It should be noted that fig. 2A and 2B only schematically illustrate one multilayer interconnection structure 19 as one substrate, but those skilled in the art will appreciate that one multilayer interconnection structure 19 can be cut into hundreds and thousands of substrates in the following processes, which is only simplified for convenience of illustration and description.

In the present embodiment, the carrier 11 is a six-hour silicon wafer, and a dielectric layer and a metal layer are sequentially overlapped on the carrier 11 to form a multi-layer interconnect structure 19, wherein the dielectric layers 12, 14, 16, 18 are made of polyimide pi (polyimide) with a low dielectric constant (less than 4) and a thickness of 8 μm, the upper metal layer 17 and the lower metal layer 13 are made of Under Bump Metallurgy (UBM) with a Cr/Cu/Ni/Au structure for subsequent solder ball electrical connection, and the middle metal layer 15 is made of a Cr/Cu/Cr multi-layer metal wire.

Etching or laser drilling may be used to penetrate through the dielectric layers 18, 14 or 16 on the multilevel interconnect structure 19 so that the metal interconnects may be electrically connected to each other or to the outside.

In the present embodiment, before the dielectric layer 12 is spin-coated on the carrier 11, a silane-based adhesion enhancer (VM-651 manufactured by dupont) is first coated on the peripheral region of the carrier 11 to increase the adhesion between the carrier 11 and the dielectric layer 12, and no treatment is performed on the remaining region of the carrier 11, so as to achieve the desired selective adhesion.

It should be noted that in the present invention, the carrier plate can be any solid material, including metal, glass, ceramic, silicon wafer, sapphire substrate, gallium arsenide, polyimide, etc. The dielectric layer material may be any organic material, including polyimide, benzocyclobutene, BCB (benzobenzocyclobutene), polymethyl methacrylate, PMMA (poly-methyl methacrylate), liquid crystal polymer, lcp (liquid crystal polymer), etc., for substrate applications of the package, the low dielectric constant and low dielectric loss facilitate high-speed and high-performance packaging applications, and the material with proper mechanical properties (e.g., CTE, young's coefficient) is selected to match the mechanical properties of the electronic component and the multilayer interconnection device, which further facilitates the reliability of the packaged product. The dielectric layer coating mode can be spin coating, extrusion die coating and roller coating. The metal interconnects can be formed by etching, metal lift-off, or the like.

In the present invention, the selective area attachment can be achieved by using the native characteristics of the carrier surface, or by using the method of increasing the surface energy, such as plasma treatment, etc., or by using the material for enhancing the cross-linking and entanglement of the interface molecules, such as coating the reinforcing agent of silane, etc. Table i shows examples of various optional attachment methods that may be used for various carrier materials and dielectric materials, but is not limited thereto.

Table one:

carrier plate material	Dielectric layer	Attachment method	Unattached region
				Silicon-dioxide-glass-silicon-aluminum nitride	Polyimide, polyimide resin composition and polyimide resin composition	Silicon methane as reinforcing agent	Do not process
Silicon	Polyimide, polyimide resin composition and polyimide resin composition	1. Coating special polyimide 2, hardening 3, full plasma treatment 4, coating dielectric layer	No processing, no masking during plasma processing
				Silicon-dioxide-glass-silicon-aluminum-nitride ceramic	Polyimide, polyimide resin composition and polyimide resin composition	Physical Vapor Deposited (PVD) chromium films	When not processed, the chromium film is required to be shielded by a shade

Next, a method for electrically connecting electronic devices by using the carrier board with the multi-layer interconnect structure and completing the package will be described.

Fig. 3A to 3D show a method for electrically connecting electronic devices and completing a package by using the carrier board with a multilayer interconnection structure of the present invention. FIG. 3A shows a carrier 11 with a multi-level interconnect structure 19 according to the present invention, which may be tested to determine if the interconnect conditions are good; next, as shown in fig. 3B, an electronic component 21 is electrically connected to the multi-layer interconnection structure 19 by flip-chip bonding with bumps 22, it should be noted that the number of the electronic components is not limited to one, and not limited to the integrated circuit IC, other components such as passive components and printed circuit board can be electrically connected to the multi-layer interconnection structure 19 of the present invention, and the bonding method of the electrical connection can be selected from other methods such as wire bonding, anisotropic conductive film acf (anisotropic conductive film m), surface mount technology (smt), ball grid array (bga ball grid array), land grid array lga (lga) and pin grid array (pga (pin grid array); next, as shown in fig. 3C, the electronic component 21 is encapsulated by an encapsulant 23, which may be formed by Epoxy molding (Epoxy molding), Dam and filled Epoxy (Dam & Fill Epoxy), Dam and filled Silicone (Dam & Fill Silicone), etc., and the encapsulant region does not need to be on the whole multilayer interconnection structure 19, and can be kept without being encapsulated in a proper region to keep the flexibility of the multilayer interconnection structure 19 at a specific position to match various application situations; finally, as shown in fig. 3D, the multilayer interconnection structure 19 is cut at a proper position, so that the resulting multilayer interconnection device 24 with the electronic component 21 packaged therein is directly separated from the carrier 11, and for the case of the double-sided substrate of this embodiment, a laser drilling process is performed on the back surface of the substrate, so that the bottom UBM can be electrically connected to the outside, thereby completing the packaging of the electronic component.

Fig. 4A to 4D show another method for electrically connecting electronic devices and completing packaging by using the carrier board with a multilayer interconnection structure of the present invention. FIG. 4A shows a carrier 11 including a multi-level interconnect structure 19 according to the present invention; next, fig. 4B shows that the multilayer interconnection structure 19 is cut at a proper position, so that the resulting multilayer interconnection device 25 is directly separated from the carrier 11, and for the case of the double-sided substrate of this embodiment, a laser drilling process is performed on the back surface of the substrate, so that the bottom UBM can be electrically connected to the outside, and in addition, a test can be performed first to determine whether the interconnection condition is good; next, as shown in fig. 4C, an electronic component 26 is electrically connected to the device 25 including the multi-layer interconnection device in a flip-chip bonding manner by using bumps 27, as mentioned above, the number of the electronic components is not limited to one, and not limited to an integrated circuit IC, other components such as passive components and printed circuit boards can be electrically connected to the multi-layer interconnection device 25 of the present invention, and the bonding manner of the electrical connection can be selected from other manners such as wire bonding, anisotropic conductive film ACF, SMT, BGA, LGA, PGA, etc.; next, as shown in fig. 4D, the electronic component 26 is encapsulated by the encapsulant 28, as mentioned above, the encapsulant 28 may be formed by Epoxy resin (Epoxy), Dam and filled Epoxy (Dam & Fill Epoxy), Dam and filled Silicone (Dam & Fill Silicone), and the like, and the encapsulant region does not need to be on the whole multilayer interconnection device 25, and the encapsulant region may be maintained without being covered by the encapsulant to maintain the flexibility of the multilayer interconnection device 25 at a specific position, so as to match various application situations, thereby completing the encapsulation of the electronic component.

The above examples only illustrate the case of packaging electronic components on the multilayer interconnection device of the present invention, but the usage of the multilayer interconnection device of the present invention is not limited to this case, and the multilayer interconnection device of the present invention can also be used as an interposer for connecting electronic components to a printed circuit board, an interposer for connecting a printed circuit board to a printed circuit board, an interposer for electrically connecting a plurality of electronic components to each other, or an interposer for electrically connecting a multilayer interconnection device to other multilayer interconnection devices.

Another aspect of the present invention further includes a method for recycling a carrier board including a multilayer interconnection structure, and fig. 5 shows that the carrier board including a multilayer interconnection structure left after being packaged by the two packaging methods can be separated from the carrier board by various methods for removing and separating the multilayer interconnection structure, such as immersing the carrier board in a mixed solution of sulfuric acid and hydrogen peroxide, and removing the multilayer interconnection structure by grinding, or directly tearing away the multilayer interconnection structure, so that the carrier board can be recycled for reuse.

The attachment area of the selective area attachment method is not limited to the peripheral area of the above embodiments, and may be in various shapes, such as a grid shape and a dot shape, as long as various defects, such as delamination and bubbles, are not generated in the subsequent processes, fig. 6 shows that the selective area attachment area is in a grid shape, and fig. 7 shows that the selective area attachment area is in a dot shape.

The present invention has been described in an illustrative manner, and it is to be understood that the above description is intended to be illustrative and not restrictive. Various modifications of the invention will become apparent to those skilled in the art in light of the foregoing description. Therefore, it is intended that the present invention cover all such modifications and variations as fall within the scope of the invention.

[ description of symbols ]

1 support plate

2 Polymer layer

3 Metal layer

4 multilayer interconnection structure

11 support plate

12 dielectric layer

13 lower metal layer

14 dielectric layer

15 Metal layer

16 dielectric layer

17 upper metal layer

18 dielectric layer

19 multilayer interconnection structure

20 area

21 electronic component

22 bump

23 sealing compound

24 multi-layer interconnect device

25 multilayer interconnection device

26 electronic component

27 bump

28 sealing compound

Claims (15)

1. A carrier board including a multi-layer interconnect structure, comprising: comprises the following steps:

a carrier plate; and

the multilayer interconnection structure is directly contacted with the carrier plate, the interface adhesive force of the area which is substantially attached is different from that of the other areas through selective area attachment, the selective area attachment is realized by utilizing the original characteristic of the surface of the carrier plate or utilizing a mode of improving the surface energy, the multilayer interconnection structure comprises a dielectric layer which is attached to the carrier plate and is made of organic materials, the area which is substantially attached to the carrier plate on the multilayer interconnection structure is an area to be cut and removed, and the area to be cut and removed is only arranged on the multilayer interconnection structure.

2. The carrier of claim 1, wherein the carrier comprises: wherein the substantially attached partial area is distributed in a peripheral area of the carrier, in a point shape in the carrier, or in a grid shape in the carrier.

3. A method for manufacturing a carrier including a multi-layer interconnect structure, comprising: comprises the following steps:

providing a carrier plate; and

forming a multilayer interconnection structure on the carrier plate, wherein the multilayer interconnection structure is substantially attached to the carrier plate only in a partial area, the multilayer interconnection structure is in direct contact with the carrier plate in the substantially attached area, the interface adhesion force of the substantially attached area is different from that of the rest area through selective area attachment, the selective area attachment is achieved by utilizing the original characteristic of the surface of the carrier plate or utilizing a mode of improving the surface energy, the area of the multilayer interconnection structure substantially attached to the carrier plate is an area to be cut and removed, and the area to be cut and removed is only arranged on the multilayer interconnection structure.

4. The method of claim 3, wherein the carrier comprises a plurality of interconnect structures, and further comprising: the substantially attached partial areas are distributed in a point shape in the peripheral area of the carrier plate, or in a grid shape in the carrier plate.

5. An electronic component packaging method, characterized in that: comprises the following steps:

providing a carrier comprising the multilayer interconnect structure of claim 1;

electrically connecting at least one electronic component to the carrier plate comprising the multilayer interconnection structure;

sealing the electronic element with glue; and

cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection structure with the electronic element packaged and the carrier plate.

6. The electronic component packaging method of claim 5, wherein: the electronic element is arranged in the area which is not substantially attached to the carrier plate on the multilayer interconnection structure.

7. The electronic component packaging method of claim 6, wherein: the step of cutting the multi-layer interconnect structure is: cutting and removing the area of the multilayer interconnection structure which is substantially attached to the carrier plate, so that the multilayer interconnection structure which is not substantially attached to the carrier plate and is packaged with the electronic element is naturally separated from the carrier plate.

8. An electronic component packaging method, characterized in that: comprises the following steps:

providing a carrier comprising the multilayer interconnect structure of claim 1;

cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection structure from the carrier;

electrically connecting at least one electronic component to the multilayer interconnection structure; and

encapsulating the electronic element.

9. The electronic component packaging method of claim 8, wherein: the electronic element is arranged in the area which is not substantially attached to the carrier plate on the multilayer interconnection structure.

10. A carrier plate recovery method is characterized in that: comprises the following steps:

providing a carrier substrate comprising the multilayer interconnect structure of claim 1;

cutting the multilayer interconnection structure to naturally separate the cut multilayer interconnection structure from the carrier; and

removing the remaining multi-layer interconnection structure on the carrier from the carrier and recycling the carrier for reuse.

11. The carrier plate recycling method according to claim 10, wherein: the removing step is performed by using a mixed solution of sulfuric acid and hydrogen peroxide, by polishing, or by peeling off the remaining multilayer interconnection structure on the carrier.

12. The carrier plate recycling method according to claim 10, wherein: the removing step is to remove the area of the multilayer interconnection structure substantially adhered to the carrier plate.

13. A method for fabricating a multilayer interconnect device, comprising: comprises the following steps:

providing a carrier plate;

forming a multilayer interconnection structure on the carrier plate, wherein the multilayer interconnection structure is substantially attached to the carrier plate only in a partial area, the multilayer interconnection structure is directly contacted with the carrier plate in the substantially attached area, the interface adhesive force of the substantially attached area is different from that of the rest areas through selective area attachment, and the selective area attachment is achieved by utilizing the original characteristic of the surface of the carrier plate or utilizing a mode of improving the surface energy; and

cutting the multilayer interconnection structure and only cutting the multilayer interconnection structure to the surface of the carrier plate, so that the cut multilayer interconnection structure is naturally separated from the carrier plate.

14. The method of claim 13, wherein: wherein the substantially attached partial area is distributed in a peripheral area of the carrier, in a point shape in the carrier, or in a grid shape in the carrier.

15. The method of claim 13, wherein: the step of cutting the multi-layer interconnect structure is: cutting and removing the area of the multilayer interconnection structure which is substantially attached to the carrier plate, so that the multilayer interconnection structure which is not substantially attached to the carrier plate is naturally separated from the carrier plate.