HK1107375A - Manufacture of cadmium mercury telluride on patterned silicon - Google Patents

Description

Cadmium mercury telluride production on patterned silicon

The present invention relates to methods of fabricating cadmium mercury telluride on patterned silicon, and in particular to methods of fabricating cadmium mercury telluride layers directly on integrated circuits and cadmium mercury telluride structures so grown.

Cadmium mercury telluride Hg_1-xCd_xTe is a well-known material used for infrared devices such as detectors, sources, LEDs, negative luminescence devices, and the like. Cadmium mercury telluride, known as CMT (or sometimes mercury cadmium telluride-MCT), is a semiconductor alloy whose bandgap can be varied by varying the alloy composition, i.e., the cadmium content x. The band gap can be varied so that the CMT can be used for various infrared devices, covering short-wave (SW), medium-wave (MW), long-wave (LW), and very long-wave (VLW) infrared wavelengths. CMT is a material of choice for many infrared focal plane array applications. The small leakage current and high carrier mobility make the detector have excellent sensitivity. Since the wavelength can be tuned by selecting the appropriate composition, and a structure can be designed and grown whose composition is tuned so that two or more wavelengths can operate in a single device, CMT becomes the best solution for a single-band or multi-band system covering a large wavelength range.

The general principle of making infrared devices is well established. CMT is epitaxially grown on a crystalline substrate. The device is then formed by mesa etching, ion implantation, or ion beam milling. Metal contacts are then formed and the device is bonded to the silicon readout circuitry. Note that CMT can also be grown as a bulk crystal from which the device is formed using ion implantation or ion beam milling, but epitaxial growth is preferred over bulk crystal growth.

Various epitaxial growth methods have been proposed for fabricating CMT. Metal Organic Vapor Phase Epitaxy (MOVPE) has been successfully used as a technique for reproducible and uniform large area growth. U.S. Pat. No. 4,650,539 describes the manufacture of CMT using MOVPE. Us patent 4,566,918 is a variation of this technique, growing thin layers of CdTe and HgTe which form a uniform CMT structure by interdiffusion. U.S. Pat. No. 4,950,621 describes a MOVPE technique for CMT growth, utilizing photocatalytic decomposition of metal organic compounds.

Other CMT growth methods bagsIncluding Molecular Beam Epitaxy (MBE). Cadmium zinc telluride (Cd) by MBE process_1-yZn_yTe, also known as CZT) substrate from which infrared devices have been formed. See, for example: m Zandian, JD Garnett, RE Dewames, M Carmody, JG Pasko, M Farris, CA Cabelli, DE Cooper, G Hildebrandt, JChow, JM Arias, K Vreal and DNB Hall, J.electronic Materials 32(7)803(2003), "Mid-wave initial-p-on-n Hg_1-xCd_xTe heterostructures detectors: 30-120 Kelvin date of the art performance "(mid-wave infrared p-on-n Hg)_1-xCd_xTe heterostructure detector: 30-120 absolute temperature states of prior art performance), or JDPhillips, DD Edwall and DL Lee j electronic Materials 31(7)664(2002) "Control of very long wavelength infrared HgCdTe detector cut-off wavelength".

Infrared imaging applications increasingly require large area two-dimensional detector arrays for long range detection and identification. As the physical size of these arrays has increased, limitations of conventional substrate materials and growth techniques for CMT have become apparent. Cadmium zinc telluride has been widely used as a CMT growth substrate, but only small dimensions can be obtained, which limits its usefulness in large size array production. Cadmium telluride is also used as the substrate and only small dimensions can be obtained. In addition, both CdTe and CZT are extremely brittle and neither crystal quality is particularly good.

Gallium arsenide (GaAs) substrates can be obtained in relatively large sizes. However, as previously mentioned, the device is typically bonded to a silicon readout circuit. In operation, the probe is typically cooled to a low temperature, for example, about 80K (although the optimum operating temperature for different devices is different) to reduce thermal noise. Thermal mismatch between the silicon readout circuitry and the GaAs substrate can cause delamination of the infrared device from the circuitry at the operating temperature of the detector. The read effect can be reduced by thinning the substrate, but the thinning process is complex, the yield is reduced, and the production cost is increased. Cadmium telluride and CZT substrates generally suffer from this thermal mismatch problem.

It is proposed to use silicon as the substrate because the silicon substrate has an inherent thermal match to the readout circuitry.

MBE technology has been applied to growth of CMT on silicon, where a buffer layer is grown on silicon prior to CMT growth, such as TJ de Lyon, JE Jensen, MD Gorwitz, CA Cockrum, SM Johnson and GM Venzor, j.electronic Materials 28, 705 (1999). MBE growth of CMT on silicon has proven to be a challenging task. First, for MBE growth of CMT on any substrate, the growth temperature must be precisely controlled, which requires reproducible wafer mounting techniques and fine substrate temperature control. Second, it has proven difficult to eliminate material defects. These defects do not always have a severe effect on the mid-wavelength infrared device characteristics (depending on the device), but they adversely affect the long-wavelength device. Therefore, growing CMT on silicon using MBE is a difficult process, producing only acceptable mid-wavelength infrared devices and arrays.

MOVPE growth of CMT on silicon to produce a workable device is also problematic. See J.electronic Materials 25 (journal of electronic Materials) 8 (1996) page 1347K Shigenaka, K Matsushi, L Sugiura, F Nakata and K Hirahara, M Uchikoshi, M Nagashima and H Wada "Orientation depletion of HgCdTe epitaxial layers grown by MOCVD on silicon substrates", page 1353K Maruyama, H Nishino, T Okamoto, S Murakami, T Nishijima, M Uchikoshi, M Nagahita and H Wada "Growth of HgCdTe (111) HgCdTe semiconductor (100) Si by PE using metal deposition Method (MOV) and vapor phase deposition (M) of metal oxide (H) and metal oxide (M) by vapor phase deposition (M) of metal oxide (H and metal oxide) (H1351) by vapor phase deposition (M and vapor phase deposition (M) of metal oxide and metal oxide (M) on silicon substrate, M1H and H growing by MOVEHI) of metal oxide (M) and H (M) by chemical vapor phase deposition (H and chemical annealing (M) on silicon oxide (100), (211) and (111) direct growth of CdTe on silicon).

It has recently been reported that CMT can be produced on a silicon substrate, i.e. a buffer layer is produced on the substrate using MBE, followed by growth of the CMT using MOVPE, see: "Long wavelength vertical planar array from HgCdTe growth on silicon substrates" (Long wavelength infrared focal plane arrays made from HgCdTe grown on silicon substrates), DJ Hall, L Buckle, NT Gordon, J Giess, JE Hails, JW Cairns, RM Lawrenone, A Graham, RS Hall, C Maltby and T Ashley in the Defence and Security Symposium2004 (Formery AeroSense)12-16 grain 2004 Gaylord Palms Resort and Convement center Orlando do (Kistemmed), Florida USA, Conference proceedings in the Long wavelength and Security Conference of DJ 12-16G focal plane array and growth center of the same, safety Conference on the Higherkurton Conference of the national institute of atomic Security and High speed detectors (safety Conference of the national institute of growth of the national institute of health and environmental research, High speed detectors in the national Conference of growth of the national institute of growth of the same and High speed detectors (Korea), j Ares, J E Hails, J W Cairns, RM Lawrence, A Graham, RS Hall, C Maltby and T Ashley, applied Physics Letters (applied physical Letters) Volume 85, Issue 11, pp.2113-2115.

This technique enables growth of CMT on silicon, which can be subsequently processed for device formation and bonding to readout circuitry.

However, this still requires that the wafer of detector arrays and read-out integrated circuits (ROICs) be sawed into individual elements ready for the hybrid process prior to bump bonding mixing (hybridization). This is an expensive technique and yields of sawed wafers and bonded are relatively low.

International patent application WO02/084741a2 discloses a monolithic infrared sensing device in which the CMT layer is grown directly on the silicon readout circuitry. The method described in this patent application involves forming a growth window on a silicon substrate, where a cadmium telluride buffer layer and a subsequent CMT layer are grown within the window using MBE. However, this method also relies on MBE growth of CMT on silicon, which has associated difficulties as well.

Thus according to the present invention there is provided a method of making an infrared device comprising the steps of: taking a silicon substrate on which an integrated circuit is formed, selectively growing at least one crystalline buffer layer within at least one window using Molecular Beam Epitaxy (MBE), and selectively growing at least one crystalline CMT layer on the buffer layer using metal-organic vapor phase epitaxy (MOVPE).

The method of the present invention thus provides a method of fabricating an infrared device in which the CMT is grown directly on a substrate having integrated circuitry, such as readout circuitry, thereon. This avoids the need to mix the CMT on the substrate layer with the circuit layer. The method thus avoids the use of low yield techniques such as sawing and bonding in the mixing step and enables wafer-level processing of infrared devices.

The buffer layer is first grown using Molecular Beam Epitaxy (MBE), whereby a crystalline CMT layer is grown within at least one growth window on the substrate. The CMT layer is subsequently grown by metal organic vapor phase epitaxy.

The present invention therefore combines MBE and MOVPE to produce a device that can be used over a wide range of wavelengths with good performance. Although the process of the present invention does require two distinct process steps, adding to the complexity of the process, mixing these two techniques can provide a reliable and controllable process that has produced superior devices.

The term cadmium mercury telluride as used in this specification refers to Hg_1-xCd_xTe, where composition x is controlled to be between 1 and 0, including 0 and 1. When x is 1, the substance is actually cadmium telluride, and when x is 0, the material is actually mercury telluride, but for the purposes of this specification both are encompassed within the terms cadmium mercury telluride or CMT.

The substrate orientation is important for achieving CMT single crystal growth on silicon, preferably the substrate orientation is shifted by a few degrees, i.e., (001) between 2 ° and 10 °, towards <110> or <111 >. The step of taking the silicon substrate on which the integrated circuit is formed therefore preferably involves taking a substrate whose (001) orientation is preferably shifted by 2 ° to 10 ° or 4 ° to 8 ° toward <110> or <111>, although <111> is generally most preferred.

It should be noted that the growth method of the present invention results in the material grown by MBE and subsequently by MOVPE following the orientation of the substrate. The MBE buffer layer or layers thus follow the (001) orientation of the silicon substrate, the displacement of which ensures single crystal growth. The MOVPE layer then also follows the (001) orientation, so the CMT layer is (001). The method thus involves the steps of growing at least one buffer layer using MBE and at least one CMT layer using MOVPE, each buffer layer and CMT layer having a crystal orientation that follows the substrate orientation.

It should also be noted that the technique disclosed in WO02/084741 teaches that the displacement of the silicon substrate is only 1 °, which is a process that uses MBE in its entirety, rather than both MBE and MOVPE as in the present invention. The inventors have found that this displacement angle is not sufficient for the present invention. More importantly, the method described in WO02/084741 does not clearly teach in which direction the silicon should be displaced, and the inventors have found that this displacement direction is an important parameter. It appears that this method teaches (111) growth of CdTe (page 14), so the CMT layer may therefore also have a (111) orientation, rather than the buffer layer and CMT layer both following the orientation of the substrate, as in the present invention.

The method thus involves fabricating an integrated circuit on a silicon substrate that is displaced from 2 ° to 10 ° from (001) towards <111 >. It should be noted that the usual substrate orientations for forming integrated circuits are not displaced (001). Prior to the present invention, it was not clear whether integrated circuits could be formed on silicon at such displacement angles. The present inventors have discovered, however, that relatively high yields can be obtained using silicon displaced in this manner. The fabrication of integrated circuits uses standard techniques known to those skilled in the art of producing specific circuits. Those skilled in the art will appreciate that the term integrated circuit encompasses a single electrical circuit formed on a substrate as well as multiple circuits on a monolithic wafer, whether or not those circuits are connected. For example, a readout circuit for a multi-pixel detector, where each pixel has associated circuitry that is not connected to the circuitry of other pixels, should be considered an integrated circuit for the purposes of this specification.

The integrated circuit defines the area of a production window for each element of the produced infrared device, e.g. each pixel within the detector or source may have a growth window and associated electronics. The substrate may thus comprise a plurality of growth windows. The growth window may simply be a silicon-free region or may be defined by regions of the substrate at different levels. Those skilled in the art will appreciate that after the integrated circuit is formed, variations in surface topography will occur due to the integrated circuit architecture. The growth window may thus comprise a pit (pit) relative to the circuit architecture, i.e. a region below the surrounding circuit architecture. The depth of the read pits can be defined simply by the height of the circuit architecture on the pit side. However, whether to etch the silicon within the growth window changes the pit depth relative to the circuit architecture. The pit depth can be set to be substantially the CMT layer height with the buffer layer or layers in the overall planar arrangement in the final device.

As will be described below, growing one or more MBE buffer layers and CMT by MOVPE can result in crystalline growth within the growth window and polycrystalline growth outside the growth window, i.e., on the circuit. The polycrystalline material may then be removed by etching. During growth, the polycrystalline material encroaches on the growth window, causing the crystalline region of the CMT to become smaller than the growth window. Such encroachment can occur when the growth window is formed as a pit as compared to the circuit architecture, because the circuitry is above the growth area, and such encroachment can result in shadowing on the growth window during the MBE (MBEs operate according to line of sight). Furthermore, during MOVPE, the circuitry will be further exposed (poke up) to the interior of the gas stream, which enhances growth on the circuitry and the growth rate of the polycrystalline material may be higher than the growth rate of the crystalline material. To isolate the finished device, the poly needs to be removed from the top of the protected circuitry, as well as removing poly formed between the sides of the integrated circuit and the crystalline islands. Thus, when the polycrystalline material is removed, the area of crystalline CMT is smaller than the window. Thus, the diode/probe area, i.e. the fill factor, is smaller than in the case where all available area on the circuit is covered by the probe material. If all the areas available for growth on the circuit, i.e. all the growth windows, contain good detector material, the diodes can be formed in smaller dimensions, resulting in an array with a smaller pitch. A smaller pitch is beneficial for some applications and for array performance, as more diodes can be accommodated on the array.

Thus in another embodiment, the growth window may be arranged at the same level as the circuit architecture. This is beneficial for the growth process, since it essentially represents growth on a planar substrate in terms of molecular beam and gas flow, and reduces the aforementioned circuitry risk leading to MBE beam shadowing. Ensuring that the growth window is at the same level as the circuit architecture thus reduces the chance of encroachment of polycrystalline material into the growth window. Thus, less polycrystalline material needs to be removed and the shape/size of the crystalline islands more closely matches the growth window. The fill factor of the device can be increased.

In yet another implementation, the growth window may be formed by a substrate pillar (stub) that extends over the circuit architecture. In this arrangement, the growth area will be higher than the surrounding circuitry, will not be within MBE shadow, and will be exposed to the MOVPE airflow. The orientation/crystallinity of the material grown on the side of the pillar may vary depending on the growth conditions used. The material grown on the sides of the pillars will likely need to be removed by etching because even if the material is crystalline, the read material has a different orientation, thickness, composition and doping, and therefore different device performance, than the desired structure grown with the correct orientation on the tops of the pillars. However, all areas on top of the pillars will be of high quality crystalline material, ensuring that all defined growth windows are effectively utilized. Thus, growing on silicon pillars may have advantages in terms of device size and fill factor.

The area of the substrate defined as the growth window can thus be processed at a different level than the rest of the substrate. It is also possible to treat the substrate area intended as the growth window to have a different orientation than the rest of the substrate. This allows the substrate on which the integrated circuit is fabricated to have a standard (001) orientation, but the region of the substrate corresponding to the growth window can be processed, for example etched, to have the displacement required for growth of a single crystal of CMT.

Preferably, the substrate outside the growth window is covered with a mask material. In other words, the growth window is defined without the mask material. The method thus involves the step of applying a masking material to the substrate outside the growth window prior to growing the buffer layer. The masking material helps protect the integrated circuit and the rest of the substrate during fabrication and growth of the buffer layer and CMT layer. In addition, the masking material may help define the growth window and aid in the selective crystalline growth of the buffer layer and the CMT layer. Conveniently, the mask material may be applied to the entire substrate on which the integrated circuit is formed, and subsequently selectively removed from particular areas to expose the growth windows. The skilled person is aware of methods of applying a mask material and subsequently removing selected portions thereof, e.g. photolithography.

The read mask material may be any material that is chemically and mechanically robust so as to protect the substrate and integrated circuit during preparation and growth of the CMT, but can be removed once the CMT process is complete to expose the underlying circuitry. One convenient mask material is titanium tungsten, Ti-W, although other materials, such as silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Aluminum (Al), chromium (Cr), platinum (Pt), palladium (Pd), or any refractory metal.

The exposed silicon within the growth window is preferably cleaned for material growth prior to MBE growth of the buffer layer. This cleaning removes any unwanted contamination. The preparing may involve one or more of solvent cleaning, barrel ashing, and/or ion beam milling. The substrate is also etched using a Hydrogen Fluoride (HF) based etchant.

It should be noted that in standard growth methods the silicon substrate is typically subjected to a thermal cleaning on the bare substrate before the material is grown, i.e. for example before the MBE growth buffer layer. However, the thermal cleaning temperature can be as high as 800 ℃, destroying the integrated circuit. Therefore, conventional thermal cleaning cannot be performed on the substrate carrying the integrated circuits. Tests have shown that integrated circuits can withstand processing temperatures up to about 500 ℃, but metal traces of the circuit melt well above that temperature to damage the circuit.

The substrate is exposed to the arsenic flow at a temperature above room temperature before the MBE buffer layer is grown, but low enough that the integrated circuit is not damaged. The arsenic flow prepares the hydrogen termination surface of the silicon substrate for subsequent MBE growth. Arsenic is the preferred material for the purge stream, but additional or other alternative materials or combinations thereof, such as cadmium, tellurium, cadmium telluride, zinc telluride, antimony or phosphorus, may also be used.

The present invention thus utilizes a low temperature cleaning process at about 450 c that can achieve good cleaning without damaging the integrated circuit. The subsequent growth steps occur at lower temperatures than conventional thermal cleans and therefore do not cause problems with the integrated circuit.

One or more buffer layers may be grown using MBE. This buffer layer sets the correct orientation for MOVPE growth-noting that the growth of the MBE buffer layer follows the orientation of the substrate-and protects the CMT from chemical contamination by the constituents within the substrate. The buffer layer also serves to isolate mercury from circuitry within the substrate during subsequent growth of the CMT layer. Suitable buffer layers include cadmium telluride and zinc telluride. May be a single buffer layer, such as a single layer of zinc telluride; or a combination of layers, for example a zinc telluride layer may be grown on top of a substrate on which a cadmium telluride layer is grown. Cadmium zinc telluride can also be used as the buffer layer. Other buffer layers may include gallium arsenide and germanium.

For growing zinc telluride, or elemental zinc and tellurium, or a combination of the elemental and compound materials may be used as the MBE source material. Similarly, cadmium telluride can be grown using elemental cadmium and tellurium or cadmium telluride or a combination of the elemental and compound materials. The buffer layer is grown using standard MBE growth procedures known to those skilled in the art.

The entire substrate is exposed to MBE growth, but due to proper preparation of the growth window, e.g. using appropriate mask materials, crystalline growth occurs only in the growth window as if the crystalline substrate were exposed only within the growth window as a base for epitaxial growth. The material deposited on the substrate outside the growth window is deposited as a polycrystalline material. According to the process conditions, it can be ensured that growth only occurs outside the growth window, i.e. no growth takes place outside the growth window and crystalline growth takes place inside the growth window. This is known in the industry as "selected area growth" and will result in a better fill factor, since the CMT area grown will (more closely) be equal to the area of the growth window. It has however proved to be more convenient to allow growth outside the growth window and to remove unwanted material in a subsequent etch stage.

After the MBE growth of the buffer layer, CMT can be grown on the buffer layer using MOVPE. However, it is preferred to wash the buffer layer surface prior to MOVPE growth. Depending on the equipment used, it may be necessary to transfer the substrate on which the buffer layer is grown from the MBE growth equipment to the move reaction chamber and/or there may be a delay between process steps. If the substrate on which the buffer layer is grown is not maintained in a controlled environment, impurities may accumulate on the surface of the top buffer layer. Cleaning removes at least some of these impurities, but any cleaning steps should not damage the integrated circuit, similar to substrate preparation. The substrate on which the buffer layer is grown may be etched using techniques well known to those skilled in the art of MOVPE, or the cleaning may be performed by any suitable cleaning process, taking into account the temperature limitations described above. If the combined MBE/MOVPE system includes a load lock between the two, then no cleaning is required.

Prior to growing the at least one CMT layer, the method may further comprise the step of growing at least one further buffer layer using MOVPE. The MOVPE buffer layer may be the same or different material than the buffer layer grown by MBE. As previously mentioned, MBE provides a well-controlled method of growing a suitable buffer layer on silicon with the correct orientation for MOVPE growth. However, to further improve the conditions for MOVPE growth of CMT, it is beneficial to lay down the buffer layer by MOVPE. For example, when the MBE buffer layer includes a cadmium telluride top layer grown on a zinc telluride based layer on the substrate, the method can include the step of growing an additional cadmium telluride layer on top of the MBE CdTe layer by MOVPE.

Additional buffer layer growth by MOVPE may increase the buffer layer thickness, which may be beneficial in some embodiments, and MOVPE is a faster growth method than MBE. MOVPE buffer layers can improve crystal quality. Furthermore, the MOVPE buffer layer is also beneficial in isolating the CMT from surfaces that have been exposed to air, i.e. laying down the MOVPE buffer layer may cover any slight surface impurities of the MBE buffer layer due to oxidation etc. and any residues of the cleaning process (if performed).

The CMT layer is grown by standard MOVPE techniques in which the concentration of the precursor entering the reaction chamber is controlled by the vapour pressure and gas flow (conveniently hydrogen) through a bubbler containing the precursor, which may be additionally diluted with an additional flow of cleaning gas (H2). In this way, Hg can be grown_1-xCd_xTe, which has a controlled value of x to obtain desired device characteristics. Conveniently, the MOVPE process utilises a CMT growth interdiffusion multilayer process as described in US4,566,918, i.e. the CMT growth step comprises growing thin layers of CdTe and HgTe in sequence which interdiffuse as they grow to form a single layer of CMT, the relative thicknesses of the CdTe and HgTe layers determining the cadmium content x.

The metal organic precursor used is any suitable volatile tellurium and cadmium compound, such as cadmium alkyl compounds and tellurium alkyl compounds. In one embodiment, the tellurium precursor is diisopropyltellurium and the cadmium precursor is dimethylcadmium.

Since the MOVPE buffer layer and CMT are grown on the MBE buffer layer, their crystal orientation is the same as the MBE buffer layer. Similarly, the crystalline growth is performed only in the growth window, and the polycrystalline growth is performed in the other region.

The CMT layer may be doped with a suitable dopant of the n-type or p-type. Suitable dopants include iodine, arsenic, indium and antimony, although other dopants may be used. Suitable precursors include isobutyliodide and tris (dimethyl) aminoarsenic.

Typically, the method includes growing more than one layer of CMT, depending on the needs of the target device. The different layers may have different thicknesses, compositions (Hg)_1-xCd_xX in Te), and/or different dopants and dopant concentrations.

After growth of the CMT layer by MOVPE, the material is preferably annealed in a mercury-rich atmosphere-the process fills the mercury vacancies and ensures the desired electrical properties. The anneal may be performed within the MOVPE reaction chamber and may be performed directly after growth of the CMT layer, or may be performed later using any suitable equipment.

The MBE growth buffer layer and MOVPE growth CMT essentially use the methods described in the following references: "Long wavelength included planar array of infrared focal plane arrays" (made from HgCdTe grown on a silicon substrate), DJ Hall, L Buckle, NTGordon, J Giess, JE Hails, JW Cairns, RM Lawrence, A Graham, RS Hall, C Maltby and T Ashley in the Defence and Security Symposium2004 (Formery AeroSense)12-16 grain 2004 Gaylord Palmsssssssssrort and Convement Center Orlando (Kistemmed), Florida USA 2004, Conference proceedings in the press provided by the Long wavelength and Security Conference of DJ 12-16 g focal array of atomic emission devices and High speed detectors (found in the national Center of growth Conference of atomic emission devices, Higherkulture and safety Conference of High speed detectors (found in the national Center of growth of atomic emission devices), NT Gordon, J Giess, JE hairls, JW Cairns, RM Lawrence, A Graham, RS Hall, C Maltby and T Ashley, Applied Physics Letters Volume 85, Issue 11, pp.2113-2115, and british patent application GB0407804.4, the contents of which are incorporated herein by reference.

When the grown material is crystalline within the growth window and polycrystalline outside the growth window, it is desirable to remove unwanted material. The method thus includes the step of removing any unwanted CMT and/or buffer layer material. Removal of the polycrystalline material may be achieved by etching. Preferably, the etching step involves a dry etching step followed by a chemical wet etching. Photolithography may be used to define the area to be etched. The removal of unwanted material can be performed at different stages. For example, the MBE and MOVPE growth stages may be completed before the polycrystalline buffer layer and CMT material are removed. Alternatively, the MBE growth buffer layer may be completed and any unwanted poly buffer layer material may be removed at this stage, i.e. prior to the MOVPE growth stage. MOVPE growth may then be performed, with crystalline growth only on the crystalline buffer layer. This MOVPE growth phase may enable selective area growth such that no growth is performed at all outside the growth area, or may again result in crystalline growth on the crystalline material and polycrystalline growth in the remaining areas within the growth window, in which case an etching step is required after MOVPE growth.

The method may also involve device processing steps to define the physical shape of the CMT layer. This step may also involve providing a landing site for electrical connection. Conveniently, the device processing steps are performed while removing any unwanted CMT/buffer material.

Device processing steps may include planar processing techniques and may include ion implantation, ion beam milling, and forming, for example, cones or lenses. Ion implantation may be accomplished by implanting p/n type dopants to form a diode or other structure after the CMT has been grown-so the CMT material may be grown with some layers undoped or partially doped and subsequently doped by ion implantation.

The method may further involve the step of coating the CMT with at least one passivation layer. Those skilled in the art will appreciate that the sidewalls of the CMT structure are preferably coated with one or more passivation layers to ensure electrical stability of the device and prevent loss of mercury from the material. The passivation layer may conveniently be a cadmium telluride layer. Conveniently, the passivation layer is an epitaxial layer grown by MOVPE.

The method may also involve the step of removing any mask material from the substrate outside the growth window. This can be achieved by an etching process such as chemical wet etching as understood by those skilled in the art.

The method may further comprise the step of forming an electrical connection between the CMT and the integrated circuit. The electrical connection may be formed as an air bridge (airbridge) by depositing a sacrificial material, depositing a conductive material over the read sacrificial material, and then removing the read sacrificial material, as is well known in the art. Alternatively, when a passivation layer is applied to the CMT material, an electrical connection may be made through a via in the passivation material. Obviously, the relationship between the CMT material and the integrated circuit will determine the manner in which the electrical contact is made. When the buffer layer/CMT is grown in a pit relative to the circuit architecture, part of the device may directly contact the integrated circuit. When the final device is planar with respect to the read circuitry, electrical connections can be made without the need for an air bridge. Those skilled in the art will appreciate that the type of connection required, the degree of passivation, etc., will vary depending on the device design.

It should be noted that the CMT growth method allows further epitaxial growth of CMT on CMT layers that have been processed through the device, as described in british patent application GB 0407804.4. Thus, the method of the invention may involve growing part of the CMT structure followed by device processing and subsequently growing at least one additional CMT layer by MOVPE. The at least one additional CMT layer will be epitaxial on the crystalline CMT region. Device processing may include any type of shaping step, such as etching, or may involve making electrical contacts. In particular, the read method may allow for the growth of one or more CMT layers, the formation of electrical contacts to portions of the structure, and the subsequent further growth of at least one additional CMT layer.

The present invention thus provides a method of forming a monolithic infrared device having circuitry and an infrared active material on the same substrate. The reading device implemented by the invention comprises a short wave detector and source, a medium wave detector and source, a long wave detector and source, and a very long wave detector and source. For all cases, a full 2D array can be produced using CMT materials that are fully integrated with the circuitry of the individual pixels. CMTs grown using the present invention can produce dual band, multiband, hyperspectral and avalanche devices. Negative-emitting devices can be fabricated as LEDs and single photon sources, and these devices can be used in a variety of technologies ranging from focal plane array infrared detectors to gas sensors. Transistors can also be fabricated using the methods of the present invention.

The CMT grown within the at least one growth window may also be processed to fabricate integrated circuits thereon. Integrated circuits fabricated within CMTs may have different performance than integrated circuits fabricated on silicon substrates, e.g., faster speed and lower power consumption. Thus, local high speed circuits can be fabricated within the CMT islands within the host silicon integrated circuit.

Thus, according to another aspect of the present invention, there is provided a monolithic infrared device comprising a silicon substrate on which an integrated circuit is fabricated, and at least one layer of cadmium mercury telluride formed on at least one buffer layer on said substrate, wherein the substrate is oriented (001) displaced by 2 ° to 10 ° towards <110> or <111>, preferably <111 >.

A device according to the present invention may be made by the method of the first aspect of the present invention, with all the attendant advantages of the first aspect of the present invention. The reading apparatus preferably comprises a plurality of CMT structures each having respective associated circuitry. Conveniently, the reading means is an infrared detector having a plurality of detector pixels. The apparatus may be a linear array or a 2D detector array.

Although the method of the present invention involves growing CMT on a silicon substrate carrying integrated circuits, it has been found that CMT grown within the growth window has excellent surface morphology. For CMT grown by traditional methods, the maximum array size and operability are limited by a large defect called hillock. Typical defect densities are about 10-20cm for high quality materials conventionally grown on bare silicon^-2. The material defect density grown within the window is much less than this range. Growing the CMT in the growth window thus provides a method of growing larger area, high quality detector arrays or other infrared devices.

Thus, according to another aspect of the present invention, there is provided a method of fabricating a monolithic array of CMT structures, comprising the steps of: taking a monolithic substrate material with a plurality of defined growth windows, and selectively growing at least one layer of crystalline cadmium mercury telluride in the growth windows.

The invention can therefore be applied to growing arrays of CMT devices that are larger in area and/or higher in quality than other growth techniques. The growth substrate may be any suitable crystalline material, physically robust and available in large areas. The substrate may be a substrate carrying an integrated circuit or some other surface feature, or may be a bare substrate with a defined growth window. Suitable substrate materials include cadmium telluride, zinc telluride, cadmium zinc arsenide and cadmium zinc telluride arsenide (although these materials are not generally available in large areas), gallium arsenide, silicon, germanium, indium antimonide, indium aluminium antimonide, indium gallium antimonide, indium phosphide, sapphire, alumina or spinel (MgAl)₂O₄)。

This aspect of the invention can therefore be used to produce high quality mixing devices. In this case, silicon is the preferred substrate because it is inherently thermally matched to the readout circuitry. An additional advantage of selective area growth for intermixing is that the strain within the material is reduced and thus the substrate/CMT bending is reduced. This effect is most pronounced when growth is only performed in the growth window.

Preferably, the growth window is defined by a substrate carrying a mask material applied to the outside of the growth window. The method thus includes the step of applying a mask material to the substrate outside the growth window prior to growing the CMT. Conveniently, the entire substrate is covered with a mask material, and then selected areas of the mask material are removed to expose the growth windows. The growth window may be defined using standard photolithographic techniques using a mask material.

The skilled person is aware of the various materials which can be used as mask material. When the substrate is a bare substrate on which no integrated circuits are formed, the masking material need only prevent the growth of the CMT crystals outside the growth window. Suitable mask materials include Ti-W, silicon dioxide (SiO)₂) Silicon nitride (Si)₃N₄) Al, Cr, Pt, Pd and other refractory metals.

Preferably, the step of growing at least one CMT layer involves the following steps: at least one crystalline buffer layer is grown by MBE at each growth window, followed by at least one crystalline CMT layer grown by MOVPE on the buffer layer. As previously mentioned, this method of growing CMT produces high quality CMT devices with controllable performance. All of the above embodiments and advantages associated with growing the buffer layer by MBE and the CMT layer (and any additional buffer layers) by MOVPE are equally applicable to this aspect of the invention.

As previously described in connection with the first aspect of the invention, the orientation of the substrate is important to ensure correct material growth. This orientation should allow for proper growth of the buffer layer by MBE and ensure that the buffer layer has the proper orientation required for MOVPE growth of CMT. The substrate is therefore preferably arranged to be displaced away (100) towards the <111> or <110> direction. Preferably, the displacement angle is 2 ° to 10 °. The substrate orientation is displaced in this manner, preventing the formation of defects within the MBE buffer layer. When the substrate is silicon, the substrate orientation is preferably (001), displaced in the [111] direction by an angle preferably in the closed range of 2 ° to 10 °, more preferably in the closed range of 4 ° to 8 °. The silicon substrate is generally a substrate on which growth is difficult, and proper orientation becomes important.

Preferably, the reading method involves the step of cleaning the substrate within the growth window prior to material growth. This step can be performed by a combination of solvent cleaning, etching, drum ashing and ion beam etching and HF based etching as described above, but standard thermal cleaning techniques can also be used when the substrate does not carry an integrated circuit.

After growth of the CMT material, the method may involve a step of removing unwanted CMT material by etching. Where a mask material is used, crystalline growth only within the growth window and polycrystalline growth in other regions may be achieved; thus, no removal of polycrystalline material will be required. This step may include device processing steps for forming the shape of the desired device.

The method may also involve the step of removing any mask material after device formation. This step may be performed by standard etching/photolithography techniques, as previously described.

The above method can be used to create a series of CMT islands on a buffer layer on a substrate. The method may then involve additional material growth over the entire substrate, i.e., over the CMT islands as well as the bare substrate. This would form an array of CMT islands buried within another material. For example, the CMT can be buried beneath CdTe, islands of CMT material tuned for long wavelength operation can be buried within CMT material tuned for medium or short wavelength operation, or CdTe (or HgTe) can be buried within the CMT.

Drawings

The invention will now be described, by way of example only, with reference to the following figures, in which:

FIG. 1 shows a schematic diagram of a test ROIC designed to prove the invention;

FIG. 2 shows an SEM image of a growth window on a substrate;

FIG. 3 shows a Nomarski (Nomarski) micrograph of a substrate after CMT growth;

FIG. 4 shows an SEM image of a substrate after CMT growth;

FIG. 5 shows a schematic diagram of an MBE apparatus for growing a buffer layer; and

figure 6 shows a schematic diagram of a MOVPE apparatus suitable for growing CMT layers.

Detailed Description

Cadmium mercury telluride is used in various infrared devices, particularly infrared detectors. As focal plane arrays become larger and larger, traditional fabrication methods are reaching a limit. Mixing a substrate with a detector array with a read-out integrated circuit (ROIC) is an expensive and low yield process. The present invention relates to growing detector material directly on a ROIC, thereby eliminating the need for mixing and enabling the fabrication of focal plane arrays with very large areas and high pixel counts using wafer-level processes.

The first stage in the production of detector arrays fabricated directly on an ROIC is the production of the ROIC. It has been found that the orientation of the substrate is important in order to grow single crystal CMT on bare silicon. For silicon, the orientation is shifted by a few degrees (001) towards <111 >. ROIC is therefore fabricated on such displaced silicon substrates. Test circuits have been fabricated on displaced silicon and examined to obtain acceptable yields, indicating that ROIC can be fabricated on off-axis silicon. The industry standard method for manufacturing ROIC is to do so in a non-displaced orientation (100).

It should be noted that the silicon substrate may comprise epitaxial silicon (epi silicon). Those skilled in the art will appreciate that the formation of integrated circuits may begin with epitaxial growth of silicon on a bulk silicon wafer prior to forming the circuits. For the purposes of this specification, a silicon substrate includes epitaxial silicon.

Fig. 1 shows a ROIC layout for demonstrating the principles of the present invention. The ROIC contains various test circuits, a lead-out circuit (lead-out circuit) and a 64 x 64 pixel ROIC. The circuit has a window opening to the silicon for growing the detector material. The central region contains a fully functional 64 x 64 pixel array with a pitch of 150 μm. The pixel is of standard design, containing a direct injection gate, a stage gate, an integrated capacitor, a reset circuit, and a 100 μm square area cleared down to the silicon substrate for growth of the buffer layer and CMT. Fig. 2 shows an SEM image of a detector growth window on a substrate.

It should be noted that the above described device is a completely 2D array. Each 64 x 64 pixel has a respective growth window and associated circuitry. This is different from the method described in WO02/084741, in which a single growth window is defined. In WO02/084741, CMT is grown within a growth window and subsequently formed into a linear array or two side-by-side linear arrays. The invention allows growth to be performed in a plurality of separate growth windows.

The ROIC is coated using a Ti-W protective mask prior to growing the buffer layer and detector material thereon. Ti-W is preferred because it has a higher mechanical robustness than other protective layers of interest, such as aluminum, chromium and silicon dioxide, but these materials can also be used if desired. The Ti-W mask protects the ROIC from chemical contamination/damage/structural damage during the detector material growth, annealing, passivation, device handling and dry etch processes that define the physical structure of the infrared device.

After depositing a Ti-W protective mask to protect the circuitry, photolithography is used to remove the Ti-W to expose the window area. This exposes the underlying silicon substrate, ready for the detector material growth and fabrication process.

After pre-treatment, the material layers of the infrared detector, i.e., the CMT detector material and any buffer layers, are grown directly on the ROIC. Importantly, the single crystal detector material is grown on the ROIC within the growth window. These windows are carefully prepared to clean out any unwanted contamination that may lead to the formation of polycrystalline material within the windows. Window preparation includes solvent cleaning, barrel ashing, ion beam milling, and HF based etching, such as HF/ethanol mixtures. All of these are relatively low temperature cleaning steps (around room temperature), but cleaning the substrate is sufficient to protect the material from background impurities. The industry standard process for growing materials on silicon substrates involves cleaning the silicon at 820 ℃. However, exposing the ROIC to temperatures above 500 ℃ can cause the aluminum interconnect traces to melt, and thus the ROIC is permanently damaged. This has been overcome by developing a new lower temperature substrate cleaning process.

Part of the cleaning/preparation process involves exposing the substrate to a flow of arsenic at a temperature. This is conveniently performed when the substrate is loaded into the MBE reaction chamber. The arsenic flow produces a hydrogen terminated surface of the silicon, which is important to allow subsequent MBE growth.

However, other cleaning/preparation methods may be used, including hydrogen cleaning and/or heating under, for example, P, As, Sb, S, Se, Te, Cd, Zn.

Once the window has been prepared for growth, the buffer layer is grown by Molecular Beam Epitaxy (MBE), followed by Metal Organic Vapor Phase Epitaxy (MOVPE) to grow the infrared detector material. The buffer layer comprises a zinc telluride layer and a subsequent cadmium telluride layer having a thickness of about 1 μm, although a single layer of zinc telluride, cadmium telluride or cadmium zinc telluride may be grown instead. The width of the buffer layer can vary from, for example, a single layer of ZnTe (and CdTe if CdTe is used) up to a total thickness of about 10 μm.

The infrared detector is in a multilayer CMT diode structure. The diode structure is theoretically simulated and optimized for performance in the mid-band of about 5 μm, although it is clear that other IR devices can be made. More details about the MBE and MOVPE growth stages are given below.

The buffer layer material and subsequent CMT layers are selectively grown to be crystalline within the growth window, but polycrystalline outside the growth window. In testing the grown material, the performance index "crystalline yield" is defined as the ratio of the window grown to the crystalline state to the total number of pixels in the array. The process of the present invention has been completely successful in producing high quality single crystal material with 100% crystalline yield. The background surface topography of the detector material grown on the ROIC within the window is comparable to the detector material grown on a conventional substrate. The nomarski and scanning electron microscope images are shown in figures 3 and 4, respectively, below. The material within the growth window is crystalline, but the material in other regions is polycrystalline.

The quality of the grown-in-window morphology is excellent for larger defects. For conventional growth, the maximum array size and operability is limited by a large conical defect called a hillock. For high quality layers on bare silicon, typical hillock densities are about 10-20cm^-2. The defect density of the material grown in the window appears to be much less than this range. The invention thus also relates to CMT growth within a window, using this useful technique to produce large area, hillock-free materials for conventional detector arrays.

After the probe material growth process, an etch recipe (recipe) is used to remove the polycrystalline material. The crystalline detector material is then ready for a subsequent process stage. It has been determined that the optimal etch recipe involves performing a dry etch followed by a wet chemical etch.

In dry etch processes, it has been determined that a variety of plasma chemistries, mostly methane based, can be used to dry etch CMT. Free radicals in the methane plasma react with cadmium, mercury and tellurium in the CMT to form Me₂M, wherein M is Cd, Te and Hg, Me is CH₃. By Me₂Interaction of Cd on Hg and CMT can also form Me₂Hg, by Me₂Interaction of Cd on Te and CMT can also form Me₂And Te. Some mercury may also evaporate from the surface. The methane plasma also deposits polymer within the chamber, often with the addition of additional gas to control this. The plasma used in the process contains methane and hydrogen gases in an inductively coupled plasma system.

Defining a region to be etched by using a photoetching technology; in this case a polycrystalline material. The polycrystalline material as shown in fig. 3 and 4 is removed by dry etching.

The Ti-W protective mask is removed by wet etching to expose the underlying circuitry.

The final process step is to connect the probe to the ROIC contact pads using metallization. Contact can be achieved in one of two ways. A passivation layer may be deposited to prevent shorting of the probe and metal contacts. Holes need to be opened in the passivation layer to make contact with the detector contact area. Alternatively, air bridge contacts may be formed, thereby avoiding the need for passivation and the risk of short circuits.

Air bridge contacts are currently used for contact with planar type devices. The air bridge requires the use of a temporary resist support structure on which the chromium/gold metal traces are deposited. The resist is removed and the metal interconnect trace is left floating. The advantage of this technique is that no electrically insulating layer is required.

Higher performance impedance area products can be obtained using passivated CMT infrared detector structures, passivation being preferred for long band devices. However, CMT infrared diodes operating in the mid-band without the deposition of a (e.g., CdTe) passivation layer have sufficiently high performance to be subject to background limitations.

For other devices, electrical contacts may be formed at different stages of device growth. The growth method of the present invention may enable device processing steps such as etching or forming electrical contacts after growing some layers of material. For example, one or more layers of CMT may be grown by MOVPE on the buffer layer before electrical contact is made to the CMT layer, and then any polycrystalline material removed by etching (if removal is required). Further MOVPE growth of CMT will subsequently result in epitaxial growth of one or more additional layers of CMT. The entire device may then be annealed, passivated, and additional electrical connections formed.

Fabrication of focal plane detector arrays has been described, but those skilled in the art will appreciate that other infrared devices may be fabricated using the methods of the present invention.

Buffer layers were grown by MBE and CMT layers were grown by MOVPE as described previously.

MBE is a process carried out in ultra-high vacuum. Referring to fig. 5, a liquid nitrogen 202 mask assists in maintaining the vacuum. The source material is contained in a crucible inside an effusion cell 204 in the machine. Effusion cell 204 is positioned such that the open end of the crucible is directed toward heated substrate 206. When the shutter 208 on the end of the crucible is removed, material is transferred from the crucible to the heated substrate. The amount of material delivered to the substrate depends on the temperature of the crucible, with higher temperatures giving higher vapor pressures of the material and hence more material is delivered. The heating coil 210 controls heating of the crucible. Since the system is under vacuum, even low vapor pressure materials will evaporate and can be transferred to the substrate if heated sufficiently. Also because the system is under vacuum, the beam of material is transferred from the effusion cell to the sample without interference from the atmosphere. The effusion cell is typically kept at an idle temperature, kept warm but not enough to evaporate the material. Before growth begins, the cell is warmed to the growth temperature so that enough material can evaporate from the crucible to grow the desired layer.

The masked and etched silicon substrate 206 is loaded into the MBE assembly by load lock. The substrate is clamped to a support 212, which is heated and ideally rotated. The rotation contributes to the uniformity of the grown layer. The temperature of the substrate during growth is below the temperature at which the deposited material re-evaporates, but hot enough to allow atoms to move across the surface and form crystalline material.

It has been found beneficial to grow the required buffer layer using previously used MBE assemblies. The previous growth run may make the MBE assembly well-conditioned, thereby enabling subsequent high quality crystal growth. Therefore, using a clean MBE assembly, it is beneficial to perform several state-modulated growths first.

The substrate is then cleaned at an arsenic flow and a specific temperature (i.e., above room temperature), however, the temperature is low enough to avoid any damage to the ROIC.

Depending on the source to be used for growth, the shutter in front of the zinc telluride, zinc and tellurium cells is then removed as required, thereby initiating zinc telluride growth. Once the desired thickness of zinc telluride has been grown, the shutter is restored. Similarly, cadmium telluride is grown by removing the shield in front of the cadmium telluride, cadmium and tellurium cells as needed. Similarly, at the end of the CdTe growth, the shutter is restored. Once growth is complete, the cells are cooled to an idle temperature and the substrate is cooled and removed from the machine.

A thin ZnTe buffer layer was grown on the ROIC inner window by MBE to set the substrate orientation to (001) and improve the adhesion of the subsequently grown CdTe buffer layer. CdTe grown directly on silicon by MBE is more prone to flaking from the substrate. The total buffer thickness is about 1 μm, although it may be thicker for some devices and may be only zinc telluride or CZT.

This portion of the growth process may be performed using Migration Enhanced Epitaxy (MEE), and for purposes of this specification reference to MBE includes reference to MEE.

The substrate, on which any etching/cleaning steps required are performed, is then transferred to a MOVPE reaction chamber. To produce a multilayer device, various CMT layers were grown within each growth window, each layer being grown by the interdiffusion multilayer process described in us patent 4,566,918. Although the MBE equipment and MOVPE equipment are often separate pieces of equipment, they may be combined into a single unit by a load lock or transfer mechanism between the two equipment. The MBE and MOVPE chambers and the load locks or transfer mechanisms therebetween may be used to arrange the particular assembly.

Figure 6 illustrates the principles of MOVPE growth and shows equipment suitable for MOVPE growth, although the actual equipment used may vary. As described more fully in US4,566,918, a source of hydrogen is supplied from manifold 1 to bubblers 6, 7 and 25 through mass flow controllers 3, 4 and 23. Valve 8 is closed and valves 10 and 11 are open and gas flows through bubbler 6 and valves 10 and 11 are closed and valve 8 is open and the hydrogen gas stream from mass flow controller 3 is directed to scrubber or filter 31 via bypass line 14. Similarly, bubbler 7 may be controlled by valves 9, 12 and 13, and bubbler 25 may be controlled by valves 26, 27 and 28. Although more bubblers may be required in practice, only three bubblers are shown in fig. 3 for simplicity. The air flow through each bubbler can be controlled. The gas flows from bubblers 6, 7 and 25 may be mixed in mixer 15, which may be diluted with a gas flow from controller 5 (controlled by valves 32, 33) before entering the reaction chamber container 16, but in other arrangements it may be preferable to feed the precursors separately to the reaction chamber container and mix them within the reaction chamber.

A substrate 20 bearing a crystalline buffer layer within the growth window is positioned within the reaction chamber container 16 on a susceptor 21. The elemental mercury bath 19 is heated and the partial pressure of the mercury vapor is maintained by the reaction chamber wall 24 with the heating element 17 or with any suitable heating means, such as an internal cartridge heater located below the mercury bath. The substrate is heated using an induction heater 18 or any other suitable means so that the metal-organic precursor within the gas stream from bubblers 6, 7, and 25 decomposes in the vicinity of the substrate.

The bubbler 6 contains a cadmium precursor such as dimethyl cadmium and the bubbler 7 contains a tellurium precursor such as diisopropyl tellurium. The gas flow from bubblers 6 and 7 to the chamber cavity is controlled in turn by appropriate control of the valves to grow thin layers of mercury and cadmium telluride within each growth window, the thickness of the layers being controlled to control the overall cadmium content of the final CMT layer formed by interdiffusion of the layers within the growth windows during the growth process.

To produce the first CMT layer in each growth window, this layer is, for example, p⁺CMT layer, a p-type dopant needs to be introduced. A suitable p-type dopant is arsenic, although other dopants such as phosphorus and antimony are contemplated. Thus, the dopant bubbler 25 contains a suitable precursor, such as tris (dimethyl) amino arsenic (other volatile arsenic components may be used), and the bubbler temperature and gas flow through the bubbler is controlled to achieve the proper doping. After the first CMT layer is grown, additional CMT layers may be grown next. Suitable n-type doping of any n-type layerThe agent is iodine, for example isobutyl iodide as a precursor, but other precursors may be used and indeed other dopants such as indium may be used. As previously described, when different dopants are used, the MOVPE device will have multiple dopant bubblers that need to be separately controlled, rather than the single dopant bubbler shown in fig. 6. Similarly, if any MOVPE buffer layers are to be grown, the apparatus contains a bubbler containing precursors for the buffer layer composition.

After growth of the CMT layer by MOVPE, the material is preferably annealed in a mercury-rich environment-the process fills the mercury vacancies and ensures the desired electrical properties. The anneal may be performed within the MOVPE reaction chamber and may be performed directly after growth of the CMT layer, or may be performed later using any suitable equipment.

Claims (39)

1. A method of making an infrared device comprising the steps of: taking a silicon substrate on which an integrated circuit is formed, selectively growing at least one crystalline buffer layer on at least one growth window by molecular beam epitaxy, and selectively growing at least one crystalline CMT layer on the buffer layer by metal organic vapor phase epitaxy.

2. The method of claim 1 wherein the silicon substrate has a (001) orientation that is displaced 2 ° to 10 ° toward <110> or <111 >.

3. A method as claimed in claim 1 or 2, wherein the method comprises the step of forming an integrated circuit on a silicon substrate.

4. The method of any preceding claim, wherein the substrate has a plurality of growth windows.

5. A method as claimed in any preceding claim, wherein the substrate within the or each growth window is at a different level relative to the integrated circuit architecture.

6. A method as claimed in claim 5, wherein the substrate within the or each growth window is below the integrated circuit architecture.

7. A method as claimed in claim 5, wherein the substrate within the or each growth window extends above the integrated circuit architecture.

8. A method as claimed in any one of claims 1 to 4, wherein the substrate within the or each growth window is at the same level as the integrated circuit architecture.

9. The method of any preceding claim, wherein the or each growth window is defined by a mask material applied to the exterior of the or each growth window.

10. A method as claimed in any preceding claim, wherein the method includes the step of applying a mask material to the substrate outside the or each growth window.

11. The method of claim 9 or 10, wherein the mask material is titanium tungsten.

12. A method according to any preceding claim, further comprising the step of cleaning the substrate within the or each growth window prior to growing the buffer layer.

13. The method of claim 12, wherein the cleaning step comprises one or more of solvent cleaning, drum ashing, ion beam milling, and etching using a hydrofluoric acid based etchant.

14. The method of claim 12 or 13, wherein the substrate preparation step comprises a thermal clean under arsenic flow, the thermal clean being performed at a maximum temperature of not substantially higher than 500 ℃.

15. The method of any one of the preceding claims, wherein the at least one buffer layer is selected from one of cadmium telluride, zinc telluride, and cadmium zinc telluride.

16. The method of any preceding claim, wherein the step of growing the at least one buffer layer comprises growing a first buffer layer of zinc telluride on the substrate and a second buffer layer of cadmium telluride on the first buffer layer.

17. The method of any one of the preceding claims, comprising the step of growing at least one buffer layer by metal-organic vapor phase epitaxy on the at least one buffer layer grown by molecular beam epitaxy before growing at least one layer of cadmium mercury telluride.

18. The method of any one of the preceding claims, wherein the step of growing at least one cadmium mercury telluride layer comprises an interdiffusion multi-layer process.

19. The method of any one of the preceding claims, wherein at least one cadmium mercury telluride layer is grown as a doped layer.

20. A method according to any preceding claim, wherein the step of growing at least one buffer layer comprises growing crystalline material in the growth window and growing polycrystalline material in other regions.

21. The method of any one of the preceding claims, wherein the step of growing at least one cadmium mercury telluride layer comprises growing crystalline material in a growth window and growing polycrystalline material in other areas.

22. The method of any of the preceding claims, wherein the method comprises, after the growing at least one cadmium mercury telluride layer, the step of removing any unwanted cadmium mercury telluride and/or buffer layer material.

23. The method of any one of the preceding claims, wherein the method further comprises a device treatment step to define the shape of the at least one cadmium mercury telluride layer.

24. The method of claim 10 or any one of claims 11 to 23 as directly or indirectly dependent on claim 10, further comprising, after growing the at least one cadmium mercury telluride layer, the step of removing any unwanted mask material.

25. The method of claim 10, further comprising forming an electrical connection between the integrated circuit and the at least one layer of cadmium mercury telluride within the or each growth window.

26. A monolithic infrared device formed by the method of any of the preceding claims.

27. A monolithic infrared device comprising a silicon substrate on which an integrated circuit is fabricated, and at least one layer of cadmium mercury telluride formed on at least one buffer layer on the substrate, wherein the substrate has a (001) orientation that is shifted 2 ° to 10 ° toward <111 >.

28. The device of claim 27, comprising a plurality of cadmium mercury telluride structures each having associated circuitry.

29. The device of claim 27 or 28, wherein the device is an infrared detector.

30. A method of making a monolithic array of cadmium mercury telluride structures comprising the steps of: taking a monolithic substrate material having a plurality of defined growth windows, and selectively growing at least one layer of crystalline cadmium mercury telluride within said growth windows.

31. The method of claim 30, wherein the substrate is silicon.

32. The method of claim 31 wherein the silicon substrate orientation is (001) shifted by 2 ° to 10 ° toward <111 >.

33. The method of any one of claims 30 to 32, wherein the growth window is defined by a mask material applied to the exterior of the growth window.

34. A method according to any preceding claim, wherein the method comprises the step of applying a mask material to the substrate outside the growth window.

35. The method of any one of claims 30 to 34, wherein the method comprises the step of cleaning the substrate within the growth window prior to material growth.

36. The method of any one of claims 30-35, wherein the step of growing at least one layer of cadmium mercury telluride comprises the steps of: and selectively growing at least one crystalline buffer layer in each growth window by molecular beam epitaxy, and then selectively growing at least one layer of crystalline cadmium mercury telluride on the at least one buffer layer by metal organic vapor phase epitaxy.

37. The method of claim 36, wherein the method involves, prior to growing the at least one layer of cadmium mercury telluride, the step of growing at least one buffer layer by metal organic vapor phase epitaxy on the buffer layer previously grown by molecular beam epitaxy.

38. The method of any one of claims 30-37, wherein the method further comprises the step of removing any unwanted cadmium mercury telluride material after growth.

39. A method as claimed in claim 34 or any one of claims 35 to 38 as dependent directly or indirectly on claim 34, further comprising the step of removing any unwanted mask material after the material has grown.