HK1106344A - Amplifiers with compensation - Google Patents

Description

Amplifier with compensation

Technical Field

The present invention relates to amplifiers, and more particularly to amplifiers with compensation.

Background

An amplifier may comprise one or more stages. Each stage may include an amplifier that provides gain. As the frequency increases, the gain provided by the amplifier tends to decrease, which limits the bandwidth of the amplifier. As the operating frequency of electronic computing devices has increased, amplifiers with high bandwidth and gain and low noise have become increasingly important.

Miller compensation is a conventional frequency compensation technique that involves moving the dominant pole of the gain stage to a lower frequency by increasing the effective input capacitance of the gain stage. The miller compensation circuit includes a miller capacitance that utilizes the miller effect. When the miller capacitance is connected in a feedback arrangement, the capacitance appears much larger at the input of the amplifier. Although the dominant pole can be moved to lower frequencies using this method, the gain and bandwidth of the system is still somewhat limited.

Referring now to fig. 1 and 2, an amplifier circuit 10 with miller compensation is shown and includes first and second amplifiers 14 and 16, respectively. The output of the first amplifier 14 is in communication with the input of the second amplifier 16. A first terminal of the miller capacitance 18 is in communication with an input of the second amplifier 16 and a second terminal of the miller capacitance 18 is in communication with an output of the second amplifier 16.

The input voltage of the amplifier circuit 10 is applied to the input of the first amplifier 14. The output voltage of the amplifier circuit 10 is referenced to the output from the second amplifier 16. Transconductance g of the second amplifier 16 due to miller compensation_mCan be increased which increases the bandwidth of the amplifier circuit 10. As can be seen in FIG. 2, the gain of the amplifier with Miller compensation has a 20dB/decade slope.

Amplifiers may also be used with switched capacitive input signals. The switched capacitive input signal may be generated in an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a filter, and/or other circuitry. Conventional amplifiers, such as those shown in fig. 1, tend to have difficulty providing sufficient gain and bandwidth at acceptable noise levels, particularly for switched capacitive input signals.

Disclosure of Invention

According to a first aspect of the present invention, there is disclosed an amplifier circuit comprising: a first amplifier having an input and an output; a second operational transconductance amplifier having an input in communication with an output of the first amplifier; a third amplifier having an input in communication with the input of the first amplifier and an output; a fourth operational transconductance amplifier having an output and an input in communication with an output of the third amplifier; a feedback resistor in communication with an input and an output of the fourth operational transconductance amplifier; and a capacitor in communication with an output of the fourth operational transconductance amplifier and in communication with an input of the second operational transconductance amplifier.

Further, a digital-to-analog converter, an analog-to-digital converter and a filter comprising the above-described amplifier circuit are disclosed, such digital-to-analog converter, analog-to-digital converter and filter further comprising a circuit generating a switched-capacitor input signal, which is input to an input of the amplifier circuit.

According to a second aspect of the present invention, another amplifier circuit is disclosed, comprising: a first operational transconductance amplifier having an input and an output; a second operational transconductance amplifier having an input in communication with an output of the first operational transconductance amplifier; a third operational transconductance amplifier having an input in communication with an input of the first operational transconductance amplifier; a fourth operational transconductance amplifier having an input in communication with an output of the third operational transconductance amplifier and an output in communication with an input of the second operational transconductance amplifier; a switched capacitor circuit selectively coupling a capacitance to at least one of an input and an output of the third operational transconductance amplifier.

Further, a digital-to-analog converter, an analog-to-digital converter and a filter comprising the above amplifier circuit are disclosed, such digital-to-analog converter, analog-to-digital converter and filter further comprising a circuit generating a switched-capacitor input signal which is input to the input of the first operational transconductance amplifier.

According to a third aspect of the present invention, there is disclosed yet another amplifier circuit comprising: a first amplifier module comprising an input and an output and having a first gain, a first bandwidth, and a first output impedance; a second amplifier module comprising an input in communication with the input of the first amplifier module and an output and having a second gain less than the first gain, a second bandwidth greater than the first bandwidth, and an output impedance less than the first output impedance; and a capacitor in communication with an output of the second amplifier module and in communication with an output of the first amplifier module.

Drawings

The present invention will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1 is an electrical schematic diagram of an amplifier with Miller compensation according to the prior art;

FIG. 2 is a graph illustrating the gain and bandwidth of the amplifier of FIG. 1;

FIG. 3A is an electrical schematic diagram of an exemplary amplifier with compensation according to the present invention;

FIG. 3B is an electrical schematic diagram of an exemplary amplifier with compensation according to the present invention;

FIG. 3C is an electrical schematic diagram of an exemplary amplifier with compensation according to the present invention;

FIG. 3D is an electrical schematic diagram of an exemplary amplifier with compensation in accordance with the present invention;

4A-4C are diagrams illustrating exemplary gains and bandwidths of an amplifier;

FIGS. 5 and 6 are electrical schematic diagrams of an amplifier with compensation and additional gain stages according to the present invention;

FIG. 7A is an electrical schematic of an exemplary amplifier according to the present invention;

FIG. 7B is an electrical schematic of the amplifier of FIG. 7A with parasitic capacitance;

FIG. 7C is an electrical schematic of an amplifier according to the invention with a switched capacitor circuit;

FIG. 8 is a functional block diagram illustrating an exemplary switched input including the switched-capacitor circuit of FIG. 7C and an amplifier;

FIG. 9 is a functional block diagram and electrical schematic diagram illustrating an exemplary switched-capacitor circuit:

FIG. 10 is an electrical schematic diagram of the amplifier of FIG. 7C with an additional amplifier stage;

FIG. 11 is an electrical schematic diagram of the amplifier of FIG. 7C configured in a differential mode;

FIG. 12A is a functional block diagram of a hard disk drive;

FIG. 12B is a functional block diagram of a Digital Versatile Disc (DVD);

FIG. 12C is a functional block diagram of a high definition television;

FIG. 12D is a functional block diagram of a vehicle control system;

FIG. 12E is a functional block diagram of a cellular telephone;

FIG. 12F is a functional block diagram of a set-top box; and

fig. 12G is a functional block diagram of the media player.

Detailed Description

The following description of the preferred embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. As used herein, the term module, circuit and/or device refers to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and/or other suitable components that provide the described functionality. As used herein, the phrase "at least one of A, B and C" should be interpreted to mean logic (A or B or C) that uses non-mutually exclusive logical ORs. It should be understood that the steps of a method may be performed in a different order without altering the principles of the present invention. For purposes of clarity, the same reference numbers will be used in the drawings to identify similar elements.

Referring now to FIG. 3A, an electrical schematic of an amplifier circuit 50 with compensation according to the present invention is shown. While specific examples of amplifier circuits will be shown and described, other combinations are also contemplated. The amplifier circuit 50 includes a first amplifier module 52 having an input and an output. The input of the amplifier module 52 communicates with the input of the amplifier module 55. The output of amplifier module 55 is coupled to the output of amplifier module 52 through capacitor 56.

The amplifier module 55 may have a gain that is less than the gain of the amplifier module 52. The amplifier module 52 may have a gain greater than or equal to 100. The amplifier module 55 may have a gain of less than 100. In some implementations, the gain of the amplifier module 55 is much less than 100. The amplifier module 55 may have a very high bandwidth and low output impedance. The amplifier module 55 may have a bandwidth that is greater than the bandwidth of the amplifier module 52. The output impedance of amplifier module 52 may be greater than the output impedance of amplifier module 55. Amplifier module 55 may include a transconductance amplifier. The amplifier circuit 50 has a first DC path 57 and a second high frequency path 58.

Referring now to fig. 3B-3D, various combinations of amplifiers may be used in the amplifier modules 52 and 55 of the amplifier circuit 50. Although specific examples will be shown, other combinations are also contemplated. In fig. 3B, the amplifier module 52 may include an amplifier 53. In fig. 3C, amplifier module 55 may include a transconductance amplifier. In fig. 3D, the amplifier module 52 may include a miller compensation amplifier. Other variations are still contemplated.

Referring back to fig. 3C, the amplifier circuit 50 includes an amplifier module 52, the amplifier module 52 including a first amplifier 53, the first amplifier 53 having an output in communication with an input of a second amplifier 54. The input of the amplifier 53 is coupled to an amplifier module 55. Amplifier module 55 includes an amplifier 62, an amplifier 66, and a feedback resistor 70. The output of amplifier 62 is coupled to the input of amplifier 66. A feedback resistor 70 is connected between the input and the output of amplifier 66. Capacitive element 56 capacitively couples the output of amplifier 66 to the input of amplifier 54. Amplifiers 53 and 54 provide a DC gain path 80. Additional amplifiers may be used to adjust the gain of the DC gain path 80. Amplifiers 62 and 66 and capacitor 56 provide a high frequency gain path 84.

Referring now to fig. 3D, the amplifier module 52 may include an amplifier 53 and a miller compensation amplifier 85 with capacitive feedback CM. An additional amplifier 86 may be provided between the output of miller compensation amplifier 85 and the input of amplifier 54. Other combinations are still contemplated.

Referring now to fig. 4A-4C, exemplary diagrams illustrating gain and bandwidth of an amplifier circuit are shown. As can be appreciated, the amplifier circuit 50 in fig. 3A has extra bandwidth at higher gain values. The slope of the gain is increased to 40dB/decade, causing the gain to drop later but faster. The additional gain stage may further increase the slope to 60dB/decade as shown in fig. 4B. Depending on the stage and/or configuration, the region of gain-bandwidth response may have a slope of 20, 40, 60, etc. dB/decade, as shown in FIG. 4C.

Referring now to fig. 5 and 6, electrical representations of other amplifiers with compensation and additional gain are shown. One or more additional amplifiers may be provided in the DC gain path 80 to provide additional gain. In fig. 5, the amplifier circuit 90 includes amplifiers 53 and 101 connected between the input of the amplifier circuit 90 and the amplifier 54. In fig. 6, amplifier circuit 100 includes one or more additional amplifiers 101-M connected between amplifiers 52-2 and 54, where M is an integer greater than 1. As can be appreciated, additional amplifier stages may be added to the DC path as needed to provide additional gain.

The amplifier circuit according to the invention has an improved gain and an improved settling time (settling time) at both high and low frequencies. The amplifier circuit has a high gain at low voltage operation, as each stage can now be configured in a non-cascaded arrangement.

Referring now to fig. 7A and 7B, the amplifier circuit 108 includes an amplifier 110, the amplifier 110 having an input and an output coupled to an input of an amplifier 114. The input of amplifier 110 is coupled to the input of amplifier 118 through capacitor 116. The output of amplifier 118 is coupled to the input of amplifier 120. The output of amplifier 120 is coupled to the input of amplifier 114 through capacitor 122.

A feedback resistor 124 is connected to the input and output of the amplifier 120. A feedback resistor 126 is connected to the input and output of the amplifier 118. The feedback resistor 126 may have a high resistance value. For example, the feedback resistor may have a resistance value greater than the resistance value of the resistor 124. The feedback resistor 126 may have a very high resistance value, e.g., a resistance approaching infinity. A load capacitor 128 may be connected to the output of the amplifier 114. In fig. 7B, parasitic capacitance 129 associated with the relatively high feedback resistance 126 may tend to limit the bandwidth of the circuit.

In fig. 7C, an amplifier circuit 130 according to the present invention is shown. The amplifier circuit 130 may include switched capacitances to mimic the high feedback resistance 126 without the problems associated with parasitic capacitances. The amplifier circuit 130 includes an amplifier 110, the amplifier 110 having an output coupled to an input of the amplifier 114. The input of amplifier 110 is also coupled to the input of amplifier 118 through capacitor 116. The output of amplifier 118 is coupled to the input of amplifier 120. The output of amplifier 120 is coupled to the input of amplifier 114 through capacitor 122.

The input and output of the amplifier 118 may be in communication with a switched-capacitor circuit 131. Switched capacitor circuit 131 includes first and second switches 132 and 134. A capacitor 136 is connected between the switches 132 and 134 and a reference potential such as ground. In the first phase phi₁During this time, the first switch 132 is closed and the second switch 134 is opened, and the capacitor 136 is charged. In the second phase phi₂During this time, the first switch 132 is opened and the second switch 134 is closed, which allows the capacitor 136 to discharge. The first and second phases may correspond to the first and second phases of the switch input and/or vice versa. A feedback resistor 124 is connected to the input and output of the amplifier 120. A load capacitor 146 may be connected to the output of the amplifier 114. In some applications, amplifier 130 may receive a switching input. The switched input may be a switched capacitive input such as found in capacitive ADCs, DACs, filters, and the like.

Referring now to fig. 8 and 9, an exemplary circuit is shown that includes the switched-capacitor circuit 148 of fig. 7C and the amplifier 130. The input voltage of the amplifier circuit 130 may be a switched capacitor input. The switched-capacitor input may be generated in circuits such as filters, digital-to-analog converters (DACs), analog-to-digital converters (ADCs), and other circuits. As can be appreciated, other kinds of inputs and/or other switched-capacitor circuits may be used. Switched capacitor circuit 148 includes first and second switches 152 and 154. A capacitor 158 is connected between the switches 152 and 154 and a reference potential such as ground. In the first phase phi₁During this time, the first switch 152 is closed and the second switch 154 is opened, and the capacitor 158 is charged. In the second phase phi₂During this time, the first switch 152 is opened and the second switch 154 is closed, and the capacitor 158 is discharged via the amplifier 100.

Referring now to fig. 10, amplifier circuit 180 is similar to that shown in fig. 7C and further includes amplifiers 182-1, 182-2. The additional amplifier 182 tends to increase the slope of the gain-bandwidth response in region 200 shown in fig. 4.

Any of the amplifier circuits described above may be configured in a differential mode. For example, referring now to fig. 11, the amplifier of fig. 7C may be configured in a differential mode. The other amplifiers described herein may also be configured in a differential mode. An amplifier 202 receiving differential switch inputs in accordance with the present invention is shown. The amplifier 202 includes a differential amplifier 110D, the differential amplifier 110D having a differential output coupled to a differential input of the differential amplifier 114D. The differential input of the differential amplifier 110D is also coupled to the differential input of the differential amplifier 118D through capacitors 116-1 and 116-2. The differential output of the differential amplifier 118D is coupled to the differential input of the differential amplifier 120D. The differential output of the differential amplifier 120D is coupled to the differential input of the differential amplifier 114D through capacitors 122-1 and 122-2.

The differential inputs and differential outputs of the differential amplifier 118D are in communication with switched-capacitor circuits 131-1 and 131-2. A load capacitor (not shown) may be connected to the differential output of the differential amplifier 114D.

The amplifiers described herein may be amplifiers, Operational Transconductance Amplifiers (OTAs), amplifiers with Miller compensation, and/or other suitable amplifiers. OTA is a transconductance type device. The input voltage controls the output current based on the transconductance gm. In other words, the OTA is a Voltage Controlled Current Source (VCCS), which is in contrast to a conventional amplifier (opamp) which is a Voltage Controlled Voltage Source (VCVS).

The transconductance parameters of the OTA are controlled by the amplifier bias current. According to the controlled transconductance, the output current is a function of the voltage difference applied between the input pins. There are two key differences between OTA and traditional opamp. First, because the OTA is a current source, the output impedance of the device is high. In contrast, the output impedance of opamp is low. Second, the circuit can be designed using an OTA without using negative feedback. In other words, feedback is not utilized to reduce the sensitivity of circuit performance to device parameters.

Referring now to fig. 12A-12G, various exemplary implementations of the present invention are shown. Referring now to FIG. 12A, the present invention may be implemented in amplifiers, ADCs, DACs, filters, and other circuitry in hard disk drive 400. In some implementations, signal processing and/or control circuits 402 and/or other circuits (not shown) in HDD 400 may process data, perform coding and/or encryption, perform calculations, and/or format data for output to and/or reception from magnetic storage medium 406.

HDD 400 may communicate with a host device (not shown) such as a computer, a mobile computing device such as a personal digital assistant, cellular telephone, media or MP3 player, and/or other devices via one or more wired or wireless communication links 408. HDD 400 may be connected to memory 409 such as Random Access Memory (RAM), low latency nonvolatile memory such as flash memory, Read Only Memory (ROM), and/or other suitable electronic data storage.

Referring now to fig. 12B, the present invention may be implemented as amplifiers, ADCs, DACs, filters, and other circuits of a Digital Versatile Disc (DVD) drive 410. Signal processing and/or control circuits 412 and/or other circuits (not shown) in the DVD 410 may process data, perform coding and/or encryption, perform calculations, and/or format data read from and/or written to the optical storage medium 416. In some implementations, the signal processing and/or control circuits 412 and/or other circuits (not shown) in the DVD 410 can also perform other functions such as encoding and/or decoding and/or any other signal processing functions associated with a DVD drive.

DVD drive 410 may communicate with an output device (not shown), such as a computer, television, or other device, via one or more wired or wireless communication links 417. DVD drive 410 may communicate with mass data storage 418 that stores data in a nonvolatile manner. The mass data storage 418 may include a Hard Disk Drive (HDD). The HDD may have the configuration shown in fig. 12A. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. The DVD 410 may be connected to memory 419 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring now to fig. 12C, the present invention may be implemented as amplifiers, ADCs, DACs, filters, and other circuits of a High Definition Television (HDTV) 420. The HDTV420 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 426. In some implementations, signal processing and/or control circuit 422 and/or other circuits (not shown) of HDTV420 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other type of HDTV processing that may be required.

The HDTV420 may communicate with mass data storage 427 that stores data in a nonvolatile manner such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in fig. 12A and/or at least one DVD may have the configuration shown in fig. 12B. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. HDTV420 may be connected to memory 428 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV420 may also support connections with a WLAN via a WLAN network interface 429.

Referring now to FIG. 12D, the present invention may be implemented in the control system of the vehicle 430, the WLAN interface, the mass data storage of the vehicle control system, and/or the amplifier, ADC, DAC, filter and other circuitry of the power supply 433. In some implementations, the present invention implements a powertrain control system 432 that receives input from one or more sensors, such as temperature sensors, pressure sensors, rotation sensors, airflow sensors, and/or any other suitable sensors, and/or generates output one or more control signals, such as engine operating parameters, transmission operating parameters, and/or other control signals.

The present invention may also be implemented in other control systems 440 of the vehicle 430. The control system 440 may likewise receive signals from input sensors 442 and/or output control signals to one or more output devices 444. In some implementations, the control system 440 may be part of an anti-lock braking system (ABS), a navigation system, a telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc, or the like. Other implementations are still contemplated.

The powertrain control system 432 may communicate with mass data storage 446 that stores data in a nonvolatile manner. The mass data storage 446 may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 12A and/or at least one DVD may have the configuration shown in fig. 12B. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. Powertrain control system 432 may be connected to memory 447 such as RAM, ROM, a low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The powertrain control system 432 may also support connections with a WLAN via a WLAN network interface 448. The control system 440 may also include mass data storage, memory, and/or a WLAN interface (all not shown).

Referring now to fig. 12E, the invention may be implemented as amplifiers, ADCs, DACs, filters and other circuitry of a cellular telephone 450 that may include a cellular antenna 451. In some implementations, the cellular telephone 450 includes a microphone 456, an audio output 458 such as a speaker and/or audio output jack, a display 460, and/or an input device 462 such as a keypad, pointing device, voice actuation (actuation), and/or other input device. Signal processing and/or control circuits 452 and/or other circuits (not shown) in cellular telephone 450 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular phone 450 may communicate with mass data storage 464 that stores data in a nonvolatile manner, such as optical and/or magnetic storage devices. The optical and/or magnetic storage device is for example a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 12A and/or at least one DVD may have the configuration shown in fig. 12B. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. The cellular telephone 450 may be connected to memory 466 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The cellular telephone 450 may also support connections with a WLAN via a WLAN network interface 468.

Referring now to fig. 12F, the present invention may be implemented as amplifiers, ADCs, DACs, filters, and other circuitry of the set top box 480. The set top box 480 receives signals from a source such as a broadband source and outputs standard and/or high definition audio/video signals suitable for a display 488 such as a television and/or monitor and/or other video and/or audio output device. Signal processing and/or control circuits 484 and/or other circuits (not shown) of the set top box 480 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box 480 may communicate with mass data storage 490 that stores data in a nonvolatile manner. The mass data storage 490 may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 12A and/or at least one DVD may have the configuration shown in fig. 12B. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. The set top box 480 may be connected to memory 494 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box 480 may also support connections with a WLAN via a WLAN network interface 496.

Referring now to fig. 12G, the present invention can be implemented as amplifiers, ADCs, DACs, filters, and other circuitry of the media player 500. In some implementations, the media player 500 includes a display 507 and/or a user input 508 such as a keypad, touch pad, or the like. In some implementations, media player 500 may use a Graphical User Interface (GUI) that typically employs menus, drop down menus, icons, and/or a point-and-click interface via display 507 and/or user input 508. Media player 500 also includes an audio output 509 such as a speaker and/or an audio output jack. Signal processing and/or control circuits 504 and/or other circuits (not shown) of media player 500 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player 500 may communicate with mass data storage 510 that stores data, such as compressed audio and/or video content, in a non-volatile manner. In some implementations, the compressed audio files include files compatible with MP3 format or other suitable compressed audio and/or video formats. The mass data storage may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 12A and/or at least one DVD may have the configuration shown in fig. 12B. The HDD may be a miniature HDD having a diameter of less than about 1.8 inches that includes one or more platters. The media player 500 may be connected to memory 514 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The media player 500 may also support connections with a WLAN via a WLAN network interface 516. Other implementations than those described above are contemplated.

Those skilled in the art can now appreciate from the foregoing description that the broad teachings of the present invention can be implemented in a variety of forms. Therefore, while this invention has been described in connection with particular examples thereof, the true scope of the invention should not be so limited since other modifications will become apparent to the skilled practitioner upon a study of the drawings, the specification and the following claims.

Claims (30)

1. An amplifier circuit, comprising:

a first amplifier having an input and an output;

a second operational transconductance amplifier having an input in communication with an output of the first amplifier;

a third amplifier having an input in communication with the input of the first amplifier and an output;

a fourth operational transconductance amplifier having an output and an input in communication with an output of the third amplifier;

a feedback resistor in communication with an input and an output of the fourth operational transconductance amplifier; and

a capacitor in communication with an output of the fourth operational transconductance amplifier and in communication with an input of the second operational transconductance amplifier.

2. The amplifier circuit of claim 1 further comprising N operational transconductance amplifiers connected in series, where N is an integer greater than zero, and wherein an input of a first one of the N operational transconductance amplifiers is in communication with an output of the first amplifier and an output of a last one of the N operational transconductance amplifiers is in communication with an input of the second operational transconductance amplifier.

3. The amplifier circuit of claim 1 wherein an input of the third amplifier is capacitively coupled to the first amplifier, and further comprising a switched-capacitor circuit in selective communication with an input and an output of the third amplifier.

4. The amplifier circuit of claim 3, wherein the switched-capacitor circuit comprises:

a first switch having a first terminal in communication with an input of the third amplifier;

a second switch having a first terminal in communication with an output of the third amplifier; and

a capacitor having one end in communication with the second terminals of the first and second switches.

5. A digital to analogue converter comprising an amplifier circuit as claimed in claim 3 and further comprising a circuit for generating a switched capacitor input signal which is input to an input of the amplifier circuit.

6. An analog-to-digital converter comprising the amplifier circuit of claim 3 and further comprising circuitry to generate a switched-capacitor input signal that is input to an input of the amplifier circuit.

7. A filter comprising the amplifier circuit of claim 3 and further comprising circuitry to generate a switched-capacitor input signal that is input to an input of the amplifier circuit.

8. An amplifier circuit, comprising:

a first operational transconductance amplifier having an input and an output;

a second operational transconductance amplifier having an input in communication with an output of the first operational transconductance amplifier;

a third operational transconductance amplifier having an input in communication with an input of the first operational transconductance amplifier;

a fourth operational transconductance amplifier having an input in communication with an output of the third operational transconductance amplifier and an output in communication with an input of the second operational transconductance amplifier;

a switched capacitor circuit selectively coupling a capacitance to at least one of an input and an output of the third operational transconductance amplifier.

9. The amplifier circuit of claim 8, further comprising a resistor having an input in communication with an input of the fourth operational transconductance amplifier and an output in communication with an output of the fourth operational transconductance amplifier.

10. The amplifier circuit of claim 8, wherein the switched-capacitor circuit comprises:

a first switch having a first terminal in communication with an input of the third operational transconductance amplifier;

a second switch having a first terminal in communication with an output of the third operational transconductance amplifier; and

a capacitor having one end in communication with the second terminals of the first and second switches.

11. The amplifier circuit of claim 8, further comprising a capacitor having one end in communication with an input of the first operational transconductance amplifier and an opposite end in communication with an output of the second operational transconductance amplifier.

12. The amplifier circuit of claim 8, further comprising N additional operational transconductance amplifiers connected in series between an output of the first operational transconductance amplifier and an input of the second operational transconductance amplifier.

13. A digital to analogue converter comprising the amplifier circuit of claim 8 and further comprising circuitry to generate a switched capacitor input signal which is input to the input of the first operational transconductance amplifier.

14. An analog-to-digital converter comprising the amplifier circuit of claim 8 and further comprising circuitry to generate a switched-capacitor input signal that is input to the input of the first operational transconductance amplifier.

15. A filter comprising the amplifier circuit of claim 8 and further comprising circuitry to generate a switched-capacitor input signal that is input to the input of the first operational transconductance amplifier.

16. The digital-to-analog converter of claim 13, wherein the switched-capacitor input signal includes first and second phases, and wherein switches in the switched-capacitor circuit switch based on the first and second phases of the switched-capacitor input signal.

17. The analog-to-digital converter of claim 14, wherein the switched-capacitor input signal comprises first and second phases, and wherein a switch in the switched-capacitor circuit switches based on the first and second phases of the switched-capacitor input signal.

18. The filter of claim 15, wherein the switched-capacitor input signal comprises first and second stages, and wherein the switches in the switched-capacitor circuit switch based on the first and second stages of the switched-capacitor input signal.

19. The amplifier circuit of claim 8, wherein the amplifier circuit is configured in a differential mode.

20. The amplifier circuit of claim 8, further comprising a capacitor having one end in communication with an input of the first operational transconductance amplifier and an opposite end in communication with an input of the third operational transconductance amplifier.

21. An amplifier circuit, comprising:

a first amplifier module comprising an input and an output and having a first gain, a first bandwidth, and a first output impedance;

a second amplifier module comprising an input in communication with the input of the first amplifier module and an output and having a second gain less than the first gain, a second bandwidth greater than the first bandwidth, and an output impedance less than the first output impedance; and

a capacitor in communication with an output of the second amplifier module and in communication with an output of the first amplifier module.

22. The amplifier circuit of claim 21 wherein the first gain is greater than or equal to 100 and the second gain is less than 100.

23. The amplifier circuit of claim 21 wherein the second amplifier module comprises an operational transconductance amplifier.

24. The amplifier circuit of claim 21 wherein the second amplifier module comprises:

a third amplifier having an output and an input in communication with the input of the first amplifier module;

a fourth operational transconductance amplifier having an output and an input in communication with an output of the third amplifier;

a first resistor in communication with an input and an output of the fourth operational transconductance amplifier.

25. The amplifier circuit of claim 21 further comprising a third operational transconductance amplifier in communication with an output of the first amplifier module.

26. The amplifier circuit of claim 25 further comprising N operational transconductance amplifiers connected in series, where N is an integer greater than zero, and wherein an input of a first one of the N operational transconductance amplifiers is in communication with an output of the first amplifier module and an output of a last one of the N operational transconductance amplifiers is in communication with an input of the third operational transconductance amplifier.

27. The amplifier circuit of claim 21 wherein the first amplifier module comprises a first amplifier.

28. The amplifier circuit of claim 21 further comprising a first amplifier having an input in communication with an output of the first amplifier module and the capacitance.

29. The amplifier circuit of claim 21, wherein the first amplifier module comprises:

a first amplifier having an input and an output;

a second amplifier having an output and an input in communication with the output of the first amplifier;

a capacitor in communication with an input and an output of the second amplifier; and

a third amplifier having an input in communication with an output of the second amplifier.

30. The amplifier circuit of claim 21 wherein the second and third amplifiers comprise transconductance amplifiers.