HK1104391A - Spread spectrum isolator - Google Patents

Description

Spread spectrum isolator

Cross Reference to Related Applications

The present application is a partial continuation of the application of co-pending U.S. application serial No. 10/860,399 entitled "transformer isolator for digital power supply" filed on 6/3/2004, co-pending U.S. application serial No. 10/860,519 entitled "on-chip transformer isolator" filed on 6/3/2004, and co-pending U.S. application serial No. 11/020,977 entitled "RF isolator with differential input/output" (attorney docket number CYGL/26,965) filed on 12/22/2004 and co-pending U.S. patent application serial No. 11/064,413 entitled "RF isolator for isolating voltage sense and gate driver" (attorney docket number CYGL-27,015) filed on 23/2/2005.

Technical Field

The present invention relates to digital isolators, and more particularly to digital isolators that provide isolation of voltage sensing and gate drivers.

Background

In power conversion products, there is a need for high speed digital links that provide high isolation at low cost. Typical digital links in power conversion products require speeds of 50-100 megabits per second. The isolation between the input and output of the power conversion product needs to be in the range of 2,500-5,000V. Existing solutions to provide high speed digital isolation links have focused on the use of magnetic pulse couplers, magnetoresistive couplers, capacitive couplers, and optical couplers.

Referring now to fig. 1, a general block diagram of a system that uses a magnetic pulse coupler to isolate a digital link 102 between a driver 104 and a detector 106 is illustrated. Driver 104 is located on one side of digital link 102 and sends information over digital link 102 to detector 106, which is located on the other side of the digital link. Located between driver 104 and detector 106 is pulse transformer 108. Pulse transformer 108 provides an electromagnetic coupling transformer between driver 104 and detector 106. The pulse transformer 108 generates a pulse output in response to a supply input from the driver as shown in fig. 2. The input from driver 104 includes two pulses 202 and 204. Each pulse 202, 204 includes a rising edge 206 and a falling edge 208. In response to the rising edge 206, the output of the pulse transformer 108 generates a positive pulse 210. The falling edge 208 of the pulse produces a negative pulse 212. The pulse transformer circuits described with respect to fig. 1 and 2 suffer from a number of deficiencies. These include start-up, where the detector 106 will not know at which point the input from the driver begins, whether high or low, until the first edge is detected. In addition, if any errors occur in the pulse output of the pulse transformer 108, it will be difficult for the detector 106 to determine when to return to the normal state, since there may be a long period of time between pulses.

Referring now to fig. 2, an alternative prior art solution using a magneto resistive coupler is illustrated. Magnetoresistive coupler 302 includes a resistor 304 and an associated transformer 306. The resistor 304 has a resistance value that varies in response to the magnetic flux around the resistor. The transformer detector 306 detects the magnetic flux of the resistor and the determined transmission data using a wheatstone bridge.

Another method of isolation between the driver 404 and the detector 406 is illustrated in fig. 4. Driver 404 and detector 406 are isolated on opposite sides of digital link 402 by capacitor 408. Capacitor 408 capacitively couples driver 404 and detector 406 together to achieve a level of isolation. A problem with using capacitive coupling to isolate the digital link is that capacitive coupling does not provide common mode rejection.

Another problem with some isolator designs relates to the reception of RF interference from nearby transmitting GSM, DCS, and CDMA cellular telephones. This problem is caused by the use of printed circuit boards as a GHz frequency dipole antenna. This results in a large common mode signal being seen at the isolator at RF frequencies. Some method of minimizing these large common mode signals at GHz frequencies would be highly desirable.

Accordingly, an improved method of providing isolation on a high speed digital link within a power supply assembly is highly desirable.

Disclosure of Invention

The invention disclosed and claimed herein, in one aspect thereof, comprises a circuit package comprising a first unit containing functional circuitry and a second unit containing functional circuitry. At least one RF isolation link interconnects the first and second units. The at least one RF isolation link provides voltage isolation between the first unit and the second unit and enables data to be provided between the first and second units using an RF carrier signal. The RF carrier signal swings between a first frequency and a second frequency.

Drawings

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a block diagram of a prior art magnetic pulse coupler isolator;

FIG. 2 illustrates the input and output signals of the prior art magnetic pulse transformer of FIG. 1;

FIG. 3 illustrates a prior art magnetoresistive coupler;

FIG. 4 illustrates a prior art capacitive coupler;

FIG. 5 illustrates a switching power supply including isolation circuitry;

FIG. 6 illustrates an RF isolation link of the present disclosure;

FIG. 6a illustrates a schematic block diagram of circuitry providing an RF isolation link using frequency modulation;

FIG. 7 illustrates a schematic diagram of circuitry that provides an RF isolation link using amplitude modulation;

FIG. 8 illustrates waveforms present at the transmit side of the RF isolation link of FIG. 7;

FIG. 9 illustrates waveforms present at the receive side of the RF isolation link of FIG. 7;

FIG. 10 illustrates the frequency response of the RF isolation link;

FIG. 11 illustrates a model of one of the transformers contained within the RF isolation link;

FIG. 12 illustrates the frequency response of one transformer of the RF isolation link;

FIG. 13 illustrates the voltage across each transformer contained within the RF isolation link and across the entire RF isolation link;

FIG. 14a is a block diagram illustrating circuitry contained within a chip on one side of an RF isolation link for providing a plurality of isolation link lanes;

FIG. 14b is a schematic diagram of an oscillator circuit;

FIG. 14c is a block diagram of the logic circuit of FIG. 17 a;

FIG. 15 illustrates a pair of chips within a single package including four independent lanes for providing four isolated digital data links;

FIG. 15a illustrates an RF isolation link within a chip package;

fig. 16 illustrates an integrated RF isolation link in a single package including two die;

fig. 16a illustrates an integrated RF isolation link in a single package with a digital input and a digital output;

FIG. 16b illustrates an integrated RF isolation link in a single package including digital input/output and analog input/output;

FIG. 16c illustrates an integrated RF isolation link in a single package including analog input/output and analog input/output;

FIG. 17a illustrates an RF isolation link integrated with a microcontroller;

FIG. 17b illustrates an RF isolation link integrated with a microcontroller interconnected to a second chip providing an analog input and an analog output;

FIG. 18a illustrates one coil of a transformer of the RF isolation link;

FIG. 18b illustrates a second coil of the transformer of the RF isolation link;

fig. 19 illustrates an overlay of the transformer depicted in fig. 21a and 21 b;

FIG. 20 is a side view of a coil of a transformer forming an RF isolation link;

FIG. 21 illustrates an offset between metal layers to increase breakdown voltage within a transformer;

FIG. 22 illustrates a perspective cross-sectional view of a coil construction;

FIG. 23 illustrates the separate areas where the transformer coil and circuitry will be implemented on a chip utilizing RF isolation circuitry; and

FIG. 24 illustrates the structure of an RF isolation link integrated on a single chip;

FIG. 25 illustrates an isolator chip having two printed circuit boards that may be used as a higher frequency dipole antenna;

FIG. 26 illustrates the parasitic capacitance between windings at higher frequencies;

FIG. 27 illustrates how an RF signal can pass through a transformer as a common mode signal;

FIG. 28 illustrates a schematic diagram of an RF isolator including differential outputs;

FIG. 29 is a more detailed schematic diagram of the RF isolator of FIG. 28;

FIG. 30 is an illustration of a transformer coil including a center-tapped RF isolator;

FIG. 31 illustrates a method by which voltage may be altered to maintain optimal receiver/transmitter gain;

FIG. 32 is a schematic diagram illustrating a prior art method of generating a bandgap reference voltage;

FIG. 33 is a schematic diagram of a method of generating a bandgap reference voltage according to the present disclosure;

FIG. 34 illustrates a prior art method of generating a reference voltage;

FIG. 35 illustrates an improved method of generating a bandgap reference voltage;

fig. 36 illustrates a switching power supply including a PWM controller and a power transistor;

fig. 37 illustrates a prior art method of isolating a PWM controller on the primary side of a switching power supply from a driver on the secondary side;

fig. 38 illustrates a second prior art approach to isolating the PWM controller on the primary side of the switching power supply from the driver circuit on the secondary side;

fig. 39 illustrates a final prior art implementation of isolating the PWM controller of the primary side of the switching power supply from the driver of the secondary side;

FIG. 40 illustrates a block diagram of an isolated gate driver that isolates a PWM controller from power transistor circuitry voltages;

FIG. 41 is a general schematic diagram of an isolated gate driver;

fig. 42 illustrates a circuit package including two independent dies implementing isolated gate drivers;

FIG. 43 is a detailed schematic diagram of circuitry implementing an isolated gate driver;

FIG. 44 is a schematic diagram of the level shifter of FIG. 41;

FIG. 45 illustrates a prior art method of isolating a voltage sensing circuit from a PWM controller;

FIG. 46 is a schematic block diagram of a method for isolating voltage sensing between the output voltage of the secondary side and the PWM controller of the primary side;

FIG. 47 illustrates an integrated chip including circuitry to isolate the gate driver from the PWM controller voltage on the primary and secondary sides of the switching power supply, and to isolate the voltage sensing function on the secondary side of the switching power supply from the PWM controller voltage on the primary side;

FIG. 48a illustrates the use of a single RF frequency with an RF isolator;

FIG. 48b illustrates the radiated emissions of an RF isolator using a single RF frequency;

FIG. 49a illustrates the use of stepped frequencies that are stepped between first and second frequencies;

figure 49b illustrates the radiated emissions of a stepped frequency RF isolator;

fig. 50 illustrates a block diagram of a first embodiment of a circuit that generates a hierarchical RF carrier signal;

FIG. 51 is a schematic diagram of an RF oscillator circuit for use in the circuit of FIG. 50;

FIG. 52 illustrates a schematic diagram of the slow oscillator circuit of FIG. 50;

FIG. 53 illustrates a block diagram of a second embodiment of a circuit that generates a stepped RF carrier signal;

FIG. 54 is a schematic diagram of the circuit of FIG. 52;

FIG. 55 illustrates simulation results for the circuit of FIG. 50; and

fig. 56 illustrates an alternative embodiment of creating a random code for generating a hierarchical RF carrier signal.

Detailed Description

Referring now to the drawings, and more particularly to fig. 5, there is illustrated a block diagram of a DC-DC switching power supply utilizing an RF isolation link. Switching power supplies utilize a plurality of switches that turn on and off to switch an input DC voltage across a transformer to a load, the output voltage being at different DC voltage levels. By switching the current inductively coupled to the load via the transformer in a specific manner, a DC output voltage at a different voltage level than the input DC voltage may be provided to the load. Controlled switches are typically simplified using some type of control circuitry. The control circuit may be an analog control circuit formed from a plurality of analog discrete devices, or it may be a digital circuit. In digital control circuits, Digital Signal Processors (DSPs) and micro-controller units (MCUs) have been utilized. The DSP controls the duty cycle and associated timing of the switches so that the edge of each control pulse to the various transistor switches that control power delivery to the load is varied. To perform this operation in the digital domain, the DSP must perform a large number of computations, which require the generation of a significant amount of code to support a particular power supply topology, operating frequency, component characteristics, and performance requirements. For example, inductor size decreases with increasing PWM frequency, dead time increases with increasing transistor off time, and so on. While DSPs can handle regular tasks, they are quite complex and expensive, and code changes in power applications are difficult.

With further reference to fig. 5, the power supply includes a primary switch bank 502 operable to receive an input voltage, which is a DC voltage, on a node 504 and to ground on a node 506. The primary switch set 502 is coupled to a secondary switch set 510 through an isolation transformer 508. The secondary switch set 510 is operable to drive an input voltage node 512 connected to one terminal of a load 514, the secondary switch set 510 also having a ground connection on a node 516, the load 514 being disposed between the node 512 and the node 516. The two switch sets 502 and 510 are operable to operate in conjunction with various pulse inputs on a control bus 518 associated with the primary switch set 502 and various pulse inputs on a control bus 526 associated with the secondary switch set 510.

A digital control circuit 524 is provided to control the operation of the primary switch set 502 and the secondary switch set 510. The voltages on nodes 504 and 506 are provided as inputs to a digital control circuit 524 for sensing the voltage and current on the primary side, and the digital control circuit 524 generates signals on bus 518 that control the primary switch bank 502. The control circuit 524 must be isolated from the secondary bank switch 510 because there may be a significant DC voltage difference therebetween. This is simplified by driving the bus 526 through an isolation circuit 528, such as an RF isolation circuit as will be discussed below, to drive the bus 520. Similarly, the control circuit 524 is operable to sense the voltage and current levels on the output node 512 via sense line 530, the output line 530 also being connected to the digital control circuit 524 via isolation circuit 532. Digital control circuitry 524 also interfaces with bus 536 to receive external control/configuration information. This may be simplified using a serial data bus, such as an SMB serial data bus.

Referring now to fig. 6, an RF isolation link of the present disclosure is illustrated. The RF isolation link 600 of the present disclosure is implemented by integrating a portion of the link in two chips or dies between which a high speed data link with voltage isolation is required. Each chip 602 includes a transformer 604 and transmit and receive circuitry 606 that provide an RF isolation link 600 between chips. Alternatively, chip 602 may include only transmit circuitry or receive circuitry with a patterned chip, including a corresponding receiver or transmitter. RF signals are generated in transmit/receive circuitry 606 on one side of the RF isolation link and are transmitted between chips 602 using transformers 604 in each chip and the magnetic coupling effect therebetween.

Upon receiving the RF signal at the receiving side, the transmit and receive circuitry 606 detects the data contained in the transmission from the first chip and utilizes the data appropriately. Although the description with respect to fig. 6 illustrates only transformer 604 and transmit and receive circuitry 606 in each chip 602, additional circuitry for performing processing functions associated with data transmitted via RF isolation link 600 will be implemented on chip 602. Data transmitted via RF isolation link 600 may be transmitted using a frequency modulation technique or an amplitude modulation technique. In a preferred embodiment of the disclosure discussed below with respect to fig. 7, AM modulation is used to transmit the data.

In operation, each of the transmit/receive circuits 606 operates in either a transmit or receive mode. In transmit mode, digital data received on the digital bus 603 is serially transmitted from one of the transmit/receive circuits 606 to another on another die 602. This is simplified by driving the transformer 606 with a signal so that energy is coupled from its primary to its secondary. This will allow energy to be transferred on the transmission line 605 coupling the transformers 604 together. Each of the transformers includes a primary 607 and a secondary 609. The primary 607 is driven with an input signal and the energy associated with it is coupled from the primary 607 to the secondary 609 across a high voltage isolation boundary and onto the transmission line 605. As described below, the transmit/receive circuitry 606 and the transformer 604 are fabricated on an integrated circuit such that the primary 607 and secondary 609 are both formed thereon using conventional processing techniques and available conductive layers shared with the transmit/receive circuitry. There will be losses associated with the coupling coefficient between the primary and secondary so that the amount of energy that can be transferred from the transmit/receive circuitry 606 to the transmission line 605 is reduced and, in addition, there will be more losses at some frequencies than others. For example, the transformer 604 will have a unique frequency response, where losses will be greater at certain frequencies than others. To accommodate this, transmit/receive circuitry 606 has a transmitter contained therein that operates at a specified frequency that is within the lowest loss portion of the frequency response of transformer 604. Data may be transmitted on the carrier to the transmission line 605 using various modulation schemes. The operation of the transmitter/receiver circuit 606 will be described in more detail below.

Referring now to fig. 6a, an alternative embodiment of a switching power supply that utilizes frequency modulation to transmit data between a pair of chips via an RF isolation link 600 is illustrated. The description with respect to fig. 6a is provided merely as an illustration of one possible embodiment of FM circuitry for creating an RF isolation link, and one skilled in the art will recognize the possibility of many additional embodiments. Data is input on data bus 610 to manchester encoding circuitry 612, a conventional data encoding circuit. Also input to manchester encoding circuit 612 is a clock signal. The clock signal is also input to the voltage controlled oscillator 614. Data is output from manchester encoding circuit 612 and applied to frequency dividing circuit 616. A second input of the divider circuit 616 is connected to the output of the voltage controlled oscillator 614. The output of the divider circuit 616 is connected to a second input of the voltage controlled oscillator 614 to allow modulation thereof using the manchester encoding circuit 616. The voltage controlled oscillator 614 outputs a frequency modulated signal representing the received data on the bus 610 to the driver 618. The signal is filtered by capacitor 620 before being applied to transformer 622. The FM modulated signal is coupled by transformer 622 onto transmission line 624 traversing interface 626 between the first and second chips that are voltage isolated from each other.

The received data signal is electromagnetically coupled to the receiver circuitry by a second transformer 628. The received signal passes through a slicer circuit 630 whose output is applied to a divide-by-N circuit 632 and a discriminator circuit 634. The output of the divide-by-N circuit 632 is applied to the input of a PFD (phase/frequency detector) circuit 636. A second input to the PFD circuit 636 is provided by a second divide-by-N circuit 638 having its input connected to the output of the voltage controlled oscillator 640. The input of the voltage controlled oscillator 640 is connected to the output of the PFD circuit 636. The output of the voltage controlled oscillator 640 is connected to a second input of the discriminator 634, which is a phase locked output phase locked to the data clock. Discriminator circuit 634 determines the data contained in the received signal in response to the outputs of voltage controlled oscillator 640 and slicer 630. The data is provided to a latch circuit 636 whose clock input is connected to the output of divide-by-N circuit 638. The data output of the receiver is provided from latch circuit 642.

Referring now to fig. 7, a preferred embodiment of an RF isolation link 600 of the present disclosure is illustrated in which data is transmitted over the link using amplitude modulation. The RF isolation link 600 includes transmitter circuitry 702 and receiver circuitry 704. Transmitter circuitry 702 includes a NAND gate 708 having a first input connection to receive data to be transmitted via RF isolation link 600 and a second input connection to receive an RF carrier signal. The RF carrier in the preferred embodiment comprises a 2GHz signal. First input to NAND gate 708The incoming data includes a logic "1" or "0" which, in the presence of a logic "1", will selectively gate the RF carrier signal to the output of NAND gate 708. This causes the output 709 of the NAND gate 708 to provide an RF carrier signal when the data bit is a "1" or no RF signal when the data bit is a "0". The output 709 of the NAND gate is connected to the gate of a p-channel transistor 710. The drain-source path of p-channel transistor 710 is connected at V through resistor 712 and first transformer 714_DDAnd the ground. Transformer 714 electromagnetically couples the RF carrier signal to transformer 718 via line 716. This connects data represented by the RF carrier signal between the first chip 602a and the second chip 602b while providing voltage isolation between the chips 602 via the first and second transformers 714, 718. Each of transformers 714 and 718 is associated with a particular chip 602 on opposite sides of interface 720. Thus, where prior systems required separate chips to provide an isolation link between the two separate chips, the disclosed device integrates the RF isolation link 600 onto the chip 602.

Receiver circuit 704 receives a signal that has been electromagnetically coupled to transmission line 716, via transformer 714, to transformer 718. Receiver circuit 704 includes an amplifier 705 and a detector 706. Amplifier 705 provides two stages of amplification including a first amplification stage comprising a capacitor 722 in series with an amplifier 724 and a feedback resistor 726. The second amplification stage is similar to the first amplification stage and includes a capacitor 728 in series with an amplifier 730 and a feedback resistor 732. These two stages amplify the received signal from transformer 718.

Detector 706 detects the presence or absence of an RF carrier signal in the amplified received signal to determine the data being transmitted from first chip 602 a. The amplified signal from amplifier 705 is first filtered by capacitor 734. An N-channel transistor 736 has its gate connected to the capacitor 734 and its source-drain path connected to one side of the current mirror comprised of p-channel transistors 738 and 740. The source-drain path of transistor 738 is connected at V_DDAnd node 742 with its gate connected to the gate of transistor 740. The source-drain path of transistor 740 is connected at V_DDAnd node 743, the gate thereofIs connected to node 743 to provide a diode connected configuration. The output of detector 706 is provided from node 742 where the source-drain path of n-channel transistor 736 is connected to p-channel transistor 738 of the current mirror. The bias network is provided by n-channel transistors 744 and 746 whose source-drain paths are connected between node 743 and ground and whose gates are connected to node 745 through resistor 748, and capacitor 750 is connected between node 745 and ground. Bias is also provided by a resistor 752 connected between node 745 and the gate of transistor 736, a diode-connected p-channel transistor 754 connected between node 745 and ground, and a current source 756 that drives node 745. When the receiver does not detect an RF signal, the data output from node 742 of detector circuit 706 will be equal to V_DDSince the PMOS current is 1.33 times larger than the NMOS current, and a logic "0" is detected. In the presence of an RF signal, the data output from node 742 will change in response to a detected change in the RF carrier signal and a logic "1". Detector 706 outputs a low voltage when RF is present and a high voltage when RF is not present, depending on the non-linear (square root) behavior of the MOS device controlled by the alternating current.

Referring now to fig. 8 and 9, waveforms and data provided at the transmit side of the RF isolation link 600 (fig. 8) and the receive side of the RF isolation link (fig. 9) are illustrated. On the transmit side illustrated in fig. 8, data 800 is transmitted as either a one bit (high) or a zero bit (low). One bit pulses are indicated at 802, 804 and 806. The zero pulses are indicated at 808 and 810. The transmit data provided to transformer 714 is illustrated by waveform 812. The transmit data waveform represents a 2ghz rf carrier signal. The presence of the 2ghz rf carrier is provided at the transmit data output when a logic "1" data bit is being transmitted and the data signal is high. When a logic "0" bit is being transmitted, the signal is effectively zero at the transmit data output. Thus, whether a logic "1" bit or a logic "0" bit is transmitted is indicated by the presence or absence of a 2GHz RF carrier signal.

Fig. 9 illustrates waveforms associated with receiver 704. The received data of logical "1" bits is represented at points 902, 904, and 906 and indicates that it was transmitted from the transmitter 702 of the RF isolation link 600Three 2.5GHz RF carrier pulses. The received pulses are amplified by amplifier 705 so that when a signal is input to detector circuit 706, the pulses are represented by amplified waveform pulses 908, 910, and 912. As previously discussed, the detector data output rises to V at points 916, 918 where the detector 706 does not detect that the RF carrier signal indicates a logic "0"_DD. When the RF carrier signal is detected, the output of detector 706 begins to change and decreases at points 920, 922, and 924 indicating a logic "1," which is a result of an increase in NMOS current in transistor 736.

Referring now to fig. 10, the frequency response of the channel with the RF isolation circuit 600 depicted in fig. 7 is illustrated.

Referring now to fig. 11, a model of the transformer (714, 718) illustrated in fig. 7 is illustrated. The input to the transformer includes nodes 1002 and 1100. Node 1002 is connected to ground through capacitor 1104 and resistor 1106. Node 1100 is connected to ground through capacitor 1116 and resistor 1118. Node 1102 is interconnected with node 1100 via the parallel connection of a capacitor 1108 in series with a resistor 1110 and an inductor 1112 in series with a resistor 1114. The output of the transformer includes nodes 1122 and 1124. Node 1122 is connected to ground through capacitor 1126 and resistor 1128. Node 1124 is connected to ground through capacitor 1130 and resistor 1132. Node 1122 is interconnected to node 1124 via the parallel connection of a capacitor 1134 in series with a resistor 1136 and an inductor 1138 in series with resistor 1140. Nodes 1102 and 1122 are interconnected via a capacitor 1142 having a value of about 125 Ff. Nodes 1100 and 1124 are interconnected via a capacitor 1144 having a value of about 125 Ff.

Referring specifically to fig. 13, it can be seen that the low frequency response of the transformer is relatively lossy, however the peak of the response occurs at about 2.5 GHz. This is due to the method of transformer manufacture. Each side of the transformer includes an inductive element, each inductive element on either side of the transformer being coupled together via a layer of dielectric material, as will be described below. The series inductance value will result in an effect on the frequency response which will narrow the frequency response slightly. The amount of energy coupled from the output is a function of the coupling coefficient. Both sides of the transformer are located on the substrate, as will be described below, such that one element is located on the other and separated therefrom by a high voltage dielectric to increase the effective breakdown voltage. This will allow high frequency energy to be coupled from one conductive element to another. The voltage breakdown is a function of the properties at DC of the material located between the two conductors and the distance separating them. If the transformer is manufactured on a single layer material in a semiconductor substrate, the distance between its edges will define the voltage breakdown. For example, the transformer device may be fabricated using a directional coupler, which will provide a wider band response. However, the area of such a design may be significant.

It can be seen that coupling through the energy from the DC pulse will be difficult because of the low frequency attenuation of the transformer, since only high frequency energy will pass there. For example, spectral energy coupled through a transformer of the present disclosure is concentrated there using a high frequency carrier that is substantially centered in the transformer frequency response. This will allow most of the energy generated to be coupled through the transformer.

Using the RF isolation link 600 described above, voltage isolation of up to 5,000 volts, 2,500 volts per side, can be achieved. Thus, as shown in fig. 16, the RF isolation circuitry 602 may provide 5,000 volts of isolation between the first chip 602a and the second chip 602 b. Although the voltage between the input terminals of die 602a will be zero volts and the voltage between the input terminals of die 602b will also be zero volts, the total voltage difference between the two dies may be 5,000 volts, across each 2,500 voltage difference of transformers 714, 718 associated with the interface to the RF isolation circuitry on each die 602.

Referring now to fig. 14a, a block diagram of an interface architecture of a single chip 602 containing a portion of multiple channels 1402 including RF isolation links of the present disclosure is illustrated. Each channel 1402 includes a transformer 1406 and transmit and/or receive circuitry described with respect to fig. 7. Data may be input or received at interface 1404 of transformer 1406. Each channel 1402 is interconnected with a shim driver 1408, the shim driver 1408 driving transmit data from the shim driver via the channel 1402 to output on an interface 1404 or driving receive data to an associated shim of the chip 602. The manner in which data is sent or received via a particular channel 1402a is controlled on chip 602 by logic circuitry 1410 that provides control over various control lines 1412. The method by which logic control 1410 controls whether a channel is used for transmit or receive is set by input pad option 1414. Thus, in this embodiment, when the shim is configured as a transmitter, (or not driven), the data is received as a logical "1" or a logical "0" and drives the associated transformer. For receive data on the associated transformer, the output of the pad is either high or low when configured to receive the data.

An oscillator circuit 1430 is also associated with all channels of the interface. A band gap generator 1420 is provided on the chip and connected to V_DDTo provide a bandgap reference voltage to the regulator circuit 1422. Although the description with respect to fig. 14a illustrates only a single voltage regulator 1422, it should be noted that a separate voltage regulator 1422 would be associated with each channel of the interface for noise. The voltage regulator 1422 includes an amplifier 1424 having an input connected to the output of the bandgap generator 1420. The output of amplifier 1424 is connected to the gate of transistor 1426. The drain-source path of transistor 1426 is connected at V_DDAnd node 1427. Node 1427 is also connected to a second input of differential amplifier 1424. Capacitor 1428 is connected between node 1422 and ground. Each of the channels 1402a, 1402b, 1402c, and 1402d has an adjuster 1422 associated therewith. Connected to node 1427 is an oscillator circuit 1430.

Fig. 14b illustrates the oscillator circuit 1430 of fig. 14 a. The output 1435 is connected to a node 1437 between the transistor 1436 and the transistor 1438. The drain-source path of transistor 1436 is connected at V_DDAnd node 1437. The drain-source path of transistor 1438 is connected between node 1437 and ground. The gates of transistors 1436 and 1438 are connected to each other through node 1439. Transistor 1440 has its gate connected to ground and its drain-source path connected at V_DDAnd the gate of transistor 1440. Node 1439 also interconnects transistor 1442 and transistor 1444. The drain-source path of transistor 1442 is connected at V_DDAnd node 1439. Crystal grainThe drain-source path of transistor 1444 is connected between node 1439 and ground. The gates of transistors 1442 and 1444 are interconnected to each other via node 1445. Capacitor 1446 is connected between node 1445 and ground. Node 1445 is connected to a first terminal of coil 1450. A second terminal of coil 1450 is interconnected with circuitry via node 1460. Transistors 1452 and 1454 are interconnected via node 1445. The drain-source path of transistor 1452 is connected at V_DDAnd node 1445. The drain-source path of transistor 1454 is connected between node 1445 and ground. The gates of transistors 1452 and 1454 are connected to node 1460. Transistors 1458 and 1456 are interconnected via node 1460. The drain-source path of transistor 1458 is connected at V_DDAnd node 1460. The drain-source path of transistor 1456 is connected between node 1460 and ground. The gates of transistors 1458 and 1456 are connected to node 1445. Capacitor 1462 is connected between node 1460 and ground. Also connected to node 1460 are the gates of transistors 1464 and 1466. The drain-source path of transistor 1464 is connected at V_DDAnd node 1465, and the drain-source path of transistor 1466 is connected between node 1465 and ground. The oscillator thus comprises a conventional LC oscillator.

Referring now to FIG. 14c, one embodiment of circuitry that may be included in logic circuitry 1410 is illustrated. In this embodiment, the logic circuitry 1410 includes a decoder 1432. The decoder has a total of three pad inputs B0, B1, and B2 for receiving a version indication of the chip being implemented. The output 1434 of the decoder is input to the appropriate channel so that the channel can be configured in either transmit or receive mode.

Referring now also to fig. 15, a method is illustrated by which the single chip design depicted in fig. 16 can be used to simplify the overall RF isolation circuitry including four independent RF isolation channels. Inverting the first chip 1502 reverses only the output channels 1402 between the first chip 1502 and the second chip 1504. Thus, when chip 1502 is viewed from the top to the bottom of chip one, channel one is on the top, channel two is second, channel three is third, and channel four is last. For the second chip 1504, the channels proceed in the opposite direction, channel one starting from the bottom and channel four at the top. The physical design of chip 1502 and chip 1504 are the same. The chip 1504 is merely flipped to simplify the three versions of the chip as described below. Three different bonding option patterns may be selected for input to the logic circuitry 1410 of the package containing the first chip 1502 and the second chip 1504 using the decoder circuit 1432. Referring now to table 1, three independent versions of the operation of the first chip 1502 and the second chip 1504 are illustrated, along with an indication of whether the channel includes an associated version of a transmit or receive channel.

Types of	Chip and method for manufacturing the same	Channel 1	Channel 2	Channel 3	Channel 4
						1	1	Tx	Tx	Tx	Tx
2	1	Tx	Tx	Rx	Rx
						3	1	Tx	Rx	Rx	Rx
1	2	Rx	Rx	Rx	Rx
						2	2	Tx	Tx	Rx	Rx
3	2	Rx	Tx	Tx	Tx

Table 1

It can be seen that the associated chips 602 and 604 lanes correspond such that when a lane on one chip transmits or receives, the corresponding lane on the other chip performs the opposite operation.

Referring now to fig. 15a, an RF isolation link 600 within a chip package is illustrated. As previously discussed in fig. 15, chips 1602a and 1602b are illustrated interconnected by four independent channels 604. Each via 604 is represented by two wire bonds interconnecting a transformer (not shown) in each of chips 1602a and 1602 b. Each of the chips 1602a and 1602b is also connected to various pads 1504 within the package by bond wires 1542 that provide connections to another electronic circuitry.

The embodiment of fig. 15a is referred to as a "split leadframe" package. This is simplified by using lead frame 1550 on one side thereof and lead frame 1552 on the other side thereof. Lead frame 1550 interfaces with terminals 1554 and lead frame 1550 interfaces with terminals 1556. Lead frames 1550 and 1556, which are not electrically connected to each other, provide support for chips 602a and 602b, respectively, during manufacturing. When chips 602a and 602b are bonded to respective portions of their lead frames, they are then bonded to appropriate terminals 1554 and 1556, and then to bonding wire 604 located therebetween. The entire package is then sealed within a conventional seal. Thus, wire bonds 604 each comprise a high frequency transmission line between two chips, and each transformer is associated with two wire bonds providing a "two-wire" transmission line.

Referring now to fig. 15b, a side view of one of the wire bonds 604 is illustrated. It can be seen that the substrate associated with die 602a has pads 1560 located thereon, and die 602b has pads 1562 located thereon. Wire 604 is bonded to pad 1516 on one side using conventional bonding and also to pad 1562 on die 602 b. The length of the bond wire 604 is a fraction of the wavelength of the 2.4GHz frequency. However, it will be inductive in nature and will have distributed inductance and capacitance associated with it. For example, the transmission characteristics of the wire bonds can affect the transmission of information between the two die 602a and 602 b. As noted above, the input impedance of each of the pads 1560 is in the range of 500 ohms. Thus, for ideal information transmission, there may be some matching circuitry required, although not stated here, except for the bond wire 604, which forms only a two-wire transmission line.

Referring now to fig. 16, a method by which an RF isolation link 600, represented as RF isolation circuitry 1602, can be integrated into two separate multifunction dies 1604 and 1606 within a single package 1608 is illustrated. RF isolation circuitry 1602 may provide isolation between components on two separate dies 1604 and 1606. Associated with one or both of the dice may be additional circuitry 1610 such as a microcontroller or other electronic component. This additional circuitry will be isolated from components in another die via RF isolation link 1602.

Referring now also to fig. 16a, where RF isolation link 600 is integrated onto two separate dies 1604 and 1606 in a single package 1608. An isolation interface 1602 including a transceiver 1612 and a transformer 1614 may be used to provide only a digital IN, digital OUT package 1608. In this embodiment, a digital input 1620 is applied to the first transceiver 1612 a. Alternatively, digital input 1620 may be applied to digital circuitry connected to transceiver 1612 a. The isolation circuit operates in the manner described above, and a second digital output 1622 is provided from transceiver 1612b or associated digital circuitry.

Referring now to fig. 16b, rather than providing only digital input/digital output circuitry, a single package 1608 including first and second dies 1604, 1606 implementing the RF isolation circuitry described above may provide circuitry having both digital input/output and analog input/output. In this case, the digital input/output 1924 would be connected to the transceiver 1612a or digital circuitry of the first die 1604. The first die 1604 is coupled to the second die 1606 via the RF isolation link, and the transceiver 1612b is coupled to an analog input/analog output 1626 through a data converter, depending on the direction ADC1614 or DAC 1616.

Referring now to fig. 16c, a single package 1908 including first and second dice 1604, 1606 implementing the RF isolation circuitry described above may provide circuitry with analog input/outputs on one side and analog input/outputs on the other side. In this case, the analog input/output 1640 would be connected to an A-D converter 1642 and a D-A converter 1644, and then to the transceiver 1612a or digital circuitry of the first die 1604. First die 1604 is coupled with second die 1606 via the RF isolation link, and transceiver 1612b is coupled to analog input/output 1646 via a-to-D converter 1648 and D-to-a converter 1650. In this way, analog signals may be transmitted in either direction across the single package 1608.

Referring now to fig. 17a, there is illustrated a chip 1702 that includes a portion of the RF isolation link described hereinabove. Chip 2002 includes a single transformer 1704 of RF isolation link 600 and transmit and receive circuitry 1706. The RF isolation link 600, including the transceiver 1706 and transformer 1704, is integrated with the microcontroller unit 1708 through digital input/output 1710. Memory 1712 stores operating instructions and data needed by microcontroller unit 1708. Chip 1702 would be capable of interconnecting with a second chip that contains an interface similar to that contained in chip 1702, including transformer 1704 and transceiver 1706. By interconnecting to such chips, microcontroller 1708 and the interconnect chip will be voltage isolated from each other via a complete RF isolation link between them.

The transmit and receive circuitry 1706 is part of an integrated circuit I/O interface. One type of integrated circuit that provides all of the functionality illustrated in fig. 17a is a conventional microcontroller unit of the C8051FXXX type manufactured by the present assignee. This chip provides an on-board processing through the MCU 1708, an interface to the analog domain and an interface to the digital domain. The integrated circuit also has the capability to configure various outputs, for example, digital outputs may be provided on a serial interface for driving transmit/receive circuitry 1706 or receiving serial data therefrom.

The process of manufacturing the MCU 1708, the memory 2012, and the digital I/O1710 is quite complex, except for various analog-to-digital data converters or digital-to-analog data converters. For example, rather than making the process compatible with the transformer, the transmit and receive circuitry 1706 and transformer 1704 must be compatible with the process. As will be described below, there are multiple metal layers used to fabricate the various interconnects associated with the fabrication of integrated circuits. By utilizing multiple metal layers that are already present during the manufacturing process, both sides of the transformer 1704 can be manufactured and isolated from each other with sufficient isolation to provide adequate overvoltage protection. Additionally, because of the high voltage and high frequency of the transformer, transformer 1704 is actually located in a separate portion of the chip surface area so that it does not cover any circuitry associated with digital or analog operation, as this is a mixed signal integrated circuit.

One example is illustrated in fig. 17b, where chip 1702, which includes an RF isolation link comprising transformer 1704 and transceiver 1706, is integrated with microcontroller unit 1708 through digital input/output 1710. The MCU 1708 also includes an associated memory 1712. In this case, a first portion of the RF isolation link including transformer 1704 and transceiver 1706 is interconnected with a second portion of the RF isolation link including transformer 1714 and transceiver 1716. In this case, the chip 1718 including the second portion of the RF isolation link includes a digital-to-analog converter 1720 and an analog-to-digital converter 1722 for converting the digital output of the transceiver 1716 of the RF isolation link to an analog output and converting the received analog input to a digital input. The chip 1718 allows for output of an analog signal at analog output 1724 and input of an analog signal at analog input 1726. These analog signals may then be used in any desired manner by a circuit designer.

Referring now to fig. 18a, 18b, 19 and 20, the structure of the transformer coil of the transformer 714 or 718 (fig. 7) integrally formed on the CMOS device is illustrated. Each transformer 714 and 718 is integrated as part of one of the chips or dice that include the RF isolation link. Referring particularly to fig. 18a and 18b, two coils included in each of the transformers 714 or 718 are illustrated. The first coil 1802 includes a first terminal 1804 and a second terminal 1806 formed in a metal layer of the chip called a "metal 1" layer. Each terminal in the metal 1 layer is connected to a transformer coil 1808 located on a second metal layer of the chip, referred to as the "metal 2" layer. Conductive vias 1810 interconnect the coils 1808 with the terminals 1804. A second conductive path 1812 interconnects the coil 1808 with a second terminal 1806. The second coil is located on a fifth metal layer called the "metal 5" layer. The coil includes a first pad 1814 and a second pad 1816. Each of the first and second conductive pads 1814, 1816 is interconnected by a second coil 1818 surrounding the pad 1816 and interconnected with the pad 1814. Unlike the coil depicted in fig. 18a, coil 1818 includes pads 1814, 1816 and coil 1818 on the same metal layer (metal 5).

Typically, the metal 5 layer is the uppermost layer. Referring now also to fig. 19, an overlay of the first and second coils of the on-chip transformer is illustrated. As can be seen, the pad 1816 is sized so that it is 1/32 μ x 94 μ n. The overall coil was dimensioned 268 μm by 205 μm. The shim 1814 is sized to be 70 μm by 80 μm. The two coils 1818 and 1808 are similar in construction and are oriented such that they are substantially "non-overlapping". However, they may overlap.

Referring now to fig. 20, there is illustrated a side view of a die 602 containing the transformer structure described with respect to fig. 18a, 18b and 19. Chip 602 includes transceiver circuitry including the RF isolation link and substrate layer 2002 of any electronic circuitry integrated with the RF isolation link as previously described. A metal 1 layer 2004 is located on the substrate 2002 and includes first and second terminals 1804, 1806 of the first transformer coil. Above the metal 1 layer is a metal 2 layer 2006 that contains a first coil 1808 interconnected by vias to first and second terminals 1804 and 1806 (not shown). Finally, metal 5 layer is located on metal 2 layer 2008. Metal 5 layer 2010 contains another portion of the transformer including solder conductive pads 1816 and solder pads 1814 (not shown) and a coil 1818 interconnecting solder pads 1816 and solder pads 1814. The metal 1 layer of the transformer is primarily used to provide interconnections for terminals 1804 and 1806 to the rest of the circuit. However, the process utilizes all five metal layers for the various interconnects. For over-voltage protection, it is desirable to space coil 1818 as far as coil 1808, recognizing that the material located therebetween is silicon dioxide, a dielectric. An additional consideration is the capacitor loaded on coil 1818 to ground, with substrate 2002 typically at ground. A high voltage will be present on the coil 1818 so it is as far as possible from the substrate and the coil 1818. Although the coil 1818 may already be fabricated in the metal 1 layer, there will be a need to provide interconnections from the coil ends to the circuitry. This would require a "path" to be provided under the metal 1 layer, which would require the use of a polysilicon layer. Even multi-layer silicidation will not be provided as well as the conductive layers associated with the metal layers. For example, the construction uses a metal 1 layer for the interconnects and a metal 2 layer for the coils.

While it is desirable to provide even additional metal layers to further space coil 1818 from coil 1808, it is not feasible to complicate processing using special additional layers. The only reason for using the additional layer is to fabricate another circuitry on the integrated circuit. The reason for this is that once the process is defined to be able to utilize multiple metal layers, substantially all of the circuit paths through the process will use multiple layers. It is difficult to dedicate the process to a single integrated circuit using only this further metal layer, and therefore the coil is manufactured in an existing process from an already existing metal layer. However, if additional metal layers are used in the future in existing processes, it is possible that the coil 1818 is located in an even higher layer than metal 5.

Referring now to fig. 21, an offset is illustrated that is used between the metal path 2102 of the coil 1818 on the metal 5 layer and the metal path 2104 of the coil 1808 on the metal 2 layer. Rather than having metal paths 2104 on the metal 2 layer directly underneath metal paths 2102 on the metal 5 layer, they are diagonally offset from each other to increase the breakdown voltage between components by increasing the distance. In the disclosed embodiment, the total distance between metal 5 layer path 2102 and metal 2 layer path 2404 is 3.63 μm. The metal 2 layer path 2104 is vertically shifted 3.54 μm and horizontally shifted 0.8 μm from the metal 5 layer path 2102. The metal 5 via layer 2102 is vertically spaced 5.24 μm from the silicon layer. The structure should be isolated according to equation 3.63 × 10 for breakdown voltage^-6m*8×10⁸2904v provides the breakdown voltage between metal 5 and metal 2 layers. The breakdown voltage between the metal 5 layer 2402 and the silicon layer 2406 may be according to equation 5.24 × 10^-6m*8×10⁸And v/m is determined by 4192 v.

Referring now to FIG. 22, a cutaway perspective view of the coils 1818 and 1808 illustrated in FIG. 21 is illustrated. It can be seen that metal paths 2104 are substantially the same shape as metal paths 2102, but they do not overlap and are separated by a dielectric layer. The description only illustrates a single corner of the coil.

Referring now to fig. 23, a chip 602 including an RF isolation link according to the present disclosure is illustrated. The area of chip 602 will be divided into at least two portions. The first portion 2302 will include circuitry that provides a transformer that electromagnetically couples with a transformer on another chip to provide a voltage isolation link between the chips. The remaining electronic circuitry of the chip will be located in the independent region 2304, and will include the transmitter and receiver circuitry of the voltage isolation link associated with the transformer, as well as any electronic circuitry that will be integrated with the voltage isolation link, such as a microcontroller or other type of electronic device. This will be repeated for multiple voltage isolated links for additional data paths. In addition, it should be noted that the layout is such that the area 2302 containing the transformer on its top surface will have the pads 2116 provided in the center of the coil 2118 and the pads 2114 provided at its periphery. Pad 2114 is located near the edge of the chip so that a wire bond 604 can be connected thereto. In addition, pad 2116 is located on the same surface as pad 2114 so that a wire bond 604 associated therewith may be connected thereto. For example, in a coil that needs to extend through other layers and be closer to the coil at right angles thereto, there is no path that needs to be connected to the pads 2116. Wire bond 604 associated therewith will actually be further from the actual metal path 2102 associated with coil 1818. Additional areas may include additional electronic circuitry on the chip for voltage isolation via voltage isolation links on the same chip.

Fig. 24 illustrates the overall structure of the RF isolation link implemented on chip 2402. Four independent interface connections 2404 provide connections to each of the four channels of the RF isolation link integrated into chip 2402. Each of the four interfaces 2404 is linked with an oscillator 2406 and a coil 2408. Connected to each of the interfaces 2404 is a transformer 2410 that includes a first coil 2412 and a second coil 2414. The coil 2414 is connected with the interface 2404 to provide interconnection with an external chip via an RF isolation link. The coil 2412 is interconnected to the pad 2416. Should be used forNote that channel one and channel four coils 2414 each include two independent pads 2416. However, channel two and three coils 2414 each have pads located inside the coils, but share an outer pad 2416 between channel two and three. Shim circuitry 2418 is associated with oscillator circuit 2406 and coil 2410. The pad circuitry 2418 is interconnected with the rest of the circuitry on the chip 2402 via a number of pads. The pads include ground pad 2418, V_DDA pad 2420, two enable pads 2422, four output pads 2424 and four input pads 2426, one for each lane.

One problem with the above-described RF isolation link design is that RF interference from nearby transmitting cellular telephones may produce common mode interference that may not be filtered in the receive section. Referring now to fig. 25, at GHz frequencies, an application printed circuit board comprising two separate portions 2502 produces a split ground plane that can be used as a dipole antenna. The split ground plane may have dimensions close to the size of a quarter wavelength of 900 MHz. This results in a very large common mode signal that may pass through the isolator chip 2504. Measurements from nearby GSM cellular phones transmitting at maximum power can produce common mode voltages up to 3.4V peak at 900 MHz. This will cause interference within the RF isolation link as described above, such that a "0" is incorrectly detected as a "1" when the cellular telephone is operating nearby. One way to reduce this problem is by adding an EMI capacitor 2506 between the isolated ground planes. Thus, at a frequency of 900MHz, a circuit without EMI capacitor 2506 would have a peak common mode voltage of 3.4V, but a circuit with 300pF capacitor 2506 would only have a 1.1V peak. Similarly, at 2GHz, a circuit without EMI capacitor 2506 would have a.85V peak common mode voltage, but when 300 picofarad EMI capacitor 2506 is included, a 0.07V peak common mode voltage. An RF isolator as described hereinabove cannot handle this level of common mode interference.

The previously described single-ended design relies on the transformer to provide all common mode rejection. Although the transformer has very good common mode rejection below 100MGz, the common mode rejection of the transformer is poor at GHz frequencies. This is because of parasitic capacitance 2602 generated in the transformer 2604 as shown in fig. 26. This is more fully illustrated in fig. 27, where the vertical axis illustrates common mode gain and the horizontal axis illustrates frequency. As can be seen in fig. 27, at 100MHz frequency, the common mode gain is relatively minimal. However, as GHz frequencies are approached, the common mode gain increases, thereby increasing the amount of common mode interference that will pass through the transformer circuitry of the RF isolation link.

In the embodiment illustrated in fig. 28, the problem of common mode interference is solved by modifying the transformer 2802 to be a center-tapped transformer and including a differential amplifier 2810. The use of the center-tapped transformer 2802 removes the frequency of the circuit resonance by splitting the parasitic capacitance. The center tap of the transformer 2802 on the transmission side is grounded via a capacitor 2804. The center tap of the transformer 2802 on the reception side is grounded. For common mode signals, the bandwidth of the center-tapped transformer is twice as high as that of a single-ended design. This helps suppress the 900MHz common mode interference. The data to be transmitted is applied to a first input of the NAND gate 2814 and the RF signal is applied to a second input of the NAND gate 2814, before being applied to the center-tapped transformer 2802. A differential amplifier 2810 is used on the receive side to further suppress common mode interference. In this circuit, common mode interference is applied to the inputs of the differential amplifier 2810 as a common mode signal rejected by the differential amplifier 2810. The transmitted RF signal is differential and amplified by the receiver RF and applied to the detector circuit 2810, an example of which may be the detector circuit described above.

Referring now to fig. 29, an alternative embodiment of the RF isolation link 2900 of fig. 28 including transmitter circuitry 2902 and receiver circuitry 2904 is illustrated. Transmitter circuitry 2902 includes a NAND gate 2908 having a first input connected to receive data transmitted via RF isolation link 2900 and a second input connected to receive an RF carrier signal. The RF carrier in the preferred embodiment comprises a 2GHz signal. The data input to the first input of NAND gate 2908 comprises a logic "1" or "0" which, in the presence of a logic "1", will selectively gate the RF carrier signal to the output of NAND gate 2908. This causes the output of the NAND gate to provide an RF carrier when the data bit is "1The wave signal or no RF signal is provided when the data bit is "0". The output of NAND gate 2908 is connected to the gate of p-channel transistor 2910. The drain-source path of p-channel transistor 2910 is connected at V_DDAnd a first input of first transformer 2912. Transformer 2912 is a center-tapped transformer with center-tapped node 2914 connected to transistor 2916. The drain-source path of transistor 2916 is connected between node 2914 and ground. The gate of transistor 2916 is connected to receive signal tx _ ena-bar. The output of NAND gate 2908 is also connected to the input of inverter 2918. The output of inverter 2918 is connected to the gate of transistor 2920. The drain-source path of transistor 2920 is connected between the transformer 2912 and ground. The receiver amplifier 2922 is connected across the transformer 2912 and may be disabled by the disable input 2924 when the chip is transmitting. Transformer 2912 electromagnetically couples the RF carrier signal to transformer 2926 via wire bond 2928. This links the data represented by the RF carrier signal between the transformers and limits common mode signals while providing voltage isolation between the chips via the first and second transformers 2912 and 2926. Each of the transformers 2912 and 2926 is associated with an opposite side of the interface.

The receiver circuitry 2904 receives a signal that has been electromagnetically coupled via the center-tap transformer 2912 onto the wire bond 2928 to the center-tap transformer 2926. Connected to the center-tap node 2930 of the center-tap transformer 2926 is a transistor 2932. The drain-source path of transistor 2932 is connected between the center-tap node 2930 and ground. The gate of transistor 2932 is connected to V_DD. The output of the center-tapped transformer 2926 is connected to the input of a differential amplifier 2934. The differential amplifier 2934 includes first and second stages 2936 and 2938 that provide common mode rejection and a third stage 2940 that provides single-ended gain.

The first stage 2936 includes a set of two p-channel transistors 2942, 2944 and two n-channel transistors 2946 and 2948. The drain-source path of transistor 2946 is connected between node 2950 and node 2952, which is connected to the center-tapped transformer 2926. The gates of transistors 2946 and 2948 are cross-coupled to nodes 2950 and 2956, respectively, through capacitors 2956 and 2958. Transistor 2942 having its drain-source path connectedIs connected to V_DDAnd node 2952. Transistor 2948 is connected in its drain-source path between node 2954 and node 2956. Transistor 2944 having its drain-source path connected at node V_DDAnd node 2954. The gate of transistor 2942 is connected to node 2952. The gate of transistor 2944 is connected to node 2954. A resistor 2962 is additionally connected between the gate of transistor 2946 and the bias node 2964. A resistor 2966 is also connected between the gate of transistor 2948 and the bias node 2964.

The second stage 2938 is coupled to the first stage 2936 at nodes 2952 and 2954. Transistor 2968 has a gate connected to node 2952. Transistor 2970 has its gate connected to node 2954. The drain-source path of transistor 2968 is connected between node 2972 and node 2974. Transistor 2970 is connected in its drain-source path between node 2976 and node 2974. A current source 2978 is connected between the node 2974 and ground. Transistor 2980 is connected in its drain-source path between and node 2972. The gate of transistor 2980 is connected to node 2972. Transistor 2982 with its drain-source path connected at V_DDAnd node 2976. The gate of transistor 2982 is connected to node 2972. Transistor 2984 has its gate connected to node 2976. The drain-source path of transistor 2984 is connected at V_DDAnd node 2976. A current source 2986 is connected between the node 2976 and ground.

Third stage 2940 is coupled to second stage 2938 at node 2976. A capacitor 2988 is connected between the node 2976 and the input of the amplifier 2990. The output of amplifier 2990 has a feedback resistor 2992 connected to its input. The output of amplifier 2990 is also connected to a detector circuit 2994 for detecting the amplified data from the gain amplifier. Transmitter circuit 2926 is coupled to a single-tap transformer 2926 at node 2950. Transistor 2928 is connected in its drain-source path between node 2956 and ground. The gate of transistor 2928 is also connected to ground.

Referring now to fig. 30a, 30b, 31 and 32, the structure of the transformer coil of the transformer 2912 or 2926 (fig. 7) integrally formed on a CMOS device is illustrated. Each transformer 2912 and 2926 is integrated as part of one of the chips or dies that include the RF isolation link. Referring particularly to fig. 30a and 30b, two coils included in each of the transformers 2912 or 2926 are illustrated. The first coil 3002 includes a first terminal 3004 and a second terminal 3006 formed in a metal layer of the chip called a "metal 1" layer. Each terminal in the metal 1 layer is connected to a transformer coil 3008 located on a second metal layer of the chip, referred to as the "metal 2" layer. Conductive vias 3010 interconnect the coils 3008 with the terminals 3004. A second conductive pathway 3012 interconnects the coil 3008 and the second terminal 3006. The second coil is located on a fifth metal layer called the "metal 5" layer. The coil includes a first pad 3014 and a second pad 3016. Each of the first and second conductive pads 3014, 3016 is interconnected by a second coil 3018 surrounding the pad 3016 and interconnected with the pad 3014. Unlike the coil depicted in fig. 30a, coil 3018 includes pads 3014, 3016 and coil 3018 on the same metal layer (metal 5).

Typically, the metal 5 layer is the uppermost layer. Referring now also to fig. 31, an overlay of the first and second coils of the on-chip transformer is illustrated. As can be seen, the pad 3016 is sized so that it is 70 μm by 70 μm. The overall coil was dimensioned 205 μm by 205 μm. The pads 3014 are sized to 70 μm × 70 μm. The two coils 3018 and 3008 are similar in construction and are oriented such that they are substantially "non-overlapping". However, they may overlap. The intermediate taps are provided on the M1 layer using stripes 3104 that extend all the way across the coil of the transformer and include conductive vias 3102, providing intermediate taps that interconnect the metal 1 layer to the metal 2 layer in coil 3008.

Referring now to fig. 32, there is illustrated a side view of a chip 3200 including the transformer structure described in relation to fig. 30a, 30b and 31. Chip 3200 includes a substrate layer 3202 that includes transceiver circuitry of the RF isolation link and any electronic circuitry integrated with the RF isolation link as previously described. The metal 1 layer 3204 is located on the substrate 3202 and includes first and second terminals 3004, 3006 of the first transformer coil. Overlying the metal 1 layer is a metal 2 layer 3206 which contains a first coil 3008 interconnected by vias to first and second terminals 3004 and 3006 (not shown). Finally, the metal 5 layer is located on the metal 2 layer 3008. Metal 5 layer 3210 comprises another portion of the transformer, including bond pad 3016 and bond pad 3014 (not shown) and coil 3018 interconnecting bond pad 3016 and bond pad 3014. The metal 1 layer of the transformer is primarily used to provide interconnection for terminals 3004 and 3006 to the remaining circuitry. However, the process utilizes all five metal layers for the various interconnects. For over-voltage protection, it is desirable to space the coil 3018 as far as possible from the coil 3008, recognizing that the material located therebetween is silicon dioxide, a dielectric. An additional consideration is the capacitors loaded on the coil 3018 to ground, the substrate 3202 typically being at ground. A high voltage will be present on the coil 3018 so it is as far as possible from the substrate and the coil 3018. Although the coil 3018 may have been fabricated in a metal 1 layer, there will be a need to provide interconnections from the coil ends to the circuitry. This would require a "path" to be provided under the metal 1 layer, which would require the use of a polysilicon layer. Even multi-layer silicidation will not be provided as well as the conductive layers associated with the metal layers. For example, the construction uses a metal 1 layer for the interconnects and a metal 2 layer for the coils. The center tap stripe 3104 runs through the metal 1 layer and is connected to the coil 3008 in the metal 2 layer using conductive vias 3102.

While it is desirable to provide even additional metal layers to further space the coil 3018 from the coil 3008, it is not feasible to complicate processing using special additional layers. The only reason for using the additional layer is to fabricate another circuitry on the integrated circuit. The reason for this is that once the process is defined to be able to utilize multiple metal layers, substantially all of the circuit paths through the process will use multiple layers. It is difficult to dedicate the process to a single integrated circuit using only this further metal layer, and therefore the coil is manufactured in an existing process from an already existing metal layer. However, if additional metal layers are used in the future in existing processes, it is possible that the coil 3018 is located in an even higher layer than metal 5.

Another consideration in reducing common mode rejection is to sum receiver gainsThe transmit power is set to a level to allow data to pass through reliably but not at a higher capacity. This conserves power in the transmitter and improves common mode rejection which is worse at higher receiver gains. Once the gain is established, it should remain constant over temperature and process variations to provide optimal system performance. This may be done by setting the supply voltage (V) to the transmitter and receiver_DD) Instead of a constant stable voltage, with temperature and process variations. This is illustrated in fig. 33. It can be seen that for slow and fast processes, the voltage V is_DDIncreasing with increasing temperature. This helps to keep the RF gain of the amplifier more constant over temperature variations and allows for lower supply currents at lower temperatures.

Referring now to fig. 34, a prior art method of generating a reference voltage is illustrated in which a PTAT current generator 3402 is connected to the gate of a transistor 3404. The drain-source path of transistor 3404 is connected between the voltage and node 3406. A resistor 3408 is connected between the node 3406 and the transistor 3410. The emitter/collector path of transistor 3410 is connected between transistor 3408 and ground. The base of transistor 3410 is connected to its collector.

FIG. 35 illustrates an improved method of generating a bandgap reference voltage such that the voltage will vary with respect to temperature. The PTAT current generator 3402 again provides a voltage to the gate of the transistor 3404 that provides the PTAT current. The PTAT current provided by PTAT current generator 3402 is proportional to absolute temperature. The source-drain path of transistor 3404 is connected between the voltage and node 3406. p-channel transistor 3502 has its source-drain path connected between node 3406 and node 3504. The gate of transistor 3502 is also connected to node 3504. A resistance 3506 larger than that of the resistor 3408 in fig. 34 is connected between the node 3504 and the ground. By setting the sizes of the PMOS transistor 3502 and the resistor 3504, the reference voltage can be set to a desired level. This keeps the receiver gain constant because the bias current provided to the receiver is a PTAT current.

Referring now to fig. 36, in a switching power supply, there is a pair of power MOSFETs or I connected to a power transformer for drivingThe requirement of the gate driver of the GBT. The driver on the secondary side is typically controlled by the PWM controller on the primary side, and therefore, the connection from the PWM controller to the driver requires high voltage isolation. Power transformer 3602 includes a primary side 3604 and a secondary side 3606. Connected to each end of primary side 3604 of power transformer 3602 is a pair of power transistors 3608. The drain/source path of the transistor 3608a is connected to the input voltage (V)_IN) And node 3610. The drain/source path of transistor 3608b is connected between node 3610 and ground. The drain/source path of transistor 3608c is connected at V_INAnd node 3612. The drain/source path of transistor 3608d is connected between node 3612 and ground. The gate of each transistor 3608 is connected to a driver 3614, and the driver 3614 is connected to a PWM controller 3616.

The PWM controller 3616 provides a switching signal to the power transistor 3608, and the power transistor 3608 turns on and off in response to the switching signal provided to the driver 3614. PWM controller 3616 also provides the switching signal to transistor 3618 on the secondary side 3606 of power transformer 3602 through isolation barrier 3620. The drain/source path of transistor 3618a is connected between node 3622 and ground. The drain/source path of transistor 3618b is connected between node 3624 and ground. The gate of transistor 3618 is connected to a driver 3626 that receives a signal from PWM controller 3616 through an isolation barrier 3620. Each end of secondary side 3606 of power transformer 3602 is connected between node 3624 and node 3622. Inductor 3628 is connected between node 3624 and V_OUTIn the meantime. Inductor 3630 is connected between node 3622 and V_OUTIn the meantime. Finally, capacitor 3632 is connected at V_OUTAnd the ground. Therefore, there must be some way to isolate the signal provided to the secondary side transistor 3618 via the isolation barrier 3620 from the PWM controller 3616 voltage.

Currently, this problem is solved in many non-integrated ways. The first common method illustrated in fig. 37 utilizes an optical isolator. In this solution, the PWM controller 3702 provides a control signal to the base of transistor 3706 through resistor 3704. The emitter/collector path of transistor 3706 is connected between optical isolator 3708 and ground. Optical partitionIonizer 3708 connected to V through transistor 3710_DD. Optical isolator 3708 includes a light emitting diode 3712 and a light detecting transistor 3714 between resistor 3710 and the emitter of transistor 3706. The emitter of transistor 3714 is connected to V through resistor 3716_DD. The collector of transistor 3714 is connected to ground. The emitter of transistor 3714 is also connected to a gate driver integrated circuit 3718 which provides a signal to power FET 3720.

An alternative prior art solution uses a pulse transformer as shown in fig. 38. The PWM controller 3802 provides a control signal to the driver 3804. The driver 3804 provides pulses that are electromagnetically transmitted through the transformer 3806. The pulses are received at the receiver 3808 and used to operate the gate driver 3810.

The third prior art alternative illustrated in fig. 39 uses an integrated digital isolator 3904 with independent gate driver ICs. In this case, PWM controller 3902 is connected to digital isolator 3904, and digital isolator 3904 is connected to driver IC 3906. The digital isolator 3904 and the gate driver IC 3906 provide isolation between the PWM controller 3902 and a power FET 3908 connected to the driver IC 3906. This approach is currently a faster system and smaller than other implementations. However, this implementation is expensive due to the high cost of digital isolator 3904.

Referring now to fig. 40, an implementation of an embodiment where an isolated gate driver 4002 is used to voltage isolate the PWM controller 4004 from the power FET circuitry 4006 is illustrated. The isolated gate driver 4002 combines the digital isolator and the gate driver into a fast, integrated, low cost isolated gate driver. This provides some basic benefits for the isolated circuitry. First, the cost is substantially less because only a single IC must provide isolation rather than the two chips discussed in fig. 39. Furthermore, a single isolated gate driver IC will have lower delay than the implementation discussed in fig. 39, because the digital isolator 3904 of fig. 39 uses a major portion of its delay when the signal driving the digital isolator chip 3904 is off. This requirement is eliminated in an integrated solution where the isolator and the gate driver are on the same chip.

The general structure of the integrated isolator and gate driver of the present disclosure is illustrated in fig. 41. The structure comprises the isolation structure described above and further comprises a gate driver having said isolation structure. The isolated gate driver includes a NAND gate 4102. NAND gate 4102 is connected to receive data transmitted over the isolation link. In this case, the data includes a control signal from the PWM controller. NAND gate 4102 is additionally connected to receive RF signals. The RF output of NAND gate 4102 is connected to the input of inverter 4104. The output of inverter 4104 is connected to a first transformer 4106. Transformer 4106 electromagnetically couples the provided PWM controller signal to a second transformer 4108. The output of the second transformer 4108 is connected to a receiver and detector circuit 4110 which may be constructed in any of the ways discussed above. The output of the receiver and detector circuit 4110 is provided to the input of an inverter amplifier 4112, the inverter amplifier 4112 being connected to a gate driver 4114 that drives a connected power transistor.

Referring now to fig. 42, two separate dies 4202 and 4204 integrated on a single package 4206 providing integrated digital isolators and gate drivers are illustrated. In the previous embodiment of the digital isolator, die one 4202 and die two 4204 were implemented in 0.25 μm cmos technology. The 0.25 μm CMOS technology needs to process the 2.1GHz RF carrier signal provided at NAND gate 4102 of fig. 41. However, power MOSFET gate driver ICs typically have to be driven between 10V to 20V. High voltage transistors capable of supporting these voltage ranges are not available in.25 μm CMOS processing. Therefore, an 18V CMOS process using high voltage NMOS and PMOS transistors to provide 0.35 μm, 3.3V CMOS logic transistors must be used when implementing the circuitry within die 4202 and 4208. Using this process, it is possible to integrate a 10-20V gate driver using high voltage transistors operating in the 18V range, and an RF receiver using.35 μm logic transistors operating in the 3.3V range.

Referring now to fig. 43, a more detailed description of the circuitry implementing the isolated gate driver IC is provided. As previously described, the NAND gate 4302 is connected to receive the data stream from the PWM controller and an RF carrier signal. The output of NAND gate 4302 is connected to the gate of transistor 4302 and to the input of inverter 4304. The output of the inverter 4304 is connected to the gate of the transistor 4306. The drain/source path of the transistor 4306 is connected between the transformer 4306 and ground. The source/drain path of transistor 4302 is connected between 3.3V and transformer 4306.

The transformer 4310 of the isolated link is a center-tapped transformer. The output of transformer 4310 is connected to separate the inputs of differential amplifier circuit 4312. The output of the differential amplifier circuit 4312 is connected to a capacitor 4314. The other side of the capacitor 4314 is connected to the parallel connection of an inverter 4316 and a resistor 4318. The other side of the parallel connection of the inverter 4316 and the resistor 4318 is connected to another capacitor 4320. The capacitor 4320 is also connected to a detector circuit 4322 that detects the PWM control signal provided by the PWM controller via the isolated link. A regulator 4324 is connected between the 18V power supply and the detector 4322. The circuitry between comparator circuit 4312 up to and including detector circuit 4322 operates on a 3.3V supply. The remaining circuitry operates using an 18V power supply and includes level shifting circuitry 4326 with an input connected to the output of detector circuit 4322 and an output connected to driver 4314. The level shift circuit 4326 increases the voltage level of the detected PWM control signal to a voltage level capable of operating the driver 3914. The output of driver 3914 would then be connected to the power FET transistor.

Referring now to FIG. 44, a more detailed description of the level shifter circuit 4326 is illustrated. An input supplied from the detector 4322 to the level shifter 4326 is connected to the first inverter 4402. An output of the inverter 4402 is connected to an input of the second inverter 4404 and to a gate of the transistor 4406. An output of the inverter 4404 is connected to a gate of the transistor 4408. The source/drain path of transistor 4408 is connected between node 4410 and ground. The transistor 4412 has its source/drain path connected between the 18V system power supply and the node 4410. The gate of the transistor 4412 is connected to the node 4414. Also connected to node 4414 is transistor 4416. The source/drain path of transistor 4416 is connected between the 18V system power supply and node 4414. A 50 μ a current source 4418 is connected between node 4414 and ground. The transistor 4420 has its source/drain path connected between the 18V system power supply and the node 4422. The gate of the transistor 4420 is connected to the node 4410. The transistor 4424 has its source/drain path connected between the node 4422 and ground. The gate of the transistor 4424 is connected to the node 4410. The transistor 4430 has its source/drain path connected between the 18V system power supply and the node 4410. The gate of transistor 4430 is connected to the drain of transistor 4432 at node 4434. The source/drain path of transistor 4432 is connected between the 18V system power supply and node 4434. The gate of transistor 4432 is connected to node 4414. Transistor 4406 has its source/drain path connected between node 4434 and ground. The series of inverters 4440 will have their inputs connected to node 4422 and their outputs connected to driver 3914.

Referring now back to fig. 40, in addition to providing PWM control signals to drivers located on opposite sides of isolation barrier 4020, the output voltage V is indicated_outMust be read from V_outProvided back to the PWM controller 4016 via the isolation barrier 4020. Since the output voltage is on the secondary side and the PWM controller 401b is on the primary side, high voltage isolation is again required. The output voltage must be accurately measured (typically with less than 1% error) and sent as a feedback signal across isolation barrier 4020.

The most common prior art method of isolating the feedback signal provided to the PWM controller 4016 is illustrated in fig. 45. This method uses an optical isolator 4502. Comprising a connection to V_outA voltage divider circuit of a resistor 4504, which is coupled to node 4506, and a second resistor 4508, which is coupled between node 4506 and ground, is coupled to a first input of an operational amplifier 4510. The second input of the operational amplifier 4510 is connected to generate the voltage V_REFReference voltage generator 4512. The operational amplifier 4510 generates an error voltage VE applied to an input of the driver 4514 based on the comparison. The output of driver 4514 is connected to optical isolator 4502, which includes light emitting diode 4516 and light detecting transistor 4518. The output of the optical isolator 4502 is connected to provide a feedback voltage V_FBTo the detector circuit 4520 of the PWM controller 4016. The problem with the implementation illustrated in FIG. 45 is that of simulating optical isolationThe 4502 is typically slow (i.e., one to ten microseconds of delay time) and temperature variations will affect the error signal V_E。

Referring now to fig. 46, an alternative embodiment of an isolated voltage sensing method is illustrated. In this solution, the voltage sensing process is voltage isolated by an integrated IC package comprising two dies. An RF digital isolator is used to transmit data across the isolation barrier. A voltage divider comprising resistors 4602 and 4604 enables an output voltage to be measured and provided to a first input of operational amplifier 4606. A first resistor 4602 is connected at V_OUTAnd node 4608. A second resistor 4604 is connected between node 4608 and ground. A capacitor 4610 is connected between node 4608 and the output of operational amplifier 4606. A second input of the operational amplifier 4606 is connected to the reference voltage generator 4612.

Reference voltage generator 4612 is programmed via a digital trim memory. The reference voltage would need to be trimmed to meet the 0.5% accuracy necessary to measure the output voltage. This can be performed at IC test time by using one-time programmable (OTP) nonvolatile memory. In the preferred embodiment this may be 32-bit memory available from TSMC. The output of operational amplifier 4606 provides a voltage error signal V_EWhich is applied to the input of a/D converter 4616. Voltage error signal V_EServing as a voltage feedback signal on the primary side. The output of a/D converter 4616 is provided as a 6-bit digital output to a transmitter/data encoding circuit 4618, where the voltage error signal is encoded and transmitted. The output of transmit/data encoding circuitry 4618 is a single-bit serial output that is output via the RF isolation link described hereinabove.

Data recovery circuit 4620 receives data from the RF isolation link and recovers the voltage error signal as described above. This signal is provided to a digital-to-analog converter 4622. The output of the digital-to-analog converter 4622 is provided as a voltage feedback signal V_FBAs an output voltage V on the secondary side by the PWM controller_outThe indication of (2) is used. The speed and resolution of the analog-to-digital converter 4616 and the digital-to-analog converter 4622 are the loop bandwidth and the inputA function of the error requirement is derived. A 10MHz 6 bit ADC is sufficient for PWM frequencies up to 1.5 MHz. However, an ADC with a lower speed may be used, since most of the loop bandwidth is much lower.

Referring now to fig. 47, an integrated chip including two isolated gate drivers and an isolated voltage sensing function is illustrated. This component will integrate many of the components in the switching power supply and provide isolation between the primary and secondary sides for these functions. Signals a _ IN and B _ IN are provided to inputs 4702 and 4704 and are provided as signals a _ DRV and B _ DRV at output pins 4706 and 4708. The single integrated chip will receive the PWM controller signals at input pins 4702 and 4704 and provide an output signal on the secondary side that drives the power transistors associated with the switching power supply. The input and output are isolated from each other according to the system described hereinabove. Alternatively, the output voltage may be sensed at a connection to V_OUTAnd a voltage feedback pin V connected to the PWM controller_FB4712. The isolation of the voltage sensing function between the primary side and the secondary side is performed in the same way as described above. Thus, the integrated device 4700 described with respect to fig. 47 will provide isolation of the driver on the primary or secondary side of the switching power supply from the PWM controller and provide isolation voltage sensing of the secondary or primary side from the PWM controller.

One problem with RF isolators such as those described above is the radiated emissions caused by the use of an RF carrier to transmit data. The FCC mandates that the radiation emission from the device must be less than 500 μ V per meter at 3 meters. The use of balanced driver circuits may help reduce emission levels. However, there is no shielding and when a half-wave dipole antenna PCB layout is used (worst case), the emission from the RF isolator will be about 500 μ V per meter per channel. Thus, a four-channel RF isolator may have up to 2mV emissions per meter, which in the worst case would violate FCC regulations. This situation is illustrated in fig. 48a and 48b, where a single RF frequency of 2.1GHz is used to transmit data via the RF isolator. The single frequency usage causes the 2.1GHz emission peak to appear in the spectral emission of the RF isolator.

One way to greatly minimize radiated emissions is to use an RF carrier that changes frequency over time. Thus, rather than transmitting using a single carrier at 2.1GHz, the circuitry used to generate the RF carrier signal is modified so that the oscillator constantly oscillates between, for example, 2.1GHz and 2.2 GHz. This is more fully illustrated in fig. 49a and 49 b. Fig. 49a illustrates how the RF carrier signal swings between 2.1GHz and 2.2GHz at sixteen levels. Thus, at any particular time, rather than just a single frequency being used as an RF carrier, any one of sixteen frequencies may be provided to transmit data via an RF isolation link. Thus, rather than having a single peak transmission spectrum of 2.1GHz as shown in FIG. 48b, a transmission spectrum such as that shown in FIG. 49b is provided in which sixteen separate peaks are provided between 2.1GHz and 2.2 GHz. The average peak at any one frequency is significantly smaller than the average peak of the emission spectrum using only a single RF frequency.

It is possible to use analog or digital wobble. The preferred embodiment uses digital wobble because it is easier to implement. By using sixteen levels between 2.1GHz and 2.2GHz, the transmit level of the isolator is reduced by sixteen levels. Since the FCC sees a 1MHz band, the hierarchy from 2.1GHz frequency to 2.2GHz frequency should be set larger than this. While the present disclosure has described the swing between 2.1GHz and 2.2GHz, it should of course be appreciated that the swing may be between any two frequencies. The number of stages may also be set higher to give further emission reduction from the isolator.

Referring now to fig. 50, a block diagram of a circuit providing a hierarchical RF carrier signal between 2.1 and 2.2GHz is illustrated. The slow ring oscillator 5002 generates a 50-60MHz oscillating signal that is provided to the frequency divider circuit 5006 via line 5004. The divider circuit 5006 utilizes the 50-60MHz signal provided by the slow oscillator 5002 to generate a four-bit control code that is used to drive the RF oscillator circuit 5010. The control codes generated by the frequency divider circuit 5006 are provided to the RF oscillator circuit 5010 via the four-wire bus 5008. The control code generated by divider circuit 5006 may include more than four bits, however, only four bits are provided to RF oscillator 5020 via four-wire bus 5008. The RF isolator circuit uses the four-bit code to generate a wobble signal between the first and second frequency levels and provides an output wobble signal from output 5012. Each of the 16 four-bit codes causes the generation of a different frequency between and including the first and second frequency levels. Using the circuit of FIG. 50, the RF carrier frequency will vary at 400-500KHz rates over sixteen frequencies spaced 2-4MHz apart, and will repeat at 50-63KHz rates.

The circuit of figure 50 uses a free slow (60-70MHz) ring oscillator 5002 to charge the RF carrier. This uses a very low current of about 50 μ amps. A slow ring oscillator 5002 is illustrated in fig. 52. The ring oscillator 5002 includes a plurality of inverters 5202 connected in series with each other. A series of five inverters 5202 are interconnected with each other and have a feedback loop connected from node 5204 to the input of inverter 5202 a. Inverter 5206 has its input connected to node 5204 and its output connected to inverter 5208. The output of inverter 5208 includes the output of ring oscillator 5002 which is provided to frequency divider circuit 5006. The Vdd of the slow oscillator 5002 is derived from a reference voltage having a large PTAT component. This keeps the oscillation frequency fairly stable over process and temperature.

Referring now to fig. 51, the RF oscillator circuit 5010 is more fully illustrated. The input of the RF oscillator circuit 5010 is connected to receive a four bit code from the frequency divider circuit 5006 of fig. 50. A four bit code is provided to the gates of the first and second sets of transistors 5102 and 5103 to turn the transistors on and off. Each of the four transistors in the bank 5102 has its source/drain path connected between the capacitor 5104 and ground. At the other end, each of the capacitors 5104 is connected to a node 5106. Each of the transistors 5103 has its source/drain path connected between the capacitor 5108 and ground. The other side of each of the capacitors 5108 is connected to the node 5110. An additional capacitor 5112 is connected between node 5106 and ground. A capacitor 5114 is also connected between node 5110 and ground.

Connected between nodes 5106 and 5110 is inductor 5116. The transistor 5118 is connected to the inductor 5116 at node 5110 and has its source/drain path connected between node 5110 and ground. The gate of the transistor 5118 is connected to the opposite end of the inductor 5116 at node 5106. Another transistor 5120 is connected to the inductor 5116 at node 5106. Transistor 5120 has its source/drain path connected between node 5106 and ground. The gate of transistor 5120 is connected to the opposite end of inductor 5116 at node 5110. Another transistor 5122 has its source/drain path connected between Vdd and node 5106. A gate of the transistor 5122 is connected to the node 5120. The last transistor 5124 has its source/drain path connected between Vdd and node 5110. The gate of transistor 5124 is connected to node 5106. An inverter 5126 is connected between the node 5106 and the output node 5012 of the RF oscillator 5010. In response to the control code applied to the first and second sets of transistors 5102 and 5103, the RF oscillator 5010 will generate a stepped RF carrier signal between the first and second selected frequencies at its output 5012 based on the values of the inductors and capacitors used in the circuit.

Referring now to fig. 53, an alternative embodiment of RF carrier generation circuitry is illustrated, wherein RF oscillator 5010 has its output connected to the input of frequency divider circuit 5302. Divider circuit 5302 generates a four bit code that is provided back to the RF oscillator via four bit bus 5304. The circuit depicted in fig. 53 has the advantage that it is synchronous. The rate of change of the RF frequency is locked to the RF carrier. However, the circuit includes a 2GHz divider circuit that requires approximately 1 milliamp of Vdd current.

A schematic diagram of this circuit is illustrated in fig. 54. The schematic diagram of fig. 54 is similar to that described with respect to fig. 51, and similar components are numbered in a similar manner. A four bit code is provided to the gates of the first and second sets of transistors 5102 and 5103 to turn the transistors on and off. Each of the four transistors in the bank 5102 has its source/drain path connected between the capacitor 5104 and ground. At the other end, each of the capacitors 5104 is connected to a node 5106. Each of the transistors 5103 has its source/drain path connected between the capacitor 5108 and ground. The other side of each of the capacitors 5108 is connected to the node 5110. An additional capacitor 5112 is connected between node 5106 and ground. A capacitor 5114 is also connected between node 5110 and ground.

Connected between nodes 5106 and 5110 is inductor 5116. The transistor 5118 is connected to the inductor 5116 at node 5110 and has its source/drain path connected between node 5110 and ground. The gate of the transistor 5118 is connected to the opposite end of the inductor 5116 at node 5106. Another transistor 5120 is connected to the inductor 5116 at node 5106. Transistor 5120 has its source/drain path connected between node 5106 and ground. The gate of transistor 5120 is connected to the opposite end of inductor 5116 at node 5110. Another transistor 5122 has its source/drain path connected between Vdd and node 5106. A gate of the transistor 5122 is connected to the node 5120. The last transistor 5124 has its source/drain path connected between Vdd and node 5110. The gate of transistor 5124 is connected to node 5106. An inverter 5126 is connected between the node 5106 and the output node 5012 of the RF oscillator 5010. In response to the control code applied to the first and second sets of transistors 5102 and 5103, the RF oscillator 5010 will generate a stepped RF carrier signal between the first and second selected frequencies at its output 5012 based on the values of the inductors and capacitors used in the circuit. The circuit additionally includes an inverter 5402 whose input is connected to node 5110. The output of the inverter 5402 is connected to a frequency divider circuit 5302 that provides a four-bit output to each of the transistor groups 5102 and 5103.

Referring now to fig. 55, a simulation of the RF isolated link result spectrum using stepped frequencies for the RF carrier signal as described above is illustrated. As can be seen, sixteen independent peaks are generated within the spectrum, with the average power of each peak being approximately-24 dB. This illustrates that the transmission can be spread over sixteen independent frequencies rather than focusing on a single frequency when a single RF carrier signal is used.

The circuits described in fig. 50 and 53 for generating a change in the frequency of the RF oscillator have the side effect of causing a tone in the transmitted spectrum if the isolator is used in an analog control loop, such as the switching control in a switching power supply. Referring now to FIG. 56, an embodiment is illustrated in which a random number generator is used to control the generation of a code that provides an RF frequency. A 50-60MHz ring oscillator 5602 provides an oscillation signal to a divide by 64 circuit 5604. The output of the frequency divider circuit 5604 is supplied as a clock input to the 10-bit linear shift register 5606. Linear shift register circuitWay 5606 may include a well-known Debruijn counter circuit that prevents the register from falling into an all zero state. The output of 10-bit shift register 5606 is provided as an input to NOR gate 5608. B from 10-bit shift register 5606₀Bit sum b₉The bit output is provided as an input to an exclusive or gate 5610. The output of the exclusive or gate 5610 and the output of the NOR gate 5608 are provided as inputs to the exclusive or gate 5612. The output of exclusive or gate 5612 is provided as a data input to 10-bit shift register 5606. RF oscillator circuit described with respect to FIG. 51 b having its input connected to 10-bit shift register 5606₀，b₁，b₂And b₃And (6) outputting. An RF oscillator circuit generates a stepped RF carrier signal in response to the 4-bit code input and an output RF carrier signal at output 5616.

Although the preferred embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the scope of the invention as defined by the appended claims.

Claims (20)

1. A circuit package, comprising:

a first unit comprising functional circuitry;

a second unit comprising functional circuitry; and

at least one RF isolation link interconnecting the first and second units, the RF isolation link providing voltage isolation between the first unit and the second unit, wherein the RF isolation link further provides data between the first unit and the second unit using an RF carrier signal, the RF carrier signal having a frequency that varies over time.

2. The system of claim 1, wherein the RF isolation link further comprises:

a first transformer on the first unit;

a second transformer on the second unit;

a transmitter associated with the first transformer for transmitting an RF carrier onto the RF isolation link;

a receiver associated with the second transformer for receiving an RF carrier on the RF isolation link; and

circuitry to generate an RF carrier signal having a frequency that varies over time.

3. The system of claim 2, wherein the circuitry that generates the RF carrier signal further comprises:

a slow ring oscillator;

a frequency divider circuit connected to the slow ring oscillator for generating a control code; and

an LC oscillator circuit responsive to a control code from the frequency divider circuit to generate an RF carrier signal, wherein the control code causes generation of one of a plurality of frequencies.

4. The system of claim 2, wherein the circuitry that generates the RF carrier signal further comprises:

an LC oscillator circuit for generating an RF carrier signal in response to a control code, wherein the control code causes generation of one of a plurality of frequencies; and

and a frequency divider circuit connected in a feedback loop with the LC oscillator for generating the control code.

5. The system of claim 2, wherein the circuitry that generates the RF carrier signal further comprises:

a slow ring oscillator;

a circuit for randomly generating a control code in response to an input from the slow ring oscillator; and

an LC oscillator circuit responsive to a randomly generated control code to generate an RF carrier signal, wherein the randomly generated control code causes generation of one of a plurality of frequencies.

6. The system of claim 5, wherein the circuitry further comprises:

a divider circuit for providing a clock signal;

a shift register providing a plurality of output bits in response to a clock signal and a data signal;

logic circuitry responsive to a first portion of the plurality of output bits to generate a data signal; and

wherein the randomly generated control code comprises a second portion of the plurality of output bits.

7. The system of claim 6, wherein the shift register further comprises a de Bruijn counter.

8. The system of claim 1, wherein the unit comprises a chip.

9. The system of claim 1, wherein the unit comprises a die on a chip.

10. A circuit package, comprising:

a first unit comprising functional circuitry;

a second unit comprising functional circuitry;

a first transformer on the first unit;

a second transformer on the second unit;

a transmitter associated with the first transformer for transmitting a stepped RF carrier signal onto an RF isolation link between the first unit and the second unit;

a receiver associated with the second transformer for receiving the stepped RF carrier signal on the RF isolation link; and

circuitry associated with the first unit for generating a stepped RF carrier signal, wherein the stepped RF carrier signal swings between a first frequency and a second frequency.

11. The system of claim 10, wherein the circuitry for generating a stepped RF carrier signal further comprises:

a slow ring oscillator;

a frequency divider circuit connected to the slow ring oscillator for generating a control code; and

an LC oscillator circuit responsive to a control code from the frequency divider circuit to generate a stepped RF carrier signal, wherein the control code causes generation of one of a plurality of frequencies from a first frequency to a second frequency.

12. The system of claim 10, wherein the circuitry for generating a stepped RF carrier signal further comprises:

a slow ring oscillator;

a circuit for randomly generating a control code in response to an input from the slow ring oscillator; and

an LC oscillator circuit responsive to a randomly generated control code to generate a stepped RF carrier signal, wherein the randomly generated control code causes generation of one of a plurality of frequencies from a first frequency to a second frequency.

13. The system of claim 12, wherein the circuitry further comprises:

a divider circuit for providing a clock signal;

a shift register providing a plurality of output bits in response to a clock signal and a data signal;

logic circuitry responsive to a first portion of the plurality of output bits to generate a data signal; and

wherein the randomly generated control code comprises a second portion of the plurality of output bits.

14. The system of claim 13, wherein the shift register further comprises a de Bruijn counter.

15. The system of claim 10, wherein the unit comprises a chip.

16. The system of claim 10, wherein the unit comprises a die on a chip.

17. A circuit package, comprising:

a first unit comprising functional circuitry;

a second unit comprising functional circuitry;

a first transformer on the first unit;

a second transformer on the second unit;

a transmitter associated with the first transformer for transmitting a stepped RF carrier onto an isolation link between the first unit and the second unit;

a receiver associated with the second transformer for receiving the stepped RF carrier on the isolated link;

a slow ring oscillator;

a divider circuit for providing a clock signal;

a shift register for providing a plurality of output bits in response to a clock signal and a data signal, a first portion of the plurality including a randomly generated control code;

logic circuitry responsive to a second portion of the plurality of output bits to generate a data signal; and

an RC oscillator circuit responsive to a randomly generated control code to generate a stepped RF carrier signal, wherein the stepped RF carrier signal swings between a first frequency and a second frequency, and the randomly generated control code causes the generation of one of a plurality of frequencies from the first frequency to the second frequency.

18. The system of claim 19, wherein the control code comprises a four-bit control code.

19. The system of claim 19, wherein the unit comprises a chip.

20. The system of claim 19, wherein the unit comprises a die on a chip.