HK1104390A - Phase locked loop with temperature compensation - Google Patents

Description

Phase locked loop with temperature compensation

Technical Field

The present invention relates to integrated circuits, and more particularly, to integrated circuits having annealed glass pastes disposed on a silicon wafer.

Background

Accurate frequency references are needed in a wide variety of electronic devices, such as cellular telephones and other handheld devices. Crystal oscillators are commonly used to provide accurate frequency references in these electronic devices. However, crystal oscillators have several inherent disadvantages, including being bulky, fragile, and costly. In addition, the size and cost of crystal oscillators are related to the resonant frequency, so that as the frequency increases, the size decreases, while the cost and fragility may increase rapidly. As the size of electronic devices continues to decrease, the use of crystal oscillators presents an increasing problem due to their size, fragility, and cost limitations.

Semiconductor oscillators are a poor alternative to crystal oscillators and are generally not suitable for use as accurate frequency references because their oscillation frequency varies too much, especially with temperature.

Disclosure of Invention

According to the present invention, there is provided an integrated circuit comprising: a temperature sensor that senses a temperature of the integrated circuit; a memory module that stores oscillator data relating to calibrations and selects one of the oscillator calibrations as a function of the sensed temperature; an oscillator module that generates a reference signal having a frequency; and a phase-locked loop module including a feedback loop having a feedback loop parameter, wherein the phase-locked loop module selectively adjusts the feedback loop parameter based on the selected one of the oscillator calibrations.

Drawings

FIG. 1 is a block diagram illustrating one aspect of a crystal oscillator emulator;

FIG. 2 is a table showing the relationship between temperature and correction factor;

FIG. 3 is a graph showing the relationship between temperature and correction factor;

FIG. 4 is a block diagram illustrating one aspect of a crystal oscillator emulator;

FIG. 5 is a two-dimensional view of one aspect of a crystal oscillator emulator connected to an external impedance;

FIG. 6 is a detailed block diagram of one aspect of a crystal oscillator emulator connected to an external impedance;

fig. 7A and 7B are diagrams showing a relationship between external impedance values and digital values;

FIG. 8 is a block diagram of one aspect of an oscillator assembly for generating an output having a periodic waveform;

FIG. 9 is a block diagram of one aspect of a spread spectrum generator;

FIG. 10 is a flow chart for simulating the operation of a crystal oscillator;

FIG. 11 is a block diagram of one aspect of a low power oscillator;

FIG. 12 is a block diagram of another aspect of a low power oscillator;

FIG. 13 is a functional block diagram of an integrated circuit including one or more circuits and a crystal oscillator emulator for generating clock signals for the one or more circuits;

FIG. 14 is a functional block diagram of an integrated circuit including a processor and a crystal oscillator emulator for generating a clock signal for the processor;

FIG. 15 is a functional block diagram of an integrated circuit including a processor and a crystal oscillator emulator for generating a clock signal for the processor and setting a clock rate using external components;

FIG. 16 is a functional block diagram of an integrated circuit including one or more circuits, a crystal oscillator emulator and a clock divider for generating clock signals at one or more other clock frequencies;

FIG. 17 is a functional block diagram of an integrated circuit including a processor, one or more circuits, a crystal oscillator emulator and a clock divider for generating clock signals at other clock frequencies;

FIG. 18 is a functional block diagram of an integrated circuit including a processor, a graphics processor, one or more circuits, a memory, and a crystal oscillator emulator that generates a clock signal;

FIG. 19 is a functional block diagram of an integrated circuit including a processor and the low power oscillator of FIG. 11;

FIG. 20 is a functional block diagram showing an integrated circuit encapsulated in a prior art encapsulation material;

FIG. 21 is a functional block diagram illustrating an integrated circuit with a temperature compensated semiconductor-on-chip oscillator encapsulated in a packaging material having low dielectric loss in accordance with the present invention;

FIG. 22 illustrates in more detail one exemplary implementation of the integrated circuit package of FIG. 21;

FIG. 23 is a side cross-sectional view of another integrated circuit package including a semiconductor-on-chip oscillator according to the present invention;

FIG. 24 is a side cross-sectional view of another integrated circuit package including a semiconductor-on-chip oscillator according to the present invention;

FIG. 25 is a flat cross-sectional view showing the integrated circuit package of FIG. 24 in greater detail;

FIG. 26 is a functional block diagram illustrating tuning of a capacitor of an on-chip semiconductor oscillator based on temperature compensation;

FIG. 27 is a functional block diagram of a fractional Phase Locked Loop (PLL) including a temperature compensation input;

FIG. 28 is a functional block diagram of a Delta-Sigma fractional phase-locked loop including a temperature compensation input;

FIG. 29 is a flowchart showing steps for measuring sample calibration points and using a linear curve fitting algorithm to generate calibration data between the sample calibration points;

FIG. 30 is a flowchart showing steps for measuring sample calibration points and using a higher order curve fitting algorithm to generate calibration data between the sample calibration points;

FIG. 31A is a functional block diagram of a hard disk drive;

FIG. 31B is a functional block diagram of a Digital Versatile Disk (DVD);

FIG. 31C is a functional block diagram of a high definition television;

FIG. 31D is a functional block diagram of a vehicle control system;

FIG. 31E is a functional block diagram of a cellular telephone;

FIG. 31F is a functional block diagram of a set-top box;

FIG. 31G is a functional block diagram of a media player;

FIG. 32A is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer formed on at least a portion of a silicon wafer;

FIG. 32B is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer formed on at least a portion of a silicon wafer and a layer of conductive material formed on at least a portion of the annealed glass paste and/or epoxy layer;

FIG. 32C is a side cross-sectional view of another integrated circuit package including spaced apart annealed glass paste layers formed on selected portions of a silicon wafer;

FIG. 32D is a side cross-sectional view of another integrated circuit package including spaced apart annealed glass paste and/or epoxy layers and a layer of conductive material formed on selected portions of a silicon wafer;

FIG. 33A is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer and a conductive material layer adjacent to the circuitry of a silicon wafer;

FIG. 33B is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer and a conductive material layer adjacent to an oscillator of a silicon wafer;

FIG. 33C is a side cross-sectional view of another integrated circuit package including an annealed glass paste and/or epoxy layer and a conductive material layer adjacent to an inductor of a silicon wafer;

FIG. 33D is a side cross-sectional view of another integrated circuit package including a layer of annealed glass paste and/or epoxy and a layer of conductive material adjacent to an inductor in an oscillator circuit of a silicon wafer;

fig. 34A-34D are side cross-sectional views of another integrated circuit package including a glass or silicon layer establishing an air gap and an annealed glass paste and/or epoxy portion;

FIGS. 35A-35B are side cross-sectional views of another integrated circuit package including a C-shaped glass or silicon layer creating an air gap;

FIGS. 36A-36C are side cross-sectional views of a wafer including a plurality of integrated circuit packages including a glass or silicon layer establishing an air gap and an annealed glass paste and/or epoxy portion;

FIGS. 37A-37B are side cross-sectional views of an integrated circuit package including an annealed glass paste and/or epoxy portion that has been coated with a conductive material; and

fig. 38 illustrates exemplary steps of a method for fabricating the integrated circuit package of fig. 32A-32D.

Like reference symbols in the various drawings indicate like elements.

Detailed Description

FIG. 1 illustrates one aspect of a crystal oscillator emulator 10 for generating an output signal 12 having a precise frequency. The crystal oscillator emulator 10 may be constructed on a single semiconductor die using any process, including a Complementary Metal Oxide Semiconductor (CMOS) process.

The crystal oscillator emulator 10 may include a semiconductor oscillator 14 for generating the output signal 12. Any type of semiconductor oscillator may be used, including LC oscillators, RC oscillators, and ring oscillators. The semiconductor oscillator 14 comprises a control input 16 for varying the frequency of the output signal. The control input 16 may be any electrical input that effects a controlled change in the frequency of the output signal, such as the supply voltage of a ring oscillator and the voltage input to the varactor diode of an LC oscillator.

The non-volatile memory 18 includes calibration information 20 for controlling the frequency of the output signal as a function of temperature. Any type of non-volatile memory may be used, including Content Addressable Memory (CAM). The calibration information 20 may include a correction factor to be provided to the control input 16 of the semiconductor oscillator 14 to control the output signal frequency. The calibration information 20 may be a function of the temperature change from the calibration temperature to the operating temperature, or may be a function of the absolute temperature.

The temperature sensor 22 may sense the temperature of the semiconductor die. Preferably, the temperature sensor is located on the semiconductor die in the vicinity of the semiconductor oscillator 14. Any type of temperature sensor 22 may be used, including thermistors and infrared detectors. The temperature sensor 22 may be configured to measure a change in temperature relative to a baseline temperature or a current temperature.

Fig. 2 illustrates a storage technique 30 for storing the calibration information 20 in the non-volatile memory 18. The storage technique 30 may be any form of database including a CAM, an indexing scheme, a lookup table, and a hash table.

FIG. 3 shows a series of exemplary graphs 32 of correction factor values versus temperature for maintaining a constant output signal frequency of the crystal oscillator emulator 10. The data used to construct the curves can be obtained in any manner, including device-level testing and batch mode testing.

An exemplary device level test may include testing each device to determine a correction factor to be applied to the semiconductor oscillator to maintain the output frequency constant with temperature variations. In one approach, the baseline value of the semiconductor oscillator control input is determined for a predetermined frequency and over a predetermined temperature (e.g., a minimum operating temperature) of a semiconductor die of the device. The baseline value may be measured directly or interpolated from measurements of another device characteristic. A baseline value may also be measured for each potential output frequency. Also, the baseline value for each potential output frequency may be extrapolated from the baseline value for the predetermined frequency, for example, by using known circuit relationships. The baseline value for each potential output frequency may be stored as an absolute value or as a ratio, frequency factor to calculate multiple baseline values from a single baseline value.

Subsequently, the temperature of the semiconductor die is raised in a plurality of discrete steps from about the lowest operating temperature to about the highest operating temperature. The number of discrete steps is preferably limited to about 6 temperature levels to reduce testing costs, but any number of discrete steps may be used. Preferably, an on-chip heater is used to heat the semiconductor die, but any means of changing the temperature of the semiconductor die may be employed. At each discrete step, the semiconductor die temperature and a correction factor for maintaining the output at a constant frequency may be measured.

The correction factor is preferably a ratio that is applied to the baseline value to obtain an adjusted value of the control input. The correction factor may vary according to any baseline value (e.g., 1). Preferably, a correction factor is calculated for each temperature step, so that it is applied to the semiconductor oscillator to maintain the output signal at any one of a number of predetermined frequencies. For example, if a correction factor of 1.218 is determined to correspond to a temperature change of 45 ℃, the control input of the semiconductor oscillator may be adjusted as a function of the correction factor, for example, by changing the control input in proportion to the correction factor. In another alternative, the correction factor may be applied to a baseline value corresponding to the desired output frequency to generate a calibrated value with the control input adjusted. In another alternative, the correction factor may be measured corresponding to each of several output frequencies at each temperature step.

Batch mode testing of the crystal oscillator emulator 10 to obtain the calibration information 20 may advantageously reduce costs by reducing the number of measurements on a batch of semiconductor die. In batch mode testing, test results for a subset of the crystal oscillator emulators 10 from the same batch of semiconductor die may be used for all devices in the batch. The subset tested in the crystal oscillator emulator may range from one to any proportion of the total number of devices. For example, a single crystal oscillator emulator 10 may be tested and the resulting batch calibration information stored in each device in the batch. In addition, each crystal oscillator emulator 10 may be tested for a subset of calibration information (e.g., output frequency at baseline temperature). A subset of the device-specific calibration information may be used to modify the batch calibration information stored in each device.

Fig. 4 illustrates another aspect of the crystal oscillator emulator 40. The corresponding elements of the crystal oscillator emulator 40 numbered in the range 40-52 are functionally similar to the crystal oscillator emulator 10, but the crystal oscillator emulator 40 may also include one or more heaters 54, controllers 56, and select inputs 58, either alone or in combination.

A heater 54 may be located near the semiconductor oscillator 44 on the semiconductor die to provide a localized heat source. Any type of heater 54 may be used, including transistor heaters and resistive heaters. The heater 54 may operate in response to input from the temperature sensor 52 to control the temperature of the semiconductor die. The heater 54 may increase the temperature of the semiconductor die to a level corresponding to one of the temperature levels for which the correction factor has been determined. In addition, the crystal oscillator emulator 40 may be enclosed with an encapsulation having a high thermal impedance.

In one case, the heater 54 may increase the temperature of the semiconductor die to a maximum operating temperature. Here, only the correction factor corresponding to the highest operating temperature has to be determined during device or batch level testing, thereby reducing costs.

The heater 54 may also be controlled to raise the temperature of the semiconductor die to one of several predetermined temperature levels for which correction factors have been determined. The second temperature sensor may sense an external temperature, such as an ambient temperature or a component temperature. The heater 54 may then increase the semiconductor die temperature to the temperature nearest the predetermined temperature level while continuously changing the control input during the temperature jump using the extrapolated value calculated from the correction factor.

The controller 56 may add additional functionality, such as by controlling the heater 54 in response to multiple temperature sensors or manipulating the calibration information 50 to derive a value for a control input corresponding to an intermediate temperature. The controller 56 may be any type of entity including a processor, logic circuits, and software modules.

Select input 58 may be used to select a particular output frequency from a range of output frequencies. The output frequency may be selected as a function of the impedance of the external component connected to the select input. The external component may be used directly as part of the semiconductor oscillator to select the output frequency or may be used indirectly to select the output frequency, for example the selection of an impedance value within a predetermined range may correspond to a predetermined output frequency. The external component may be any component, but it is preferably a passive component such as a resistor or a capacitor.

Fig. 5 illustrates one aspect of a crystal oscillator emulator 100, the crystal oscillator emulator 100 having, for example, two select pins 102 and 104 for connection to two external impedances 106 and 108. One or more pins may be used to interface to external components. The crystal oscillator emulator 100 detects or retrieves information from external components connected to the select pins 102 and 104. The retrieved information may have three or more predetermined level ranges corresponding to the selected simulator characteristic levels. For example, a single pin connected to an external resistor may be used to select any one of the 16 output frequency levels. The resistance of the external resistor is preferably selected to be one of 16 predetermined standard values. Each of the 16 resistance values corresponds to one of the 16 output frequency levels. In addition, low precision passive components are preferably used as external components to reduce cost and inventory. Each external component may have a plurality (N) of predetermined nominal values, where each predetermined nominal value corresponds to a selection of one of the predetermined characteristic levels. If one pin is used, N different characteristic levels may be selected. If two pins are used, then N x N different feature levels may be selected, and so on. The types of device characteristics that may be selected include, for example, output frequency, frequency tolerance, and baseline correction factors. For example, the crystal oscillator emulator 100 may have a select pin 102 connected to an external resistor, which may have a nominal value selected from the group of 16 predetermined values. Each of these 16 predetermined values has a range of measurement values corresponding to one of 16 predetermined output frequency levels, which may range from 1MHz to 100 MHz.

The external impedances 106 and 108 are preferably resistors, capacitors, or a combination of resistors and capacitors, but may be any component that behaves primarily as an inductance, a resistance, a capacitance, or a combination thereof. The external impedances 106 and 108 may be connected to the pins 102 and 104 directly or indirectly from any energy source (e.g., Vdd and ground) or any suitable reference. For example, the external impedance 106 may be connected to Vdd through a resistor/transistor network and to the select pin 102 through a capacitor network.

The crystal oscillator emulator 100 may determine a predetermined select value corresponding to a measured value of the impedance connected to the select pin. Preferably, the impedance is selected to have a standard value (e.g., a nominal resistance value) corresponding to a resistor with a tolerance of 10% (e.g., 470, 560, 680.) to reduce device and inventory costs. To account for measurement tolerances and tolerances of the external impedance, the range of impedance values may correspond to a single selected value. The selection value is preferably a digital value, but may also be an analog value. For example, a measured resistance value from 2400 ohms to 3000 ohms may be associated with a digital value corresponding to 2. And the measured resistance values from 3001 ohms to 4700 ohms may be associated with a digital value corresponding to 3. The measured resistance includes variations due to the external impedance and tolerances of the internal measurement circuitry. The measured impedance at each select pin is used to determine a corresponding digital value. The range of digital values may include 3 or more digital values, and a preferred range is 10 digital values to 16 digital values per select pin. The numerical values corresponding to each select pin may be used in combination to describe a memory address. For example, a device with three select pins, each for interfacing to an impedance value mapped to one of 10 digital values, may describe 1000 memory addresses or lookup table values. The contents of the memory locations corresponding to the memory addresses are used to set the value of the output or internal characteristics of the device. Another exemplary device may include two select pins, where each select pin is assigned an external impedance that interfaces to a digital value that is mapped to a range of 10 values. The digital value combinations may describe 1000 memory addresses or lookup table values, where each memory address or lookup table value may contain data for setting the characteristics of the crystal oscillator emulator 100.

FIG. 6 illustrates a block diagram of one aspect of a crystal oscillator emulator 120. The crystal oscillator emulator 120 includes a selection pin 122 for interfacing to an external impedance 124 that is used to select the configuration of the crystal oscillator emulator 120. The external impedance 124 is similar in function and extent to the external impedances 106 and 108.

A measurement circuit 126 connected to the select pin 122 measures the electrical characteristic as a function of the external impedance 124. For example, a current may be provided to the external impedance, and the voltage developed across the external impedance 124 may then be measured. Also, a voltage may be applied to the external impedance 124 and then the current measured. Any measurement technique for measuring passive components may be used to measure electrical characteristics, including dynamic and static techniques. Exemplary measurement techniques include timing circuits, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs). Preferably, the measurement circuit has a high dynamic range. The measurement circuit 126 may generate an output whose value corresponds to the value of the external impedance 124. The output may be digital or analog. The same output value preferably represents a range of external impedance values to compensate for variations in values due to process, temperature, power, etc., such as tolerances in external impedance values, interconnect losses, and measurement circuit tolerances. For example, all measured external impedance values ranging from greater than 22 ohms to 32 ohms may be correlated to a digital output value of "0100". While all measured external impedance values ranging from greater than 32 ohms to 54 ohms may be correlated to a digital output value of "0101". The actual external impedance values are a subset of the measured external impedance values to account for variations in values. For example, in the above case, the actual external impedance value may be from 24 ohms to 30 ohms, and from 36 ohms to 50 ohms. In each case, an inexpensive low-precision resistor can be selected, with a resistance value in the middle of the above-mentioned range, for example 27 ohms and 43 ohms. In this way, inexpensive low-precision components can be used to select from a range of high-precision outputs. The selection value may be used directly as a variable value to control the device characteristics of the crystal oscillator emulator 120. The variable value may also be determined indirectly from the selection value.

The memory circuit 127 may include a variable value that may be selected as a function of the selection value. The memory circuit 127 may be any type of memory structure including content addressable memory, static and dynamic memory, and look-up tables.

For the case where the output values generated by the measurement circuit 126 have a one-to-one correspondence with the external impedance values, the digital value determiner 128 may then set the output values to selected values corresponding to a range of external impedance values.

Fig. 7A illustrates the relationship of a set of impedance values 150 and an associated selection value 154. The set of impedance values 150 can have a one-to-one correspondence with the set of digital output values 152, and the set of digital output values 152 is converted into a selection value 154 associated with each of the set of impedance values 150. Impedance values ranging from a minimum impedance value to a maximum impedance value are divided into three or more groups, where each group has a nominal impedance. The nominal impedance values of each group may be selected such that there is some separation between the nominal impedance values. Here, the nominal values of the set of impedance values are 27 ohms and 43 ohms with a 16 ohm separation. The spacing between sets of impedance values is preferably based on a geometric progression, but any mathematical relationship may be used to establish the inter-set spacing, such as logarithmic, linear, and exponential. The spacing between impedance groups may be based on any impedance value in the group, including nominal, average, median, starting, and final values. Factors that affect the selection of the impedance range and spacing of the groups may include various tolerances, such as tolerances of the external impedance, tolerances of the internal voltage and current sources, and tolerances of the measurement circuitry. Tolerances may be caused by process, temperature and power variations, for example.

Fig. 7B shows the relationship between the range of impedance values 156 and the associated selection value 158. The range of impedance values 156 has a direct correspondence with the selection value 158. Impedance values ranging from a minimum impedance value to a maximum impedance value are divided into three or more groups, where each group has a nominal impedance. The nominal impedance values of each group may be selected to have a certain spacing between the nominal impedance values. Here, the nominal values of the set of impedance values are 27 ohms and 43 ohms with a 16 ohm separation. This direct correspondence between the range of impedance values 156 and the associated selection value 158 may be achieved using, for example, a non-linear analog-to-digital converter (not shown).

Referring back to fig. 6, address generator 130 may determine a memory location corresponding to a digital output value associated with an external impedance connected to a select pin. The memory locations may be combined in any manner, such as a list for a single select pin, a look-up table for two select pins, and a three-level table for three select pins.

The controller 132 may set the device characteristics of the crystal oscillator emulator 120 as a function of the variable values. The variable value may be generated directly by the measurement circuit, determined indirectly from the select value, and determined from the contents of the memory location corresponding to the external impedance value connected to the select pin.

The select pin 122 may also be used to implement additional functions such as reduced Power (PD), power enable, mode select, reset, and synchronous operation. In this regard, the select pin 122 becomes a multi-purpose select pin 122 for configuring the crystal oscillator emulator 120 and for implementing additional functionality.

In one aspect, a first range of impedance values connected to the multi-purpose select pin 124 may be used to configure the crystal oscillator emulator 120, while operation of the additional function may be controlled by a voltage or current applied to the multi-purpose select pin 124 or an impedance value outside the first range of impedance values.

Fig. 8 illustrates one aspect of an oscillator assembly 200 for generating an output having a periodic waveform. The oscillator assembly 200 includes a crystal oscillator emulator 202 for driving a Phase Locked Loop (PLL) 204. The crystal oscillator emulator 202 may be similar in function and structure to various aspects of the crystal oscillator emulator described above. The oscillator assembly 200 may include any type of PLL204, such as a digital PLL and an analog PLL.

The multi-purpose select pins 206 and 208 may be used to select operating parameters of the PLL204, such as a frequency division factor. The multi-purpose select pins 206 and 208 may also be used for control and operation of the crystal oscillator emulator 202, such as output frequency selection and reference clock reception for calibration. External resistors 210 and 212 may be connected to the multi-purpose select pins 206 and 208 to select the operating frequency. The range of values of external resistors 210 and 212 corresponds to the selection of different operating frequencies. Each external resistor 210 and 212 may be used to select one of 16 predetermined operating frequencies. In combination, the external resistors 210 and 212 may be selected from 256 operating frequencies. To control multiple functions, each of the multi-purpose select pins 206 and 208 may receive signals in different voltage ranges. For example, one multi-purpose select pin 206 may be connected to an external resistor 210, a voltage ranging from 0 to 2 volts may be applied across the external resistor 210 to determine resistance, and the multi-purpose select pin 206 may also receive a reference clock signal operating in the range of 2 to 3 volts. The decoder 214 may detect the signals on the multi-purpose select pins 206 and 208.

Fig. 9 shows a spread spectrum oscillator 300 for generating an output signal having a variable frequency. The spread spectrum oscillator 300 includes a crystal oscillator emulator 302 connected to a PLL 304. A frequency control device coupled to the crystal oscillator emulator 302 may dynamically control the output frequency of the crystal oscillator emulator 302. The frequency control device may be any device or technology, including a varactor, that controls a bias current source of the semiconductor oscillator and controls a control input voltage applied to a resonant capacitor of the semiconductor oscillator.

FIG. 10 illustrates operation of an aspect of a crystal oscillator emulator. In block 400, a semiconductor oscillator is used to generate an output signal having a periodic waveform. Continuing to block 402, the semiconductor oscillator may be calibrated to generate a constant frequency over a predetermined temperature range. In one aspect, the calibration may include varying the temperature of the semiconductor die over a predetermined temperature range and measuring calibration information for maintaining a constant output frequency. The die temperature may be measured near the semiconductor oscillator. The calibration information may include a relationship between control input values and die temperature for maintaining a constant output frequency. The calibration information may be stored in non-volatile memory on the semiconductor die. At block 404, the operating frequency may be determined by probing external components. Continuing to block 406, the semiconductor oscillator generates an output signal having an operating frequency. At block 408, a temperature of the semiconductor die is determined in proximity to the semiconductor oscillator. Continuing to block 410, the semiconductor die may be heated or cooled to control the die temperature to one or more predetermined temperature levels. At block 412, the control input may be controlled as a function of the die temperature to compensate for changes in the operating frequency of the output signal caused by temperature changes. The stored calibration information may be used to control the input. The calibration information may be used directly for die temperatures corresponding to stored temperatures. For other die temperatures, the control input values may be extrapolated from stored calibration information. Continuing to block 414, the frequency of the output signal may be dynamically changed as a function of the frequency control signal.

Fig. 11 illustrates one aspect of a low power oscillator 320 for generating a periodic signal. The low power oscillator 320 includes a crystal oscillator emulator 322 for calibrating an active silicon oscillator 324. The crystal oscillator emulator 322 is normally in an off state to reduce power consumption. At predetermined intervals, the crystal oscillator emulator 322 is switched to a powered on state to calibrate the active silicon oscillator 324. The active silicon oscillator 324 consumes less power than the crystal oscillator emulator 322, so operating the active silicon oscillator 324 continuously and operating the crystal oscillator emulator 322 only intermittently reduces the overall power consumption of the low power oscillator 320. Any type of active silicon oscillator may be used, including ring oscillators and RC oscillators. The crystal oscillator emulator 322 may be configured in accordance with any of the aspects of the invention described and illustrated in this specification.

Summer 326 may determine the frequency error between the active silicon oscillator output and the crystal oscillator emulator output. The controller 328 may generate a control signal to control the frequency of the active silicon oscillator 324 based on the frequency error. The controller 328 may also receive temperature information from the crystal oscillator emulator 322. The temperature information may include temperatures such as the temperature of the semiconductor and the ambient temperature. The controller 328 may include calibration information for the active silicon oscillator 324 similar to the calibration information for the crystal oscillator emulator 322. The frequency error may be used to set an initial value for the control signal and then the temperature information, in combination with the active silicon oscillator calibration information, may be used to update the control signal when the crystal oscillator emulator 322 is powered down. In one aspect, the temperature sensing circuit of the crystal oscillator emulator 322 may be continuously powered up so that continuous temperature information may be provided to the controller 328. The control signal 334 may be digital or analog. If the control signal is digital, a digital-to-analog converter (DAC)330 may convert the control signal to analog.

The regulator 332 may control the power supply of the active silicon oscillator 324 to adjust the operating frequency in response to the control signal 334. The supply of voltage and/or current to the active silicon oscillator 324 may be controlled. For example, regulator 332 may control the voltage level of the power supply voltage.

In operation, the active silicon oscillator 324 is normally in an on state to generate a periodic output signal. The crystal oscillator emulator 322 is normally in an off state. In the off state, all or a portion of the crystal oscillator emulator 322 may be powered down to save power. At a predetermined time, power is supplied to the crystal oscillator emulator 322. The semiconductor oscillator of the crystal oscillator emulator 322 is then calibrated using the stored calibration information. The frequency of the output signal of the crystal oscillator emulator 322 is compared to the frequency of the output signal of the active silicon oscillator 324 to determine the frequency error of the active silicon oscillator 324. The control signal 334 changes in response to the frequency error, causing the supply voltage from the voltage regulator 332 to shift, causing the output frequency of the active silicon oscillator 324 to change, and reducing the frequency error.

Fig. 12 illustrates an aspect of another low power oscillator 350 for generating a periodic signal. The low power oscillator 350 includes a crystal oscillator emulator 352 in communication with a charge pump oscillator 354. The crystal oscillator emulator 352 is normally in a powered down state to reduce power consumption. During the power-down state, all or a portion of the crystal oscillator emulator 352 may be powered down. At predetermined intervals, the crystal oscillator emulator 352 may be powered up and used to calibrate the charge pump oscillator 354. The predetermined interval may be determined as a function of any circuit parameter, such as operating time, temperature variations of the semiconductor, ambient temperature variations, semiconductor temperature, and supply voltage variations.

The charge pump oscillator 354 may include a charge pump 356, a loop filter 358, a Voltage Controlled Oscillator (VCO)360, and a phase detector 362. The charge pump oscillator 354 is similar in operation to a conventional charge pump oscillator except that the reference input of the phase detector 362 receives a reference clock signal from the crystal oscillator emulator 352.

The multiplexer 364 receives output signals from the crystal oscillator emulator 352 and the charge pump oscillator 354. One of the output signals is selected and passed through a multiplexer 364 to a phase locked loop 366. The phase locked loop 366 generates an output signal that is a function of the output signals from the crystal oscillator emulator 352 and the charge pump oscillator 354.

In operation, the charge pump oscillator 354 is normally in an on state to generate a periodic output signal. The crystal oscillator emulator 352 is normally in an off state. In the off state, all or a portion of the crystal oscillator emulator 352 may be powered down to reduce power consumption. At a predetermined time, power is provided to the crystal oscillator emulator 352. The semiconductor oscillator of the crystal oscillator emulator 352 is then calibrated using the stored calibration information. The output signal of the crystal oscillator emulator 352 is compared to the output signal of the charge pump oscillator 354 to determine the phase error of the charge pump oscillator 354. The VCO 360 is then controlled to reduce the phase error so that the output signal of the charge pump oscillator 354 is calibrated to the output signal of the crystal oscillator emulator 352. One of the output signals may then be selected and provided to the PLL 366.

Referring now to fig. 13-15, an integrated circuit 500 includes a crystal oscillator emulator 502 that generates a clock signal. One or more circuits 504 in integrated circuit 500 receive a clock signal. The crystal oscillator emulator 502 may be implemented in the manner described above in connection with fig. 1-12. The circuitry 502 may include the processor 512 shown in fig. 14 or other circuitry. The external component 506 may optionally be used to select the clock frequency of the crystal oscillator emulator 502, as shown in fig. 13 and 15.

Referring now to fig. 16-18, integrated circuit 518 includes a clock divider 520 that generates clock signals for circuits 522-1, 522-2. The circuits 522 may be interconnected to each other in any manner. Clock divider 520 divides the clock by an integer number (e.g., X) and/or multiplies the clock signal by Y for 1/X, Y and/or Y/X adjustment. Clock divider 520 may also use one or more other ratios and/or divisors to generate different clock signals for other circuits 522. Clock divider 520 outputs the illustrated N-1 clock signals to N-1 circuits 522 in integrated circuit 518.

In fig. 17, one of the circuits includes a processor 530. The processor 530 may be connected to the clock divider 520 without being connected to the crystal oscillator emulator 502 and/or to both the clock divider 520 and the crystal oscillator emulator 502. Additional circuits 532-1, 532-2,. and 532-N communicate with clock divider 520.

In fig. 18, crystal oscillator emulator 502 provides clock signals for one or more circuits 544 in processor 530, graphics processor 540, memory 542, and/or integrated circuit 518. A clock divider (not shown) may also be provided. The processor 530, graphics processor 540, memory 542, and/or other circuitry 544 may be interconnected in any suitable manner.

Referring now to fig. 19, integrated circuit 600 includes one or more circuits 602-1, 602-2,. and 602-N (collectively, circuits 602) and low power oscillator 320, which operate as described above in connection with fig. 11. One of the circuits may include a processor, shown as 610. As mentioned above, a clock divider (not shown) may also be provided.

Integrated Circuits (ICs) are typically encased in a packaging material. The encapsulation material may comprise plastic. The IC substrate may include pads connected to leads of the lead frame via bond wires (bondwires). The IC substrate, bond wires and portions of the leads may be encased in plastic. The properties of the packaging materials typically used to package ICs may change over time. These variations may cause the oscillation frequency of the on-chip oscillator to drift over time. The variations in encapsulation may be due to the dielectric loss of the encapsulation material changing over time. The change in encapsulation may also be due to water absorption of the encapsulating material at different humidity levels. As a result, the encapsulation material may limit the achievable calibration accuracy.

Referring now to fig. 20, an integrated circuit 700 is encapsulated in an encapsulation material 704 according to the prior art. It will be appreciated that the characteristics of the encapsulation material 704 may change over time and/or as a function of environmental conditions. For example, when the encapsulation material 704 comprises a plastic material, the dielectric loss of the plastic material may vary over time, which may adversely affect calibration accuracy. The term "dielectric loss" as used herein refers to the loss of energy that ultimately causes a rise in the temperature of a dielectric placed in an alternating electric field. Heating is due to the "molecular friction" of the dipole within the material as it attempts to re-orient itself using the oscillating (electric) field of the incident wave. For example, when heating an item in a microwave, the dipole associated with the water in the food vibrates and is heated. Certain materials, such as certain plastics, are not suitable for use in microwaves because they absorb too much heat. These materials have high dielectric loss characteristics. Other materials (e.g., other types of plastics) experience little or no heating. These materials have low dielectric loss characteristics. Since the circuits described herein can operate at microwave frequencies, low dielectric loss materials are preferred.

Water absorption of the plastic material over time may also adversely affect calibration accuracy. Since water has a high dielectric loss, increasing the water content in the encapsulating material tends to increase the dielectric loss of the encapsulating material. In other features, the encapsulation material may also be a low stress material. High stress materials are prone to bending, which may affect the circuit characteristics of adjacent circuits, for example, by changing the channel length. The term "low stress" as used herein refers to a stable packaging material that is not susceptible to changing electrical characteristics of the integrated circuit with changes in stress. In certain implementations, the encapsulation material has a Dielectric Loss Factor (DLF) less than or equal to Teflon (polytetrafluoroethylene) at the relevant operating frequency (e.g., greater than 1 GHz).

Referring now to fig. 21, an integrated circuit 710 having an on-chip semiconductor oscillator 711 with temperature compensation is shown packaged in a packaging material 714 having low dielectric losses in accordance with the present invention. The encapsulation material 714 may be a plastic encapsulation material with low dielectric loss. The term "low dielectric loss" as used herein means that the dielectric loss of the material is less than or equal to Teflon at the relevant operating frequency of the IC. The operating frequency of the IC may be greater than 1GHz and/or 2.4 GHz. The encapsulation material 714 may also include Teflon^®、Teflon^®Polychlorotrifluoroethylene (PCTFE) Teflon^®Teflon^®Fluorinated Ethylene Propylene (FEP), Polytetrafluoroethylene (PFA), Tefzel^®And Teflon^®Ethylene-tetrafluoroethylene copolymer (ETFE), low dielectric loss plastic, high quality glass, air, and/or other materials. Any other encapsulant material having a dielectric loss less than or equal to Teflon is contemplated. The encapsulating material may also have a relatively low water absorption.

Referring now to fig. 22, an exemplary implementation of the integrated circuit package of fig. 21 is shown in greater detail. The integrated circuit package 718 includes an integrated circuit 724, and the integrated circuit 724 includes pads 728. The leads 732 of the lead frame 733 are connected to pads 728 of the integrated circuit by bonding wires 734. It will be appreciated that the integrated circuit includes the above-described on-chip semiconductor oscillator with temperature compensation. A portion of leads 732, bond wires 734, and integrated circuit 724 are encapsulated in an encapsulant 736. The packaging material 736 may be a plastic packaging material with low dielectric loss. It will be appreciated that other types of packages may be employed in this and/or other embodiments, such as Ball Grid Array (BGA), flip chip, and/or any other suitable packaging technique.

Referring now to fig. 23, another integrated circuit package 738 includes a temperature compensated on-chip semiconductor oscillator 741 according to the present invention. In this embodiment, the semiconductor oscillator 741 includes an integrated circuit inductor 742. The glass layer 744 is bonded to the integrated circuit substrate 740 by a very thin epoxy layer 750. The epoxy layer 750 may have low dielectric loss. The glass layer 744, epoxy layer 750, and integrated circuit substrate 740 are encapsulated in an encapsulation material 760. In this case, the requirement for dielectric loss of the encapsulation material is no longer as demanding due to the distance between inductor 742 and encapsulation material 760. Thus, the requirements for changes in dielectric loss and/or other properties of the encapsulating material 760 as a function of time are less stringent. However, the encapsulation material may be a low dielectric loss material. Although the glass layer is shown over the entire integrated circuit, the glass layer may be confined to a smaller area proximate the semiconductor oscillator.

Referring now to fig. 24 and 25, another integrated circuit package including an on-chip semiconductor oscillator in accordance with the present invention is shown. This embodiment is similar to the embodiment shown and described above in connection with fig. 23. However, glass layer 744 defines a cavity 746. The cavity 746 is adjacent to, aligned with, and extends over the inductor 742. An air cavity 752 is formed between inductor 742 and glass layer 744. A thin epoxy layer 750 is formed between the glass layer 744 and the integrated circuit substrate 740, but does not include the area of the cavity 746. The glass layer 744 may be etched to define a cavity and dipped in epoxy. Similarly, the glass layer may comprise multiple layers of glass with a cavity formed in at least one of the layers.

Referring now to fig. 26, the capacitors of the on-chip semiconductor oscillator may be adjusted based on the temperature compensation described above. However, it will be appreciated that there are other ways to adjust the oscillation frequency independently of the adjustment of the capacitors and/or inductors of the semiconductor oscillator.

Referring now to fig. 27, an integrated circuit 830 includes a fractional phase-locked loop 831 with a temperature compensation input. Fractional phase-locked loop 831 includes a phase frequency detector 836 that receives the output of integrated circuit oscillator 832, which operates as described above. The phase frequency detector 836 generates a differential signal based on the difference between the reference frequency and the VCO frequency. The differential signal is output to the charge pump 840. The output of the charge pump 840 is input to an optional loop filter 844. The output of the loop filter 844 is input to a Voltage Controlled Oscillator (VCO) that generates a VCO output having a frequency related to the voltage input thereto. A scaling circuit 850 selectively divides the VCO frequency by N or N + 1. While divisors N and N +1 are used, the divisors may be other values.

The output of the scaling circuit 850 is fed back to the phase frequency detector 836. Temperature sensor 854 measures the temperature of integrated circuit 830 in an area near IC oscillator 832. Temperature sensor 854 outputs a temperature signal that is used to address calibration information 858 stored in memory 856. The selected calibration information is used to adjust the scaling circuit 850. The selected calibration information adjusts the ratio of the divisors N and N +1 used by the scaling circuit 850.

Referring now to FIG. 28, a Delta-Sigma fractional phase-locked loop 858 is shown that is used in an integrated circuit 860 that includes a temperature compensation input. The selected calibration information is used to adjust the output of the Sigma Delta modulator 870. The selected calibration information may adjust the modulation between the divisors N and N +1 used by the scaling circuit 850.

Referring now to fig. 29, a flow chart 900 illustrates steps for measuring sample calibration points and generating calibration data using a linear curve fitting algorithm. Control begins in step 902. In step 904, control measures sample calibration points over multiple temperatures. In step 906, a linear curve fitting algorithm is used to generate a curve for other temperature points between the sample points.

Referring now to fig. 30, a flow chart 920 shows steps for measuring sample calibration points and generating calibration data using a higher order curve fitting algorithm. The steps shown in fig. 29 may be implemented using a computer that includes a processor and memory. Control begins in step 922. In step 924, control measures sample calibration points over multiple temperatures. In step 926, a higher order curve fitting algorithm is used to generate a curve for other temperature points between the sample points. In step 928, control ends.

Referring now to fig. 31A through 31G, various exemplary implementations of the present invention are shown. Referring now to FIG. 31A, the present invention may be implemented in a hard disk drive 1000. The present invention may implement any integrated circuit, such as signal processing and/or control circuitry, which is generally identified in FIG. 31A as 1002. In some implementations, signal processing and/or control circuitry 1002 and/or other circuitry (not shown) in HDD 1000 may process data, perform coding and/or encryption, perform calculations, and/or format data output to and/or received from magnetic storage medium 1006.

HDD 1000 may communicate with a host device (not shown), such as a computer, a mobile computing device such as a personal digital assistant, cellular telephone, media or MP3 player, and/or other devices, via one or more wired or wireless communication links 1008. HDD 1000 may be connected to memory 1009 such as Random Access Memory (RAM), low latency nonvolatile memory such as flash memory, Read Only Memory (ROM), and/or other suitable electronic data storage.

Referring now to FIG. 31B, the present invention can be implemented in a Digital Versatile Disk (DVD) drive 1010. The present invention may implement any integrated circuit such as signal processing and/or control circuits, generally identified in figure 31B as 1012, and/or a mass data storage device such as a DVD drive 1010. Signal processing and/or control circuits 1012 and/or other circuits (not shown) in the DVD1010 may process data, perform coding and/or encryption, perform calculations, and/or format data read from and/or written to the optical storage medium 1016. In some implementations, the signal processing and/or control circuits 1012 and/or other circuits (not shown) in the DVD1010 can also perform other functions, such as encoding and/or decoding, and/or any other signal processing functions associated with a DVD drive.

The DVD drive 1010 may communicate with an output device (not shown), such as a computer, television, or other device, via one or more wired or wireless communication links 1017. The DVD1010 may communicate with a mass data storage device 1018 that stores data in a nonvolatile manner. The mass data storage device 1018 may include a Hard Disk Drive (HDD). The HDD may have the configuration shown in fig. 31A. The HDD may be a mini HDD that includes one or more platters (platters) having a diameter less than about 1.8 ". The DVD1010 may be connected to memory 1019 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage.

Referring now to fig. 31C, the present invention can be implemented in a High Definition Television (HDTV) 1020. The present invention may implement any integrated circuit such as signal processing and/or control circuitry, generally designated 1022 in fig. 31C, a WLAN interface and/or a mass data storage device for HDTV 1020. HDTV1020 receives HDTV input signals in either a wired or wireless format and generates HDTV output signals for a display 1026. In some implementations, signal processing and/or control circuits 1022 and/or other circuits (not shown) of HDTV1020 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any type of HDTV processing that may be required.

HDTV1020 may communicate with mass data storage 1027. this storage 1027 stores data in a nonvolatile manner such as optical and/or magnetic storage. At least one HDD may have the configuration shown in fig. 31A, and/or at least one DVD may have the configuration shown in fig. 31B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. HDTV1020 may be connected to memory 1028 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. HDTV1020 may also support connections with a WLAN via a WLAN network interface 1029.

Referring now to fig. 31D, the present invention implements any integrated circuit in the control system of the vehicle 1030, the WLAN interface, and/or the mass data storage device of the vehicle control system. In certain implementations, the present disclosure implements a powertrain control system 1032 that receives input from one or more sensors (e.g., temperature sensors, pressure sensors, rotation sensors, airflow sensors, and/or any other suitable sensors) and/or generates one or more output control signals (e.g., engine operating parameters, transmission operating parameters, and/or other control signals).

The present invention may also be implemented in other control systems 1040 of the vehicle 1030. The control system 1040 may likewise receive signals from input sensors 1042 and/or output control signals to one or more output devices 1044. In certain implementations, the control system 1040 may be part of an Antilock Braking System (ABS), a navigation system, an telematics system, a vehicle telematics system, a lane departure system, an adaptive cruise control system, a vehicle entertainment system such as a stereo, DVD, compact disc, etc. Other implementations are also contemplated.

The powertrain control system 1032 may communicate with a mass data storage device 1046 that stores data in a nonvolatile manner. The mass data storage device 1046 may include optical and/or magnetic storage devices, such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 31A, and/or at least one DVD may have the configuration shown in fig. 31B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The powertrain control system 1032 may be connected to memory 1047 such as RAM, ROM, low latency nonvolatile memory such as flash memory, and/or other suitable electronic data storage. The powertrain control system 1032 may also support connections with a WLAN via a WLAN network interface 1048. The control system 1040 may also include a mass data storage device, memory, and/or a WLAN interface (all not shown).

Referring now to fig. 31E, the present invention may be implemented in a cellular telephone 1050 that may include a cellular antenna 1051. The present invention may implement any integrated circuit such as signal processing and/or control circuits, which are generally identified in fig. 31E as 1052, a WLAN interface, and/or a mass data storage device for the cellular telephone 1050. In some implementations, the cellular telephone 1050 includes a microphone 1056, an audio output 1058 such as a speaker and/or audio output jack, a display 1060, and/or an input device 1062 such as a keyboard, pointing device, voice actuation, and/or other input devices. Signal processing and/or control circuits 1052 and/or other circuits (not shown) in the cellular telephone 1050 may process data, perform coding and/or encryption, perform calculations, format data and/or perform other cellular telephone functions.

The cellular telephone 1050 may communicate with a mass data storage device 1064 that stores data in a nonvolatile manner, the mass data storage device 1064 being, for example, an optical and/or magnetic storage device, such as a hard disk drive HDD and/or DVD. At least one HDD may have the configuration shown in fig. 31A, and/or at least one DVD may have the configuration shown in fig. 31B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The cellular telephone 1050 may be connected to memory 1066 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. Cellular telephone 1050 may also support connections with a WLAN via WLAN network interface 1068.

Referring now to fig. 31F, the present invention can be implemented in a set top box 1080. The present invention may implement any integrated circuit such as signal processing and/or control circuitry, which is generally identified as 1084 in fig. 31F, a WLAN interface, and/or a mass data storage device of set top box 1080. Set top box 1080 receives signals from a source (e.g., a broadband source) and outputs standard and/or high definition audio/video signals suitable for display 1088, such as a television and/or monitor and/or other video and/or audio output device. Signal processing and/or control circuits 1084 and/or other circuits (not shown) of the set top box 1080 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other set top box function.

The set top box 1080 may communicate with a mass data storage device 1090 that stores data in a nonvolatile manner. The mass data storage device 1090 may include optical and/or magnetic storage devices such as hard disk drives HDD and/or DVDs. At least one HDD may have the configuration shown in fig. 31A, and/or at least one DVD may have the configuration shown in fig. 31B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The set top box 1080 may be connected to memory 1094 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The set top box 1080 may also support connections with a WLAN via a WLAN network interface 1096.

Referring now to FIG. 31G, the present invention can be implemented in a media player 1100. The present invention may implement any integrated circuit such as signal processing and/or control circuitry, which is generally identified in fig. 31G as 1104, a WLAN interface, and/or a mass data storage device of the media player 1100. In some implementations, the media player 1100 includes a display 1107 and/or a user input 1108, such as a keyboard, a touch pad, and so forth. In some implementations, the media player 1100 can use a Graphical User Interface (GUI) that typically employs menus, drop down menus, icons, and/or a point-and-click interface via a display 1107 and/or user input 1108. The media player 1100 also includes an audio output 1109, such as a speaker and/or an audio output plug. Signal processing and/or control circuits 1104 and/or other circuits (not shown) of media player 1100 may process data, perform coding and/or encryption, perform calculations, format data and/or perform any other media player function.

The media player 1100 may communicate with a mass data storage 1110 that stores data (e.g., compressed audio and/or video content) in a non-volatile manner. In some implementations, the compressed audio files include files that conform to the MP3 format or other suitable compressed audio and/or video format. The mass data storage device may comprise an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in fig. 31A, and/or at least one DVD may have the configuration shown in fig. 31B. The HDD may be a mini HDD that includes one or more platters that are less than about 1.8 "in diameter. The media player 1100 may be connected to memory 1114 such as RAM, ROM, low latency nonvolatile memory such as flash memory and/or other suitable electronic data storage. The media player 1100 may also support connections with a WLAN via a WLAN network interface 1116. Other implementations than the above are also contemplated.

Referring now to fig. 32A-32D, an integrated circuit package is shown that incorporates an annealed glass paste or epoxy as a layer and/or as a plurality of "islands" adjacent to one or more selected features of a silicon wafer. One or more "islands" of annealed glass paste or epoxy layer may be disposed on some portion of one or both sides of the silicon wafer. In fig. 32A, another integrated circuit package 1200 includes a silicon wafer 1204. A layer of annealed glass paste or portions of annealed glass paste 1206 are formed on silicon wafer 1204. The mold material 1208 may be used to encapsulate all or part of the silicon wafer 1204. Annealing the glass-paste layer 1206 also reduces the change in stress over time. Annealing the glass paste layer 1206 tends to shield all or part of the silicon wafer 1204 from variations in the dielectric properties (e.g., dielectric point loss) of the mold material 1208.

The silicon wafer 1204 may include the semiconductor oscillator described above. The annealed glass paste layer 1206 may comprise a glass paste having a relatively low annealing temperature. The low anneal temperature may be lower than the temperature that would damage the silicon wafer 1204. The glass paste layer 1206 may comprise a glass frit paste. The glass paste layer may be applied in any suitable manner. The glass paste layer may be applied using a screen printing method, a dipping method, a color separation coating method, and/or using any other suitable method.

In fig. 32B, another integrated circuit package 1210 includes a layer or coating 1212 of conductive material that is applied to a layer 1206 of glass paste or epoxy. The conductive material layer 1212 may include a conductive epoxy layer. The layer of conductive material 1212 may be applied as a liquid and then cured. The conductive material layer 1212 may include a conductive epoxy paint. The layer 1212 of conductive material may be applied in any suitable manner, including dipping the silicon wafer 1204 in a container (e.g., a tray) containing conductive material. The conductive material layer 1212 tends to reduce electromagnetic interference from external devices.

In fig. 32C, an integrated circuit package 1220 includes a layer of annealed glass paste 1206 applied to selected portions of a silicon wafer 1204. In fig. 32D, an integrated circuit package 1230 includes an annealed glass paste or epoxy portion 1206 and a conductive material 1212. The conductive material 1212 may cover the annealed glass paste layer 1206 with or without touching the silicon wafer 1204.

Referring now to fig. 33A-33D, additional integrated circuit packages are shown. In fig. 33A, another integrated circuit package 1240 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212, which are located adjacent to a circuit component 1242 of a silicon wafer 1204. In fig. 33B, another integrated circuit package 1250 includes an annealed glass paste layer 1206 and a layer of conductive material 1212, which are located near an oscillator 1252 of a silicon wafer 1204.

In fig. 33C, another integrated circuit package 1260 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212, which are located near an inductor 1262 of the silicon wafer 1204. Inductor 1262 may be an on-chip inductor, such as a spiral inductor. In fig. 33D, another integrated circuit package 1270 includes a layer of annealed glass paste 1206 and a layer of conductive material 1212, which are located near an oscillator circuit 1272 with an inductor 1274.

Annealing the glass paste layer also tends to reduce the variation in stress over time that can occur. Annealing the glass paste layer leaves all or part of the silicon wafer unaffected by the change in the dielectric properties (e.g., dielectric loss) of the mold material. This is particularly beneficial when attempting to use temperature for calibration (as described above).

Referring now to fig. 34A-34D, additional integrated circuit packages are shown that include annealed glass pastes and/or epoxy portions and glass or silicon layers that establish air gaps on certain portions of the silicon wafer. In fig. 34A-34B, integrated circuit packages 1300 and 1330 include a silicon wafer 1304. Annealed glass paste portions 1306 are formed on the silicon wafer 1304 in some spaced-apart relationship. The AGP portion 1306 can be formed in the above-described manner. A casting material 1308 may be used. Post-processing of the AGP portion 1306 may be performed (e.g., polishing or other steps) to provide a flat outer surface.

A glass or silicon layer 1310 is supported above the silicon wafer 1304 by means of an AGP portion 1306. An epoxy or other bonding material may be used to affix the glass or silicon layer 1310 to the AGP portion 1306. The AGP portion 1306 and the glass or silicon layer 1310 form an air gap 1324 over the oscillator 1320 (fig. 34A) and/or any other circuitry 1322 (fig. 34B). The air gap 1324 provides the material (air) with the lowest possible dielectric loss. In contrast, when a crystal oscillator is used, air is required to allow the crystal to resonate, in other words, air is used to allow mechanical oscillation.

In fig. 34C-34D, the integrated circuit packages 1340 and 1360 include a silicon wafer 1304. The epoxy portions 1342 are formed on the silicon wafer 1304 in some spatially separated relationship. The epoxy portion 1342 may be formed as described above. Post-processing of the epoxy portion 1342 can be performed (e.g., polishing or other steps) to provide a flat outer surface. A glass or silicon layer 1310 is supported above the silicon wafer 1304 by means of an epoxy portion 1342. Epoxy or other bonding material may be used to affix the glass or silicon layer 1310 to the epoxy portion 1342. The epoxy 1342 and the glass or silicon layer 1310 form an air gap 1324 over the oscillator 1320 (fig. 34C) and/or any other circuitry 1322 (fig. 34D).

Referring now to fig. 35A-35B, additional integrated circuit packages are shown that include a glass or silicon portion that establishes an air gap. In fig. 35A, an integrated circuit package 1380 includes a "C" shaped glass or silicon portion 1382 defining an air gap 1384. The "C" shaped glass or silicon portion 1382 may include multiple segments joined together. An air gap 1384 is located above the oscillator 1320. In fig. 35B, the integrated circuit package 1390 includes a "C" shaped glass or silicon layer 1382 that defines an air gap 1384. An air gap 1384 is located over the circuit 1322.

Referring now to fig. 36A-36C, a method for manufacturing the integrated circuit package described above is shown. The integrated circuit structure 1400 includes a silicon wafer 1404, a plurality of spaced-apart AGP and/or epoxy portions 1410A and 1410B (collectively referred to as portions 1410), and a glass or silicon layer 1408. The integrated circuit structure 1400 is cut into a plurality of segments along dashed lines 1414 to create a plurality of integrated circuits that can be encapsulated in the molding material (not shown) described above.

In fig. 36B, the silicon wafer 1404 may include one or more bond pads 1420. The cutouts of layer 1408 at 1414-1 and 1414-2 may be offset from the cutouts of the silicon wafer at 1414-3 to provide spacing for attaching bond wires (not shown) to bond pads 1420. In fig. 36C, one of the integrated circuits 1450 that is singulated from the integrated circuit structure 1400 is shown.

Referring now to fig. 37A-37B, an integrated circuit package 1450 includes a silicon wafer with a plurality of spaced apart annealed glass paste and/or epoxy portions 1410 coated with a layer of conductive material 1456. In fig. 37A, the portion 1410 is immersed in a container 1454, the container 1454 containing a conductive material 1456. The silicon wafer 1408 may be diced along one or more cuts 1462 and may include bond pads 1460 as shown.

Referring now to fig. 38, steps of a method 1500 for fabricating the integrated circuit package of fig. 32A-33D are shown. Control begins with step 1502. At step 1504, a layer of glass paste 1206 is applied to one or more surfaces of the silicon wafer 1204 and/or to selected areas of the silicon wafer 1204. At step 1506, the glass paste layer 1206 is annealed by placing the silicon wafer 1204 and the glass paste layer 1206 in an oven. The temperature of the oven may be set to a temperature sufficient to cure (cure) the layer of glass paste 1206. For example, a temperature of about 400 ℃ for a predetermined period of time is sufficient to anneal the glass frit slurry and not damage the silicon wafer 1204. In step 1508, a layer of conductive material 1212 is applied to the annealed glass-paste layer 1206. At step 1510, all or a portion of the silicon wafer 1204 is loaded into a mold material 1208, such as plastic, other materials described herein, and/or other suitable mold materials. In step 1520, control ends.

In each of the above embodiments, the silicon wafer may be replaced by another wafer or other substrate, and the annealed glass paste may be replaced by epoxy.

Various embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims.

The priority of U.S. provisional application No.60/714,454 filed on 6/9/2005, U.S. provisional application No.60/756,828 filed on 6/1/2006, and U.S. provisional application No.60/730,568 filed on 27/10/2005, and the priority of this application is that of U.S. patent application No.10/892,709 filed on 16/2004, and that of application No.10/892,709 is that of U.S. patent application No.10/272,247 filed on 15/10/2002, all of which are hereby incorporated herein by reference in their entirety.

Claims (7)

1. An integrated circuit, comprising:

a temperature sensor that senses a temperature of the integrated circuit;

a memory module that stores oscillator data relating to calibrations and selects one of the oscillator calibrations as a function of the sensed temperature;

an oscillator module that generates a reference signal having a frequency; and

a phase-locked loop module including a feedback loop having a feedback loop parameter, wherein the phase-locked loop module selectively adjusts the feedback loop parameter based on the selected one of the oscillator calibrations.

2. The integrated circuit of claim 1, wherein the phase-locked loop module comprises a fractional phase-locked loop module and the feedback loop parameter is a ratio of a scaling factor.

3. The integrated circuit of claim 2, wherein the fractional phase-locked loop module comprises:

a phase frequency detector module in communication with the oscillator module and receiving the reference frequency;

a charge pump module in communication with the phase frequency detector module;

a voltage controlled oscillator module in communication with the charge pump module and generating an output frequency;

a scaling module in communication with the voltage controlled oscillator and the phase frequency detector module and selectively adjusting the output frequency by first and second scaling factors,

wherein the scaling module adjusts a ratio of the first and second scaling factors based on the selected one of the oscillator calibrations.

4. The integrated circuit of claim 3, wherein the first and second scaling factors are divisors equal to N and N +1, and N is an integer greater than 0.

5. The integrated circuit of claim 1, wherein the phase-locked loop module comprises a delta sigma fractional phase-locked loop module and the feedback loop parameter comprises a modulation of a scaled divisor.

6. The integrated circuit of claim 5, wherein the Delta Sigma fractional phase-locked loop module comprises:

a phase frequency detector module in communication with the oscillator module and receiving the reference frequency;

a charge pump module in communication with the phase frequency detector module;

a voltage controlled oscillator module in communication with the charge pump module and generating an output frequency;

a scaling module in communication with the voltage controlled oscillator and the phase frequency detector module and selectively dividing the output frequency by first and second scaling factors; and

a Sigma Delta modulator to adjust modulation of the scaling module between the first and second scaling factors based on the selected one of the oscillator calibrations.

7. The integrated circuit of claim 6, wherein the first and second scaling factors are divisors equal to N and N +1, and N is an integer greater than 0.