HK1104129B - Method and apparatus for subclocking a sar analog-to-digital converter - Google Patents

Description

Method and apparatus for sub-clocking successive approximation register analog-to-digital converters

Technical Field

The present invention relates generally to data converters, and more particularly to Successive Approximation Register (SAR) analog-to-digital converters operating in mixed signal processors having multiple clocks.

Cross Reference to Related Applications

The present invention claims priority to application serial No. 10/816,564 filed 3/31/2004

Background

The mixed signal processor unit is an integrated circuit on which a digital processing part and an analog part are included. The analog part typically includes an analog multiplexer and an analog-to-digital converter in addition to a digital-to-analog converter. This allows analog data to be sampled on a plurality of analog data inputs, converted to digital signals, and then provided to a processing section for processing thereof. On the digital processing side, the digital processor may operate at multiple frequencies. These frequencies are derived from an internal clock that generates a plurality of frequencies. Generally, there are two distinct clocks, a high frequency clock and a low frequency clock. The low frequency clock is typically utilized to enable the processor to enter a low power mode in which processing is performed at a very low frequency and the power consumed is relatively low. Typically, the high frequency rate is on the order of 20-25MHz, while the low frequency clock rate is on the order of 32 KHz. The problem is that when operating at low frequencies, the ADC must also operate at low frequencies. Typically, ADCs are facilitated by a successive approximation algorithm (successive approximation algorithm) that requires testing of multiple bits per data conversion cycle. Thus, at low frequencies, the throughput of the ADC is very low, since the conversion clock of the ADC cannot run at a higher clock rate than the high frequency clock. In addition, noise generated in the digital processing section affects the data conversion operation for both high and low frequencies. Thus, if the ADC and the digital processing section are running at the same clock frequency, noise may be injected from the digital section into the analog section, which is a conventional problem in mixed signal devices.

Disclosure of Invention

The invention disclosed and claimed herein, in one aspect thereof, comprises a method for clocking the operation of a SAR analog-to-digital converter (ADC). A low frequency clock and a high frequency clock are provided. The analog input voltage is then tracked during a tracking phase (tracking phase) in order to sample the voltage value. A transition period is then initiated that references a low frequency clock edge. The sampled data is then converted in a conversion operation that requires a number of conversion clock cycles during the data conversion period. The timing of at least a portion of the conversion operation is controlled using a high frequency clock as the conversion clock during the data conversion period.

Drawings

For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a block diagram of a mixed signal processor having an analog-to-digital converter associated therewith;

FIG. 2 illustrates a block diagram of the analog to digital converter;

FIG. 3 illustrates a timing diagram of the operation of a prior art SAR ADC;

FIG. 4 illustrates a timing diagram of a SAR ADC having an abort characteristic;

FIG. 5 illustrates a block diagram of a digital compare circuit;

FIG. 6 illustrates a block diagram of a serial-to-parallel data converter;

FIG. 7 illustrates a flow diagram of an abort operation;

FIG. 8 illustrates a schematic diagram of an ADC illustrating the utilization of multiple clock and sub-clock control features of the ADC;

FIG. 9 illustrates a timing diagram of sub-clocking operations;

FIG. 10 illustrates a more detailed timing diagram for the sub-clocking feature, showing a high frequency clock;

FIG. 11 illustrates a more detailed diagram of an ADC, illustrating SAR registers and repetition functions;

FIG. 12 illustrates a timing diagram of a repeat instruction;

FIG. 13 illustrates a timing diagram of a tracked feature;

FIG. 14 illustrates a more detailed block diagram of the clock multiplexing function;

15a-15c illustrate ADC registers;

FIG. 16 illustrates a flow chart of sub-clocking operations;

FIG. 17 illustrates a flow diagram of a conversion operation controlled with a sub-clock responsive to a single converter request;

FIG. 18 illustrates a logic diagram of a SAR controller and SAR registers;

FIG. 19 illustrates a logic diagram of a parallel to serial converter;

FIG. 20 illustrates an alternative embodiment of a sub-clocking operation; and

fig. 21 illustrates a timing diagram of the alternative embodiment of fig. 20.

Detailed Description

Referring now to fig. 1, fig. 1 illustrates a block diagram of a mixed signal integrated circuit including a SAR analog-to-digital converter (ADC). This is a conventional processor-based mixed signal circuit of type C8051F410, manufactured by Silicon Laboratories, the present assignee. This mixed signal circuit includes a conventional processor core CPU 102: 8051CPU at its center. The CPU 102 is coupled to memory, which is a flash memory 104 coupled to the CPU 102 via a bus 106 and a Random Access Memory (RAM)108 coupled to the CPU 102 via a bus 110.

The CPU 102 operates based on a plurality of clocks. An external oscillator circuit 112 is provided which can be controlled by an external crystal 114, noting that the external oscillator circuit 112 is actually mounted on-chip. This oscillator is a high frequency oscillator and operates at a frequency of about 25 MHz. This is an input to the CPU 102 through a selection Multiplexer (MUX) 116. Alternatively, the CPU 102 can be powered by a low frequency internal oscillator 120, which is a 32KHz crystal oscillator. In general, the primary processing function of CPU 102 is performed using high frequency oscillator 112, while a low frequency oscillator is employed when CPU 102 is placed in a "sleep" mode. Processing operations are generally minimal at low frequencies. CPU 102 also includes JTAG logic block 118, which JTAG logic block 118 is used to transfer external data to CPU 102 for writing to flash memory 104, which is conventional in operation.

CPU 102 is connected to a digital on-chip bus 122, which digital on-chip bus 122 is connected to a plurality of digital inputs via a digital I/O block 126The/output pin 124. This digital I/O block 126 is used to allow various digital transfers. This may be parallel digital data or it may be serial data. Typically the serial data may be transmitted in some type of serial data format. The serial data format may be RS232 data format, I²C format or any other type of serial data format. This enables digital data to be received or transmitted. In addition, the digital bus 122 is connected to a digital input of an analog-to-digital converter (ADC)128 for receiving digital data therefrom. An input to ADC128 is provided on an input analog line 130, which includes the output of a programmable amplifier 132. Analog inputs to amplifier 132 are received from an analog multiplexer 134 that receives a plurality of analog inputs on analog input lines 136. These analog inputs may be received from any source, such as an interdigital transducer. One embodiment of such an analog multiplexer is illustrated in U.S. patent 6,507,215, assigned to the present assignee and issued on 14.1.2003, the contents of which are hereby incorporated by reference in their entirety. One example input to multiplexer 134 is from temperature sensor 138, which is an internally generated temperature value, typically generated from a bandgap reference voltage generator included on the chip. The output of this temperature sensor is connected to one end of the analog input line 136 and is selected for ambient temperature measurement of the chip, which is the ambient temperature.

In addition to analog multiplexer 134 and ADC128, the digital information on bus 122 may be provided as an input to a digital-to-analog converter (DAC)140, which may be converted to an analog output signal on an analog output line 142. The comparator function is provided by a comparator 144, which comparator 144 receives an analog input for comparison with an internally generated reference voltage or an external reference voltage (not shown) to provide a selectable output that can be driven to the digital bus 122, or to an interrupt input on the CPU 102. Although the output of the comparator 144 is illustrated as being connected to the digital bus 122, it should be understood that the output of the comparator 144 may also be connected to a number of different interrupt circuits on the processor.

Referring now to fig. 2, fig. 2 illustrates a block diagram of ADC 128. The conventional SAR ADC includes a charge redistribution DAC 202 on the input for receiving an analog input signal on an analog input line 204. In response to receiving a conversion start request from the CPU 102, a data conversion operation is started. At a sampling frequency off generated by a sampling clock_sAn analog voltage is sampled, which is obtained from a high frequency oscillator or a low frequency oscillator. This is lower than the frequency of a conventional clock. The output of charge redistribution DAC 202 is connected to one input of comparator 208 for comparison with a reference voltage. To which digital inputs are received from a digital bus 214. The comparator 208 is used to compare the voltage on its input with a reference voltage, which in one embodiment is a common mode voltage. If the voltage input into the comparator 208 is higher than the reference voltage, the output of the comparator 208 changes to indicate this to the SAR logic block 212, which is a conventional logic block. SAR logic block 212 is used to provide a digital output to digital bus 214 for driving charge redistribution DAC 202. The SAR logic block 212 essentially steps through each bit of the n-bit value of the n-bit ADC to test the bit and, if positive, to retain the value of the bit. The test process to determine the value of the SAR bit is a conventional binary SAR search algorithm. When the conversion cycle is completed, there will be n bits asserted. This will be provided as an output to a register (not shown). It should be appreciated that a differential SAR data converter utilizing a differential comparator may be used to receive the differential analog input.

In the present disclosure, when one or more bits on the bus 214 are tested, an abort feature is provided by examining the bits. The above steps are facilitated by inputting each bit on the bus 214 into an n-bit multiplexer 216 to provide a serial digital output on a serial digital output line 218. This enables the serial data to be output for testing by the digital comparator, as described below. However, it should be understood that the output may also be parallel data as opposed to serial data.

Referring now to fig. 3, fig. 3 illustrates a timing diagram showing conventional operation of a SAR data converter. Prior to the conversion period, there is a "trace" period in which the data is sampled on the input sample comparator. When a transition signal occurs at time 302, a transition cycle is requested by the CPU 102. The conversion clock will provide the timing for the conversion operation and at its selected rising edge, test of the MSB is initiated, where the MSB bit, i.e., bit 11 in a 12-bit ADC, is determined. Determined by setting the MSB to "1" and then testing the output of the comparator associated with SAR operation. This is set subsequently if it is determined by testing that this MSB is now "1", otherwise it is set to "0". At the end of the test of this bit, the bit to be set remains on the output of the SAR logic block 212. At the end of the test, the bit is also forwarded to the serial data output and the next bit, bit 10, is then tested, determining whether to set or not set the bit and leaving the bit on the output of SAR logic block 212, which is then forwarded to the serial data output. This will continue for the entire 12 bits until bit 6 "0" in block 306. In block 306, the last bit, bit "0", is tested and the test operation is then completed, forwarding the last bit to the serial data output at block 308. At the end of the test, the data word (12-bit word) is forwarded as new data to an output register (not shown). Note that the data may be forwarded as parallel data words or may be sent as serial data words. However, conventional SAR ADCs require testing of all n bits before the conversion cycle is complete. After an appropriate tracking time, this will start the next switching cycle.

There are cases where it is not necessary to test all n bits of an n-bit SAR ADC. For example, in a comparison operation, if the analog signal exceeds half of the full rated voltage, only the MSB needs to be tested for determination. If so, this may constitute a positive result, and this is the total test to be performed. If the analog signal is less than half the full rated voltage, then this is again all tests that need to be done to determine that it is a negative result. Thus, only a single bit needs to be tested and thus the remaining bits do not have to be tested and this part of the conversion cycle will be wasted. In the example of fig. 4, a situation is provided where the threshold voltage is set to 1/16 of the full voltage. This means that at a minimum, the fourth MSB must be "1". Thus if the first MSB tests positive, or the second or third MSB tests positive, this would indicate a voltage greater than 1/16 full rated voltage. In addition, the fourth MSB will also be indicated as a positive result. When it has been determined that the analog input voltage is below 1/16 full rated voltage, if the first four bits are tested negative, e.g., it is determined that they are set to "0", then testing of the remaining bits will result in a negative comparison operation. Thus, only the first four MSBs need to be tested at most.

In this example, the transition cycle begins at edge 402 of the transition signal and the first MSB at block 406 is tested on the next rising edge of the transition clock, i.e., rising edge 404. The result of this operation is forwarded to the serial output of edge 408. If the result is "1", a positive test is performed. However, in this example, the first, second and third MSBs are tested to be "0" and the MSB at block 410 is tested and determined to be a logical "1". This results in a high level output being generated, which in this embodiment generates an interrupt to the processor at edge 412, which is the output of the digital compare operation into a logic high value. At this point, the conversion operation is "aborted" at block 414 before the conversion cycle is completed, thus preventing the decomposition of the lower bits and the full 12-bit value, and then enters a tracking mode for the next sample. CPU 102 provides an abort signal to ADC128 for this function. Since one clock cycle of the conversion clock is required to send the test of the fourth MSB to the serial output, one or more other bits may be tested before the digital comparison operation is completed. In addition, this is only the case of forwarding data to the serial data output. (note that the digital compare operation is a different compare operation than the compare operation used for the operation of the SAR logic). Of course, this depends on the logic implemented. Wherein a dual port register may be utilized to perform digital comparison operations at substantially the same time during testing of each bit in order to increase its speed. However, the disclosed embodiments disclose the serial output. It can thus be seen that by terminating a transition cycle earlier before testing all bits based on a condition determined based on a certain condition being satisfied, the next transition cycle can be started, or processing of other operations can be released. For the case where it is necessary to test a plurality of analog inputs, this makes it possible to transition to "cut short" based on a positive result, which makes it possible to start the next transition operation at an earlier timing. In addition, the length of the conversion period may be set in advance based on a technique that only a part of n bits in the ADC needs to be tested. In the example of FIG. 4, for example, only four bits need to be tested to determine if a true result exists, such that any one of the four bits being high will cause an abnormal termination of the conversion cycle. Since there is no need to test the remaining bits, the conversion period can be pre-limited to only a limited number of bits. The amount of time to cycle through the analog inputs can be reduced. By having a fixed abort length, an n-bit ADC may be changed to an (n-x) bit ADC, where x is a programmable variable.

Referring now to fig. 5, fig. 5 illustrates a block diagram of a digital compare operation. The serial digital output from multiplexer 216 is provided as an input to a serial-to-parallel converter 502 as shown by a register. The serial data for input to the digital comparator 504 on the digital bus 506 is substantially stored in a register. Typically, the digital bus 506 is a wider data bus than necessary so that the register 502 can accommodate all n bits and the digital bus 506 can accommodate all n bits. A reference voltage input for a reference voltage to be compared to the digital output of register 502 is provided on bus 510. Two reference voltages are illustrated, a positive reference voltage register 512 and a negative reference voltage register 514. This is to provide a "window" comparator in which a voltage range is defined. A positive test can be indicated if the voltage is less than the negative reference voltage or greater than the positive reference voltage, or if the positive test is necessarily greater than the negative reference voltage and less than the positive reference voltage. Again, only a predetermined number of bits are required in order to determine this result. In addition, the number of bits determined is less than the total number of n bits, so that the lower bits need not be tested. In this example, digital comparator 504 then generates an interrupt on line 516 to CPU 102. However, the output of this comparator may be used for purposes other than interrupts.

Referring now to fig. 6, fig. 6 illustrates a logic diagram of register 502. A serial digital input is received on input line 602 and input to the D inputs of a plurality of D input flip-flops 604. Each of the flip-flops 604 is associated with one of the n bits as long as the Q output of the flip-flop 604 is associated with the output line 606. Each of the flip-flops 604 is gated by the bit from the SAR bit circuit 606. This SAR bit circuit 606 is a component of the SAR logic block 212, this circuit 606 "targets" each of the bits. Thus, for each bit being tested, one of the flip-flops 604 will be activated to cause a clock, such as a SAR clock, a converter clock, on a clock line 608 connected to the clock input of each of the flip-flops 604 to clock the data flow through. This is basically a data flip-flop that is set when a particular associated bit is ready. Thus, when a particular serial data output is generated, it is loaded into the correct output location. Thus, only the digital comparator 504 needs to compare the desired bits in order to make the determination.

Referring now to FIG. 7, FIG. 7 illustrates a flowchart representative of an abort characteristic. The program is initiated at block 702 where the system is in a trace operation. The routine then proceeds to decision block 704 to wait for the transition period to be initiated. If the conversion operation has not been initiated, the program follows the NO path to its input to continue the trace operation. At the end of the trace operation, when a switch operation is initiated, the process proceeds along the yes path from decision block 704 to function block 708 for testing of the first MSB. The routine then proceeds to decision block 710 to determine whether the output of the digital comparator is true. If true, this indicates that a decision has been reached, and then the program follows the YES path to function block 712, where the conversion cycle is aborted. If not, the program follows the NO path to decision block 714 to determine if this is the last bit to be tested, which means that if the result has also been determined, the program will follow the YES path to abort function block 712. However, if the abort feature is activated, neither a true comparison nor the last bit to be tested, then the program will follow the NO path from decision block 714 to function block 716 to await testing of the next bit. The routine then returns to the input of decision block 710, again testing the output of the comparator to determine if the next bit has been true compared. When a true comparison is made or the last bit to be determined is tested, the program enters the abort function block 712. Note that when the abort feature is selected, the test never exceeds the minimum bit that needs to be tested.

The abort feature is also used in a mode that allows for adjusting the bit resolution of the SAR. In this mode, the test length before the CPU generates an interrupt signal to the ACD is fixed so that there is an automatic abort. In addition, a counter is also provided in the ADC, which is incremented by the conversion clock to terminate the conversion cycle earlier and indicate that the next conversion cycle is ready and to start tracking. In this manner, the bit resolution is changed only by controlling the configuration of the comparator. Additionally, the bit resolution may be changed to provide for a first operation that continues until a threshold is exceeded. At this point, an interrupt is generated and the CPU may reconfigure the comparator to set the new resolution and threshold. This allows the bit resolution of the ADC to be implemented to be dynamically changed, where the bit resolution can be changed in response to various predetermined conditions.

Referring now to fig. 8, fig. 8 illustrates another characteristic of the operation of an ADC in a mixed signal multi-processor unit. CPU operations have multiple clocks associated with them, which are independent clock generators for allowing the CPU to operate at different frequencies for power consumption and other considerations. Specifically, fig. 8 is used to illustrate a low frequency clock and a high frequency clock. However, it should be understood that a plurality of other clocks may be provided, either generated by a high frequency clock or provided by a separate clock generator. The purpose of the multiple clocks is to allow the processor to run at a low frequency clock, thereby significantly reducing power consumption. For example, the high clock frequency runs at a frequency between 20-25MHz and the low frequency clock runs at a frequency of about 32 KHz. Typically, a 32KHz clock has a crystal associated with it, whereas a high frequency clock may be a precision oscillator and operate without a crystal, but it may also be a crystal controlled oscillator. In addition, although the clock inputs are illustrated as being generated from an on-chip oscillator, these clocks may also be generated outside the chip.

Multiplexer 802 is operable, in the manner illustrated, to select one of a plurality of clock signals as an input to CPU 102. However, this means a programmable oscillator function or a combination thereof with a separate oscillator. Input on line 804 is the system clock SYSCLK. This is one output of multiplexer 802. The multiplexer 802 receives as inputs a plurality of clock signals CK0, CK 1. Output 804 comprises one output and second output 806 is provided to drive ADC 128. The ADC is operable to receive an analog signal on an input 130, the input 130 being an input selected from a plurality of inputs on a line 136 via a multiplexer 134. This provides a digital output on digital bus 808. Digital output 808 allows data to be forwarded from ADC128 to CPU 102 for processing of the data.

The CPU 102 processes instructions at the clock rate of SYSCLK. CPU 102 periodically outputs a conversion request from control line 810 to ADC128 according to programmed instructions therein so that independently operating ADC128 can convert analog values on an analog input to digital values as digital data. CPU 102 also provides configuration information to ADC128 and also provides a select input signal to analog multiplexer 134. Thus, the ADC128 will be connected to one of the analog input lines 136 to sample analog values thereon during the tracking mode, and then process the sampled analog information in the ADC using the SAR data conversion algorithm. As described above, this SAR conversion algorithm requires a conversion clock of multiple internal clocks to determine the bit values of the resulting digital values. Therefore, if the ADC has a resolution of n bits, n-bit tests are required to be performed n times, and a conversion clock of at least n clocks is required to complete the data conversion operation. Thereafter, the result of the conversion, i.e., the resulting digital value, will be forwarded to an internal register for transfer to the digital bus 808. As described above, multiplexer 802 is operable to output a clock signal to independently clock ADC128 with a higher frequency conversion clock during a conversion operation to complete the conversion operation in a very short period of time, in one embodiment, a single clock cycle of SYSCLK. This provides a number of benefits. First, the power of the ADC128 during non-conversion operation is reduced so that it utilizes less power. Second, the results are available at an earlier time. For example, a conversion request may require that the multiprocessor chip have an analog multiplexer 134 operable to receive eight analog input values on analog input lines 136. In this case, the conversion request may initiate an operation in which the next analog input to multiplexer 135 on input line 136 will be selected at the end of each conversion cycle for each analog input line, or each conversion request may be associated with a single analog input requiring each conversion request in order to configure multiplexer 134 for that conversion request. Thus, analog information from all eight analog lines 136 may be obtained in a significantly shortened period of time. A third benefit is noise management, since the entire sub-clocking operation may occur within one clock cycle of SYSCLK. Since all edges of the conversion clock occur at times that do not overlap with the clock edges of SYSCLK operating the digital portion of the processing system, any noise generated by the digital system operation does not interfere with the analog sampling operation.

Referring now to fig. 9, fig. 9 illustrates a timing diagram for a sub-clocking operation. Since the processing portion of the chip operates based on SYSCLK, the switching operation is initiated in synchronization with the rising edge 902 of SYSCLK. The transition start operation is initiated with signal CNVST at edge 904. When CNVST falls at edge 906, the START signal rises at edge 908. This corresponds to a tracking signal that falls at edge 910 when the analog signal is sampled at high frequency. This essentially locks the sampled analog signal to the switched capacitor input. Thereafter, the high speed clock, ADC CLK, is activated, indicating that the ADC is clocked by this clock signal as a conversion clock

128 is clocked, which is at edge 912. Then in the event of a full power-off and power-on operation, the ADC CLK is allowed to stabilize, then the BUSY signal goes high on edge 914. Thereafter, the SAR conversion operation is initiated with ADC CLK at edge 916. When the SAR conversion operation is complete, as shown by edge 918, the ADC CLK signal is no longer needed and goes low at edge 920, indicating that the high speed clock is powered down or off, although it still remains in the operational mode. The BUSY signal goes low at edge 924 and the TRACK signal goes high at edge 926 to sample the next analog input signal.

When the SAR conversion operation is complete, the digital result is forwarded to an output data register. The data remains in this output data register until the CPU 102 is ready to retrieve the result, the CPU 102 operating at the SYCLK rate. The operation of the ADC128 is completely transparent to the operation of the CPU 102. In the embodiment shown in fig. 9, SYSCLK is shown at a substantially lower frequency than ADC CLK, but in one embodiment where ADC128 is clocked with a 20MHz signal and SYSCLK is a 32MHz signal, the difference is over 500X. Thus, the entire conversion operation or a plurality of conversion operations may be realized within only a portion of a single cycle SYSCLK. Also, noise associated with digital processing of data by the CPU is isolated from SAR conversion operations.

Referring now to fig. 10, fig. 10 illustrates a more detailed timing diagram of the embodiment of fig. 9 illustrating SAR conversion operations. In this embodiment, it can be seen that the START signal goes high at edge 904. (it should be understood that the large number of internal delays considered are not detailed in the various timing diagrams, but are necessary to ensure proper operation.) the ADC CLK signal is enabled once the TRACK signal goes low at edge 910. Although not required, the ADC can be clocked at high frequency up to speed. A certain amount of delay 1002 will be provided for this operation. After three clock cycles, in a simplified example, the SAR conversion operation will be initiated at the clock edge 1004 of the high frequency clock. This results in testing the MSB during clock cycle 1006, followed by testing of the remaining bits 10, 9. At the end of the transition period, at edge 1008, the transition operation is completed, all within less than half of the SYSCLK period. The data is then forwarded to an output data register in which only a single conversion is configured to occur in response to the conversion request. The entire data forwarding, SAR conversion operation, and the like are performed at the high frequency rate of the high frequency ADC conversion clock ADC CLK. Since the mixed signal device is intended to operate at high frequencies, all of its components are capable of operating at these high frequencies. For example, while the low clock frequency may be as low as 32KHz, the sampling frequency of a conventional ADC is 200KHz and the SAR clock can and will run at a much higher frequency. Thus, it can be seen that when the system clock is configured to operate at a low frequency, the throughput of the ADC can be significantly increased by providing the SAR conversion clock having a frequency substantially higher than the frequency of the system clock SYSCLK, as compared to when the system clock SYSCLK operates at a lower frequency in the ADC.

Referring now to fig. 11, fig. 11 illustrates a more detailed block diagram of the internal operation of the ADC128 described above with reference to fig. 2. SAR logic block 212 has SAR controller 1102 and SAR register 1104 associated therewith. SAR controller 1102 is configured to receive the output of comparator 208 and then adjust the digital output of SAR register 1104 in accordance with a SAR conversion algorithm (conventional data conversion algorithm) for input to DAC 210. The final digital value stored in SAR register 1104 represents the converted digital value at the end of the conversion period. This is also the output provided on the digital bus 214 to the DAC 210 for use in subsequent approximation operations. The bus 214 is connected in this embodiment to a FIFO1106 for storing data therein. Typically this is a hold register or a data output register. This FIFO1106 is used to interface with a data bus 808 so that CPU 102 can access it, the data bus 808 being the system data bus. The FIFO1106 provides a flexible data storage location so that data is input to it at a faster rate than it is extracted from it. Although the FIFO is described as a flexible storage device, Random Access Memory (RAM) may also be utilized.

The FIFO1106 is controlled by the SAR controller 1102. The SAR register and SAR controller 1104 may be configured by configuration registers 1108 such that multiple samples may be taken in response to a single conversion request. This transition request may be a transition request from CPU 102, or it may be responsive to an internal timer in SAR controller 1102 that causes data to be sampled at a predetermined time.

When configured to sample multiple times in response to a conversion request during a conversion operation, the data will be generated at a faster rate than the CPU 102 will extract the data from the ADC128 over the data bus 808. Therefore, when the CPU 102 generates a transition request, data will be generated very early on the next clock edge of SYSCLK. Since the CPU 102 operates according to instructions whose fetch rate is not faster than the SYSCLK rate, this data must be fetched over multiple clock cycles of the CPU. The FIFO1106 (or RAM), which is an elastic memory buffer, can generate this information faster than the CPU 102 can extract the data.

Referring now to fig. 12, fig. 12 illustrates a timing diagram of a repeat function, which is a function that allows a plurality of conversions to occur after a conversion request is generated by the CPU 102. A transition start request is received at edge 1202 and this causes the TRACK signal to go low at edge 1204 and the high frequency clock to be active at edge 1206. This will initiate a first SAR conversion operation at edge 1208 that will be completed at edge 1210. This data is then converted to data D0 in this operation. The high frequency clock is then turned off at edge 1214, or remains unchanged during this time, depending on power saving requirements. The TRACK signal then goes high at edge 1212 to re-complete sampling of another analog signal for a predetermined amount of time in the pre-tracking operation. A high frequency clock is not required during this sampling and can therefore be turned off. After sampling new data on the associated analog input line, the TRACK signal will again go low at edge 1216 and the high frequency clock signal will again be active at edge 1218. This will start the second SAR conversion operation at edge 1220, resulting in data at time 1222, which is forwarded as data D1. Each of these data outputs is stored at a separate location in the FIFO1106, where the write pointer will be incremented for each SAR conversion operation. Note that only a single transition request at edge 1202 is needed to initiate multiple transition state machine operations at a high frequency clock. Additionally, although illustrated as being stored in the FIFO1106, in practice the data may be processed using combinatorial logic contained in and part of the ADC that allows the data to be processed to provide, for example, an average thereof. This would require accumulators and logic to perform the shift. Thus, the values are summed with the preceding values and then averaged at the end of all conversion operations, or a sliding average may be taken. Alternatively, the sum may be accumulated using an accumulator and then the averaging operation is performed using a processor. This would require only a single register to store and output the data. Of course, the above-mentioned abort feature may also be implemented in conjunction therewith during sub-clocking operations.

Referring now to fig. 13, fig. 13 illustrates a timing diagram of a post-tracking operation in which the ADC is powered up when a transition START request is received, such that a delay is required before the transition operation is initiated. An initial operation is initiated with the rising edge of the SYSCK signal at edge 1302, with the CNVST signal rising at edge 1304. The START signal rises at edge 1308 and the power on signal PUP rises at edge 1310. During this time, the high frequency clock is illustrated as being operational. However, it should be understood that the high frequency clock is not connected to other circuitry at this time, so that only the circuitry associated with the high frequency clock may draw higher power than those associated with the low frequency clock operation.

During power-up, the ADC128 is powered up and a high frequency clock is started. A high frequency clock requires a certain amount of time to achieve a well-behaved operating speed, but the ADC takes longer to "tune". A period of time 1312 is provided herein, the period 1312 being illustrated as a number of clock cycles of the high frequency clock, e.g., four or more. The ADC reset function automatically raises TRACK when the power-on signal is generated, but there are time periods when the analog input signal must be present in order to have valid sampling. To ensure that there is a sufficient amount of sampling time, the post-tracking characteristic is utilized to "force" the TRACK signal to rise for a predetermined minimum amount of time. After an adjustment period 1312 defined by the internal counter, a post-tracking timer/counter is started. This timer/counter delays the start of the conversion operation by five high frequency clock cycles, depending on the register value. Thereafter, TRACK goes low and the conversion operation is started.

Referring now to fig. 14, fig. 14 illustrates a more simplified diagram than fig. 8. In this embodiment, only two clocks are provided, a 32KHz clock on line 1402 and a high frequency clock on line 1404 generated by high frequency clock generator 1406. The 32KHz clock and the high frequency clock are input to two inputs of a multiplexer 1408 having one output on line 1410. This is the SYSCLK output to the CPU 102. In addition, the output of multiplexer 1408 is input to one input of ADC multiplexer 1416, the other input of ADC multiplexer 1416 being connected to high frequency clock line 1404. ADC multiplexer 1416 is used to select between the SYSCLK signal or the high frequency clock input so that system 1414 can operate independently of the clock of ADC 128. Multiplexer 1416 provides a clock input to ADC 128.

Referring now to fig. 15a-15c, fig. 15a-15c illustrate a diagram of ADC registers, which are a tracking register ADC0TK, a configuration register ADC0CF, and a control register ADC0CN, where "0" indicates that more than one ADC may be provided on an integrated circuit. Referring specifically to fig. 15a, the ADC0TK register has a number of bits associated with it. Four bits are provided for ADC pulse on time (adppwr). This field controls the power-on time during the ADC pulse conversion. The ADC is enabled for a minimum of 200nsec before the first conversion occurs. A single bit is provided for ADC pre-tracking enable operation (PRETRK). When set, the ADC tracks continuously between transitions. A single bit is provided for ADC trace post enable operation (postrk) which, when set, will control the ADC to trace 2 between individual conversion starts and conversion starts^*(ADCTM +1)/ADC CLK. The ADC trace time (ADCTM) is a two-bit field that controls the post-trace time as described above.

The configuration register of fig. 15b controls the basic configuration of the system. Five bits are provided for ADC clock rate control (ADCSC), which controls the sampling clock rate of the ADC. FCLK is the current system clock when pulse enable is not selected and is a maximum of 25MHz when pulse enable is selected. Two bits are provided for ADC repetition count (ADC rpt), which is a field that controls the number of transitions that occur between ADC interrupts or during ADC transition pulses. Note that after the end of the transition, the interrupt flag is set, but when the transition repetition count is not "1", the interrupt is set only after the last transition. The ADC calibration enable (CALEN) is an enable bit that enables the ADC calibration mode. This feature is not described here.

Referring to the register of FIG. 15c, the control bits provide various control functions. There is a single ADC enable bit (ADCEN) that enables the ADC. A single ADC pulse mode enable (burst) is provided that enables the ADC to perform pulse conversion. In the pulse mode, the ADC operates according to the 20MHz internal high frequency oscillator of the disclosed embodiment, as described above. Based on each conversion start signal, the ADC is enabled and allowed to stabilize 200nsec^*ADCPWR such that the energization time is incremented in 200nsec increments. One or more conversions are then performed (based on the value of ADCRPT) and the ADC is powered down. If ADCEN is also set, power on and power off operations are skipped. If ADCEN is 0, then the ADC will be configured for post-tracking. In addition, either before or after tracing may be used. The ADC conversion completion interrupt (ADCINT) bit provides an interrupt flag that is set at the end of each conversion. If the transition repetition count (ADCRPT) is not "1", then an interrupt is set only after the last transition. When ADCCM starts the transition sequence at 0, the ADC busy (ADBUSY) bit is written to ADBUSY. The read of ADBUSY (═ 1) indicates the time when the transition is in progress. The ADC window compare interrupt (adwin) provides an interrupt flag set at the end of the conversion that satisfies the window compare condition (or other normal comparison) for the interrupt characteristics. If the transition repetition count (ADCRTP) is not "1", then an interrupt is set only after the last transition. The ADC result adjust bit (ADRJUST) is set such that when "0" is asserted, the ADC result is aligned to the right, otherwise the result is aligned to the left. An ADC conversion start source (ADCCM) provides a field that sets a conversion source.

Referring now to FIG. 16, FIG. 16 illustrates a flow chart of the sub-clocking feature initiated at block 1602. The routine then proceeds to decision block 1604 to determine whether a translation request has been received. As described above, this transition request may be in response to an external rising edge of the external CNVST signal, or in response to a timer overflow constituting an internal request or write ADBUSY. When a convert request is received, the program proceeds to decision block 1606 to determine if the BUSY flag, which indicates that the convert request cannot be processed and will be ignored, is set. When the system is ready to process the request, the program follows the NO path from decision block 1606 to decision block 1608 where it is determined whether the power-on feature has been selected. If so, this indicates that the ADC was powered on during the conversion operation, and the program follows the YES path to function block 1610 to apply power to the ADC, and then to function block 1612 to allow a certain amount of time to elapse before conversion to sample the analog value after tracking is initiated, as shown in decision block 1614. When the appropriate amount of delay has elapsed, the program proceeds to function block 1622 to run the SAR conversion algorithm at the high frequency clock rate, which was selected by CPU 102 during the prior start-up operation. As shown at decision block 1624, the program will stay with the SAR conversion algorithm until completion, at which point the program follows the yes path from there to function block 1628 to forward the data and then set the interrupt bit. The routine then proceeds to decision block 1630 to determine whether a power down operation is to be performed, which is the mode that occurs if the power on feature is selected. If so, the program follows the YES path to a function block 1632 to remove power from the ADC, and then to a return block 1634. If the power down feature has not been selected, then the routine proceeds from decision block 1632 to return block 1634.

Referring now to FIG. 17, FIG. 17 illustrates a flow chart describing a plurality of translation operations in a translation request. The routine begins at block 1702 and then proceeds to decision block 1704 to determine whether a translation request has been received. In the high frequency mode that is the subject of this flowchart, the program then enters SAR conversion block 1706 to perform SAR conversion operations at the high frequency clock rate. This is similar to the operation described with respect to the flowchart of fig. 16. The routine then proceeds to decision block 1708 to determine whether the SAR conversion is complete. When complete, the program proceeds along the YES path to decision block 1710 to determine whether the BURST _ EN function is selected. If so, the program then proceeds to decision block 1714 to determine whether any data previously collected is to be processed. If so, the program follows the YES path to a function block 1716 for processing this data. This process may maintain a running average with the previous values. If no processing is required, the program follows the NO path to function block 1718 to store the data in a FIFO (or RAM). However, if processing is occurring, the flow chart would proceed from block 1716 to block 1720 for storage of data, and the program would flow to decision block 1722 to determine whether the repeat operation is complete, i.e., so that all transitions occur within a single transition request cycle. If not, the program will return to the input of SAR conversion block 1706 along the NO path so that the operation repeats until completion, at which point the program will proceed from decision block 1722 to return block 1724 along the YES path. Note that the tracking of the analog input signal will continue during this time.

Referring now to fig. 18, fig. 18 illustrates a logic diagram of SAR controller 1102 and SAR register 1104. A SAR bit control register 1802 is provided, which is functionally equivalent to the "SAR bit register" of fig. 6. This provides a bit through the registers in sequence that indicates which bit of the SAR operation is being tested. Initially, there is a signal SAR BIT, which is input to the register 1802 and rises on the rising edge of the ADC clock. Register 1802 is clocked by the ADC clock and is reset using the CLR signal. Its first output is the MSB BITs being tested, SAR _ BIT <11 >. Each successive bit being tested provides a corresponding output, only one of which is high frequency at any given time. Each of the outputs of register 1802 is input to a clocked latch 1806. The clocked latch is operable at each rising edge of the ADC clock to latch the relevant output of the comparator when its output indicates a positive comparison or the bit value indicating the bit being tested remains high (e.g. it is a "hold" bit). When the output is latched, the register 1802 is then clocked to detect the next bit. In operation, with the associated output of the updated clock latch 1806, the SAR BIT is raised at the first rising edge of the ADC clock on the input to the first register 1802 to initiate the conversion operation and test the MSB, and at the next rising edge of the ADC clock, the SAR BIT is taken low and tests the second MSB, and so on. Thus, this clocked latch provides the basic function of the SAR register, i.e., its historical aspect.

Each output of register 1802 is an input to one input of an associated plurality of input OR gates 1810 and each of the associated outputs of the clock latch is connected to another input of the associated plurality of input OR gates 1810. The output of each of the OR gates 1810 for each of the bits tested is connected to the bus 1812. Thus, this will force the output of the associated OR gate 1810 high as long as the bit is being tested, and when the test is completed, the latched value is forced high if the test is "1" and low if the test is "0". Thus, for each ADC clock rising edge, not only will the current bit being tested go high, but the prior bit being tested will remain high. This is provided to the ADC 210 via a bus 214, which bus 214 is the same as bus 1812. In addition, the bus 1812 is input to a parallel/serial converter 1814 that provides the function of the multiplexer 216 in fig. 2. The parallel/serial converter 1814 provides a serial data output on line 1818. This will be described in more detail below.

To provide an output for the CPU 102, a second register 1820 is provided. Register 1812 has an associated bit for each bit tested. Each input of register 1820 is connected on bus 1812 to the associated bit with the clock input of register 1820 connected to the LOAD signal and the reset input of register 1820 connected to the SAR reset signal. Each output of register 1820 is connected to a respective line of bus 1824, which in turn is connected to output register 1826 for connection to bus 808.

The output of register 1802 associated with SAR BIT <0> is input to SAR overflow register flip-flop 1830, there are three flip-flops 1830. This causes the SAR bit passing through register 1802 to be delayed so that the control signal can be derived therefrom. The output SOR <1> bit of the first flip-flop 1830 is input to the D input of the flip-flop 1832, which flip-flop 1832 is clocked by the inverse of ADC _ CLK such that the output occurs on the falling edge of ADC _ CLK to provide the LOAD signal. Thus, the LOAD signal is provided 1.5 clock cycles later than the last test SAR BIT <0 >. The reset input is connected to the output of an OR gate 1834 and one input of the OR gate 1834 is connected to the output SOR <2> output of the second register 1830 and the other input of the OR gate 1834 is connected to the CLR signal.

Referring now to fig. 19, fig. 9 illustrates a logic diagram of the parallel to serial converter 1814, multiplexer 216. This architecture is configured with multiple drivers 1902, each driver 1902 having an input connected to the output bit of bus 1812 for a 12-bit ADC: one of SAR <11>, SAR <10>,. SAR <0 >. Driver 1902 associated with SAR <11> is selected or gated with a test BIT SAR BIT <10> that is output by the Q output of flip-flop 1802 associated with the second flip-flop 1802. Thus, when the next lower bit is being tested, the previous bit is being output. The last of the drivers 1902 receives the input SAR <0>, i.e., LSB, and through the output of a first flip-flop 1830(SAR overflow register): bit SOR <1> is gated. Thus, the previous bit tested prior to the current bit under test is provided on output line 1818.

Referring now to fig. 20, fig. 20 illustrates an alternative embodiment in which a plurality of FIFOs 2002 are provided, each of the plurality of FIFOs 2002 being associated with a plurality of analog inputs, eight analog inputs being present in the disclosed embodiment. Thus, there are FIFO <7>, FIFO <6>,. FIFO <0 >. The output of each of the FIFOs 2002 is connected to the output bus 808. The SAR logic block 212 is used to cause each input to be tested one or more times during a conversion operation in response to a conversion request. Thus, in the disclosed embodiment, the SAR logic block 212 will control the analog multiplexer 134 to select one of the eight analog input lines 136. This operation can be performed in two ways. First, each FIFO may have multiple storage locations, an associated analog input line is selected, multiple conversions are then performed sequentially on the data thereon, the data is then stored in the storage locations, and then the multiplexer goes to the next analog input line, then filling the next FIFO 2002. Alternatively, the analog multiplexer may operate in such a way that the first conversion result is based on the first analog input line, and then the multiplexer goes to the next analog input line, samples the data, converts it, and stores it in the next FIFO 2002.

Referring now to fig. 21, a timing diagram for the second operation described with reference to fig. 20 is illustrated. The transition start signal starts at rising edge 2102 and then the power on signal is initiated at edge 2104. The ADC clock is then activated at edge 2106 and the tracking signal is activated for subsequent sampling of the data on the selected line. The transition operation for the first transition begins at edge 2108 where the trace signal goes low, and then begins at edge 2110 for the first transition. This transition is associated with the first analog input line and the result stored in the first FIFO for bit <7 >. This will occur after the conversion operation is completed at edge 2112. The tracking signal then rises again at edge 2114 and analog multiplexer 134 is controlled to select the next analog input line to be sampled. This will result in the conversion of the analog input data being performed continuously at a high frequency rate without the CPU 102 being required to provide another conversion start request; in fact, the entire conversion operation will be completed in less than a single SYSCLK clock cycle. This allows each FIFO 2002 to be filled and the CPU 102 need only access the data bus 808 and the contents of the FIFOs 2002, which FIFOs 2002 require some type of enable and read pointer control, which are conventional circuits and therefore not shown.

Although the preferred embodiments have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (40)

1. A method for clocking the operation of a successive approximation register analog to digital converter, the method comprising the steps of:

providing a low frequency clock and a high frequency clock;

tracking the analog input voltage during a tracking phase using a low frequency clock to sample a value of the analog input voltage;

starting a transition period that references an edge of a low frequency clock;

converting the sampled data in a conversion operation during a conversion period, the conversion operation requiring a plurality of conversion clock cycles; and

the timing of at least a portion of the conversion operation is controlled using the high frequency clock as the conversion clock during the conversion period.

2. The method of claim 1, wherein the step of controlling the timing of the at least a portion of the conversion operation comprises: controlling the timing of the at least a portion of the conversion operation to be proximate in time to the initiating step using the high frequency clock during the conversion period.

3. The method of claim 1, wherein at least a portion of the conversion operation comprises a full conversion operation.

4. The method of claim 1, wherein successive approximation register analog-to-digital converter has n-bit resolution and the converting operation comprises the steps of:

testing each of the n bits during a transition operation to determine a logic state thereof, the timing of the testing being determined by a transition clock used to generate a transition clock cycle; and

in the controlling step, a conversion clock is generated from a high frequency clock for the at least a portion of the conversion operation,

wherein the tracking operation comprises the steps of:

during the tracking phase, a transition clock is generated from the low frequency clock.

5. The method of claim 4, wherein generating a transition clock from a high frequency clock comprises: generating a conversion clock only during the at least a portion of the conversion operation.

6. The method of claim 4, wherein the timing of the at least a portion of the conversion operation does not include the time to test all n bits.

7. The method of claim 4, wherein the timing of the at least a portion of the conversion operation includes a time to test all n bits.

8. The method of claim 1, wherein the initiating step is responsive to generation of a transition initiation signal generated by a processing unit.

9. The method of claim 8, wherein the processing unit operates according to a low frequency clock, and in the step of controlling the timing of at least a portion of the conversion operation, the processing unit continues to operate at the low frequency clock.

10. The method of claim 1, wherein the successive approximation register analog to digital converter operates in a power-on mode and a power-off mode, when in the power-off mode, further comprising the steps of:

operating a successive approximation register analog-to-digital converter in a low power mode;

receiving a power-on signal, and in response to the received power-on signal:

applying power to the successive approximation register analog-to-digital converter,

initiating said trace operation, delaying the start of a conversion cycle by a predetermined delay to stabilize the successive approximation register analog to digital converter, and

and after the conversion period is finished, removing the power supply to the successive approximation register analog-digital converter.

11. The method of claim 10, further comprising introducing a known programmable amount of delay to force a trace operation to continue for the programmable amount of delay and delaying the start of the conversion period by the programmable amount of delay.

12. A method of operating a successive approximation register analog-to-digital converter in a mixed signal processing system, the method comprising the steps of:

operating the digital processing section with a first and low frequency clock;

generating a conversion request to instruct a successive approximation register analog-to-digital converter to initiate a conversion operation;

operating the successive approximation register analog-to-digital converter in a tracking phase with a first and low frequency clock to track an analog value on an analog input in response to generation of a conversion request;

in response to generation of a conversion request, operating a successive approximation register analog-to-digital converter in a conversion operation with a second and high frequency clock to convert analog values on an analog input to digital values in a successive approximation register conversion period, the second and high frequency clock having a clock frequency higher than a frequency of the low frequency clock;

storing the resultant digital value to be processed by the digital processing section; and

after storing the resultant digital value, the resultant digital value is processed by a digital processing section.

13. The method of claim 12, wherein the conversion operation is completed within a single cycle of the low frequency clock.

14. The method of claim 12, wherein,

the step of operating the successive approximation register analog to digital converter in a data conversion operation includes: in response to the generation of the conversion request, operating the successive approximation register analog-to-digital converter in a plurality of data conversion operations with a second and high frequency clock so as to convert the analog value on at least one analog input to a plurality of corresponding digital values, respectively, within an associated successive approximation register conversion period;

a storing step for storing a representation of the resulting digital value; and is

The processing step is for processing the representation of the resulting digital value.

15. The method of claim 14, wherein the storing step is for storing each of the resulting digital values independently.

16. The method of claim 14, wherein the storing step is for storing the accumulated digital value of the resulting digital values as a single value.

17. The method of claim 16, wherein the resulting digital values are all associated with a single analog input.

18. The method of claim 17, wherein the step of processing by the digital processing section is for determining an average of the accumulated digital values.

19. The method of claim 14, wherein a plurality of analog inputs are provided, each analog input for receiving a separate analog signal, and further comprising the step of selecting, with a multiplexer, ones of the plurality of analog inputs for connection with a successive approximation register analog-to-digital converter to thereby perform each data conversion operation in response to the generation of the conversion request.

20. The method of claim 14, wherein all data conversion operations are completed within one cycle of the low frequency clock.

21. A processing system including a successive approximation register analog-to-digital converter, comprising:

a low frequency clock and a high frequency clock;

a sampling device for tracking the analog input voltage during a tracking phase using a low frequency clock to sample a value of the analog input voltage;

a transition engine to initiate a transition cycle that references an edge of the low frequency clock;

the conversion engine converts the sampled data in a conversion operation requiring a plurality of conversion clock cycles during a conversion period; and

a timing engine for controlling timing of at least a portion of the conversion operation during the conversion period using the high frequency clock as a conversion clock.

22. The system of claim 21, wherein the timing engine is to utilize the high frequency clock during the conversion cycle to control timing of the at least a portion of the conversion operation to be proximate in time to an operation of the conversion engine to initiate the conversion cycle.

23. The system of claim 21, wherein the at least a portion of the translation operations includes all translation operations.

24. The processing system of claim 21, wherein successive approximation register analog-to-digital converter has n-bit resolution and the conversion engine comprises:

a bit tester for testing each of the n bits during a transition operation to determine a logic state of the bit, the timing of the testing being determined by a transition clock used to generate a transition clock cycle; and is

The timing engine to generate a conversion clock for the at least a portion of the conversion operation from the high frequency clock,

wherein the sampling device is configured to generate a conversion clock from the low frequency clock during the tracking phase.

25. The processing system of claim 24, wherein the timing engine is to generate the conversion clock only during the at least a portion of the conversion operation.

26. The processing system of claim 24, wherein the timing of the at least a portion of the conversion operation does not include the time to test all n bits.

27. The processing system of claim 24, wherein the timing of the at least a portion of the conversion operation includes a time to test all n bits.

28. The processing system of claim 21, wherein the transition engine is to initiate the transition operation in response to generation of a transition initiation signal generated by a processing unit.

29. The processing system of claim 28, wherein the processing unit operates according to the low frequency clock and in the process of controlling the timing of at least a portion of the conversion operation by the timing engine, the processing unit operating continuously with the low frequency clock.

30. The processing system of claim 21, wherein the successive approximation register analog-to-digital converter operates in a power-on mode and a power-off mode, the conversion engine when in the power-off mode to perform the steps of:

operating a successive approximation register analog-to-digital converter in a low power mode;

receiving a power-on signal, and in response to the received power-on signal:

applying power to the successive approximation register analog-to-digital converter,

the tracking operation is initiated and the tracking operation is initiated,

delaying the start of the conversion cycle by a predetermined delay to stabilize the successive approximation register analog-to-digital converter, an

And after the conversion period is finished, removing the power supply to the successive approximation register analog-digital converter.

31. The processing system of claim 30, further comprising a delay block for introducing a known programmable amount of delay to force the tracking operation to continue for the programmable amount of delay and to delay the start of the conversion cycle by the programmable amount of delay.

32. A mixed signal processing system for controlling the operation of a successive approximation register analog to digital converter, comprising:

a digital processing section;

a first and low frequency clock for operating the digital processing portion;

a second and high frequency clock having a clock frequency higher than the frequency of the low frequency clock,

the digital processing part generates a conversion request to instruct the successive approximation register analog-to-digital converter to start a conversion operation;

a conversion engine for operating the successive approximation register analog-to-digital converter in a trace phase with a first and low frequency clock to trace an analog value on an analog input in response to the generation of the conversion request, and operating the successive approximation register analog-to-digital converter in a conversion operation with the second and high frequency clock to convert the analog value on the analog input to a digital value in a successive approximation register conversion period;

a memory for storing a resulting digital value to be processed by the digital processing section; and

the digital processing section processes the resultant digital value after the resultant digital value is stored in the memory.

33. The processing system of claim 32, wherein the conversion operation is completed within a single cycle of the low frequency clock.

34. The processing system of claim 32, wherein:

the conversion engine operating the successive approximation register analog-to-digital converter in a plurality of data conversion operations with the second and high frequency clock in response to generation of the conversion request to convert the analog value on the at least one analog input to a plurality of corresponding digital values, respectively, in an associated successive approximation register conversion cycle;

the memory is for storing a representation of the resulting digital value; and is

The digital processing section is for processing a representation of the resulting digital value.

35. The processing system of claim 34, wherein the memory is to store each of the resulting digital values independently.

36. The processing system of claim 34, wherein the memory is to store an accumulated digital value of the resulting digital values as a single value.

37. The processing system of claim 36, wherein all of the resulting digital values are associated with a single analog input.

38. The processing system of claim 37, wherein the digital processing section is configured to determine an average of the accumulated digital values.

39. The processing system of claim 34, wherein a plurality of analog inputs are provided, each for receiving a separate analog signal, and further comprising a multiplexer for selecting ones of the analog inputs for connection with the successive approximation register analog-to-digital converter for performing each of the data conversion operations by the conversion engine in response to generation of a conversion request.

40. The processing system of claim 34, wherein all data conversion operations are completed within one cycle of the low frequency clock.