HK1104015B - Fluid ejection device - Google Patents

Description

Fluid ejection device

Citations to related applications

This application is related to the patent application serial No. [ not yet assigned ], attorney docket No.200209168-1, entitled "Fluid ejection device"; patent application serial No. (not yet assigned), attorney number 200208780-1, entitled "Fluid Ejection Device With address generator"; patent application serial No. [ not yet assigned ], No.200311485-1, entitled "Device With Gates Configured In a Loop structure"; patent application serial No. [ yet unassigned ], No.200210152-1, entitled "Fluid Ejection Device"; and patent application serial No.200209237-1, entitled "fluid ejection Device With Identification cell," each of which is assigned to the assignee of the present application and filed on even date herewith, and each of which is hereby incorporated by reference in its entirety as if fully disclosed herein.

Background

As one embodiment of a fluid ejection system, an inkjet printing system may include a printhead, an ink supply to provide ink to the printhead, and an electronic controller to control the printhead. As one embodiment of a fluid ejection device, a printhead ejects ink drops (ink drops) through a plurality of orifices or nozzles. The ink is directed to a print medium (e.g., paper) to print an image on the print medium. The nozzles are typically arranged in one or more arrays such that properly sequenced ejection of ink from the nozzles causes characters or other images to be printed upon the print medium as the printhead and the print medium are moved relative to each other.

In a typical thermal inkjet printing system, the printhead ejects ink drops through nozzles by rapidly heating small volumes of ink located in vaporization chambers. The ink is heated using a small electric heater, such as a thin film resistor referred to herein as a firing resistor. The ink is heated so that the ink vaporizes and is ejected through the nozzles.

To eject a drop of ink, an electronic controller controlling the printhead activates an electrical current from a power source external to the printhead. An electrical current is passed through a selected firing resistor to heat the ink in a corresponding selected vaporization chamber and eject the ink through a corresponding nozzle. A known drop generator includes an ignition resistor, a corresponding vaporization chamber, and a corresponding nozzle.

As inkjet printheads have evolved, the number of drop generators in a printhead has increased to improve printing speed and/or quality. An increase in the number of drop generators per printhead results in a corresponding increase in the number of input pads (input pads) required to fire an increased number of firing resistors on the printhead die. In one type of printhead, each firing resistor is coupled to a corresponding input pad to provide power to actuate the firing resistor. As the number of firing resistors increases, one input pad per firing resistor becomes impractical.

The number of drop generators per input pad increases significantly in another type of printhead with primitive (primary). A single power line provides power to all firing resistors in one picture element. Each firing resistor is coupled in series with a power supply line and a drain-source path of a corresponding Field Effect Transistor (FET). The gate of each FET in a picture element is coupled to a separately energizable address lead that is common to multiple picture elements.

Manufacturers continue to reduce the number of input pads on the printhead die and increase the number of drop generators. A printhead with fewer input pads is generally less costly than a printhead with more input pads. Also, printheads with more drop generators typically print at higher quality and/or print speeds. To maintain cost and provide a particular print line height (swing height), printhead die size may not change significantly as the number of drop generators increases. As drop generator density increases and the number of input pads decreases, printhead die layouts can become increasingly complex.

For these and other reasons, the present invention is needed.

Drawings

FIG. 1 illustrates one embodiment of an inkjet printing system.

FIG. 2 is a diagram illustrating a portion of one embodiment of a printhead die.

FIG. 3 is a diagram illustrating a layout of drop generators positioned along an ink feed slot (ink feed slot) in one embodiment of a printhead die.

FIG. 4 is a diagram illustrating one embodiment of a firing cell employed in one embodiment of a printhead die.

FIG. 5 is a schematic diagram illustrating one embodiment of an inkjet printhead firing cell array.

FIG. 6 is a schematic diagram illustrating one embodiment of a pre-charged firing cell.

FIG. 7 is a schematic diagram illustrating one embodiment of an inkjet printhead firing cell array.

FIG. 8 is a timing diagram illustrating the operation of one embodiment of an array of firing cells.

FIG. 9 is a diagram illustrating one embodiment of an address generator in a printhead die.

Fig. 10A is a diagram illustrating one shift register unit in the shift register.

Fig. 10B is a diagram illustrating a direction circuit.

Fig. 11 is a timing diagram illustrating the operation of the address generator in the forward direction.

Fig. 12 is a timing diagram illustrating the operation of the address generator in the reverse direction.

FIG. 13 is a block diagram illustrating one embodiment of two address generators and six fire groups in a printhead die.

FIG. 14 is a timing diagram illustrating forward and reverse operation of an address generator in a printhead die.

FIG. 15 is a block diagram illustrating one embodiment of address generators, latch circuits, and six fire groups in a printhead die.

FIG. 15 is a diagram illustrating one embodiment of bank select address generators in a printhead die.

FIG. 16 is a diagram illustrating one embodiment of a direction circuit.

FIG. 17 is a timing diagram illustrating the operation of one embodiment of a bank select address generator in the forward direction.

FIG. 18 is a timing diagram illustrating the operation of one embodiment of a bank select address generator in the reverse direction.

FIG. 19 is a block diagram illustrating one embodiment of two bank select address generators and six fire groups in a printhead die.

FIG. 20 is a timing diagram illustrating forward and reverse operation of one embodiment of two bank select address generators in a printhead die.

Detailed Description

In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as "top," "bottom," "front," "back," "leading," "trailing," etc., is used in connection with the orientation of the figures being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.

FIG. 1 illustrates one embodiment of an inkjet printing system 20. Inkjet printing system 20 constitutes one embodiment of a fluid ejection system that includes a fluid ejection device, such as an inkjet printhead assembly 22, and a fluid source assembly, such as an ink source assembly 24. Inkjet printing system 20 also includes a mounting assembly 26, a media transport assembly 28, and an electronic controller 30. At least one power supply 32 provides power to the various electrical components of inkjet printing system 20.

In one embodiment, inkjet printhead assembly 22 includes at least one printhead or printhead die 40 that ejects drops of ink through a plurality of orifices or nozzles 34 toward print medium 36 so as to print onto print medium 36. The printhead 40 is one embodiment of a fluid ejection device. Print medium 36 may be any type of suitable sheet material, such as paper, card stock, transparencies, mylar, fabric, and the like. Typically, nozzles 34 are arranged in one or more columns or arrays such that properly sequenced ejection of ink from nozzles 34 causes characters, symbols, and/or other graphics or images to be printed upon print medium 36 as inkjet printhead assembly 22 and print medium 36 are moved relative to each other. While the following description refers to the ejection of ink from printhead assembly 22, it should be understood that other liquids, fluids, or flowable materials, including clear fluid, may be ejected from printhead assembly 22.

Ink supply assembly 24, which is one embodiment of a fluid supply assembly, provides ink to printhead assembly 22 and includes a reservoir 38 for storing ink. As such, ink flows from reservoir 38 to inkjet printhead assembly 22. Ink supply assembly 24 and inkjet printhead assembly 22 may form a one-way ink delivery system or a recirculating ink delivery system. In a one-way ink delivery system, substantially all of the ink provided to inkjet printhead assembly 22 is consumed during printing. In a recirculating ink delivery system, only a portion of the ink provided to inkjet printhead assembly 22 is consumed during printing. In this manner, ink that is not depleted during printing is returned to the ink supply assembly 24.

In one embodiment, inkjet printhead assembly 22 and ink supply assembly 24 are housed together in an inkjet cartridge or pen. An inkjet cartridge or pen is one embodiment of a fluid ejection device. In another embodiment, ink supply assembly 24 is separate from printhead assembly 22 and provides ink to inkjet printhead assembly 22 through an interface connection, such as a supply tube (not shown). In either embodiment, the reservoir 38 of the ink supply assembly 24 may be removed, replaced, and/or refilled. In one embodiment, where inkjet printhead assembly 22 and ink supply assembly 24 are housed together in an inkjet cartridge, reservoir 38 includes a local reservoir located in the cartridge and may also include a larger reservoir located separately from the cartridge. In this way, a separate, larger container is used to refill the local container. Accordingly, the separate, larger container and/or the local container may be removed, replaced and/or refilled.

Mounting assembly 26 determines the position of inkjet printhead assembly 22 relative to media transport assembly 28, and media transport assembly 28 determines the position of print medium 36 relative to inkjet printhead assembly 22. Thus, print zone 37 is defined as being proximate to nozzles 34 in an area between inkjet printhead assembly 22 and print medium 36. In one embodiment, inkjet printhead assembly 22 is a scanning type printhead assembly. As such, mounting assembly 26 includes a carriage (not shown) for moving inkjet printhead assembly 22 relative to media transport assembly 28 to scan print medium 36. In another embodiment, inkjet printhead assembly 22 is a non-scanning type printhead assembly. In this manner, mounting assembly 26 secures inkjet printhead assembly 22 in a specified position relative to media transport assembly 28. Media transport assembly 28, therefore, determines the position of print medium 36 relative to inkjet printhead assembly 22.

Electronic controller or printer controller 30 typically includes a processor, firmware, and other electronics, or any combination thereof, for communicating with and controlling inkjet printhead assembly 22, mounting assembly 26, and media transport assembly 28. Electronic controller 30 receives data 39 from a host system, such as a computer, and typically includes memory for temporarily storing data 39. Typically, data 39 is sent to inkjet printing system 20 along an electronic, infrared, optical, or other information transfer path. Data 39 represents, for example, a document and/or file that needs to be printed. As such, data 39 forms a print job for inkjet printing system 20 and includes one or more print job commands and/or command parameters.

In one embodiment, electronic controller 30 controls inkjet printhead assembly 22 to eject ink drops from nozzles 34. In this manner, electronic controller 30 defines a pattern of ejected ink drops that form characters, symbols, and/or other graphics or images on print medium 36. The pattern of ejected ink drops is determined by the print job commands and/or command parameters.

In one embodiment, inkjet printhead assembly 22 includes a printhead 40. In another embodiment, inkjet printhead assembly 22 is a wide array or multi-headed printhead assembly. In a wide array embodiment, inkjet printhead assembly 22 includes a carrier that carries printhead die 40, provides electronic communication between printhead die 40 and electronic controller 30, and provides fluid communication between printhead die 40 and ink supply assembly 24.

FIG. 2 is a schematic diagram illustrating a portion of one embodiment of a printhead die 40. Printhead die 40 includes an array of printing or fluid ejection elements 42. Printing elements 42 are formed on a substrate 44, which substrate 44 has ink feed slot 46 formed therein. In this manner, ink feed slot 46 provides ink to printing elements 42. Ink feed slot 46 is one embodiment of a fluid supply. Other embodiments of fluid supply sources include, but are not limited to, corresponding independent ink supply apertures that supply corresponding vaporization chambers, and a plurality of shorter ink supply channels that each supply a corresponding set of fluid ejection elements. Thin-film structure 48 has an ink-feed channel 54 formed therein that communicates with ink-feed slot 46 formed in substrate 44. Orifice layer 50 has a front face 50a and a nozzle opening 34 formed in front face 50 a. Orifice layer 50 also has a nozzle chamber or vaporization chamber 56 formed therein that communicates with nozzle opening 34 and ink supply channel 54 of thin-film structure 48. An ignition resistor 52 is disposed inside vaporization chamber 56, and leads 58 electrically couple ignition resistor 52 to a circuit that controls the application of current through a selected ignition resistor. The drop generator 60 referred to herein includes firing resistor 52, nozzle chamber or vaporization chamber 56, and nozzle opening 34.

During printing, ink flows from ink feed slot 46 to vaporization chamber 56 through ink feed channel 54. Nozzle opening 34 is operatively associated with firing resistor 52 such that, upon energization of firing resistor 52, ink drops within vaporization chamber 56 are ejected through nozzle opening 34 (e.g., substantially perpendicular to the plane of firing resistor 52) and toward print medium 36.

Embodiments of printhead die 40 include thermal printheads, piezoelectric printheads, electrostatic printheads, or any other type of fluid ejection device known in the art that may be integrated into a multilayer structure. Substrate 44 is composed of, for example, silicon, glass, ceramic, or a stable polymer, and thin-film structure 48 is formed to include one or more passivation or insulation layers of silicon dioxide, silicon carbide, silicon nitride, tantalum, polysilicon glass, or other suitable material. The thin-film structure 48 also includes at least one conductive layer that defines the firing resistor 52 and the lead 58. In one embodiment, the conductive layer comprises, for example, aluminum, gold, tantalum-aluminum, or other metal or metal alloy. In one embodiment, the firing cell circuitry, such as described in detail below, is implemented in substrate and thin-film layers, such as substrate 44 and thin-film structure 48.

In one embodiment, orifice layer 50 comprises an imageable epoxy resin such as the epoxy resin known as SU8, sold by Micro-Chem corporation of newtons, massachusetts. An exemplary technique for fabricating orifice layer 50 from SU8 or other polymers is described in detail in U.S. patent No.6,162,589, which is incorporated herein by reference. In one embodiment, orifice layer 50 is comprised of two separate layers, referred to as a barrier layer (e.g., a dry film photoresist barrier layer) and a metal orifice layer (e.g., a nickel, copper, iron/nickel alloy, palladium, gold, or rhodium layer) formed over the barrier layer. However, other suitable materials may be used to form orifice layer 50.

FIG. 3 is a diagram illustrating drop generators 60 disposed along ink feed slot 46 in one embodiment of printhead die 40. Ink feed slot 46 includes opposing ink feed slot sides 46a and 46 b. Drop generators 60 are disposed along each of the opposing ink feed slot sides 46a and 46 b. A total of n drop generators 60 are positioned along ink feed slot 46, with m drop generators 60 along ink feed slot side 46a, and n-m drop generators 60 along ink feed slot side 46 b. In one embodiment, n equals 200 drop generators 60 disposed along ink feed slot 46, and m equals 100 drop generators 60 disposed along each of the opposing ink feed slot sides 46a and 46 b. In other embodiments, any suitable number of drop generators 60 can be disposed along ink feed slot 46.

The ink feed slot supplies ink to n drop generators 60 located along ink feed slot 46. Each of the n drop generators 60 includes an firing resistor 52, a vaporization chamber 56, and a nozzle opening 34. Each of the n vaporization chambers 56 is fluidly coupled to ink feed slot 46 by at least one ink feed channel 54. Firing resistors 52 of drop generators 60 are energized in a controlled sequence to eject fluid from vaporization chambers 56 and through nozzles 34 to print an image on print medium 36.

FIG. 4 is a schematic diagram illustrating one embodiment of a firing cell 70 employed in one embodiment of printhead die 40. Firing cell 70 includes firing resistor 52, resistor drive switch 72, and memory circuit 74. Firing resistor 52 is part of drop generator 60. Drive switch 72 and memory circuit 74 are part of a circuit that controls the application of current through firing resistor 52. Firing cell 70 is formed in thin-film structure 48 and on substrate 44.

In one embodiment, firing resistor 52 is a thin film resistor and drive switch 72 is a Field Effect Transistor (FET). Firing resistor 52 is electrically coupled to both firing line 76 and the drain-source path of drive switch 72. The drain-source path of drive switch 72 is also electrically coupled to a reference line 78, reference line 78 being electrically coupled to a reference voltage, such as ground. The gate of drive switch 72 is electrically coupled to a memory circuit 74 that controls the state of drive switch 72.

Memory circuit 74 is electrically coupled to data line 80 and enable line 82. Data line 80 receives a data signal representing a portion of an image and enable line 82 receives an enable signal to control the operation of memory circuit 74. The storage circuit 74 stores one bit of data when it is enabled by the enable signal. The logic level of the stored data bit sets the state (e.g., on or off, conductive or non-conductive) of the drive switch 72. The enable signals may include one or more select signals and one or more address signals.

Firing line 76 receives an energy signal comprising an energy pulse and provides the energy pulse to firing resistor 52. In one embodiment, the energy pulse is provided by electronic controller 30 to have a timed start time and a timed duration to provide the appropriate energy to heat and vaporize the fluid in vaporization chamber 56 of drop generator 60. If drive switch 72 is on (conducting), the energy pulse heats firing resistor 52 to heat and eject fluid from drop generator 60. If drive switch 72 is open (non-conductive), the energy pulse does not heat firing resistor 52 and fluid remains in drop generator 60.

FIG. 5 is a schematic diagram illustrating one embodiment of an inkjet printhead firing cell array, indicated at 100. Firing cell array 100 includes a plurality of firing cells 70 arranged in n fire groups 102a-102 n. In one embodiment, firing cells 70 are arranged in six fire groups 102a-102 n. In other embodiments, firing cells 70 may be arranged in any suitable number of fire groups 102a-102n, such as four or more fire groups 102a-102 n.

The firing cells 70 in the array 100 are schematically arranged in L rows and m columns. The L rows of firing cells 70 are electrically coupled to an enable line 104 that receives an enable signal. Each row of firing cells 70, referred to herein as a row subgroup or subgroup of firing cells 70, is electrically coupled to a set of subgroup enable lines 106 a-106L. The subgroup enable lines 106a-106L receive subgroup enable signals SG1, SG2 … … SGL that enable respective subgroups of firing cells 70.

The m columns are electrically coupled to m data lines 108a-108m that receive data signals D1, D2 … … Dm, respectively. Each of the m columns includes firing cells 70 in each of the n fire groups 102a-102n, and each column of firing cells 70, referred to herein as a data line group or data group, is electrically coupled to one of the data lines 108a-108 m. In other words, each data line 108a-108m is electrically coupled to each firing cell 70 in a column, including firing cells 70 in each fire group 102a-102 n. For example, data line 108a is electrically coupled to each of the firing cells 70 in the leftmost column, including firing cells 70 in each of the fire groups 102a-102 n. Data line 108b is electrically coupled to each firing cell 70 in the adjacent column, and so on, until data line 108m is electrically coupled to each firing cell 70 in the far right column, including firing cells 70 in each of the fire groups 102a-102 n.

In one embodiment, array 100 is arranged into six fire groups 102a-102n, and each of the six fire groups 102a-102n includes 13 subgroups and eight data line groups. In other embodiments, array 100 may be arranged in any suitable number of fire groups 102a-102n and in any suitable number of subgroups and data line groups. In either embodiment, fire groups 102a-102n are not limited to having the same number of subgroups and data line groups. Rather, each fire group 102a-102n can have a different number of subgroups and/or data line groups than any other fire group 102a-102 n. In addition, each subgroup can have a different number of firing cells 70 as compared to any other subgroup, and each data line group can have a different number of firing cells 70 as compared to any other data line group.

The firing cells 70 in each of the fire groups 102a-102n are electrically coupled to one of the fire lines 110a-110 n. In FIRE group 102a, each firing cell 70 is electrically coupled to a FIRE line 110a that receives a FIRE signal or energy signal FIRE 1. In FIRE group 102b, each firing cell 70 is electrically coupled to a FIRE line 110b that receives a FIRE signal or energy signal FIRE2, and so on, through FIRE group 102n, where each firing cell 70 is electrically coupled to a FIRE line 110n that receives a FIRE signal or energy signal FIREN. In addition, each firing cell 70 in each of the fire groups 102a-102n is electrically coupled to a common reference line 112 that is grounded.

In operation, subgroup enable signals SG1, SG2 … … SGL are provided on subgroup enable lines 106a-106L to enable a subgroup of firing cells 70. The activated firing cells 70 store the data signals D1, D2 … … Dm provided on the data lines 108a-108 m. The data signals D1, D2 … … Dm are stored in the memory circuit 74 of the activated firing cell 70. Each stored data signal D1, D2 … … Dm sets the state of the drive switch 72 in one of the activated firing cells 70. The drive switch 72 is set to conduct or not conduct based on the stored data signal value.

After the state of the selected drive switch 72 is set, energy signals FIRE1-FIREn are provided on the FIRE lines 110a-110n corresponding to the FIRE groups 102a-102n, which FIRE groups 102a-102n comprise a selected subgroup of firing cells 70. The energy signal FIRE1-FIREn includes energy pulses. An energy pulse is provided on a selected ignition line 110a-110n to energize ignition resistor 52 in ignition cell 70 with conducting drive switch 72. The activated firing resistor 52 heats and ejects ink onto print medium 36 to print the image represented by data signals D1, D2 … … Dm. The subgroups of firing cells 70 are activated, storing the data signals D1, D2 … … Dm in the activated subgroups and providing the energy signals FIRE1-FIRE to activate the firing resistors 52 in the activated subgroups, and the above process continues until printing stops.

In one embodiment, when the energy signal FIRE1-FIREn is provided to a selected one of the FIRE groups 102a-102n, the subgroup enable signals SG1, SG2 … … SGL are varied to select and enable another subgroup of the different FIRE groups 102a-102 n. The newly activated subgroup stores the data signals D1, D2 … … Dm provided on the data lines 108a-108m, and the energy signals FIRE1-FIRE are provided on one of the firing lines 110a-110n to activate the firing resistor 52 in the newly activated firing cell 70. At any one time, only one subgroup of firing cells 70 is activated by the subgroup enable signals SG1, SG2 … … SGL to store the data signals D1, D2 … … Dm provided on the data lines 108a-108 m. In this regard, the data signals D1, D2 … … Dm on the data lines 108a-108m are time division multiplexed data signals. Also, while energy signals FIRE1-FIREn are provided to the selected FIRE group 102a-102n, only one subgroup within the selected FIRE group 102a-102n includes drive switch 72 set to conduct. However, the energy signals FIRE1-FIREn provided to the different FIRE groups 102a-102n can and do overlap.

FIG. 6 is a schematic diagram illustrating one embodiment of a pre-charged firing cell 120. Pre-charged firing cell 120 is one embodiment of firing cell 70. The pre-charged firing cell 120 includes a drive switch 172 electrically coupled to the firing resistor 52. In one embodiment, drive switch 172 is a FET that includes a drain-source path electrically coupled at one end to one end of firing resistor 52 and coupled at the other end to reference line 122. Reference line 122 is connected to a reference voltage, such as ground. The other end of firing resistor 52 is electrically coupled to a firing line 124, which firing line 124 receives a firing signal or energy signal FIRE that contains an energy pulse. If drive switch 172 is on (conducting), the energy pulse activates firing resistor 52.

The gate of drive switch 172 forms a storage node capacitance 126 which functions as a storage element to store data pursuant to the sequential activation of pre-charge transistor 128 and select transistor 130. The drain-source path and gate of precharge transistor 128 are electrically coupled to precharge line 132, which receives a precharge signal. The gate of drive switch 172 is electrically coupled to the drain-source path of pre-charge transistor 128 and the drain-source path of select transistor 130. The gate of select transistor 130 is electrically coupled to a select line 134 that receives a select signal. Storage node capacitance 126 is shown in dashed lines as part of drive switch 172. Alternatively, a capacitor separate from the drive switch 172 may be used as the storage element.

Data transistor 136, first address transistor 138, and second address transistor 140 include drain-source paths that are electrically coupled in parallel. The parallel combination of data transistor 136, first address transistor 138, and second address transistor 140 is electrically coupled between the drain-source path of select transistor 130 and reference line 122. A series circuit comprising select transistor 130 coupled to a parallel combination of data transistor 136, first address transistor 138, and second address transistor 140 is electrically coupled across node capacitance 126 of drive switch 172. The gate of DATA transistor 136 is electrically coupled to a DATA line 142 that receives the DATA signal DATA. The gate of first ADDRESS transistor 138 is electrically coupled to an ADDRESS line 144 that receives ADDRESS signals ADDRESS1, and the gate of second ADDRESS transistor 140 is electrically coupled to a second ADDRESS line 146 that receives ADDRESS signals ADDRESS 2. Hereinafter, when tilda () is marked in front of the signal name, the DATA signals DATA and the ADDRESS signals ADDRESS1 and ADDRESS2 are valid. The node capacitance 126, precharge transistor 128, select transistor 130, data transistor 136 and address transistors 138 and 140 constitute a memory cell.

In operation, node capacitance 126 is precharged through precharge transistor 128 by providing a high level voltage pulse on precharge line 132. In one embodiment, after a high level voltage pulse is provided on precharge line 132, a DATA signal DATA is provided on DATA line 142 to set the state of DATA transistor 136, and ADDRESS signals ADDRESS1 and ADDRESS2 are provided on ADDRESS lines 144 and 146 to set the states of first ADDRESS transistor 138 and second ADDRESS transistor 140. A voltage pulse of sufficient magnitude is provided on select line 134 to turn on select transistor 130 and node capacitance 126 discharges if data transistor 136, first address transistor 138, and/or second address transistor 140 are turned on. Alternatively, node capacitance 126 remains charged if data transistor 136, first address transistor 138, and second address transistor 140 are all off.

Pre-charged firing cell 120 is the addressed firing cell if ADDRESS signals ADDRESS1 and ADDRESS2 are both low, and node capacitance 126 is discharged if DATA signal DATA is high or node capacitance 126 remains charged if DATA signal DATA is low. If at least one of the ADDRESS signals ADDRESS1 and ADDRESS2 is high, then pre-charged firing cell 120 is not an addressed firing cell, and node capacitance 126 discharges regardless of the voltage level of the DATA signal DATA. First and second address transistors 136 and 138 comprise an address decoder and data transistor 136 controls the voltage level on node capacitance 126 if pre-charged firing cell 120 is addressed.

Pre-charged firing cells 120 may take any number of other layouts or arrangements so long as the operational relationships described above are maintained. For example, an OR gate may be coupled to address lines 144 and 146, the output of which is coupled to a separate transistor.

FIG. 7 is a schematic diagram illustrating one embodiment of an inkjet printhead firing cell array 200. The firing cell array 200 includes a plurality of pre-charged firing cells 120 arranged into 6 fire groups 202a-202 f. The pre-charged firing cells 120 in each fire group 202a-202f are schematically arranged into 13 rows and eight columns. The fire groups 202a-202f and pre-charged firing cells 120 in array 200 are schematically arranged in 78 rows and eight columns, although the number of pre-charged firing cells and their layout may vary as desired.

Eight columns of pre-charged firing cells 120 are each electrically coupled to eight data lines 208a-208h that receive data signals D1D 2 … … D8. Each of the eight columns, referred to herein as a data line group or data group, contains pre-charged firing cells 120 in each of the six fire groups 202a-202 f. Each of the firing cells 120 in each column of pre-charged firing cells 120 is electrically coupled to one of the data lines 208a-208 h. All of the pre-charged firing cells 120 in a data line group are electrically coupled to the same data line 208a-208h, and data lines 208a-208h are electrically coupled to the gates of data transistors 136 in the column of pre-charged firing cells 120.

Data line 208a is electrically coupled to each pre-charged firing cell 120 in the leftmost column, including the pre-charged firing cells in each fire group 202a-202 f. Data line 208b is electrically connected to each pre-charged firing cell 120 in the adjacent column, and so on, until data line 208h is electrically connected to each pre-charged firing cell 120 in the rightmost column, including the pre-charged firing cells 120 in each fire group 202a-202 f.

The banks of pre-charged firing cells 120 are electrically coupled to address lines 206a-206g that receive address signals A1, A2. Each pre-charged firing cell 120 in a row of pre-charged firing cells 120, referred to herein as a row subgroup or subgroup of pre-charged firing cells 120, is electrically coupled to two of the address lines 206a-206 g. All of the pre-charged firing cells 120 in a row subgroup are electrically coupled to the same two address lines 206a-206 g.

Subgroups of fire groups 202a-202f are identified as subgroups SG1-1 through SG1-13 in fire group one (FG1)202a, subgroups SG2-1 through SG2-13 in fire group two (FG2)202b, and so on, up to subgroups SG6-1 through SG6-13 in fire group six (FG6)202 f. In other embodiments, each fire group 202a-202f may include any suitable number of subgroups, such as 14 or more subgroups.

Each subgroup of pre-charged firing cells 120 is electrically coupled to two address lines 206a-206 g. Two address lines 206a-206g corresponding to a subgroup are electrically coupled to first and second address transistors 138 and 140 in all pre-charged firing cells 120 of the subgroup. One address line 206a-206g is electrically coupled to the gate of one of first and second address transistors 138 and 140, and another address line 206a-206g is electrically coupled to the gate of the other of first and second address transistors 138 and 140. Address lines 206a-206g receive address signals A1, A2. -A7 and are coupled to provide address signals A1, A2. -A7 for a subgroup of array 200 as set forth in the following table:

row subgroup address signals	Group of rows
		～A1、～A2	SG1-1，SG2-1...SG6-1
～A1、～A3	SG1-2，SG2-2...SG6-2
		～A1、～A4	SG1-3，SG2-3...SG6-3
～A1、～A5	SG1-4，SG2-4...SG6-4
		～A1、～A6	SG1-5，SG2-5...SG6-5
～A1、～A7	SG1-6，SG2-6...SG6-6
		～A2、～A3	SG1-7，SG2-7...SG6-7
～A2、～A4	SG1-8，SG2-8...SG6-8
		～A2、～A5	SG1-9，SG2-9...SG6-9
～A2、～A6	SG1-10，SG2-10...SG6-10
		～A2、～A7	SG1-11，SG2-11...SG6-11
～A3、～A4	SG1-12，SG2-12...SG6-12
		～A3、～A5	SG1-13，SG2-13...SG6-13

A subgroup of pre-charged firing cells 120 is addressed by providing address signals A1, A2. In one embodiment, address lines 206a-206g are electrically coupled to one or more address generators provided on printhead die 40.

The PRE-charge lines 210a-210f receive PRE-charge signals PRE1, PRE2.. PRE6 and provide PRE-charge signals PRE1, PRE2 … … PRE6 to the respective fire groups 202a-202 f. The pre-charged line 210a is electrically coupled to all pre-charged firing cells 120 in FG 1202 a. The pre-charge line 210b is electrically coupled to all pre-charged firing cells 120 in FG 2202 b, and so on, until the pre-charge line 210f is electrically coupled to all pre-charged firing cells 120 in FG6202 f. Each pre-charge line 210a-210f is electrically coupled to the gate and drain-source paths of all pre-charge transistors 128 in the corresponding fire group 202a-202f, and all pre-charged firing cells 120 in a fire group 202a-202f are electrically coupled to only one pre-charge line 210a-210 f. Thus, the node capacitances 126 of all PRE-charged firing cells 120 in a fire group 202a-202f are charged by providing the respective PRE-charge signals PRE1, PRE2 … … PRE6 to the respective PRE-charge lines 210a-210 f.

The select lines 212a-212f receive select signals SEL1, SEL2 … … SEL6 and provide select signals SEL1, SEL2 … … SEL6 to the respective fire groups 202a-202 f. Select line 212a is electrically coupled to all pre-charged firing cells 120 in FG1202 a. Select line 212b is electrically coupled to all pre-charged firing cells 120 in FG 2202 b, and so on, until select line 212f is electrically coupled to all pre-charged firing cells 120 in FG 6202 f. Each select line 212a-212f is electrically coupled to the gates of all select charge transistors 130 in a corresponding fire group 202a-202f, and all pre-charged firing cells 120 in a fire group 202a-202f are electrically coupled to only one select line 212a-212 f.

The FIRE lines 214a-214f receive FIRE or energy signals FIRE1, FIRE2 … … FIRE6 and provide energy signals FIRE1, FIRE2 … … FIRE6 to the respective FIRE groups 202a-202 f. Ignition line 214a is electrically coupled to all pre-charged ignition cells 120 in FG1202 a. Fire line 214b is electrically coupled to all pre-charged firing cells 120 in FG 2202 b, and so on, until fire line 214f is electrically coupled to all pre-charged firing cells 120 in FG 6202 f. Each fire line 214a-214f is electrically coupled to all of the select firing resistors 52 in the corresponding fire group 202a-202f, and all of the pre-charged firing cells 120 in the fire group 202a-202f are electrically coupled to only one fire line 214a-214 f. The ignition lines 214a-214f are electrically coupled to external power circuitry through appropriate interface pads (interface pads). (see FIG. 25). All of the pre-charged firing cells 120 in array 200 are electrically coupled to a reference line 216, which reference line 216 is connected to a reference voltage, such as ground. Thus, pre-charged firing cells 120 in a row subgroup of pre-charged firing cells 120 are electrically coupled to the same address lines 206a-206g, pre-charge lines 210a-210f, select lines 212a-212f, and fire lines 214a-214 f.

In operation, in one embodiment, fire groups 202a-202f are selected to fire continuously. FG 1202 a was selected before FG 2202 b, FG 2202 b was selected before FG3, and so on until FG6202f was selected. After FG6202f, the fire group cycle is restarted from FG 1202 a. However, other orders and non-ordered selections may be used.

The address signals A1, A2 … … A7 cycle through the 13 row subgroup addresses before repeating the row subgroup addresses. During each cycle through the fire groups 202a-202f, the address signals A1, A2 … … A7 provided on the address lines 206a-206g are set to a row subgroup address. Address signals A1-A2. -A7 select one row group in each fire group 202a-202f for one cycle through fire groups 202a-202 f. Address signals A1, A2.. A7 instead select another row subgroup within each fire group 202a-202f for the next cycle through fire groups 202a-202 f. This continues until the address signals A1A 2 … … A7 select the last row subgroup in the fire groups 202a-202 f. After the last row subgroup is selected, the address signals A1, A2 … … A7 select the first row subgroup to begin the address cycle again.

In another aspect of operation, one of the fire groups 202a-202f is operated by providing a precharge signal PRE1, PRE2.. PRE6 on precharge line 210a-210f of one fire group 202a-202 f. The precharge signals PRE1, PRE2 … PRE6 determine a precharge time interval or period during which the node capacitance 126 on each drive switch 172 in one fire group 202a-202f is charged to a high voltage level to precharge the one fire group 202a-202 f.

Address signals A1, A2 … … A7 are provided on address lines 206a-206g to address a row subgroup in each of the fire groups 202a-202f, including a row subgroup in the pre-charged fire groups 202a-202 f. Data signals D1D 2 … … D8 are provided on data lines 208a-208h to provide data to all fire groups 202a-202f, including a row of subgroups that are addressed in a pre-charge group 202a-202 f.

Select signals SEL1, SEL2.. SEL6 are then provided on select lines 212a-212f of pre-charged fire groups 202a-202f in order to select pre-charged fire groups 202a-202 f. The select signals SEL1, SEL2.. SEL6 define a discharge time interval for discharging the node capacitance 126 on each drive switch 172 in a pre-charged firing cell 120 that is either not in the addressed subset of rows in the selected fire group 202a-202f or is addressed and receives the high level data signals D1, -D2.. -D8 in the selected fire group 202a-202 f. The node capacitance 126 does not discharge in the pre-charged firing cells 120 that the pre-charged firing cells 120 are addressed and receive the low level data signals D1D 2 … … D8 in the selected fire group 202a-202 f. The high voltage level on node capacitance 126 turns on drive switch 172 (conducting).

After drive switches 172 in a selected fire group 202a-202f are set to conduct or not conduct, an energy pulse or voltage pulse is provided on fire lines 214a-214f of the selected fire group 202a-202 f. The pre-charged firing cells 120 with the conducting drive switches 172 conduct current through the firing resistors 52 to heat the ink and eject the ink from the corresponding drop generators 60.

Since the fire groups 202a-202f are operating continuously, the select signals SEL1, SEL2 … … SEL6 for one fire group 202a-202f are used as the precharge signals PRE1, PRE2 … … PRE6 for the next fire group 202a-202 f. The precharge signals PRE1, PRE2 … … PRE6 for one FIRE group 202a-202f are present before the select signals SEL1, SEL2 … … SEL6 and the energy signals FIRE1, FIRE2 … … FIRE6 for this one FIRE group 202a-202 f. After the precharge signals PRE1, PRE2 … … PRE6, the data signals D1, D2 … … D8 are multiplexed over time and stored in the addressed bank group of fire groups 202a-202f by the select signals SEL1, SEL2 … … SEL 6. The select signals SEL1, SEL2 … … SEL6 for the selected fire group 202a-202f are also the precharge signals PRE1, PRE2 … … PRE6 for the next fire group 202a-202 f. After the select signals SEL1, SEL2 … … SEL6 for the selected fire group 202a-202f end, the select signals SEL1, SEL2 … … SEL6 for the next fire group 202a-202f are provided. As the energy signals FIRE1, FIRE2 … … FIRE6, including the energy pulses, are provided to the selected FIRE group 202a-202f, the pre-charged firing cells 120 in the selected subgroup FIRE or heat the ink based on the stored data signals D1, D2 … … -D8.

Fig. 8 is a timing diagram illustrating the operation of one embodiment of firing cell array 200. Fire groups 202a-202f are successively selected to activate pre-charged firing cells 120 based on data signals D1D 2 … … D8 labeled 300. The data signals D1D 2 … … D8 at 300 vary depending on the nozzle to eject fluid, which is labeled 302, for each row of sub-group address and fire group 202a-202f combinations. Address signals A1A 2 … … A7 are provided on address lines 206a-206g at 304 to address a row group from each fire group 202a-202 f. The address signals A1, A2 … … A7 at 304 are set to an address, labeled 306, for one cycle through the fire groups 202a-202 f. After the cycle is complete, the address signals A1, A2 … … A7 at 304 are changed at 308 to address a different row group from each fire group 202a-202 f. The address signals a1, -a 2 … … -a 7 at 304 add 1 through the row subgroups to address the row subgroups in sequential order from 1 to 13 and then back to 1. In other embodiments, the address signals A1, A2 … … A7 at 304 may be set to address the various subgroups in any suitable order.

During one cycle through the fire groups 202a-202f, the select line 212f connected to FG 6202 f and the PRE-charge line 210a connected to FG 1202 a receive the SEL6/PRE1 signals 309, including the SEL6/PRE1 signal pulses 310. In one embodiment, select line 212f and precharge line 210a are electrically coupled together to receive the same signal. In another embodiment, select line 212f and precharge line 210a are not electrically coupled together, but receive similar signals.

The SEL6/PRE1 signal pulse at 310 on the precharge line 210a precharges all firing cells 120 in the FG 1202 a. The node capacitance 126 of each pre-charged firing cell 120 in FG 1202 a is charged to a high voltage level. The node capacitances 126 for pre-charged firing cells 120 in row subgroup SG1-K, labeled 311, are pre-charged to a high voltage level at 312. At 306, the row subgroup address selects subgroup SG1-K, and the data signal set at 314 is provided to data transistors 136 in all pre-charged firing cells 120 of all fire groups 202a-202f, including the address selected row subgroup SG 1-K.

The select line 212a for FG 1202 a and the precharge line 210b for FG 2202 b receive the SEL1/PRE2 signals 315, including the SEL1/PRE2 signal pulses 316. The SEL1/PRE2 signal pulse 316 on select line 212a turns on the select transistor 130 in each PRE-charged firing cell 120 in FG 1202 a. The node capacitances 126 of all pre-charged firing cells 120 in FG 1202 a that are not within the address selected row subgroup SG1-K are discharged. In the address selected row subgroup SG1-K, the data at 314 is stored in node capacitance 126 of drive switch 172 in row subgroup SG1-K, labeled 318, to turn the drive switch on (conducting) or off (non-conducting).

The SEL1/PRE2 signal pulse at 316 on the PRE-charge line 210b PRE-charges all firing cells 120 in the FG2202 b. The node capacitance 126 of each pre-charged firing cell 120 in FG2202b is charged to a high voltage level. The node capacitances 126 for pre-charged firing cells 120 in one row subgroup SG2-K, labeled 319, are pre-charged to a high voltage level at 320. The row subgroup address at 306 selects subgroup SG2-K, and the data signal set at 328 is provided to data transistors 136 in all pre-charged firing cells 120 of all fire groups 202a-202f, including the address selected row subgroup SG 2-K.

Ignition line 214a receives an energy signal FIRE1, labeled 323, including an energy pulse at 322 to activate ignition resistor 52 of pre-charged ignition cell 120 in FG1202a with drive switch 172 turned on. The FIRE1 energy pulse 322 goes high while the SEL1/PRE2 signal pulse 316 is high and while the node capacitance 126 on the non-conductive drive switch 172 is being effectively lowered, labeled 324 with respect to the energy signal FIRE 1323. Switching the energy pulse 322 high while the node capacitance 126 is actively being lowered prevents the node capacitance 126 from being inadvertently charged by driving the switch 172 when the energy pulse 322 goes high. The SEL1/PRE2 signal 315 goes low and provides an energy pulse 322 to the FG1202a at a predetermined time to heat and eject ink through the nozzle 34 corresponding to the turned-on PRE-charged firing cell 120.

The select line 212b for FG2202b and the precharge line 210c for FG3202c receive the SEL2/PRE3 signals 325, including the SEL2/PRE3 signal pulses 326. After the SEL1/PRE2 signal pulse 316 goes low and while the energy pulse 322 is high, the SEL2/PRE3 signal pulse 326 on the select line 212b turns on the select transistor 130 of each PRE-charged firing cell 120 in the FG2202 b. The node capacitances 126 on all pre-charged firing cells 120 in FG2202b that are not in the address selected row subgroup SG2-K are discharged. The set of data signals 328 for subgroup SG2-K is stored in pre-charged firing cells 120 of subgroup SG2-K, labeled 330, to turn the drive switches 172 on (conducting) or off (non-conducting). The SEL2/PRE3 signal pulse on the PRE-charge line 210c PRE-charges all PRE-charged firing cells 120 in FG3202 c.

FIRE line 214b receives energy signal FIRE2, labeled 331, and includes an energy pulse 332 to activate firing resistor 52 of pre-charged firing cell 120 in FG2202b with conducting drive switch 172. The FIRE2 energy pulse 332 goes high while the SEL2/PRE3 signal pulse 326 is high, labeled 334. The SEL2/PRE3 signal pulse 326 goes low and the FIRE2 energy pulse 332 remains high to heat and eject ink from the corresponding drop generator 60.

After SEL2/PRE3 signal pulse 326 goes low, and while energy pulse 332 is high, the SEL3/PRE4 signal is provided to select FG 3202 c and precharge FG 4202 d. The process of precharging, selecting and providing an energy signal, including an energy pulse, continues until FG6202 f.

The SEL5/PRE6 signal pulse on the precharge line 210f precharges all the firing cells 120 in FG6202 f. The node capacitance 126 of each pre-charged firing cell 120 in FG6202f is charged to a high voltage level. The node capacitances 126 of pre-charged firing cells 120 in one row subgroup SG6-K, labeled 339, are pre-charged to a high voltage level at 341. The row subgroup address at 306 selects subgroup SG6-K, and data signal group 338 is provided to data transistors 136 in all pre-charged firing cells 120 of all fire groups 202a-202f, including the address selected row subgroup SG 6-K.

The select line 212f for FG6202f and the precharge line 210a for FG 1202 a receive a second SEL6/PRE1 signal pulse at 336. The SEL6/PRE1 signal pulse 336 on select line 212f turns on the select transistor 130 in each PRE-charged firing cell 120 in FG6202 f. The node capacitances 126 of all pre-charged firing cells 120 in FG6202f that are not in the address selected row subgroup SG6-K are discharged. In the address selected row subgroup SG6-K, data 338 are stored at 340 in node capacitance 126 of each drive switch 172 to turn the drive switch on or off.

The SEL6/PRE1 signal on the PRE-charge line 210a PRE-charges the node capacitances 126 in all firing cells 120 in the FG 1202 a, including the firing cells 120 in row subgroup SG1-K, labeled 342, to a high voltage level. The firing cells 120 in FG 1202 a are precharged while address signals A1, A2 … … A7304 select row subgroup SG1-K, SG2-K, etc. until row subgroup SG 6-K.

FIRE line 214f receives energy signal FIRE6, labeled 343, which includes an energy pulse at 344 to activate firing resistor 52 of pre-charged firing cell 120 in FG 6202 f having conducting drive switch 172. The energy pulse 344 goes high while the SEL6/PRE1 signal pulse 336 is high and the node capacitance 126 on the non-conductive drive switch 172 is being actively lowered, labeled 346. Switching the energy pulse 344 high while the node capacitance 126 is actively being lowered prevents the node capacitance 126 from being inadvertently charged by driving the switch 172 when the energy pulse 344 goes high. The SEL6/PRE1 signal pulse 336 goes low and the energy pulse 344 is held high for a predetermined time to heat and eject ink through the nozzles 34 corresponding to the conducting PRE-charged firing cells 120.

After the SEL6/PRE1 signal pulse 336 goes low, when the energy pulse 344 is high, the address signals A1, A2. -A7304 are changed at 308 to select another group of subgroups SG1-K +1, SG2-K +1, and so on, until SG6-K + 1. The select line 212a for FG 1202 a and the precharge line 210b for FG2202b receive the SEL1/PRE2 signal pulse, labeled 348. The SEL1/PRE2 signal pulse 348 on select line 212a turns on the select transistor 130 in each PRE-charged firing cell 120 in FG 1202 a. The node capacitance FG126 of all pre-charged firing cells FG120 in FG 1202 a that are not in the address selected row subgroup SG1-k +1 is discharged. The data signal group 350 of subgroup SG1-k +1 is stored in pre-charged firing cells 120 of subgroup SG1-k +1 to turn drive switches 172 on or off. The SEL1/PRE2 signal pulse 348 on the PRE-charge line 210b PRE-charges all firing cells 120 in the FG2202 b.

The fire line 214a receives an energy pulse 352 to activate the firing resistor 52 in FG 1202 a with the drive switch 172 turned on and the pre-charged firing cell 120. The energy pulse 352 goes high while the SEL1/PRE2 signal pulse at 348 is high. The SEL1/PRE2 signal pulse 348 goes low and the energy pulse 352 remains high to heat and eject ink from the corresponding drop generator 60. This process continues until printing is complete.

FIG. 9 is a schematic diagram illustrating one embodiment of an address generator 400 in printhead die 40. The address generator 400 includes a shift register 402, a direction circuit 404, and a logic array 406. The shift register 402 is electrically coupled to the direction circuit 404 through a direction control line 408. Also, shift register 402 is electrically coupled to logic array 406 through shift register output lines 410a-410 m.

In the embodiment described below, the address generator 400 provides address signals to the firing cells 120. In one embodiment, the address generator 400 receives external signals, see FIG. 25, including the control signal CSYNC and six timing signals T1-T6, and in response provides seven address signals A1, A2, … … A7. The address signals a1, a2, … …, a7 are active when they are at a low voltage level, and are represented by a symbol before each signal name. In one implementation, the timing signals T1-T6 are provided on select lines (e.g., select lines 212a-212f shown in FIG. 7). Address generator 400 is one embodiment of a control circuit configured to initiate a sequence (e.g., a forward or reverse sequential series of addresses-A1, -A2 … … -A7) in response to a control signal (e.g., CSYNC) to initiate activation of firing cells 120.

The address generator 400 includes resistor dividing networks (dividetworks) 412, 414, and 416 that receive timing signals T2, T4, and T6. The resistor divider network 412 receives the timing signal T2 through timing signal line 418 and decrements the voltage level of the divided timing signal T2 to provide a reduced voltage level T2 timing signal on a first evaluation signal line (evaluation signal line) 420. The resistor divide network 414 receives the timing signal T4 through the timing signal line 422 and divides down the voltage level of the timing signal T4 to provide a reduced voltage level T4 timing signal on the second evaluation signal line 424. The resistor divide network 416 receives the timing signal T6 through the timing signal line 426 and divides down the voltage level of the timing signal T6 to provide a reduced voltage level T6 timing signal on the third evaluation signal line 428.

Shift register 402 receives control signal CSYNC via control signal line 430 and direction signals via direction signal line 408. Also, shift register 402 receives timing signal T1 as first PRE-charge signal PRE1 via timing signal line 432. The dropped voltage level T2 is received as a first evaluation signal EVAL1 through a first evaluation signal line 420. Timing signal T3 is received as second PRE-charge signal PRE2 through timing signal line 434, and the reduced voltage level T4 timing signal is received as second evaluation signal EVAL2 through second evaluation signal line 424. Shift register 402 provides shift register output signals SO1-SO13 on shift register output lines 410a-410 m.

Shift register 402 includes thirteen shift register cells 403a-403m that provide thirteen shift register output signals SO1-SO 13. Each of the shift register cells 403a-403m provides one of the thirteen shift register output signals SO1-SO 13. The thirteen shift register cells 403a-403m are electrically coupled in series to provide shifting in the forward and reverse directions. In other embodiments, shift register 402 may include any suitable number of shift register cells 403 to provide any suitable number of shift register output signals to provide any number of desired address signals.

Shift register cell 403a provides shift register output signal SO1 on shift register output line 410 a. Shift register cell 403b provides shift register output signal SO2 on shift register output line 410 b. Shift register cell 403c provides shift register output signal SO3 on shift register output line 410 c. Shift register cell 403d provides shift register output signal SO4 on shift register output line 410 d. Shift register cell 403e provides shift register output signal SO5 on shift register output line 410 e. Shift register cell 403f provides shift register output signal SO6 on shift register output line 410 f. Shift register cell 403g provides shift register output signal SO7 on shift register output line 410 g. Shift register cell 403h provides shift register output signal SO8 on shift register output line 410 h. Shift register cell 403i provides shift register output signal SO9 on shift register output line 410 i. Shift register cell 403j provides shift register output signal SO10 on shift register output line 410 j. Shift register cell 403k provides shift register output signal SO11 on shift register output line 410 k. Shift register cell 4031 provides shift register output signal SO12 on shift register output lines 4101 and shift register cell 403m provides shift register output signal SO13 on shift register output lines 410 m.

Direction circuit 404 receives control signal CSYNC on control signal line 430. Timing signal T3 is received on timing signal line 434 as fourth PRE-charge signal PRE 4. The dropped voltage level T4 is received on evaluation signal line 424 as fourth evaluation signal EVAL 4. The timing signal T5 is received on the timing signal line 436 as the third PRE-charge signal PRE3, and the reduced voltage level T6 timing signal is received on the third evaluation signal line 428 as the third evaluation signal EVAL 3. The direction circuit 404 provides a direction signal to the shift register 402 via a direction signal line 408.

Logic array 406 includes address line precharge transistors 438a-438g, address evaluation transistors 440a-440m, evaluation prevention transistors 442a and 442b, and logic evaluation precharge transistor 444. Also, the logic array 406 includes a pair of address transistors 446, 448 … … 470 that decode the shift register output signals SO1-SO13 on the shift register output lines 410a-410m to provide address signals A1, A2 … … A7. The logic array 406 includes address one transistors 446a and 446b, address two transistors 448a and 448b, address three transistors 450a and 450b, address four transistors 452a and 452b, address five transistors 454a and 454b, address six transistors 456a and 456b, address seven transistors 458a and 458b, address eight transistors 460a and 460b, address nine transistors 462a and 462b, address ten transistors 464a and 464b, address eleven transistors 466a and 466b, address twelve transistors 468a and 468b, and address thirteen transistors 470a and 470 b.

Address line precharge transistors 438a-438g are electrically coupled to signal line 434 and address lines 472a-472g of T3. One side of the drain-source path and the gate of address line precharge transistor 438a are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438a is electrically coupled to address line 472 a. One side and the gate of the drain-source path of address line precharge transistor 438b are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438b is electrically coupled to address line 472 b. One side and the gate of the drain-source path of address line precharge transistor 438c are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438c is electrically coupled to address line 472 c. One side of the drain-source path and the gate of address line precharge transistor 438d are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438d is electrically coupled to address line 472 d. One side of the drain-source path and the gate of address line precharge transistor 438e are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438e is electrically coupled to address line 472 e. One side of the drain-source path and the gate of address line precharge transistor 438f are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438f is electrically coupled to address line 472 f. One side and the gate of the drain-source path of address line precharge transistor 438g are electrically coupled to signal line 434 of T3. The other side of the drain-source path of address line precharge transistor 438g is electrically coupled to address line 472 g. In one embodiment, address line precharge transistors 438a-438g are electrically coupled to T4 signal line 422, rather than T3 signal line 434. The T4 signal line 422 is electrically coupled to one side of the drain-source path and the gate of each address line precharge transistor 438a-438 g.

The gate of each address evaluation transistor 440a-440m is electrically coupled to a logic evaluation signal line 474. One side of the drain-source path of each address evaluation transistor 440a-440m is electrically coupled to ground. Additionally, the drain-source path of address evaluation transistor 440a is electrically coupled to evaluation line 476 a. The drain-source path of address evaluation transistor 440b is electrically coupled to evaluation line 476 b. The drain-source path of address evaluation transistor 440c is electrically coupled to evaluation line 476 c. The drain-source path of address evaluation transistor 440d is electrically coupled to evaluation line 476 d. The drain-source path of address evaluation transistor 440e is electrically coupled to evaluation line 476 e. The drain-source path of address evaluation transistor 440f is electrically coupled to evaluation line 476 f. The drain-source path of address evaluation transistor 440g is electrically coupled to evaluation line 476 g. The drain-source path of address evaluation transistor 440h is electrically coupled to evaluation line 476 h. The drain-source path of address evaluation transistor 440i is electrically coupled to evaluation line 476 i. The drain-source path of address evaluation transistor 440j is electrically coupled to evaluation line 476 j. The drain-source path of address evaluation transistor 440k is electrically coupled to evaluation line 476 k. The drain-source path of address evaluation transistor 4401 is electrically coupled to evaluation line 4761. The drain-source path of address evaluation transistor 440m is electrically coupled to evaluation line 476 m.

One side and gate of the pull-in path of logic evaluation precharge transistor 444 is electrically coupled to T5 signal line 436 and the other side of the drain-source path is electrically coupled to logic evaluation signal line 474. The gate of evaluation prevention transistor 442a is electrically coupled to signal line 434 of T3. The drain-source path of the evaluation prevention transistor 442a is electrically coupled on one side thereof to a logic evaluation signal line 474 and on the other side to a reference at 478. The gate of evaluation prevention transistor 442b is electrically coupled to signal line 422 of T4. The drain-source path of evaluation prevention transistor 442b is electrically coupled on one side thereof to a logic evaluation signal line 474 and on the other side to a reference at 478.

The drain-source paths of address transistor pair 446, 448 … … 470 are electrically coupled between address lines 472a-472g and evaluation lines 476a-476 m. The gates of the pair of address transistors 446, 448 … … 470 are driven by shift register output signals SO1-SO13 through shift register output signal lines 410a-410 m.

The gates of address one transistors 446a and 446b are electrically coupled to shift register output signal line 410 a. The drain-source path of address one transistor 446a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 a. The drain-source path of address one transistor 446b is electrically coupled on one side to address line 472b and on the other side to evaluation line 476 a. The high level shift register output signal SO1 on shift register output signal line 410a turns on address one transistors 446a and 446b, while address evaluation transistor 440a is turned on by the high voltage level evaluation signal LEVAL on logic evaluation signal line 474. The address one transistor 446a and the address evaluation transistor 440a conduct to actively pull the address line 472a to a low voltage level. The address one transistor 446b and the address evaluation transistor 440a conduct to actively pull the address line 472b to a low voltage level.

The gates of address two transistors 448a and 448b are electrically coupled to shift register output signal line 410 b. The drain-source path of address two transistor 448a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 b. The drain-source path of address two transistor 448b is electrically coupled on one side to address line 472c and on the other side to evaluation line 476 b. A high level shift register output signal SO2 on shift register output signal line 410b turns on address two transistors 448a and 448b while address evaluation transistor 440b is turned on by a high voltage level evaluation signal LEVAL on logic evaluation signal line 474. Address two transistor 448a and address evaluation transistor 440b conduct to actively pull address line 472a to a low voltage level. Address two transistor 448b and address evaluation transistor 440b conduct to actively pull address line 472c to a low voltage level.

The gates of address three transistors 450a and 450b are electrically coupled to shift register output signal line 410 c. The drain-source path of address three transistor 450a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 c. The drain-source path of address three transistor 450b is electrically coupled on one side to address line 472d and on the other side to evaluation line 476 c. A high level shift register output signal SO3 on shift register output signal line 410c turns on address three transistors 450a and 450b while address evaluation transistor 440c is turned on by a high voltage level evaluation signal LEVAL on logic evaluation signal line 474. Address three transistor 450a and address evaluation transistor 440c conduct to actively pull address line 472a to a low voltage level. Address three transistor 450b and address evaluation transistor 440c conduct to actively pull address line 472d to a low voltage level.

The gates of address four transistors 452a and 452b are electrically coupled to shift register output signal line 410 d. The drain-source path of address four transistor 452a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 d. The drain-source path of address four transistor 452b is electrically coupled on one side to address line 472e and on the other side to evaluation line 476 d. A high level shift register output signal SO4 on shift register output signal line 410d turns on address four transistors 452a and 452b while address evaluation transistor 440d is turned on by a high voltage level evaluation signal LEVAL on logic evaluation signal line 474. Address four transistor 452a and address evaluation transistor 440d conduct to actively pull address line 472a to a low voltage level. Address four transistor 452b and address evaluation transistor 440d conduct to actively pull address line 472e to a low voltage level.

The gates of address five transistors 454a and 454b are electrically coupled to shift register output signal line 410 e. The drain-source path of address five transistor 454a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 e. The drain-source path of address five transistor 454b is electrically coupled on one side to address line 472f and on the other side to evaluation line 476 e. A high level shift register output signal SO5 on shift register output signal line 410e turns on address pentatransistors 454a and 454b while address evaluation transistor 440e is turned on by a high voltage level evaluation signal LEVAL on logic evaluation signal line 474. Address five transistor 454a and address evaluation transistor 440e conduct to actively pull address line 472a to a low voltage level. The address five transistor 454b and the address evaluation transistor 440e conduct to actively pull the address line 472f to a low voltage level.

The gates of address six transistors 456a and 456b are electrically coupled to shift register output signal line 410 f. The drain-source path of address six transistor 456a is electrically coupled on one side to address line 472a and on the other side to evaluation line 476 f. The drain-source path of address six transistor 456b is electrically coupled on one side to address line 472g and on the other side to evaluation line 476 f. A high level shift register output signal SO6 on shift register output signal line 410f turns on address hexa transistors 456a and 456b to conduct while address evaluation transistor 440f is turned on by a high voltage level evaluation signal LEVAL. The address six transistor 456a and the address evaluation transistor 440f conduct to actively pull the address line 472a to a low voltage level. The address six transistor 456b and the address evaluation transistor 440f conduct to actively pull the address line 472g to a low voltage level.

The gates of address seven transistors 458a and 458b are electrically coupled to shift register output signal line 410 g. The drain-source path of address six transistor 458a is electrically coupled on one side to address line 472b and on the other side to evaluation line 476 g. The drain-source path of address six transistor 458b is electrically coupled on one side to address line 472c and on the other side to evaluation line 476 g. The high level shift register output signal SO7 on shift register output signal line 410g turns on address hexatransistors 458a and 458b, while address evaluation transistor 440g is turned on by a high voltage level evaluation signal LEVAL. Address seven transistor 458a and address evaluation transistor 440g conduct to actively pull address line 472b to a low voltage level. Address seven transistor 458b and address evaluation transistor 440g conduct to actively pull address line 472c to a low voltage level.

The gates of address eight transistors 460a and 460b are electrically coupled to shift register output signal line 410 h. The drain-source path of address eight transistor 460a is electrically coupled on one side to address line 472b and on the other side to evaluation line 476 h. The drain-source path of address eight transistor 460b is electrically coupled on one side to address line 472d and on the other side to evaluation line 476 h. The high level shift register output signal SO8 on shift register output signal line 410h turns on address eight transistors 460a and 460b, while address evaluation transistor 440h is turned on by the high voltage level evaluation signal LEVAL. The address eight transistor 460a and the address evaluation transistor 440h conduct to actively pull the address line 472b to a low voltage level. Address eight transistor 460b and address evaluation transistor 440h conduct to actively pull address line 472d to a low voltage level.

The gates of address nine transistors 462a and 462b are electrically coupled to shift register output signal line 410 i. The drain-source path of address nine transistor 462a is electrically coupled on one side to address line 472b and on the other side to evaluation line 476 i. The drain-source path of address nine transistor 462b is electrically coupled on one side to address line 472e and on the other side to evaluation line 476 i. The high level shift register output signal SO9 on shift register output signal line 410i turns on address nine transistors 462a and 462b to conduct, while address evaluation transistor 440i is turned on by a high voltage level evaluation signal LEVAL. The address nine transistor 462a and the address evaluation transistor 440i conduct to actively pull the address line 472b to a low voltage level. The address nine transistor 462b and the address evaluation transistor 440i conduct to actively pull the address line 472e to a low voltage level.

The gates of address ten transistors 464a and 464b are electrically coupled to shift register output signal line 410 j. The drain-source path of address ten transistor 464a is electrically coupled on one side to address line 472b and on the other side to evaluation line 476 j. The drain-source path of address ten transistor 464b is electrically coupled on one side to address line 472f and on the other side to evaluation line 476 j. The high level shift register output signal SO10 on shift register output signal line 410j turns on address ten transistors 464a and 464b, while address evaluation transistor 440j is turned on by the high voltage level evaluation signal LEVAL. The address ten transistor 464a and the address evaluation transistor 440j conduct to actively pull the address line 472b to a low voltage level. The address ten transistor 464b and the address evaluation transistor 440j conduct to actively pull the address line 472f to a low voltage level.

The gates of address eleven transistors 466a and 466b are electrically coupled to shift register output signal line 410 k. The drain-source path of address eleven transistor 466a is electrically coupled on one side thereof to address line 472b and on the other side thereof to evaluation line 476 k. The drain-source path of address eleven transistor 466b is electrically coupled on one side thereof to address line 472g and on the other side thereof to evaluation line 476 k. A high level shift register output signal SO11 on shift register output signal line 410k turns on address eleven transistors 466a and 466b, while address evaluation transistor 440k is turned on by a high voltage level evaluation signal LEVAL. The address eleven transistor 466a and the address evaluation transistor 440k conduct to actively pull the address line 472b to a low voltage level. Address eleven transistor 466b and address evaluation transistor 440k conduct to actively pull address line 472g to a low voltage level.

The gates of address twelve transistors 468a and 468b are electrically coupled to shift register output signal line 4101. The drain-source path of address twelve transistor 468a is electrically coupled on one side to address line 472c and on the other side to evaluation line 4761. The drain-source path of address twelve transistor 468b is electrically coupled on one side to address line 472d and on the other side to evaluation line 4761. A high level shift register output signal SO12 on shift register output signal line 4101 turns on address twelve transistors 468a and 468b, while address evaluation transistor 4401 is turned on by a high voltage level evaluation signal LEVAL. Address twelve transistor 468a and address evaluation transistor 4401 conduct to actively pull address line 472c to a low voltage level. Address twelve transistor 468b and address evaluation transistor 4401 conduct to actively pull address line 472d to a low voltage level.

The gates of address thirteen transistors 470a and 470b are electrically coupled to shift register output signal line 410 m. The drain-source path of address thirteen transistor 470a is electrically coupled to address line 472c on one side thereof and connected to evaluation line 476m on the other side thereof. The drain-source path of address thirteen transistor 470b is electrically coupled to address line 472e on one side thereof and connected to evaluation line 476m on the other side thereof. A high level shift register output signal SO13 on shift register output signal line 410m turns on address thirteen transistors 470a and 470b while address evaluation transistor 440m is turned on by a high voltage level evaluation signal LEVAL. Address thirteen transistor 470a and address evaluation transistor 440m conduct to actively pull address line 472c to a low voltage level. Address thirteen transistor 470b and address evaluation transistor 440m conduct to actively pull address line 472e to a low voltage level.

Shift register 402 shifts a single high voltage level output signal from one shift register output signal line 410a-410m to the next shift register output signal line 410a-410 m. Shift register 402 receives a control pulse in control signal CSYNC on control line 430 and a series of timing pulses from timing signals T1-T4 to shift the received control pulse into shift register 402. In response, shift register 402 provides a single high voltage level shift register output signal SO1 or SO 13. All other shift register output signals SO1-SO13 are provided at low voltage levels. The shift register 402 receives another series of timing pulses from the timing signals T1-T4 and shifts a single high voltage level output signal from one shift register output signal SO1-SO13 to the next shift register output signal SO1-SO13, while all other shift register output signals SO1-SO13 are provided at a low voltage level. Shift register 402 receives a repeating series of timing pulses, and in response to each series of timing pulses, shift register 402 shifts the single high voltage level output signal to provide a series of up to thirteen high voltage level shift register output signals SO1-SO 13. Each high voltage level shift register output signal SO1-SO13 turns on two address transistor pairs 446, 448 … … 470 to provide address signals A1, A2 … … A7 to firing cells 120. The address signals A1, A2 … … A7 are provided in thirteen address slots corresponding to the thirteen shift register output signals SO1-SO 13. In another embodiment, shift register 402 may contain any suitable number of shift register output signals, such as fourteen, to provide address signals A1, A2 … … A7 in any suitable number of address slots, such as fourteen address slots.

The shift register 402 receives direction signals from the direction circuit 404 via direction signal lines 408. The direction signal sets the shift direction in shift register 402. The shift register 402 can be set to shift the high voltage output signal in a forward direction, i.e., from the shift register output signal SO1 to the shift register output signal SO13, or in a reverse direction, i.e., from the shift register output signal SO13 to the shift register output signal SO 1.

In the forward direction, shift register 402 receives a control pulse in control signal CSYNC and provides a high voltage level shift register output signal SO 1. All other shift register output signals SO2-SO13 are provided at low voltage levels. The shift register 402 receives the next series of timing pulses and provides a high voltage level shift register output signal SO2, while all other shift register output signals SO1 and SO3-SO13 are provided at low voltage levels. The shift register 402 receives the next series of timing pulses and provides a high voltage level shift register output signal SO3, while all other shift register output signals SO1, SO2, and SO4-SO13 are provided at low voltage levels. The shift register 402 continues to shift the high level output signals in response to each series of timing pulses until and including the high voltage level shift register output signal SO13 is provided, while all other shift register output signals SO1-SO12 are provided at low voltage levels. After providing the high voltage level shift register output signal SO13, the shift register 402 receives the next series of timing pulses and provides low voltage level signals for all of the shift register output signals SO1-SO 13. Another control pulse in control signal CSYNC is provided to start or initiate shifting of shift register 402 in the forward direction, i.e., the series of high voltage level output signals from shift register output signal SO1 to shift register output signal SO 13.

In the reverse direction, shift register 402 receives a control pulse in control signal CSYNC and provides a high level shift register output signal SO 13. All other shift register output signals SO1-SO12 are provided at low voltage levels. The shift register 402 receives the next series of timing pulses and provides a high voltage level shift register output signal SO12, while all other shift register output signals SO1-SO11 and SO13 are provided at low voltage levels. The shift register 402 receives the next series of timing pulses and provides a high voltage level shift register output signal SO11, while all other shift register output signals SO1-SO10, SO12, and SO13 are provided at low voltage levels. The shift register 402 continues to shift the high level output signals in response to each series of timing pulses until and including the high voltage level shift register output signal SO1 is provided, while all other shift register output signals SO2-SO13 are provided at low voltage levels. After the high voltage level shift register output signal SO1 is provided, the shift register 402 receives the next series of timing pulses and provides a low voltage level signal for all of the shift register output signals SO1-SO 13. Another control pulse in control signal CSYNC is provided to start or initiate shift register 402 shifting in the reverse direction, i.e., the series of high voltage level output signals from shift register output signal SO13 to shift register output signal SO 1.

The direction circuit 404 provides two direction signals via direction signal lines 408. The direction signal sets the forward/reverse shift direction in shift register 402. Also, the direction signal may be used to clear the high voltage level output signal from the shift register 402.

The direction circuit 404 receives a repeating series of timing pulses from the timing signals T3-T6. In addition, direction circuit 404 receives a control pulse in control signal CSYNC on control line 430. The direction circuit 404 provides a forward direction signal in response to receiving a control pulse that coincides with a timing pulse from the timing signal T4. The forward direction signal sets shift register 402 to shift in the forward direction from shift register output signal SO1 to shift register output signal SO 13. The direction circuit 404 provides a reverse direction signal in response to receiving a control pulse that coincides with a timing pulse from the timing signal T6. The reverse direction signal sets shift register 402 to shift in the reverse direction, i.e., from shift register output signal SO13 to shift register output signal SO 1. The direction circuit 404 provides a direction signal to clear the shift register 402 in response to receiving a control pulse that coincides with both the timing pulse from the timing signal T4 and the timing pulse from the timing signal T6.

The logic array 406 receives the shift register output signals SO1-SO13 on shift register output signal lines 410a-410m and timing pulses from timing signals T3-T5 on timing signal lines 434, 422, and 436. In response to a single high voltage output signal of the shift register output signals SO1-SO13 and timing pulses from the timing signals T3-T5, the logic array 406 provides two low voltage level address signals from the seven address signals A1, A2 … … A7.

Logic array 406 receives a timing pulse from timing signal T3 that turns on evaluation prevention transistor 442a to lower evaluation signal line 474 to a low voltage level and turns off address evaluation transistor 440. Also, the timing pulse from timing signal T3 charges address lines 472a-472g to a high voltage level through address line precharge transistor 438. In one embodiment, the timing pulse from timing signal T3 is replaced with a timing pulse from timing signal T4 to charge address lines 472a-472g to a high voltage level through address line precharge transistor 438.

The timing pulse from timing signal T4 turns on evaluation prevention transistor 442b to pull evaluation signal line 474 to a low voltage level and turns off address evaluation transistor 440. The shift register output signals SO1-SO13 are used to assert the output signals during timing pulses from the timing signal T4. A single high voltage level output signal in the shift register output signals SO1-SO13 is provided to the gates of the pair of address transistors 446, 448 … … 470 in the logic array 406. The timing pulse from timing signal T5 charges evaluation signal line 474 to a high voltage level to turn on address evaluation transistor 440. When the address evaluation transistor 440 is turned on, the address transistor pair 446, 448 … …, or 470 in the logic array 406 that receives the high voltage level shift register output signal SO1-SO13 conducts, thereby discharging the corresponding address line 472. With the address transistor pair 446, 448 … … 470 conducting and the address evaluation transistor 440 conducting, the corresponding address line 472 is effectively reduced in level. The other address lines 472 remain charged to a high voltage level state.

In each address slot, the logic array 406 provides two low voltage level address signals from the seven address signals A1, A2 … … A7. If the shift register output signal SO1 is at a high voltage level, the address one transistors 446a and 446b conduct to pull the address lines 472a and 472b low to a low voltage level and provide active low address signals A1 and A2. If the shift register output signal SO2 is at a high voltage level, address two transistors 448a and 448b conduct to pull address lines 472a and 472c low to a low voltage level and provide active low address signals A1 and A3. If the shift register output signal SO3 is at a high voltage level, the address three transistors 450a and 450b conduct to pull the address lines 472a and 472d low to a low voltage level and provide active low address signals A1 and A4, and SO on for each shift register output signal SO4-SO 13. The address signals A1, A2 … … A7 for each of the thirteen address slots are listed in the following table, which are associated with the shift register output signals SO1-SO 13.

Address time slot	Efficient address signal
		1	A1 and A2
2	A1 and A3
		3	A1 and A4
4	A1 and A5
		5	A1 and A6
6	E1EA7
		7	A2 and A3
8	A2 and A4
		9	A2 and A5
10	A2 and A6
		11	A2 and A7
12	A3 and A4
		13	A3 and A5

In another embodiment, the logic array 406 may provide valid address signals A1, A2 … … A7 for each of the thirteen address slots, which are listed in the following table:

address time slot	Efficient address signal
		1	A1 and A3
2	A1 and A4
		3	A1 and A5
4	A1 and A6
		5	A2 and A4
6	A2 and A5
		7	A2 and A6
8	A2 and A7
		9	A3 and A5
10	A3 and A6
		11	A3 and A7
12	A4 and A6
		13	A4 and A7

Also, in other embodiments, the logic array 406 may include address transistors that: they provide any suitable number of low voltage level address signals-A1, -A2 … … -A7 and in any suitable series of low voltage level address signals-A1, -A2 … … -A7 for each high voltage level output signal SO1-SO 13. These may be accomplished, for example, by appropriately configuring each transistor pair 446, 448 … … 470 to discharge any two desired address lines 672 a-g.

Additionally, in other embodiments, logic array 406 may include any suitable number of address lines to provide any suitable number of address signals in any suitable number of address time slots.

In operation, a repeating series of six timing pulses is provided from timing signals T1-T6. Each timing signal T1-T6 provides one timing pulse in each series of six timing pulses. The timing pulse from timing signal T1 is followed by a timing pulse from timing signal T2, which is followed by a timing pulse from timing signal T3, which is followed by a timing pulse from timing signal T4, which is followed by a timing pulse from timing signal T5, which is followed by a timing pulse from timing signal T6. The series of six timing pulses repeats as a repeating series of six timing pulses.

In one series of six timing pulses, direction circuit 404 receives a timing pulse from timing signal T3 in fourth PRE-charge signal PRE 4. The timing pulse in fourth PRE-charge signal PRE4 charges the first direction line of direction lines 408 to a high voltage level. Direction circuit 404 receives the falling voltage level timing pulse from timing signal T4 in fourth evaluation signal EVAL 4. If direction circuit 404 receives a control pulse in control signal CSYNC that coincides with fourth evaluation signal EVAL4, direction circuit 404 discharges first direction line 408. If direction circuit 404 receives low voltage level control signal CSYNC that coincides with a timing pulse in fourth evaluation signal EVAL4, first direction line 408 remains charged to the high voltage level.

Direction circuit 404 then receives a timing pulse from timing signal T5 in third PRE-charge signal PRE 3. The timing pulse in third PRE-charge signal PRE3 charges the second direction line of direction lines 408. Direction circuit 404 receives the falling voltage level timing pulse from timing signal T6 in third evaluation signal EVAL 3. If direction circuit 404 receives a control pulse in control signal CSYNC that coincides with a timing pulse in third evaluation signal EVAL3, direction circuit 404 discharges second direction line 408 to a low voltage level. Second direction circuit 408 remains charged to the high voltage level if direction circuit 404 receives low voltage level control signal CSYNC that coincides with a timing pulse in third evaluation signal EVAL 3.

If the first direction line 408 is discharged to a low voltage level and the second direction line 408 remains at a high voltage level, the signal levels on the first and second direction lines 408 cause the shift register 402 to shift in the forward direction. If the first direction line 408 remains at a high voltage level and the second direction line 408 is discharged to a low voltage level, the signal level on the direction line 408 causes the shift register 402 to shift in the reverse direction. If both the first and second direction lines 408 are discharged to a low voltage level, the shift register 402 is prevented from providing the high voltage level shift register output signals SO1-SO 13. The direction signal on direction line 408 is set during each series of six timing pulses.

Initially, the direction is set in one series of six timing pulses, and the shift register 402 starts in the next series of six timing pulses. To activate shift register 402, shift register 402 receives a timing pulse from timing signal T1 in first PRE-charge signal PRE 1. The timing pulses in first PRE-charge signal PRE1 PRE-charge the internal nodes in each of the thirteen shift register cells, which are labeled 403a-403 m. Shift register 402 receives the falling voltage level timing pulse from timing signal T2 in first evaluation signal EVAL 1. If shift register 402 receives a control pulse in control signal CSYNC that coincides with a timing pulse in first evaluation signal EVAL1, shift register 402 discharges the internal node of one of the thirteen shift register cells to provide a low voltage level at the discharged internal node. If control signal CSYNC remains at a low voltage level consistent with the timing pulses in first evaluation signal EVAL1, the internal nodes in each of the thirteen shift register cells remain at a high voltage level.

Shift register 402 receives a timing pulse from timing signal T3 in second PRE-charge signal PRE 2. The timing pulses in second PRE-charge signal PRE2 PRE-charge each of the thirteen shift register output lines 410a-410m to provide the high voltage level shift register output signals SO1-SO 13. Shift register 402 receives the falling voltage level timing pulse from timing signal T4 in second evaluation signal EVAL 2. If the internal node in shift register cell 403 is at a low voltage level, shift register 402 maintains shift register output signals SO1-SO13 at a high voltage level, for example, after receiving a control pulse from control signal CSYNC that coincides with a timing pulse in first evaluation signal EVAL 1. If the internal node in shift register cell 403 is at a high voltage level, such as in all other shift register cells 403, shift register 402 discharges shift register output lines 410a-410m to provide shift register output signals SO1-SO13 at a low voltage level. The shift register 402 starts in a series of six timing pulses. The shift register output signals SO1-SO13 are active during the timing pulse of the timing signal T4 from the second evaluation signal EVAL2 and remain active until the timing pulse of the timing signal T3 from the next series of six timing pulses. In each subsequent series of six timing pulses, shift register 402 shifts high voltage level shift register output signals SO1-SO13 from one shift register cell 403 to the next shift register cell 403.

The logic array 406 receives the shift register output signals SO1-SO 13. In one embodiment, logic array 406 receives a timing pulse from timing signal T3 to precharge address lines 472 and turn off address evaluation transistor 440. In one embodiment, logic array 406 receives a timing pulse from timing signal T3 to turn off address evaluation transistor 440 and a timing pulse from timing signal T4 to precharge address lines 472.

The logic array 406 receives timing pulses from the timing signal T4 to turn off the address evaluation transistors 440, while the shift register output signals SO1-SO13 are used to assert the shift register output signals SO1-SO 13. If the shift register 402 is enabled, one of the shift register output signals SO1-SO13 remains at a high voltage level after a timing pulse from the timing signal T4. Logic array 406 receives a timing pulse from timing signal T5 to charge evaluation signal line 474 and turn on address evaluation transistor 440. The address transistor pair 446, 448 … … 470 that receives the high voltage level shift register output signals SO1-SO13 are turned on to lower two of the seven address lines 472a-472g to a low voltage level. Two low voltage level address signals among the address signals a1 a2 … … a7 are used to initiate the activation of firing cells 120 and the firing cell subgroups. During the timing pulse from the timing signal T5, the address signals A1, A2 … … A7 become active and remain active until the timing pulse from the timing signal T3 in the next series of six timing pulses.

If the shift register 402 is not enabled, all of the shift register output lines 410 are discharged to provide the low voltage level shift register output signals SO1-SO 13. The low voltage level shift register output signals SO1-SO13 turn off the address transistor pair 446, 448 … … 470, and address line 472 remains charged to provide the high voltage level address signals A1, A2 … … A7. The address signals of high voltage levels a1 a2 … … a7 prevent the firing cells 120 and the firing cell subgroups from being allowed to be activated.

Although FIG. 9 depicts one embodiment of an address circuit, other embodiments employing different logic components may be utilized. For example, a controller may be utilized that receives the input signals described above, such as signals T1-T6, and that provides address signals A1 and A2 … … A7.

Fig. 10A is a diagram illustrating one shift register cell 403a in the shift register 402. Shift register 402 includes thirteen shift register cells 403a-403m that provide thirteen shift register output signals SO1-SO 13. Each shift register cell 403a-403m provides one of the shift register output signals SO1-SO13, and each shift register cell 403a-403m is similar to shift register cell 403 a. Thirteen shift register cells 403 are electrically connected in series to provide forward and reverse direction shifting. In other embodiments, shift register 402 may include any suitable number of shift register cells 403 to provide any suitable number of shift register output signals.

The shift register cell 403a contains a first stage, shown in dashed lines at 500, as an input stage, and a second stage, shown in dashed lines at 502, as an output stage. The first stage 500 includes a first precharge transistor 504, a first evaluation transistor 506, a forward input transistor 508, an inverting input transistor 510, a forward transistor 512, and an inverting transistor 514. The second stage 502 includes a second precharge transistor 516, a second evaluation transistor 518, and an internal node transistor 520.

In the first stage 500, one side of the drain-source path and the gate of the first pre-charge transistor 504 are electrically coupled to a timing signal line 432. Timing signal line 432 provides timing signal T1 to shift register 402 as first PRE-charge signal PRE 1. The other side of the drain-source path of first pre-charge transistor 504 is electrically coupled to one side of the drain-source path of first evaluation transistor 506 and is connected to the gate of internal node transistor 520 through internal node 522. The internal node 520 provides a shift register internal node signal SN1 between stages 500 and 502 to the gate of the internal node transistor 520.

The gate of the first evaluation transistor 506 is electrically coupled to a first evaluation signal line 420. First evaluation signal line 420 provides a reduced voltage level T2 timing signal to shift register 402 as first evaluation signal EVAL 1. The other side of the drain-source path of the first evaluation transistor 506 is electrically coupled to one side of the drain-source path of the forward input transistor 508 and one side of the drain-source of the reverse input transistor 510 through an internal path 524.

The other side of the drain-source path of forward input transistor 508 is electrically coupled to one side of the drain-source path of forward transistor 512 at 526, and the other side of the drain-source path of reverse input transistor 510 is electrically coupled to one side of the drain-source path of reverse transistor 514 at 528. The drain-source paths of forward transistor 512 and reverse transistor 514 are electrically coupled to a reference, such as ground, at 530.

The gate of forward transistor 512 is electrically coupled to direction line 408a, which receives forward signal DIRF from direction circuit 404. The gate of the inversion transistor 514 is electrically coupled to the direction line 408b that receives the inversion signal DIRR from the direction circuit 404.

In second stage 502, one side of the drain-source path and the gate of second precharge transistor 516 are electrically coupled to timing signal line 434. Timing signal line 434 provides timing signal T3 to shift register 402 as second PRE-charge signal PRE 2. The other side of the drain-source path of second precharge transistor 516 is electrically coupled to one side of the drain-source path of second evaluation transistor 518 and to shift register output line 410 a. The other side of the drain-source path of second evaluation transistor 518 is electrically coupled to one side of the drain-source path of internal node transistor 520 at 532. The gate of second evaluation transistor 518 is electrically coupled to second evaluation signal line 424 to provide a reduced voltage level T4 timing signal to shift register 402 as second evaluation signal EVAL 2. The gate of internal node transistor 520 is electrically coupled to internal node 522, while the other side of the drain-source path of internal node transistor 520 is electrically coupled to a reference, such as ground, at 534. The gate of internal node transistor 520 includes a capacitance at 536 for storing shift register cell internal node signal SN 1. The shift register output signal line 410a contains a capacitance at 538 for storing the shift register output signal SO 1.

Each shift register cell 403a-403m in the series of thirteen shift register cells 403 is similar to shift register cell 403 a. The gate of forward transistor 508 in each of shift register cells 403a-403m is electrically coupled to control line 430 or one of shift register output lines 410a-4101 for shifting in the forward direction. The gate of the inversion transistor 510 in each of the shift register cells 403a-403m is electrically coupled to either the control line 430 or one of the shift register output lines 410b-410m for shifting in the reverse direction. Shift register output signal line 410 is electrically coupled to a forward transistor 508 and a reverse transistor 510, with the exception of shift register output signal lines 410a and 410 m. Shift register output signal line 410a is electrically coupled to forward transistor 508 in shift register cell 403b, but not to reverse transistor 510. The shift register output signal line 410m is electrically coupled to the inversion transistor 510 in the shift register unit 4031, and is not electrically coupled to the forward transistor 508.

Shift register cell 403a is the first shift register 403 in the series of thirteen shift registers 403 when shift register 402 is shifted in the forward direction. The gate of forward input transistor 508 in shift register cell 403a is electrically coupled to control signal line 430 to receive control signal CSYNC. Second shift register cell 403b includes a gate of a forward input transistor electrically coupled to shift register output line 410a to receive shift register output signal SO 1. Third shift register cell 403c includes a gate of a forward input transistor electrically coupled to shift register output line 410b to receive shift register output signal SO 2. Fourth shift register cell 403d includes a gate of a forward input transistor electrically coupled to shift register output line 410c to receive shift register output signal SO 3. Fifth shift register cell 403e includes a gate of a forward input transistor electrically coupled to shift register output line 410d to receive shift register output signal SO 4. Sixth shift register cell 403f includes a gate of a forward input transistor electrically coupled to shift register output line 410e to receive shift register output signal SO 5. Seventh shift register cell 403g includes a gate of a forward input transistor electrically coupled to shift register output line 410f to receive shift register output signal SO 6. Eighth shift register cell 403h includes a gate of a forward input transistor electrically coupled to shift register output line 410g to receive shift register output signal SO 7. Ninth shift register cell 403i includes a gate of a forward input transistor electrically coupled to shift register output line 410h to receive shift register output signal SO 8. Tenth shift register cell 403j includes a gate of a forward input transistor electrically coupled to shift register output line 410I to receive shift register output signal SO 9. The eleventh shift register cell 403k includes a gate of a forward input transistor electrically coupled to shift register output line 410j to receive shift register output signal SO 10. The twelfth shift register cell 4031 includes a gate of a forward input transistor electrically coupled to shift register output trace 410k to receive shift register output signal SO 11. The thirteenth shift register cell 403m includes a gate of a forward input transistor electrically coupled to shift register output line 4101 to receive shift register output signal SO 12.

When shift register 402 is shifted in the reverse direction, shift register cell 403a is the last shift register cell 403 in the series of thirteen shift register cells 403. The gate of inverting input transistor 510 in shift register cell 403a is electrically coupled to preceding shift register output line 410b to receive shift register output signal SO 2. Shift register cell 403b includes a gate of an inverting input transistor electrically coupled to shift register output line 410c to receive shift register output signal SO 3. Shift register cell 403c includes a gate of an inverting input transistor electrically coupled to shift register output line 410d to receive shift register output signal SO 4. Shift register cell 403d includes a gate of an inverting input transistor electrically coupled to shift register output line 410e to receive shift register output signal SO 5. Shift register cell 403e includes a gate of an inverting input transistor electrically coupled to shift register output line 410f to receive shift register output signal SO 6. Shift register cell 403f includes a gate of an inverting input transistor electrically coupled to shift register output line 410g to receive shift register output signal SO 7. Shift register cell 403g includes a gate of an inverting input transistor electrically coupled to shift register output line 410h to receive shift register output signal SO 8. Shift register cell 403h includes a gate of an inverting input transistor electrically coupled to shift register output line 410I to receive shift register output signal SO 9. Shift register cell 403i includes a gate of an inverting input transistor electrically coupled to shift register output line 410j to receive shift register output signal SO 10. Shift register cell 403j includes a gate of an inverting input transistor electrically coupled to shift register output line 410k to receive shift register output signal S011. Shift register cell 403k includes a gate of an inverting input transistor electrically coupled to shift register output line 4101 to receive shift register output signal SO 12. Shift register cell 4031 includes a gate of an inverting input transistor electrically coupled to shift register output line 410m to receive shift register output signal SO 13. Shift register cell 403m includes a gate of an inverting input transistor electrically coupled to control signal line 430 to receive control signal CSYNC. Shift register output lines 410a-410m are also electrically coupled to logic array 406.

Shift register 402 receives the control pulses in control signal CSYNC and provides a single high voltage level output signal. As described above and in detail below, the shift direction of shift register 402 is set in response to direction signals DIRF and DIRR, which are generated during timing pulses in timing signals T3-T6 based on control signal CSYNC on control signal line 430. If the shift register 402 is shifted in the forward direction, the shift register 402 sets the shift register output line 410a and the shift register output signal SO1 to high voltage levels in response to the control pulses and the timing pulses on the timing signals T1-T4. If the shift register 402 is shifted in the reverse direction, the shift register 402 sets the shift register output line 410m and the shift register output signal SO13 to high voltage levels in response to the control pulse and the timing pulse in the timing signals T1-T4. In response to the timing pulses in the timing signals T1-T4, the high voltage level output signal SO1 or SO13 is shifted from one shift register cell 403 to the next shift register cell 403 through the shift register 402.

The shift register 402 shifts in a control pulse and shifts a single high-level output signal from one shift register cell 403 to the next shift register cell 403 with two precharge operations and two evaluation operations. The first stage 500 of each shift register cell 403 receives a forward signal DIRF and a reverse signal DIRR. Also, the first stage 500 of each shift register 403 receives a forward shift register input signal SIF and a reverse shift register input signal SIR. All shift register cells 403 in shift register 402 are set to shift in the same direction and at the same time as the timing pulses are received into timing signals T1-T4.

The first stage 500 of each shift register cell 403 is shifted by either the forward shift register input signal SIF or the reverse shift register input signal SIR. The high or low level selected shift register input signal SIF or SIR is provided as the shift register output signal SO1-SO 13. The first stage 500 of each shift register cell 403 precharges the internal node 522 during a timing pulse from timing signal T1 and evaluates the selected shift register input signal SIF or SIR during a timing pulse from timing signal T2. The second stage 502 in each shift register cell 403 precharges the shift register output lines 410a-410m during a timing pulse from timing signal T3 and evaluates the internal node signal SN (e.g., SN1) during a timing pulse from timing signal T4.

The direction signals DIRF and DIRR set the forward/reverse shift of shift register cell 403a in shift register 402 and all other shift register cells 403. If the forward signal DIRF is at a high voltage level and the reverse signal DIRR is at a low voltage level, the shift register 402 shifts in the forward direction. If reverse signal DIRR is at a high voltage level and forward signal DIRF is at a low voltage level, shift register 402 shifts in the reverse direction. If both direction signals DIRF and DIRR are at a low voltage level, shift register 402 is not shifted in both directions and all shift register output signals SO1-SO13 are cleared to an inactive low voltage level.

In the operation of shifting the shift register cell 403a in the forward direction, the forward signal DIRF is set to a high voltage level and the reverse signal DIRR is set to a low voltage level. The high voltage level forward signal DIRF turns on the forward transistor 512, while the low voltage level reverse signal DIRR turns off the reverse transistor 514. A timing pulse from timing signal T1 is provided to shift register 402 in first PRE-charge signal PRE1 to charge internal node 522 to a high voltage level through first PRE-charge transistor 504. Then, a timing pulse from timing signal T2 is provided to resistor divider network 412, and a falling voltage level T2 timing pulse is provided to shift register 402 in first evaluation signal EVAL 1. The timing pulse in first evaluation signal EVAL1 turns on first evaluation transistor 506. If the forward shift register input signal SIF is at a high voltage level, the forward input transistor 508 will be turned on and since the forward transistor 512 has been turned on, the internal node 522 is discharged to provide the low voltage level internal node signal SN 1. The internal node 522 is discharged through the first evaluation transistor 506, the forward input transistor 508, and the forward transistor 512. If the forward shift register input signal SIF is at a low voltage level, the forward input transistor 508 is turned off and the internal node 522 remains charged to provide the high voltage level internal node signal SN 1. The reverse shift register input signal SIR controls the reverse input transistor 510. However, the inverting transistor 514 is turned off so that the internal node 522 cannot be discharged through the inverting input transistor 510.

Internal node transistor 520 is controlled by internal node signal SN1 on internal node 522. The internal node transistor 520 is turned off by the internal node signal SN1 of the low voltage level, and the internal node transistor 520 is turned on by the internal node signal SN1 of the high voltage level.

The timing pulse from timing signal T3 is provided to shift register 402 as second PRE-charge signal PRE 2. The timing pulse in second PRE-charge signal PRE2 charges shift register output line 410a to a high voltage level through second PRE-charge transistor 516. The resistor divide network 414 is then provided with timing pulses from timing signal T4 and provides the falling voltage level T4 timing pulses to the shift register 402 as a second evaluation signal EVAL 2. The timing pulse in second evaluation signal EVAL2 turns on second evaluation transistor 518. If internal node transistor 520 is off, shift register output line 410a remains charged to the high voltage level. If internal node transistor 520 is on, shift register output line 410a is discharged to a low voltage level. The shift register output signal SO1 is a high/low inversion of the internal node signal SN1, which is a high/low inversion of the forward shift register input signal SIF. The level of the forward shift register input signal SIF is shifted to the shift register output signal SO 1.

In shift register cell 403a, the forward shift register input signal SIF is control signal CSYNC on control line 430. To discharge internal node 522 to a low voltage level, the control pulses in control signal CSYNC are provided at the same time as the timing pulses in first evaluation signal EVAL 1. A control pulse in control signal CSYNC that coincides with a timing pulse from timing signal T2 starts shift register 402 to shift in the forward direction.

In the operation of shifting the shift register cell 403a in the reverse direction, the forward signal DIRF is set to a low voltage level and the reverse signal DIRR is set to a high voltage level. The low voltage level forward signal DIRF turns off the forward transistor 512, while the high voltage level reverse signal DIRR turns on the reverse transistor 514. A timing pulse from timing signal T1 is provided in first PRE-charge signal PRE1 to charge internal node 522 to a high voltage level through first PRE-charge transistor 504. Then, the timing pulse from timing signal T2 is provided to resistor divider network 412, and the falling voltage level T2 timing pulse is provided in first evaluation signal EVAL 1. The timing pulse in first evaluation signal EVAL1 turns on first evaluation transistor 506. If the reverse shift register input signal SIR is at a high voltage level, the reverse input transistor 510 is turned on and since the reverse transistor 514 has been turned on, the internal node 522 is discharged to provide the low voltage level internal node signal SN 1. The internal node 522 is discharged through the first evaluation transistor 506, the inverting input transistor 510, and the inverting transistor 514. If the reverse shift register input signal SIR is at a low voltage level, the reverse input transistor 510 is turned off and the internal node 522 remains charged to provide the high voltage level internal node signal SN 1. The forward shift register input signal SIF controls the forward input transistor 508. However, the forward direction transistor 512 is turned off so that the internal node 522 cannot be discharged through the forward direction input transistor 508.

The timing pulse from timing signal T3 is provided in second PRE-charge signal PRE 2. The timing pulse in second PRE-charge signal PRE2 charges shift register output line 410a to a high voltage level through second PRE-charge resistor 516. Then, the timing pulse from timing signal T4 is provided to resistor divider network 414, and the falling voltage level T4 timing pulse is provided in second evaluation signal EVAL 2. The timing pulse in second evaluation signal EVAL2 turns on second evaluation transistor 518. If internal node transistor 520 is turned off, shift register output line 410a remains charged to the high voltage level. If internal node transistor 520 is on, shift register output line 410a is discharged to a low voltage level. The shift register output signal SO1 is a high/low inversion of the internal node signal SN1, which is a high/low inversion of the inverse shift register input signal SIR. The level of the reverse shift register input signal SIR is shifted to the shift register output signal SO 1.

In shift register cell 403a, the reverse shift register input signal SIR is shift register output signal SO2 on shift register output line 410 b. In shift register cell 403m, the reverse shift register input signal SIR is control signal CSYNC on control line 430. To discharge internal node 522 in shift register cell 403m to a low voltage level, a control pulse in control signal CSYNC is provided at the same time as a timing pulse in first evaluation signal EVAL 1. The start pulse in control signal CSYNC, which coincides with the timing pulse from timing signal T2, causes shift register 402 to shift in the reverse direction, i.e., from shift register cell 403m to shift register cell 403 a.

In an operation to clear shift register cell 403a and all shift register cells 403 in shift register 402, direction signals DIRF and DIRR are set to a low voltage level. The low voltage level forward signal DIRF turns off the forward transistor 512 and the low voltage level reverse signal DIRR turns off the reverse transistor 514. A timing pulse from timing signal T1 is provided in first PRE-charge signal PRE1 to charge internal node 522 and provide a high voltage level internal node signal SN 1. The timing pulse from timing signal T2 is provided as a falling voltage level T2 timing pulse in the first evaluation signal EVAL1 to turn on the first evaluation transistor 506. Both the forward direction transistor 512 and the reverse direction transistor 514 are turned off so that the internal node 522 is not discharged through either the forward direction input transistor 508 or the reverse direction input transistor 510.

The internal node signal SN1 of the high voltage level turns on the internal node transistor 520. A timing pulse from timing signal T3 is provided in second PRE-charge signal PRE2 to charge shift register output signal line 410a and all shift register output signal lines 410. Then, the timing pulse from the timing signal T4 is provided as a falling voltage level T4 timing pulse in the second evaluation signal EVAL2 to turn on the second evaluation transistor 518. The shift register output line 410a is discharged through the second evaluation transistor 518 and the internal node transistor 520 to provide the shift register output signal SO1 at a low voltage level. Also, all other shift register output lines 410 are discharged to provide inactive low voltage level shift register output signals SO2-SO 13.

Fig. 10B is a diagram illustrating the direction circuit 404. The direction circuit 404 includes a forward signal circuit 550 and a reverse signal circuit 552. The forward signal circuit 550 includes a third precharge transistor 554, a third evaluation transistor 556, and a first control transistor 558. The invert signal circuit 552 includes a fourth precharge transistor 560, a fourth evaluation transistor 562, and a second control transistor 564.

One side of the drain-source path and the gate of third precharge transistor 554 are electrically coupled to timing signal line 436. Timing signal line 436 provides timing signal T5 to direction circuit 404 as third PRE-charge signal PRE 3. The other side of the drain-source path of third pre-charge transistor 554 is electrically coupled to one side of the drain-source path of third evaluation transistor 556 by way of direction signal line 408 a. A direction signal line 408a provides a forward signal DIRF to the gate of the forward transistor in each shift register cell 403 in shift register 402, e.g., the gate of forward transistor 512 in shift register cell 403 a. The gate of the third evaluation transistor 556 is electrically coupled to a third evaluation signal line 428, the third evaluation signal line 428 providing a reduced voltage level T6 timing signal to the direction circuit 404. The other side of the drain-source path of the third evaluation transistor 556 is electrically coupled to the drain-source path of the control transistor 558 at 566. The drain-source path of the control transistor 558 is also electrically coupled to a reference, such as ground, at 568. The gate of control transistor 558 is electrically coupled to control line 430 to receive control signal CSYNC.

One side of the drain-source path and the gate of the fourth precharge transistor 560 are electrically coupled to the timing signal line 434. Timing signal line 434 provides timing signal T3 to direction circuit 404 as fourth PRE-charge signal PRE 4. The other side of the drain-source path of fourth pre-charge transistor 560 is electrically coupled to one side of the drain-source path of fourth evaluation transistor 562 via direction signal line 408 b. The direction signal line 408b provides an inversion signal DIRR to the gate of the inversion transistor in each shift register cell 403 in the shift register 402, e.g., the gate of the inversion transistor 514 in shift register cell 403 a. The gate of the fourth evaluation transistor 562 is electrically coupled to a fourth evaluation signal line 424, the fourth evaluation signal line 424 providing a reduced voltage level T4 timing signal to the direction circuit 404. The other side of the drain-source path of fourth evaluation transistor 562 is electrically coupled to the drain-source path of control transistor 564 at 570. The drain-source path of the control transistor 564 is also electrically coupled to a reference, such as ground, at 572. The gate of control transistor 564 is electrically coupled to control line 430 to receive control signal CSYNC.

The direction signals DIRF and DIRR set the shift direction in the shift register 402. If forward signal DIRF is set to a high voltage level and reverse signal DIRR is set to a low voltage level, then the forward transistors, such as forward transistor 512, are turned on and the reverse transistors, such as reverse transistor 514, are turned off. The shift register 402 shifts in the forward direction. If forward signal DIRF is set to a low voltage level and reverse signal DIRR is set to a high voltage level, then the forward transistors, such as forward transistor 512, are turned off and the reverse transistors, such as reverse transistor 514, are turned on. The shift register 402 shifts in the reverse direction. The direction signals DIRF and DIRR are set during each series of timing pulses from timing signals T3-T6 while shift register 402 is effectively shifted in either the forward or reverse direction. To terminate the shift or prevent shifting of shift register 402, direction signals DIRF and DIRR are set to a low voltage level. This clears the single high voltage level signal from the shift register output signals SO1-SO13 SO that all of the shift register output signals SO1-SO13 are at a low voltage level. Shift register output signal SO1-SO13 at a low voltage level turns off all address transistor pairs 446, 448 … …, and address signals A1, A2.

In operation, timing signal line 434 provides a timing pulse from timing signal T3 to direction circuit 404 in fourth PRE-charge signal PRE 4. The timing pulse in fourth PRE-charge signal PRE4 charges inversion signal line 408b to a high voltage level. The timing pulses from timing signal T4 are provided to resistor divider network 414, and resistor divider network 414 provides the reduced voltage level T4 timing pulses to directional circuit 404 in fourth evaluation signal EVAL 4. A timing pulse in fourth evaluation signal EVAL4 turns on fourth evaluation transistor 562. If a control pulse from control signal CSYNC is provided to the gate of control transistor 564 while a timing pulse in fourth evaluation signal EVAL4 is provided to fourth evaluation transistor 562, then inverted signal line 408b discharges to a low voltage level. If control signal CSYNC remains at a low voltage level while the timing pulses in fourth evaluation signal EVAL4 are provided to fourth evaluation transistor 562, then reverse signal line 408b remains charged to a high voltage level.

Timing signal line 436 provides a timing pulse from timing signal T5 to direction circuit 404 in third PRE-charge signal PRE 3. The timing pulse in third PRE-charge signal PRE3 charges forward signal line 408a to a high voltage level. The timing pulses from timing signal T6 are provided to resistor divider network 416, which resistor divider network 416 provides the falling voltage level T6 timing pulses to a third evaluation circuit EVAL3 of direction circuit 404. The timing pulse in third evaluation signal EVAL3 turns on third evaluation transistor 556. If a control pulse from control signal CSYNC is provided to the gate of control transistor 558 while a timing pulse in third evaluation signal EVAL3 is provided to third evaluation transistor 556, forward signal line 408a discharges to a low voltage level. If control signal CSYNC remains at a low voltage level when a timing pulse in third evaluation signal EVAL3 is provided to third evaluation transistor 556, forward signal line 408a remains charged to a high voltage level.

Fig. 11 is a timing diagram illustrating the operation of the address generator 400 in the forward direction. The timing signals T1-T6 provide a series of six repeating pulses. Each timing signal T1-T6 provides one pulse of the series of timing pulses.

In one series of six pulses, timing signal T1 at 600 includes timing pulse 602, timing signal T2 at 604 includes timing pulse 606, timing signal T3 at 608 includes timing pulse 610, timing signal T4 at 612 includes timing pulse 614, timing signal T5 at 616 includes timing pulse 618, timing signal T6 at 620 includes timing pulse 622. The control signal CSYNC at 624 contains control pulses that set the shift direction in the shift register 402 and activate the shift register 402 to generate the address signals A1, A2 … … A7 labeled 625.

Timing pulse 602 of timing signal T1 at 600 is provided to shift register 402 in first PRE-charge signal PRE 1. During the timing pulse 602, the internal node 522 in each of the shift register cells 403a-403m charges to provide the high voltage level internal node signals SN1-SN 13. All shift register internal node signals SN, labeled 626, are set to a high voltage level at 628. The high voltage level internal node signal SN 626 turns on the internal node transistor 520 in each of the shift register cells 403a-403 m. In this embodiment, the series of six timing pulses have been provided prior to timing pulse 602, and shift register 402 has not been enabled, such that all shift register output signals SO labeled 630 are discharged to a low voltage level, labeled 632, and all address signals A1, A2 … … A7 at 625 remain at a high voltage level, labeled 633.

Timing pulse 606 of timing signal T2 at 604 is provided to shift register 402 in first evaluation signal EVAL 1. The timing pulse 606 turns on the first evaluation transistor 506 in each of the shift register cells 403a-403 m. When control signal CSYNC624 is held at a low voltage level at 634 and all shift register output signals SO 630 are held at a low voltage level at 636, the forward input transistor 508 and the reverse input transistor 510 in each of the shift register cells 403a-403m are turned off. The non-conductive forward input transistor 508 and the non-conductive reverse input transistor 510 prevent the internal node 522 in each shift register cell 403a-403m from discharging to a low voltage level. All shift register internal node signals SN626 remain at a high voltage level at 638.

Timing pulse 610 of timing signal T3 at 608 is provided to shift register 402 in second PRE-charge signal PRE2, to direction circuit 404 in fourth PRE-charge signal PRE4, and to address line PRE-charge transistor 438 and evaluation prevention transistor 422a in logic array 406. During timing pulse 610 of second PRE-charge signal PRE2, all shift register output signals SO 630 charge to a high voltage level at 640. Also, during timing pulse 610 in fourth PRE-charge signal PRE4, reverse signal DIRR642 charges to a high voltage level at 644. In addition, timing pulse 610 charges all address signals 625 to a high voltage level at 646 and turns on evaluation prevention transistor 422a to cause logic evaluation signal LEVAL 648 to drop to a low voltage level at 650.

Timing pulse 614 of timing signal T4 at 612 is provided to shift register 402 in second pre-charge signal EVAL2, to direction circuit 404 in fourth evaluation signal EVAL4, and to evaluation prevention transistor 422b in logic array 406. Timing pulse 614 in second evaluation signal EVAL2 turns on second evaluation transistor 518 in each of shift register cells 403a-403 m. Since internal node signal SN626, which is at a high voltage level, has turned on internal node transistor 520 in each of shift register cells 403a-403m, all shift register output signals SO630 discharge to a low voltage level at 652. Also, timing pulse 614 in fourth evaluation signal EVAL4 turns on fourth evaluation transistor 562. The control pulse of control signal CSYNC624 at 654 turns on control transistor 564. Since the fourth evaluation transistor 562 and the control transistor 564 are turned on, the direction signal DIRR 642 is discharged to a low voltage level at 656. In addition, timing pulse 614 turns on evaluation prevention transistor 442b to hold logic evaluation signal LEVAL648 at a low voltage level at 658. The low voltage level logic evaluation signal LEVAL648 turns off the address evaluation transistor 440.

Timing pulse 618 of timing signal T5 at 616 is provided to direction circuit 404 in third precharge signal PRE3 and to logic evaluation precharge transistors 444 in logic array 406. During timing pulse 618 in third PRE-charge signal PRE3, forward signal DIRF658 charges to a high voltage level at 660. A high voltage level forward signal DIRF658 turns on the forward transistor 512 in each shift register cell 403a-403m to set the shift register 402 to shift in the forward direction. Also during timing pulse 618, logic evaluation signal LEVAL648 charges to a high voltage level at 662, which turns on all logic evaluation transistors 440. Since all the shift register output signals SO 630 are at a low voltage level, all the address transistor pairs 446, 448 … … 470 are turned off, and all the address signals A1, A2 … … A7 remain at a high voltage level at 625.

Timing pulse 622 from timing signal T6 is provided to direction circuit 404 as third evaluation signal EVAL 3. The timing pulse 622 turns on the third evaluation transistor 556. Because control signal CSYNC624 remains at a low voltage level at 664, control transistor 558 turns off and forward signal DIRF658 remains at a high voltage level. A high voltage level forward signal DIRF658 and a low voltage level reverse signal DIRR642 set each shift register cell 403a-403m to shift in the forward direction.

In the next series of six timing pulses, timing pulse 666 charges all internal node signals SN626 to a high voltage level. Timing pulse 668 turns on the first evaluation transistor 506 in each shift register cell 403a-403 m. Control signal CSYNC624 provides a control pulse at 670 to the positive input transistor 508 in shift register cell 403 a. Since the forward transistor 512 has been turned on, the internal node signal SN1 in shift register cell 403a discharges to a low voltage level, labeled 672. Shift register output signal SO630 is at a low voltage level at 674, which turns off the forward input transistors in shift register cells 403b-403 m. Each of the other internal node signals SN2-SN13 in shift register cells 403b-403m remains at a high voltage level, labeled 676, due to the forward input transistor being turned off.

During timing pulse 678, all shift register output signals SO630 are charged to a high voltage level at 680, and reverse signal DIRR 642 is charged to a high voltage level at 682. In addition, during timing pulse 678, all address signals A1, A2 … … A7625 are charged to a high voltage level at 684, and logic evaluation signal LEVAL648 is discharged to a low voltage level at 686. The low level logic evaluation signal LEVAL648 turns off the address evaluation transistor 440, which prevents the address transistor pair 446, 448 … … 470 from dropping the address signals A1A 2 … … A7625 to the low voltage level.

During timing pulse 688, shift register output signals SO2-SO13 discharge to a low voltage level at 690. The shift register output signal SO1 remains at a high voltage level, labeled 692 because internal node signal SN1 turns off internal node transistor 520 of shift register cell 403a at 672. Also, timing pulse 688 turns on second evaluation transistor 562 and control pulse 694 turns on control transistor 564 to discharge reverse signal DIRR642 to a low voltage level at 696. In addition, timing pulse 688 turns on evaluation prevention transistor 442b to pull logic evaluation signal LEVAL648 low to a low voltage level at 698 and keep evaluation transistor 440 off.

During timing pulse 700, forward signal DIRF658 is maintained at a high voltage level, and logic evaluation signal lev 648 is charged to the high voltage level at 702. The logic evaluation signal LEVAL648 at a high voltage level turns on the evaluation transistor 440 at 702. The high level shift register output signal SO1 at 692 turns on the address transistor pair 446a and 446b, and the address signals A1 and A2 at 625 are effectively pulled low to a low voltage level at 704. The other shift register output signals SO2-SO13 are pulled low to a low voltage level at 690 such that the address transistors 448, 450 … … 470 are turned off and the address signals A3-A7 remain at a high voltage level, labeled 706. The address signals A1 and A2 … … A7 at 625 become active during the timing pulse 700 in the timing signal T5 at 616. The timing pulse 708 turns on the third evaluation transistor 556. However, control signal CSYNC624 is at a low voltage level at 710, and forward signal DIRF658 remains at a high voltage level at 712.

In the next series of six timing pulses, timing pulse 714 charges all internal node signals SN626 to a high voltage level at 716. If the forward input signal SIF at each shift register cell 403a-403m is at a high voltage level, the timing pulse 718 turns on the first evaluation transistor 506 in each shift register cell 403a-403m to allow the node 522 to discharge. The forward input signal SIF at shift register cell 403a is control signal CSYNC624, which is at a low voltage level at 720. The forward input signal SIF at each of the other shift register cells 403b-403m is the shift register output signal SO630 of the preceding shift register cell 403. Shift register output signal SO1 is at a high voltage level at 692 and is the forward input signal SIF of second shift register cell 403 b. The shift register output signals SO2-SO23 are all at a low voltage level at 690.

The shift register cells 403a and 403c-403m receive a low voltage level forward input signal SIF that turns off the forward input transistor 508 in each of the shift register cells 403a and 403c-403m so that the internal node signals SN1 and SN3-SN13 remain high at 722. The shift register cell 403b receives the high voltage level shift register output signal SO1 as the forward input signal SIF, which turns on the forward input transistor to discharge the internal node signal SN2 at 724.

During timing pulse 726, all shift register output signals SO630 are charged to a high voltage level at 728, and reverse signal DIRR642 is charged to a high voltage level at 730. Also, timing pulse 726 charges all address signals A1, A2 … … A7625 to a high voltage level at 732 and turns on evaluation prevention transistor 442a to pull LEVAL648 to a low voltage level at 734.

From the time address signals A1, A2 are pulled low to low at 704 until all address signals A1, A2 … …, A7625 are pulled high to high at 732, address signals A1, A2 … …, A7625 are active. The address signals A1 and A2 … … A7625 are valid during the timing pulse 708 from timing signal T6 at 620 of the first six timing pulses and during timing pulses 714 and 718 from timing signal T1 at 600 and timing pulse T2 at 604 of the current six timing pulses.

Timing pulse 736 turns on the second evaluation transistor 518 in each of the shift register cells 403a-403m to evaluate the internal node signal SN 626. The internal node signals SN1 and SN3-SN13 are at a high voltage level at 722 and discharge the shift register output signals SO1 and SO3-SO13 to a low voltage level at 738. The internal node signal SN2 is at a low voltage level at 724, which turns off the internal node transistors of shift register cell 403b and maintains the shift register output signal SO2 at a high voltage level at 740.

When fourth evaluation transistor 562 turns on with timing pulse 736 and control pulse 742 in CSYNC624 turns on control transistor 564, reverse signal DIRR642 discharges to a low voltage level at 744. The direction signals DIRR642 and DIRF658 are set during each series of six timing pulses. In addition, timing pulse 736 turns on evaluation prevention transistor 442b to hold LEVAL648 at a low voltage level at 746.

During timing pulse 748, forward signal DIRF658 is maintained at a high voltage level at 750, and LEVAL648 charges to a high voltage level at 752. A high voltage level logic evaluation signal LEVAL678 at 752 turns on evaluation transistor 440. The high voltage level shift register output signal SO2 at 740 turns on to address transistors 448a and 448b to pull address signals A1 and A3 low to a low voltage level at 754. The other address signals A2 and A4A 7 are maintained at a high voltage level at 756.

The timing pulse 758 turns on the third evaluation transistor 556. Control signal CSYNC624 remains at a low voltage level at 760 to turn off control transistor 558 and to maintain forward signal DIRF642 at a high voltage level.

The next series of six timing pulses shifts the high voltage level shift register output signal SO2 to the next shift register cell 403c, which shift register cell 403c provides a high voltage level shift register output signal SO 3. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 has gone high once. The series of high voltage level shift register output signals SO630 stops after the shift register output signal SO13 has gone high. The shift register 402 can be restarted by providing a control pulse, such as control pulse 670, in control signal CSYNC that coincides with the timing pulse from timing signal T2 at 604.

In forward operation, a control pulse in control signal CSYNC624 is provided that coincides with a timing pulse from timing signal T4 at 612 to set the shift direction to the forward direction. Also, a control pulse from control signal CSYNC624 is provided that coincides with the timing pulse from timing signal T2 at 604 to start or initiate shifting of the high voltage signal by the shift register output signals SO1-SO13 by the shift register 402.

Fig. 12 is a timing diagram illustrating the operation of the address generator 400 in the reverse direction. The timing signals T1-T6 provide a repeating series of six pulses. Each timing signal T1-T6 provides one pulse in a series of timing pulses. In one series of six pulses, timing signal T1 at 800 contains timing pulse 802, timing signal T2 at 804 contains timing pulse 806, timing signal T3 at 808 contains timing pulse 810, timing signal T4 at 812 contains timing pulse 814, timing signal T5 at 816 contains timing pulse 818, and timing signal T6 at 820 contains timing pulse 822. The control signal CSYNC at 824 contains control pulses that set the shift direction in the shift register 402 and enable the shift register 402 to generate the address signals A1, A2 … … A7, labeled 825.

Timing pulse 802 is provided to shift register 402 in first precharge signal PRE 1. During timing pulse 802, internal node 522 in each of the shift register cells 403a-403m charges to provide a corresponding high voltage level internal node signal SN1-SN 13. The shift register internal node signal SN826 is set to a high voltage level at 828. The high voltage level internal node signal SN826 turns on the internal node transistor 520 in the shift register cell 403. In this embodiment, a series of six timing pulses have been provided prior to timing pulse 802, and shift register 402 is not activated, such that all shift register output signals SO830 are discharged to a low voltage level, indicated at 832, and all address signals A1, A2 … … A7 at 825 remain at a high voltage level, indicated at 833.

Timing pulse 806 is provided to shift register 402 in first evaluation signal EVAL 1. The timing pulse 806 turns on the first evaluation transistor 506 in each of the shift register cells 403a-403 m. The control signal CSYNC824 remains at a low voltage level at 834 and all shift register output signals SO830 remain at a low voltage level at 836 to turn off the forward input transistor 508 and the reverse input transistor 510 in each shift register cell 403a-403 m. The non-conductive forward and reverse input transistors 508 and 510 prevent the internal node 522 in each shift register cell 403a-403m from discharging to a low voltage level. All shift register internal node signals SN826 remain at a high voltage level at 838.

Timing pulse 810 is provided to shift register 402 in second PRE-charge signal PRE2, to direction circuit 404 in fourth PRE-charge signal PRE4, and to address line PRE-charge transistor 438 and evaluation prevention transistor 422a in logic array 406. During timing pulse 810, all shift register output signals SO830 are charged to a high voltage level at 840. Also, during timing pulse 810, the reverse signal DIRR842 charges to a high voltage level at 844. In addition, timing pulse 810 holds all address signals 825 at a high voltage level and turns on evaluation prevention transistor 422a to cause logic evaluation signal LEVAL848 to drop to a low voltage level at 850.

Timing pulse 814 is provided to shift register 402 in second pre-charge signal EVAL2, to direction circuit 404 in fourth evaluation signal EVAL4, and to evaluation prevention transistor 422b in logic array 406. Timing pulse 814 turns on the second evaluation transistor 518 in each of the shift register cells 403a-403 m. All shift register output signals SO830 discharge to a low voltage level at 852 due to internal node signal SN826, which is at a high voltage level, turning on internal node transistor 520 in each of shift register cells 403a-403 m. Also, timing pulse 814 turns on fourth evaluation transistor 562 and control signal CSYNC824 provides a low voltage to turn off control transistor 564. The reverse signal DIRR842 remains charged to a high voltage level as the control transistor 564 is turned off. In addition, timing pulse 814 turns on evaluation prevention transistor 442b to hold logic evaluation signal LEVAL848 at a low voltage level at 858. The low voltage level logic evaluation signal LEVAL848 turns off the address evaluation transistor 440.

Timing pulse 818 is provided to direction circuit 404 in third precharge signal PRE3 and to logic evaluation precharge transistors 444 in logic array 406. During timing pulse 818, forward signal DIRF858 charges to a high voltage level at 860. Also during timing pulse 818, logic evaluation signal LEVAL848 charges to a high voltage level at 662 to turn on all logic evaluation transistors 440. Since all of the shift register output signals SO830 are at a low voltage level, all of the address transistor pairs 446, 448 … … 470 are turned off, and all of the address signals A1, A2 … … A7 at 825 remain at a high voltage level.

Timing pulse 822 is provided to directional circuit 404 as third evaluation signal EVAL 3. The timing pulse 822 turns on the third evaluation transistor 556. Control signal CSYNC824 provides control pulse 864 to turn on control transistor 558 and forward signal DIRF858 is discharged to a low voltage level at 865. Low voltage level forward signal DIRF858 and high voltage level reverse signal DIRR842 set each shift register cell 403a-403m to shift in the reverse direction.

In the next series of six timing pulses, all internal node signals SN826 are charged to a high voltage level during timing pulse 866. Timing pulse 868 turns on the first evaluation transistor 506 in each shift register cell 403a-403 m. A control pulse 870 is provided which may be in control signal CSYNC to turn on the inverting input transistor in shift register cell 403m and, since the inverting transistor is turned on, internal node signal SN13 discharges to a low voltage level, labeled 872. The shift register output signal SO830 is at a low voltage level at 874, which turns off the inverting input transistors in the shift register cells 403 a-4031. With the inverting input transistor off, each of the other internal node signals SN1-SN12 remains at a high voltage level, designated 876.

During timing pulse 878, all shift register output signals SO830 are charged to a high voltage level at 880 and the reverse signal DIRR842 is maintained at a high voltage level at 882. In addition, timing pulse 878 holds all of the address signals A1, A2 … … A7825 at a high voltage level at 884 and pulls logic evaluation signal LEVAL848 low to a low voltage level at 886. The low voltage level logic evaluation signal LEVAL848 turns off the address evaluation transistor 440, which prevents the address transistor pair 446, 448 … … 470 from dropping the address signals A1A 2 … … A7825 to a low voltage level.

During timing pulse 888, shift register output signals SO1-SO12 are discharged to a low voltage level at 890. The shift register output signal SO13 remains at a high voltage level based on the low voltage level internal node signal SN13 at 872, which turns off the internal node transistor 520 of the shift register cell 403 m. Also, timing pulse 888 turns on the second evaluation transistor and control signal CSYNC824 turns off control transistor 564 to hold reverse signal DIRR842 at a high voltage level at 896. In addition, timing pulse 888 turns on evaluation prevention transistor 442b to hold logic evaluation signal LEVAL848 at 898 at a low voltage level and to keep evaluation transistor 440 turned off. The shift register output signal SO830 is asserted (set) during the timing pulse 888 such that one shift register output signal SO13 is at a high voltage level and all other shift register output signals SO1-SO12 are at a low voltage level.

During timing pulse 900, forward signal DIRF858 charges to a high voltage level at 901, and logic evaluation signal LEVAL848 charges to a high voltage level at 902. The high voltage level logic evaluation signal LEVAL848 at 902 turns on the evaluation transistor 440. The high voltage level shift register output signal SO13 at 892 is routed to the address transistors 470a and 470b and the address signals A3 and A5 are effectively pulled low to a low voltage level, labeled 904. The other shift register output signals SO1-SO12 are pulled low to a low voltage level at 890, such that address transistor pair 446, 448 … … 468 is turned off, and address signals A1, A2, A4, A6, and A7 remain at a high voltage level, labeled 906. The address signals a1 and a2 … … a7825 become active during the timing pulse 900. Timing pulse 908 turns on third evaluation transistor 556 and control pulse 910 in control signal CSYNC824 turns on control transistor 558 to discharge forward signal DIRF858 to a low voltage at 912.

In the next series of six timing pulses, all internal node signals SN826 are charged to a high voltage level at 916 during timing pulse 914. If the reverse input signal SIR at each shift register cell 403a-403m is at a high voltage level, timing pulse 918 turns on first evaluation transistor 506 in each shift register cell 403a-403m to discharge node 522. The reverse input signal SIR at shift register cell 403m is control signal CSYNC824, which is at a low voltage level at 920. The inverted input signal SIR at each of the other shift register cells 403a-4031 is the shift register output signal SO830 of the subsequent shift register cell 403. The shift register output signal SO13 is at a high voltage level at 892 and is the inverted input signal SIR of the shift register cell 4031. The shift register output signals SO1-SO12 are all at a low voltage level at 890. The shift register cells 403a-403k and 403m have low voltage level inverted input signals SIR that turn off the inverted input transistors 510 so that the internal node signals SN1-SN11 and SN13 remain at high voltage levels at 922. The shift register cell 4031 receives the high voltage level shift register output signal SO13 as the inverting input signal SIR, which turns on the inverting input transistor to discharge the internal node signal SN12 at 924.

During timing pulse 926, all shift register output signals SO830 are charged to a high voltage level at 928, and reverse signal DIRR842 is maintained at a high voltage level at 930. Also, during timing pulse 926, all address signals A1, A2 … … A7825 are charged to a high voltage level at 932, and evaluation prevention transistor 442a is turned on to pull LEVAL848 low to a low voltage level at 934. Address signals A1, A2 … … A7825 are active from address signals A3 and A5 being pulled low at 904 until all address signals A1, A2 … … A7825 are pulled high at 932. Address signals A1, A2 … … A7825 are active during timing pulses 908, 914, and 918.

Timing pulse 936 turns on the second evaluation transistor 518 in each of the shift register cells 403a-403m to evaluate the internal node signal SN 826. The internal node signals SN1-SN11 and SN13 are at a high voltage level at 922 to discharge the shift register output signals SO1-S011 and SO13 to a low voltage level at 938. The internal node signal SN12 is at a low voltage level at 924, which turns off the internal node transistors of the shift register cell 4031 and holds the shift register output signal SO12 at a high voltage level at 940.

Also, timing pulse 936 turns on fourth evaluation transistor 562 and control signal CSYNC 824 is at a low voltage level to turn off control transistor 564 to hold reverse signal DIRR 842 at a low voltage level at 944. In addition, timing pulse 936 turns on evaluation prevention transistor 442b to hold logic evaluation signal LEVAL848 at a low voltage level at 946.

During timing pulse 948, forward signal DIRF 858 is charged to a high voltage level, and logic evaluation signal LEVAL648 is charged to a high voltage level at 952. The high voltage level logic evaluation signal LEVAL848 at 952 turns on the evaluation transistor 440. The high voltage level shift register output signal SO12 at 940 is routed to address transistors 468a and 468b to pull the address signals A3 and A4 low to a low voltage level at 954. The other address signals A1, A2, and A5-A7 are maintained at a high voltage level at 956.

The timing pulse 958 turns on the third evaluation transistor 556. A control pulse 960 in control signal CSYNC 824 turns on control transistor 558 and forward signal DIRF 842 discharges to a low voltage level at 962.

The next series of six timing pulses shifts high voltage level shift register output signal SO12 to the next shift register cell 403k, shift register cell 403k providing high voltage level shift register output signal S011. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 has gone high once. After shift register output signal SO1 is high, the series of high voltage level shift register output signals SO 830 are stopped. The shift register 402 may be restarted by providing a control pulse, such as control pulse 870, that coincides with the timing pulse from timing signal T2804.

In the reverse operation, a control pulse from CSYNC824 is provided that coincides with a timing pulse from timing signal T6 at 820 to set the shift direction to the reverse direction. Also, a control pulse from the control level signal CSYNC824 is provided that coincides with the timing pulse from the timing level signal T2 at 804 to start or initiate shifting of the high voltage level signal by the shift register 402 via the shift register output level signals SO1-SO 13.

FIG. 13 is a block diagram illustrating one embodiment of two address generators 1000 and 1002 and six fire groups 1004a-1004 f. Each address generator 1000 and 1002 is similar to the address generator 400 of FIG. 9, and the fire groups 1004a-1004f are similar to the fire groups 202a-202f illustrated in FIG. 7. The address generator 1000 is electrically coupled to the fire groups 1004a-1004c via first address lines 1006. The address lines 1006 provide address signals A1, A2, … … A7 from the address generator 1000 to each fire group 1004a-1004 c. Also, the address generator 1000 is electrically coupled to the control lines 1010. Control line 1010 receives a turn-on control signal CSYNC to address generator 1000. In one embodiment, the CSYNC signal is provided by an external controller to a printhead die on which two address generators 1000 and 1002 and six fire groups 1004a-1004f are mounted. In addition, address generator 1000 is electrically coupled to select lines 1008a-1008 f. Select lines 1008a-1008f are similar to select lines 212a-212f illustrated in FIG. 7. The select lines 1008a-1008f turn on select signals SEL1, SEL2 … … SEL6 to the address generator 1000 and corresponding fire groups 1004a-1004f (not shown).

The select line 1008a conducts a select signal SEL1, which in one embodiment is a timing signal T3 and a timing signal T6, to the address generator 1000. The select line 1008b conducts a select signal SEL2, which in one embodiment is a timing signal T3 and a timing signal T1, to the address generator 1000. The select line 1008c conducts a select signal SEL3, which in one embodiment is a timing signal T3 and a timing signal T2, to the address generator 1000. The select line 1008d conducts a select signal SEL4, which in one embodiment is a timing signal T3 and a timing signal T3, to the address generator 1000. The select line 1008e conducts the select signal SEL5 to the address generator 1000, in one embodiment a timing signal T3 a timing signal T4, and the select line 1008f conducts the select signal SEL6 to the address generator 1000, in one embodiment a timing signal T3 a timing signal T5.

Address generator 1002 is electrically coupled to fire groups 1004d-1004f via second address lines 1012. Address lines 1012 provide address signals B1B 2 … … B7 from address generator 1002 to each fire group 1004d-1004 f. Also, address generator 1002 is electrically coupled to control line 1010 which transmits control signal CSYNC to address generator 1002. In addition, address generator 1002 is electrically coupled to select lines 1008a-1008 f. The select lines 1008a-1008f turn on select signals SEL1, SEL2 … … SEL6 to the address generator 1002 and corresponding fire groups 1004a-1004f (not shown).

The select line 1008a turns on a select signal SEL1 to the address generator 1002, which in one embodiment is a timing signal T3. The select line 1008b turns on a select signal SEL2 to the address generator 1002, which in one embodiment is a timing signal T4. The select line 1008c turns on a select signal SEL3 to the address generator 1002, which in one embodiment is a timing signal T5. The select line 1008d conducts a select signal SEL4 to the address generator 1002, which in one embodiment is a timing signal T6. The select line 1008e conducts the select signal SEL5 to the address generator 1002, which in one embodiment is the timing signal T1, and the select line 1008f conducts the select signal SEL6 to the address generator 1002, which in one embodiment is the timing signal T2.

The select signals SEL1, SEL2 … … SEL6 include a series of six pulses that repeat in a repeating series of six pulses. Each select signal SEL1, SEL2 … … SEL6 contains one pulse in the series of six pulses. In one embodiment, a pulse in select signal SEL1 is followed by a pulse in select signal SEL2, which is followed by a pulse in select signal SEL3, which is followed by a pulse in select signal SEL4, which is followed by a pulse in select signal SEL5, which is followed by a pulse in select signal SEL 6. This series repeats from a pulse in select signal SEL1 after a pulse in select signal SEL 6. The control signal CSYNC contains pulses that coincide with the pulses in the select signals SEL1, SEL2 … … SEL6 in order to activate the address generators 1000 and 1002 and set the shift direction or address generation in the address generators 1000 and 1002, such as discussed with respect to fig. 11 and 12. To initiate address generation from address generator 1000, control signal CSYNC contains control pulses that coincide with the timing pulses in timing signal T2, which correspond to the timing pulses in select signal SEL3 in timing signal T2.

The address generator 1000 generates address signals-a 1, -a 2 … … -a 7 in response to select signals SEL1, SEL2 … … SEL6 and control signal CSYNC. Address signals A1, A2, … … A7 are provided to fire groups 1004a-1004c via first address lines 1006.

In the address generator 1000, during the timing pulses in the timing signals T6, T1, and T2, the timing pulses in the timing signals T6, T1, and T2 correspond to the timing pulses in the selection signals SEL1, SEL2, and SEL3, and the address signals a1 and a2 … … to a7 are effective. The control signal CSYNC contains a control pulse in accordance with a timing pulse in the timing signal T4, the timing pulse in the timing signal T4 corresponding to a timing pulse in the selection signal SEL5, so as to set the address generator 1000 to shift in the forward direction. The control signal CSYNC contains a control pulse in accordance with a timing pulse in the timing signal T6, wherein the timing pulse in the timing signal T6 corresponds to the timing pulse in the selection signal SEL1, so as to set the address generator 1000 to shift in the reverse direction.

During the pulses of select signals SEL1, SEL2, and SEL3, fire groups 1004a-1004c receive valid address signals A1 and A2 … … A7. Firing cells 120 in selected row subgroup SG1 are activated by FIRE signal FIRE1, when FIRE group one (FG1) at 1004a receives pulses in address signals A1, A2 … … A7, and select signal SEL 1. Firing cells 120 in selected row subgroup SG2 are activated by FIRE signal FIRE2, when FIRE group two (FG2) at 1004b receives pulses in address signals A1, A2 … … A7, and select signal SEL 2. When FIRE group three (FG3) at 1004c receives pulses in address signals A1, A2 … … A7, and select signal SEL3, firing cells 120 in selected row subgroup SG3 are allowed to activate with FIRE signal FIRE 3.

The address generator 1002 generates address signals-B1, -B2 … … -B7 in response to selection signals SEL1, SEL2 … … SEL6, and a control signal CSYNC. Address signals B1 through B2 … … through B7 are provided to fire groups 1004d-1004f via second address lines 1012. In address generator 1002, during the timing pulses of timing signals T6, T1, and T2, timing pulses of timing signals T6, T1, and T2 correspond to the timing pulses in select signals SEL4, SEL5, and SEL6, and address signals B1 and B2 … … B7 are valid. The control signal CSYNC contains a control pulse in accordance with a timing pulse in the timing signal T4, where the timing pulse in the timing signal T4 corresponds to the timing pulse in the selection signal SEL2, in order to set the address generator 1002 to shift in the forward direction. The control signal CSYNC contains a control pulse in accordance with a timing pulse in the timing signal T6, where the timing pulse in the timing signal T6 corresponds to the timing pulse in the selection signal SEL4, in order to set the address generator 1002 to shift in the reverse direction. To initiate address generation from address generator 1002, control signal CSYNC contains control pulses that coincide with timing pulses in timing signal T2, where the timing pulses in timing signal T2 correspond to the timing pulses in select signal SEL 6.

The fire groups 1004d-1004f receive valid address signals-B1, -B2 … … -B7 during the pulses of the select signals SEL4, SEL5 and SEL 6. Firing cells 120 in selected row subgroup SG4 are allowed to activate with firing signal FIRE4 when the FIRE group four (FG4) at 1004d receives pulses in address signals B1, B2 … … B7, and select signal SEL 4. Firing cells 120 in selected row subgroup SG5 are allowed to activate with firing signal FIRE5 when FIRE group five (FG5) at 1004e receives pulses in address signals B1, B2 … … B7, and select signal SEL 5. Firing cells 120 in selected row subgroup SG6 are allowed to activate with firing signal FIRE6 when the FIRE group six (FG6) at 1004f receives pulses in address signals B1, B2 … … B7, and select signal SEL 6.

In one operating embodiment, during a series of six pulses, control signal CSYNC contains control pulses that coincide with the timing pulses in select signals SEL2 and SEL5 to set address generators 1000 and 1002 to shift in the forward direction. The control pulse in accordance with the timing pulse in the selection signal SEL2 sets the address generator 1002 to shift in the forward direction. The control pulse in accordance with the timing pulse in the selection signal SEL5 sets the address generator 1000 to shift in the forward direction.

In the next series of six pulses, control signal CSYNC contains control pulses consistent with the timing pulses in select signals SEL2, SEL3, SEL5 and SEL 6. The control pulses in accordance with the timing pulses in the selection signals SEL2 and SEL5 set the shift direction to the positive direction in the address generators 1000 and 1002. Control pulses consistent with timing pulses in select signals SEL3 and SEL6 enable address generators 1000 and 1002 to generate address signals A1, A2 … … A7 and B1, B2 … … B7. A control pulse consistent with a timing pulse in select signal SEL3 starts address generator 1000 and a control pulse consistent with a timing pulse in select signal SEL6 starts address generator 1002.

During the third series of timing pulses, address generator 1000 generates address signals-A1, -A2 … … -A7, which are active during the timing pulses in select signals SEL1, SEL2 and SEL 3. Valid address signals A1, A2, … … A7 are used to activate firing cells 120 in row subgroups SG1, SG2, SG3 in fire groups FG1, FG2, and FG3 at 1004a-1004 c. During the third series of timing pulses, address generator 1002 generates address signals-B1, -B2 … … -B7, which are active during the timing pulses in select signals SEL4, SEL5 and SEL 6. Valid address signals-B1, -B2, … … -B7 are used to activate firing cells 120 in row subgroups SG4, SG5, SG6 in the fire groups FG4, FG5, FG6 at 1004d-1004 f.

During the third series of timing pulses in the selection signals SEL1, SEL2 … … SEL6, the address signals a1, a2 … …, a7 include low voltage level signals corresponding to one of the thirteen addresses, and the address signals B1, B2 … …, B7 include low voltage level signals corresponding to the same one of the thirteen addresses. During each subsequent series of timing pulses from select signals SEL1, SEL2 … … SEL6, address signals A1, A2 … … A7 and address signals B1, B2 … … B7 contain low voltage level signals corresponding to the same one of the thirteen addresses. Each series of timing pulses is an address time slot such that one of thirteen addresses is provided during each series of timing pulses.

In forward operation, address one is provided first by address generators 1000 and 1002, followed by address two and so on until address thirteen. After address thirteen, address generators 1000 and 1002 provide all high voltage level address signals-A1, -A2 … … -A7 and-B1, -B2 … … -B7. Also, during each series of timing pulses from the select signals SEL1, SEL2 … … SEL6, control pulses in accordance with the timing pulses in the select signals SEL2 and SEL5 are provided to continue shifting in the positive direction.

In another operating embodiment, control signal CSYNC contains control pulses that coincide with the timing pulses in select signals SEL1 and SEL4 during a series of six pulses to set address generators 1000 and 1002 to reverse shift. The control pulse in accordance with the timing pulse in the selection signal SEL1 sets the address generator 1000 to be shifted in the reverse direction. The control pulse in accordance with the timing pulse in the selection signal SEL4 sets the address generator 1002 to be shifted in the reverse direction.

In the next series of six pulses, control signal CSYNC contains control pulses consistent with the timing pulses in select signals SEL1, SEL3, SEL4 and SEL 6. The control pulses in accordance with the timing pulses in the selection signals SEL1 and SEL4 set the shift direction to the reverse direction in the address generators 1000 and 1002. Control pulses consistent with timing pulses in select signals SEL3 and SEL6 enable address generators 1000 and 1002 to generate address signals A1, A2 … … A7 and B1, B2 … … B7. A control pulse in accordance with the timing pulse in select signal SEL3 starts address generator 1000, and a control pulse in accordance with the timing pulse in select signal SEL6 starts address generator 1002.

During the third series of timing pulses, address generator 1000 generates address signals-A1, -A2 … … -A7, which are active during the timing pulses in select signals SEL1, SEL2 and SEL 3. Valid address signals A1, A2, … … A7 are used to activate firing cells 120 in row subgroups SG1, SG2, SG3 in fire groups FG1, FG2, and FG3 at 1004a-1004 c. During the third series of timing pulses, address generator 1002 generates address signals-B1, -B2 … … -B7, which are valid during the timing pulses in select signals SEL4, SEL5 and SEL 6. Valid address signals-B1, -B2, … … -B7 are used to activate firing cells 120 in row subgroups SG4, SG5, SG6 in the fire groups FG4, FG5, FG6 at 1004d-1004 f.

In the reverse operation, during the third series of timing pulses in the select signals SEL1, SEL2 … … SEL6, the address signals a1, a2 … …, a7 contain low voltage level signals corresponding to one of the thirteen addresses, and the address signals B1, B2 … …, B7 contain low voltage level signals corresponding to the same one of the thirteen addresses. During each subsequent series of timing pulses from select signals SEL1, SEL2 … … SEL6, address signals A1, A2 … … A7 and address signals B1, B2 … … B7 contain low voltage level signals corresponding to the same one of the thirteen addresses. Each series of timing pulses is an address time slot, and thus one of the thirteen addresses is provided during each series of timing pulses.

In reverse operation, address thirteen is provided first by address generators 1000 and 1002, followed by address twelve and so on until address one. After address one, the address generators 1000 and 1002 provide all address signals of high voltage level-A1, -A2 … … -A7 and-B1, -B2 … … -B7. Also, during each series of timing pulses from the select signals SEL1, SEL1 … … SEL6, control pulses consistent with the timing pulses in the select signals SEL1 and SEL4 are provided to continue shifting in the reverse direction.

To terminate or prevent address generation, control signal CSYNC contains control pulses consistent with timing pulses in select signals SEL1, SEL2, SEL4, and SEL 5. This clears the shift registers in address generators 1000 and 1002, such as shift register 402. A constant high voltage level or series of high voltage pulses in control signal CSYNC also terminates or prevents address generation, and a constant low voltage level in control signal CSYNC will not enable address generators 1000 and 1002.

Fig. 14 is a timing diagram illustrating the forward and reverse operations of the address generators 1000 and 1002. The control signal for shifting in the forward direction is CSYNC (FWD) at 1124, and the control signal for shifting in the reverse direction is CSYNC (REV) at 1126. The address signals A1, A2 … … A7 at 1128 are provided by the address generator 1000 and contain forward and reverse operating address references. The address signals B1, B2 … … B7 at 1130 are provided by the address generator 1002 and contain operating address references in both forward and reverse directions.

The select signals SEL1, SEL2 … … SEL6 contain a repeating series of six pulses. Each select signal SEL1, SEL2 … … SEL6 contains one pulse in the series of six pulses. In one series of the repeating series of six pulses, select signal SEL1 at 1100 includes timing pulse 1102, select signal SEL2 at 1104 includes timing pulse 1106, select signal SEL3 at 1108 includes timing pulse 1110, select signal SEL4 at 1112 includes timing pulse 1114, select signal SEL5 at 1116 includes timing pulse 1118, and select signal SEL6 at 1120 includes timing pulse 1122.

In forward operation, control signal CSYNC (FWD)1124 includes control pulse 1132 consistent with timing pulse 1106 in select signal SEL2 at 1104. The control pulse 1132 sets the address generator 1002 to shift in the forward direction. Also, control signal CSYNC (FWD)1124 includes control pulse 1134 that coincides with timing pulse 1118 in select signal SEL5 at 1116. The control pulse 1134 sets the address generator 1000 to shift in the forward direction.

In the next repeating series of six pulses, select signal SEL1 at 1100 includes timing pulse 1136, select signal SEL2 at 1104 includes timing pulse 1138, select signal SEL3 at 1108 includes timing pulse 1140, select signal SEL4 at 1112 includes timing pulse 1142, select signal SEL5 at 1116 includes timing pulse 1144, and select signal SEL6 at 1120 includes timing pulse 1146.

Control signal CSYNC (FWD)1124 includes a control pulse 1148 in conformity with timing pulse 1138 to continue to set address generator 1002 to shift in the forward direction, and includes a control pulse 1152 in conformity with timing pulse 1144 to continue to set address generator 1000 to shift in the forward direction. Also, control signal CSYNC (FWD)1124 includes control pulse 1150 that coincides with timing pulse 1140 in select signal SEL3 at 1108. Control pulse 1150 enables address generator 1000 for generating address signals A1A 2 … … A7 at 1128. In addition, control signal CSYNC (FWD)1124 includes control pulse 1154 that coincides with timing pulse 1146 in select signal SEL6 at 1120. The control pulse 1154 enables the address generator 1002 for generating the address signals B1B 2 … … B7 at 1130.

In the next or third series of six pulses, select signal SEL1 at 1100 includes timing pulse 1156, select signal SEL2 at 1104 includes timing pulse 1158, select signal SEL3 at 1108 includes timing pulse 1160, select signal SEL4 at 1112 includes timing pulse 1162, select signal SEL5 at 1116 includes timing pulse 1164, and select signal SEL6 at 1120 includes timing pulse 1166. Control signal CSYNC (FWD)1124 includes a control pulse 1168 in conformity with timing pulse 1158 to continue to set address generator 1002 to shift in the forward direction, and includes a control pulse 1170 in conformity with timing pulse 1164 to continue to set address generator 1000 to shift in the forward direction.

The address generator 1000 provides address signals A1A 2 … … A7 at 1128. After the forward operation is initiated, the address signals A1, A2 … … A7 at the address generators 1000 and 1128 provide address one at 1172. During timing pulse 1146 in select signal SEL6 at 1120, address one at 1172 becomes valid and remains valid until timing pulse 1162 in select signal SEL4 at 1112. During timing pulses 1156, 1158, and 1160 in select signals SEL1, SEL2, and SEL3 at 1100, 1104, and 1108, the address at 1172 is valid.

Address generator 1002 provides address signals B1B 2 … … B7 at 1130. After the forward operation is initiated, the address signals B1, A2 … … A7 at address generators 1002 and 1130 provide address one at 1174. During timing pulse 1160 in select signal SEL3 at 1108, address one at 1174 becomes valid and remains valid until timing pulse 1176 in select signal SEL1 at 1100. During timing pulses 1162, 1164, and 1166 in select signals SEL4, SEL5, and SEL6 at 1112, 1116, and 1120, the address at 1174 is valid.

Address signals A1 at 1128, A2 … … A7 and B1 at 1130, B2 … … B7 provide the same address, address one at 1172 and 1174. Address one is provided during the series of six timing pulses beginning with timing pulse 1156 and ending with timing pulse 1166, which is the address slot for address one. During the next series of six pulses, beginning with timing pulse 1176, address signals A1, -A2 … … -A7 at 1128 provide address two at 1178, and address signals B1, -B2 … … -B7 at 1130 also provide address two. Thus, the address generators 1000 and 1002 provide addresses from address one to address thirteen in the forward direction. After address thirteen, the address generators 1000 and 1002 are restarted to cycle through valid addresses again in the same manner.

In the reverse operation, control signal CSYNC (REV)1126 includes control pulse 1180 consistent with timing pulse 1102 in select signal SEL1 at 1100. The control pulse 1180 sets the address generator 1000 to shift in the reverse direction. Also, control signal CSYNC (REV)1126 includes control pulse 1182 that coincides with timing pulse 1114 in select signal SEL4 at 1112. The control pulse 1182 sets the address generator 1002 to shift in the reverse direction.

Control signal CSYNC (REV)1126 includes control pulse 1184 in accordance with timing pulse 1136 to continue to set address generator 1002 to shift in the reverse direction, and includes control pulse 1188 in accordance with timing pulse 1142 to continue to set address generator 1002 to shift in the reverse direction. Also, control signal CSYNC (REV)1126 includes a control pulse 1186 that coincides with timing pulse 1140 in select signal SEL3 at 1108. The control pulse 1186 enables the address generator 1000 to generate the address signals A1, A2 … … A7 at 1128. In addition, control signal CSYNC (REV)1126 includes control pulse 1190 which coincides with timing pulse 1146 in select signal SEL6 at 1120. Control pulse 1190 enables address generator 1002 to generate address signals B1B 2 … … B7 at 1130.

Control signal CSYNC (REV)1126 includes control pulse 1192 in accordance with timing pulse 1156 to continue setting address generator 1000 for the reverse shift, and includes control pulse 1194 in accordance with timing pulse 1162 to continue setting address generator 1002 for the reverse shift.

Address generator 1000 provides address signals A1-A7 at 1128. After the reverse operation is initiated, the address signals A1, A2 … … A7 at address generators 1000 and 1128 provide address thirteen at 1172. Address thirteen at 1172 becomes valid during timing pulse 1146 and remains valid until timing pulse 1162. During timing pulses 1156, 1158, and 1160 in select signals SEL1, SEL2, and SEL3 at 1100, 1104, and 1108, address thirteen at 1172 is valid.

Address generator 1002 provides address signals B1B 2 … … B7 at 1130. After the reverse operation is initiated, the address signals B1, B2 … … B7 at address generators 1002 and 1130 provide address thirteen at 1174. Address thirteen at 1174 becomes valid during timing pulse 1160 and remains valid until timing pulse 1176. Address thirteen at 1174 is valid during timing pulses 1162, 1164, and 1166 in select signals SEL4, SEL5, and SEL6 at 1112, 1116, and 1120.

Address signals A1 at 1128, A2 … … A7, B1 at 1130, and B2 … … B7 provide the same address, thirteen at 1172 and 1174. Address thirteen is provided during the series of six timing pulses beginning with timing pulse 1156 and ending with timing pulse 1166, which is the address time slot for address thirteen. During the next series of six pulses, beginning with timing pulse 1176, address signals A1, -A2 … … -A7 at 1128 provide address twelve at 1178, and address signals B1, -B2 … … -B7 at 1130 also provide address twelve. Address generators 1000 and 1002 provide addresses in the reverse direction from address thirteen to address one. After address one, the address generators 1000 and 1002 are restarted to again provide a valid address.

Fig. 15 is a diagram illustrating one embodiment of a bank select address generator 1200 in a printhead die 40. Bank select address generator 1200 is one embodiment of control circuitry in printhead die 40. The bank select address generator 1200 is configured to provide twenty-six address signal combinations, referred to as addresses 1-26, at eight address signals A1, A2 … … A8. Addresses 1-13 of small numbers, referred to as lower bank addresses 1-13, are provided to activate firing cells in the first group of firing cells, referred to as lower bank firing cells. The large number of addresses 14-26, referred to as the higher bank addresses 14-26, are provided to enable firing cells in the second group of firing cells, referred to as the higher bank firing cells. In one embodiment, two of the eight address signals A1, A2 … … A8 are asserted at a time to provide twenty-six addresses 1-26.

Bank select address generator 1200 includes a lower bank shift register 1202, an upper bank shift register 1204, a lower bank logic circuit 1206, an upper bank logic circuit 1208, and a direction circuit 1210. Lower bank shift register 1202 is similar to shift register 402 (shown in FIG. 9), and upper bank shift register 1204 is also similar to shift register 402. Lower bank shift register 1202 receives a different timing signal than shift register 402 and upper bank shift register 1204 receives a different timing signal than shift register 402. Lower bank logic 1206 includes transistor logic similar to logic 406 (shown in FIG. 9) to provide lower bank addresses 1-13 and higher bank logic 1208 includes transistor logic similar to logic 406 to provide higher bank addresses 14-26.

Lower bank shift register 1202 is electrically coupled to lower bank logic 1206 via shift register output lines 1212a-1212 m. The shift register output lines 1212a-1212m provide shift register output signals SO1-SO13, respectively, to the logic circuit 1206 as logic circuit input signals AI1-AI 13. Also, lower bank shift register 1202 is electrically coupled to control signal lines 1214 that provide control signals CSYNC to lower bank shift register 1202. In addition, the lower bank shift register 1202 receives timing pulses in bank timing signals BT1, BT4, BT5, and BT 6.

Lower bank shift register 1202 is electrically coupled to timing signal line 1216, timing signal line 1216 providing bank timing signal BT6 to lower bank shift register 1202 as first precharge signal PRE 1. The lower bank shift register 1202 is electrically coupled to a first resistor divider network 1218 via a first evaluation signal line 1220. The first resistor divide network 1218 is electrically coupled to timing signal line 1222, and timing signal line 1222 provides bank timing signal BT1 to the first resistor divide network 1218. First resistor divide network 1218 provides a reduced voltage level BT1 timing signal on first evaluation signal line 1220 to lower bank shift register 1202 as first evaluation signal EVAL 1. Lower bank shift register 1202 is electrically coupled to timing signal line 1224, timing signal line 1224 provides bank timing signal BT4 to lower bank shift register 1202 as second precharge signal PRE2, and lower bank shift register 1202 is electrically coupled to second resistor divide network 1226 by second evaluation signal line 1228. The second resistor divide network 1226 is electrically coupled to a timing signal line 1230, the timing signal line 1230 providing the bank timing signal BT5 to the second resistor divide network 1226. Second resistor divider network 1226 provides a reduced voltage level BT5 timing signal to lower bank shift register 1202 as second evaluation signal EVAL2 via second evaluation signal line 1228.

The upper bank shift register 1204 is electrically coupled to upper bank logic circuitry 1208 via shift register output lines 1232a-1232 m. The shift register output lines 1232a-1232m provide shift register output signals SO1-SO13, respectively, to the logic circuit 1208 as logic circuit input signals AI14-AI26, respectively. Also, upper bank shift register 1204 is electrically coupled to control signal lines 1214 that provide control signals CSYNC to upper bank shift register 1204. In addition, the higher bank shift register 1204 receives timing pulses in timing signals BT3, BT4, BT5, and BT 6.

The upper bank shift register 1204 is electrically coupled to timing signal line 1216, with timing signal line 1216 providing the bank timing signal BT6 to the upper bank shift register 1204 as a first precharge signal PRE 1. The higher bank shift register 1204 is electrically coupled to a third resistor dividing network 1227 through a third evaluation signal line 1221. The third resistor divide network 1227 is electrically coupled to a timing signal line 1229, the timing signal line 1229 providing the bank timing signal BT3 to the third resistor divide network 1227. Third resistor divide network 1227 provides a reduced voltage level BT3 timing signal to higher bank shift register 1204 as first evaluation signal EVAL1 via first evaluation signal line 1221. The upper bank shift register 1204 is electrically coupled to timing signal lines 1224, and timing signal lines 1224 provide the bank timing signal BT4 to the upper bank shift register 1204 as a second precharge signal PRE 2. Higher bank shift register 1204 is electrically coupled to a second evaluation signal line 1228, and second evaluation signal line 1228 provides a reduced voltage level BT5 timing signal to higher bank shift register 1204 as a second evaluation signal EVAL 2.

The direction circuit 1210 is electrically coupled to the lower bank shift register 1202 and the upper bank shift register 1204 via direction signal lines 1240. Direction signal lines 1240 provide direction signals DIRR and DIRF from direction circuit 1210 to lower bank shift register 1202 and upper bank shift register 1204. Also, direction circuit 1210 is electrically coupled to control signal lines 1214, which control signal lines 1214 provide control signals CSYNC to direction circuit 1210. In addition, the direction circuit 1210 receives timing pulses in the timing signals BT4-BT 6.

Direction circuit 1210 is electrically coupled to timing signal line 1224, and timing signal line 1224 provides timing signal BT4 to direction circuit 1210 as third PRE-charge signal PRE 3. The direction circuit 1210 is electrically coupled to a second evaluation signal line 1228, the second evaluation signal line 1228 providing a reduced voltage BT5 timing signal to the direction circuit 1210 as a third evaluation signal EVAL 3. Also, the direction circuit 1210 is electrically coupled to a fourth resistor divider network 1246 through an evaluation signal line 1248. The fourth resistor divide network 1246 is electrically coupled to timing signal line 1216, with timing signal line 1216 providing the bank timing signal BT6 to the fourth resistor divide network 1246. Fourth resistor divide network 1246 provides a reduced voltage BT6 timing signal to directional circuit 1210 as fourth evaluation signal EVAL 4.

The lower bank logic circuit 1206 is electrically coupled to the shift register output lines 1212a-1212m, respectively, to receive the shift register output signals SO1-SO13 as input signals AI1-AI 13. Also, the lower bank logic 1206 is electrically coupled to the address lines 1252a-1252h to provide the address signals A1, A2 … … A8, respectively. Additionally, the lower bank logic circuit 1206 is electrically coupled to timing signal line 1224, the timing signal line 1224 provides a timing signal BT4 to the lower bank logic circuit 1206 as timing signal T3, the lower bank logic circuit 1206 is electrically coupled to timing signal line 1230, the timing signal line 1230 provides a timing signal BT5 to the lower bank logic circuit 1206 as timing signal T4, and the lower bank logic circuit 1206 is electrically coupled to timing signal line 1216, the timing signal line 1216 provides a timing signal BT6 to the lower bank logic circuit 1206 as timing signal T5.

The higher bank logic circuit 1208 is electrically coupled to the shift register output lines 1232a-1232m to receive the shift register output signals SO1-SO13 as input signals AI14-AI26, respectively. Also, the higher bank logic circuit 1208 is electrically coupled to address lines 1252a-1252h, respectively, to provide address signals A1A 2 … … A8. Additionally, the higher bank logic circuitry 1208 is electrically coupled to timing signal line 1224, timing signal line 1224 provides timing signal BT4 to the higher bank logic circuitry 1208 as timing signal T3, higher bank logic circuitry 1208 is electrically coupled to timing signal line 1230, timing signal line 1230 provides timing signal BT5 to the higher bank logic circuitry 1208 as timing signal T4, and higher bank logic circuitry 1208 is electrically coupled to timing signal line 1216, timing signal line 1216 provides timing signal BT6 to the higher bank logic circuitry 1206 as timing signal T5.

The lower bank shift register 1202 and the lower bank logic 1206 provide signals at a low voltage level among the address signals A1, A2 … … A8 to provide thirteen lower bank addresses 1-13. Lower bank shift register 1202 and lower bank logic 1206 provide lower bank addresses 1-13, from address one to address thirteen in the forward direction and address thirteen to address one in the reverse direction. The higher bank shift register 1204 and the higher bank logic 1208 provide signals at a low voltage level among the address signals A1, A2 … … A8 to provide thirteen higher bank addresses 14-26. Higher bank shift register 1204 and higher bank logic 1208 provide higher bank addresses 14-26, ranging from address fourteen to address twenty-six in the forward direction and from address twenty-six to address fourteen in the reverse direction. The direction circuit 1210 supplies direction signals DIRF and DIRR that set forward or reverse operation in the lower bank shift register 1202 and the upper bank shift register 1204.

Each of the thirteen shift register cells is electrically coupled to receive first PRE-charge signal PRE1, first evaluation signal EVAL1, second PRE-charge signal PRE2, and second evaluation signal EVAL 2. Lower bank shift register 1202 is activated by receiving a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT 1. In response, a high voltage level signal is provided at either SO1 or SO 13. During each subsequent series of six timing pulses, lower bank shift register 1202 shifts the high voltage level signal to the next shift register cell 403, and the high voltage level signal serves as one of shift register output signals SO1-SO 13. In the forward direction, the high voltage level signal is shifted from the shift register output signal SO1 to the shift register output signal SO2, and SO on, up to and including the shift register output signal SO 13. In the reverse direction, the high voltage level signal is shifted from shift register output signal SO13 to shift register output signal SO12, and SO on, up to and including shift register output signal SO 1. During one sequence, after each of the shift register inter-output signals SO1-SO13 has been set to a high voltage level, all of the shift register output signals SO1-SO13 are set to a low voltage level.

The lower bank logic 1206 comprises transistor logic that provides low voltage level address signals among address signals A1, A2 … … A8. The low bank logic 1206 receives the high voltage level signal at one of the low bank input signals AI1-AI13 and provides a corresponding set of low voltage level address signals in address signals A1A 2 … … A8. The lower bank input signals AI1-AI13 correspond to lower bank addresses 1-13, respectively. In one embodiment, in response to the high voltage level input signal AI1, lower bank logic circuit 1206 provides two low voltage level address signals, e.g., -A1 and-A2, among address signals-A1, -A2 … … -A8, as lower bank address 1. In response to the high voltage level input signal AI2, lower bank logic circuit 1206 provides two low voltage level address signals, e.g., -A1 and-A3, as lower bank address 2, in address signals-A2, -A2 … … -A8. This continues until the lower bank logic circuit 1206 receives the high voltage level input signal AI13 and provides two low voltage level address signals as the lower bank address 13 in address signals A1A 2 … … A8.

The upper bank shift register 1204 includes thirteen shift register cells 403 that provide thirteen shift register output signals SO1-SO 13. Each of the thirteen shift register cells is electrically coupled to receive first PRE-charge signal PRE1, first evaluation signal EVAL1, second PRE-charge signal PRE2, and second evaluation signal EVAL 2. Higher bank shift register 1204 is activated by receiving a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT 3. In response, a high voltage level signal is provided at either SO1 or SO 13. During each subsequent series of six timing pulses, upper bank shift register 1204 shifts the high voltage level signal to the next shift register cell 403 and one of shift register output signals SO1-SO 13. In the forward direction, the high voltage level signal is shifted from shift register output signal SO1 to shift register output signal SO2, and SO on, up to and including shift register output signal SO 13. In the reverse direction, the high voltage level signal is shifted from the shift register output signal SO13 to the shift register output signal SO12, and SO on, up to and including the shift register output signal SO 1. After each of the shift register output signals SO1-SO13 has been set to a high voltage level, all of the shift register output signals SO1-SO13 are set to a low voltage level.

The higher bank logic circuit 1208 includes transistor logic circuits that provide low voltage level address signals among the address signals A1, A2 … … A8. The higher bank logic circuit 1208 receives the high voltage level signal at one of the higher bank input signals AI14-AI26 and provides a corresponding set of low voltage level address signals in address signals A1A 2 … … A8. Higher bank input signals AI14-AI26 correspond to higher bank addresses 14-26, respectively. In one embodiment, in response to the high voltage level input signal AI14, higher bank logic circuit 1208 provides two low voltage level address signals as higher bank addresses 14 in address signals A1A 2 … … A8. In response to the high voltage level input signal AI15, higher bank logic circuit 1208 provides two low voltage level address signals as higher bank address 15 in address signals A1, A2 … …, and A8. This continues until the higher bank logic circuit 1208 receives the high voltage level input signal AI26 and provides two low voltage level address signals as the higher bank address 26 in address signals A1A 2 … … A8.

The direction signal line 1210 supplies direction signals DIRR and DIRF to the lower bank shift register 1202 and the upper bank shift register 1204 so as to set a shift direction. If direction circuit 1210 receives a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT5, direction circuit 1210 provides a low voltage handle direction signal DIRR and a high voltage level direction signal DIRF to shift and provide an address in the forward direction. If direction circuit 1210 does not receive a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT5, direction circuit 1210 provides a low voltage handle direction signal DIRR and a high voltage level direction signal DIRR to shift and provide an address in a reverse direction.

The bank timing signals BT1-BT6 provide a repeating series of six pulses. Each of the timing signals BT1-BT6 is supplied in one pulse in the series of six pulses, and the timing signals BT1-BT6 are supplied in pulses in order from the timing signal BT1 to the timing signal BT 6.

In the forward operation of the lower bank shift register 1202, the direction circuit 1210 receives timing pulses in the timing signal BT4 to precharge the direction signals DIRR and DIRF to a high voltage level. Direction circuit 1210 receives control pulses in control signal CSYNC that substantially coincide with timing pulses in timing signal BT5 to discharge direction signal DIRR to a low voltage level. The high voltage level direction signal DIRF and the low voltage level direction signal DIRR set the lower bank shift register 1202 and the upper bank shift register 1204 to shift in the forward direction. The operation direction is set during each series of timing pulses in the timing signals BT1-BT 6. Also, during the timing pulse in the timing signal BT6, all the internal nodes SN in the shift register unit 403 are precharged to a high voltage level in the lower bank shift register 1202 and the upper bank shift register 1204.

To enable the lower bank shift register 1202 in the next series of six pulses in timing signals BT1-BT6, a control pulse in control signal CSYNC is provided that substantially coincides with the timing pulse in timing signal BT 1. During the control pulse in control signal CSYNC which substantially coincides with the timing pulse in timing signal BT1, internal node SN1 in lower bank shift register 1202 discharges to a low voltage level. Internal nodes SN2-SN13 in lower bank shift register 1202 remain at high voltage levels, and internal nodes SN1-SN13 in upper bank shift register 1204 remain at high voltage levels. The upper bank shift register 1204 is not activated.

The lower bank shift register 1202 and the upper bank shift register 1204 receive a timing pulse in the timing signal BT4 during which all shift register output signals SO1-SO13 in the lower bank shift register 1202 and the upper bank shift register 1204 are precharged to a high voltage level. The lower bank shift register 1202 and the upper bank shift register 1204 receive timing pulses in the timing signal BT5, during which the shift register output signals SO2-SO13 in the lower bank shift register 1202 and the shift register output signals SO1-SO13 in the upper bank shift register 1204 discharge. The shift register output signal SO1 in lower bank shift register 1202 remains at a high voltage level while internal node signal SN1 is at a low voltage level. Lower bank shift register 1202 provides a high voltage level output signal SO1 to lower bank logic 1206.

The lower bank logic 1206 and the upper bank logic 1208 receive timing pulses in the timing signal BT4 to precharge the address lines 1252a-1252 h. The timing pulses in timing signal BT5 prevent the logic evaluation transistors from turning on in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. In one embodiment, address lines 1252a-1252h are precharged during a timing pulse in timing signal BT5, rather than during a timing pulse in timing signal BT 4.

The lower bank logic circuit 1206 and the upper bank logic circuit 1208 then receive timing pulses in the timing signal BT6 to turn on the logic evaluation transistors. The low bank logic 1206 receives a high voltage level shift register output signal SO1 as the low bank input signal AI1 and low voltage level shift register output signals SO2-SO13 as the low bank input signals AI2-AI13, respectively. In response, the lower bank logic circuit 1206 effectively pulls down the address lines corresponding to the low voltage level address signals in lower bank address 1 to a low voltage level. The high bank logic 1208 receives the low voltage level shift register output signals SO1-SO13 as the high bank input signals AI14-AI26 and does not discharge any of the address lines 1252a-1252 h.

Each subsequent series of six timing pulses shifts the high voltage level signal from one of the shift register output signals SO1-SO13 in the lower bank shift register 1202 to an adjacent one of the shift register output signals SO1-SO 13. Lower bank logic 1206 receives each of the high voltage level output signals SO1-SO13 and provides a corresponding lower bank address 1-13 from lower bank address 1 to lower bank address 13 in address signals A1 and A2 … … A8. After the shift register output signal SO13 has gone high, all of the shift register output signals SO1-SO13 are set to a low voltage level, and the address signals A1, A2 … … -A8 remain charged to the high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of other banks.

In the forward operation of upper bank shift register 1204, direction circuit 1210 receives timing pulses in timing signal BT4 to precharge direction signals DIRR and DIRF to a high voltage level. Direction circuit 1210 receives control pulses in control signal CSYNC that substantially coincide with timing pulses in timing signal BT5 to discharge direction signal DIRR to a low voltage level. Direction circuit 1210 receives the timing pulses in timing signal BT6 and direction signal DIRR is at a low voltage level and direction signal DIRF remains at a high voltage level. The high voltage level direction signal DIRF and the low voltage level direction signal DIRR set the lower bank shift register 1202 and the upper bank shift register 1204 to shift in the forward direction. The operation direction is set during each series of timing pulses in the timing signals BT1-BT 6. Also, during the timing pulse in the timing signal BT6, all the internal nodes SN in the shift register unit 403 are precharged to a high voltage level in the lower bank shift register 1202 and the upper bank shift register 1204.

To activate the higher bank shift register 1204 in the next series of six pulses in timing signals BT1-BT6, the control pulse in control signal CSYNC is provided substantially coincident with the timing pulse in timing signal BT 3. The control pulse in control signal CSYNC substantially coincides with the timing pulse in timing signal BT3 during which internal node SN1 in higher bank shift register 1202 discharges to a low voltage level. The internal nodes SN2-SN13 of the higher bank shift register 1204 remain at a high voltage level, and the internal nodes SN1-SN13 in the lower bank shift register 1202 remain at a high voltage level. Lower bank shift register 1202 is not enabled.

The lower bank shift register 1202 and the upper bank shift register 1204 receive a timing pulse in the timing signal BT4, during which the shift register output signals SO1-SO13 in the lower bank shift register 1202 and the upper bank shift register 1204 are precharged to a high voltage level. The lower bank shift register 1202 and the upper bank shift register 1204 receive timing pulses in the timing signal BT5, and all shift register output signals SO1-SO13 in the lower bank shift register 1202 and shift register output signals SO2-SO13 in the upper bank shift register 1204 discharge during the timing pulses. The shift register output signal SO1 in higher bank shift register 1204 remains at a high voltage level because internal node signal SN1 is at a low voltage level. The upper bank shift register 1204 provides a high voltage level output signal SO1 to the upper bank logic 1208.

The lower bank logic 1206 and the upper bank logic 1208 receive timing pulses in the timing signal BT4 to precharge the address lines 1252a-1252 h. The timing pulses in timing signal BT5 prevent the logic evaluation transistors from turning on in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. In one embodiment, address lines 1252a-1252h are precharged during a timing pulse in timing signal BT5, rather than during a timing pulse in timing signal BT 4.

The lower bank logic circuit 1206 and the upper bank logic circuit 1208 then receive timing pulses in the timing signal BT6 to turn on the logic evaluation transistors. The higher bank logic circuit 1208 receives a high voltage level shift register output signal SO1 as the higher bank input signal AI14 and low voltage level shift register output signals SO2-SO13 as the higher bank input signals AI15-AI26, respectively. In response, the higher bank logic circuit 1208 effectively pulls down the address lines corresponding to the low voltage level address signals in the higher bank address 14 to a low voltage level. The low bank logic 1206 receives the low voltage level shift register output signals SO1-SO13 as the low bank input signals AI1-AI13 and does not discharge any of the address lines 1252a-1252 h.

Each subsequent series of six pulses shifts the high voltage level signal from one of the shift register output signals SO1-SO13 in the higher bank shift register 1204 to the next shift register output signal SO1-SO 13. Higher bank logic circuit 1208 receives each of the high voltage level output signals SO1-SO13 and provides a corresponding higher bank address 14-26 from higher bank address 14 to higher bank address 26 among address signals A1 and A2 … … A8. After the shift register output signal SO13 in the upper bank shift register 1204 goes high, all of the shift register output signals SO1-SO13 are set to a low voltage level, and the address signals A1, A2 … … -A8 remain charged to the high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of the other banks.

In the reverse operation of the lower bank shift register 1202, the direction circuit 1210 receives the timing pulses in the timing signal BT4 in one series of six pulses in the timing signals BT1-BT6 so as to precharge the direction signals DIRR and DIRF to a high voltage level. Direction circuit 1210 receives low voltage level control signal CSYNC substantially coincident with timing pulses in timing signal BT5 to maintain direction signal DIRR at a high voltage level. Direction circuit 1210 receives the timing pulses in timing signal BT6 and direction signal DIRR is at a high voltage level, then direction signal DIRF discharges to a low voltage level. The low voltage level direction signal DIRF and the high voltage level direction signal DIRR set the lower bank shift register 1202 and the upper bank shift register 1204 to shift in the reverse direction. The operation direction is set during each series of timing pulses in the timing signals BT1-BT 6. Also, in the timing pulse period in the timing signal BT6, all the internal nodes SN in the shift register cells 403 in the lower bank shift register 1202 and the upper bank shift register 1204 are precharged to the high voltage level.

To activate the lower bank shift register 1202 in the next series of six pulses in timing signals BT1-BT6, the control pulse in control signal CSYNC is provided substantially coincident with the timing pulse in timing signal BT 1. The control pulse in control signal CSYNC substantially coincides with the timing pulse in timing signal BT1, and internal node SN13 in lower bank shift register 1202 discharges to a low voltage level. The internal nodes SN1-SN12 of lower bank shift register 1202 remain at high voltage levels, and the internal nodes SN1-SN13 in upper bank shift register 1204 remain at high voltage levels. The upper bank shift register 1204 is not activated.

The lower bank shift register 1202 and the upper bank shift register 1204 receive a timing pulse in the timing signal BT4, during which all shift register output signals SO1-SO13 in the lower bank shift register 1202 and the upper bank shift register 1204 are precharged to a high voltage level. The lower bank shift register 1202 and the upper bank shift register 1204 receive timing pulses in the timing signal BT5, during which the shift register output signals SO1-SO12 in the lower bank shift register 1202 and all the shift register output signals SO1-SO13 in the upper bank shift register 1204 are discharged. The shift register output signal SO13 in the lower bank register 1202 remains at a high voltage level because the internal node signal SN13 is at a low voltage level. Lower bank shift register 1202 provides a high voltage level output signal SO13 to lower bank logic 1206.

The lower bank logic 1206 and the upper bank logic 1208 receive timing pulses in the timing signal BT4 to precharge the address lines 1252a-1252 h. The timing pulses in timing signal BT5 prevent the logic evaluation transistors from turning on in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. In one embodiment, address lines 1252a-1252h are precharged during a timing pulse in timing signal BT5, rather than during a timing pulse in timing signal BT 4.

The lower bank logic circuit 1206 and the upper bank logic circuit 1208 then receive timing pulses in the timing signal BT6 to turn on the logic evaluation transistors. The low bank logic 1206 receives a high voltage level shift register output signal SO13 as the low bank input signal AI13 and low voltage level shift register output signals SO1-SO12 as the low bank input signals AI1-AI12, respectively. In response, lower bank logic 1206 effectively pulls down the address lines corresponding to the low voltage level address signals in lower bank address 13 to a low voltage level. The high bank logic 1208 receives the low voltage level shift register output signals SO1-SO13 as the high bank input signals AI14-AI26 and does not discharge any of the address lines 1252a-1252 h.

Each subsequent series of six timing pulses shifts the high voltage level signal from one shift register output signal SO1-SO13 in the lower bank shift register 1202 to the next shift register output signal SO1-SO 13. Lower bank logic 1206 receives each of the high voltage level output signals SO1-SO13 and provides a corresponding lower bank address 1-13 from lower bank address 13 to lower bank address 1 in address signals A1 and A2 … … A8. After the shift register output signal SO1 has gone high, all of the shift register output signals SO1-SO13 are set to a low voltage level, and the address signals A1, A2 … … -A8 remain charged to the high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of other banks.

In the reverse operation of the higher bank shift register 1204, the direction circuit 1210 receives the timing pulse in the timing signal BT4 in one series of six pulses in the timing signals BT1-BT6 so as to precharge the direction signals DIRR and DIRF to a high voltage level. Direction circuit 1210 receives control signal CSYNC at a low voltage level that substantially coincides with a timing pulse in timing signal BT5 in order to maintain direction signal DIRR at a high voltage level. Direction circuit 1210 receives the timing pulses in timing signal BT6 and direction signal DIRR is at a low voltage level and direction signal DIRF discharges to a low voltage level. The low voltage level direction signal DIRF and the high voltage level direction signal DIRR set the lower bank shift register 1202 and the upper bank shift register 1204 to shift in the reverse direction. The operation direction is set during each series of timing pulses in the timing signals BT1-BT 6. Also, during the timing pulse in the timing signal BT6, all the internal nodes SN in the shift register cells 403 in the lower bank shift register 1202 and the upper bank shift register 1204 are precharged to the high voltage level.

To activate the higher bank shift register 1204 in the next series of six pulses in timing signals BT1-BT6, a control pulse in control signal CSYNC is provided that substantially coincides with the timing pulse in timing signal BT 3. The control pulse in control signal CSYNC substantially coincides with the timing pulse in timing signal BT3, and internal node SN13 in upper bank shift register 1204 discharges to a low voltage level. The internal nodes SN1-SN12 in the higher bank shift register 1204 remain at high voltage levels, and the internal nodes SN1-SN13 in the lower bank shift register 1202 remain at high voltage levels. Lower bank shift register 1202 is not enabled.

The lower bank shift register 1202 and the upper bank shift register 1204 receive timing pulses in the timing signal BT4, during which all shift register output signals SO1-SO13 in the lower bank shift register 1202 and the upper bank shift register 1204 discharge to a high voltage level. The lower bank shift register 1202 and the upper bank shift register 1204 receive the timing pulse in the timing signal BT5, and all the shift register output signals SO1-SO13 in the lower bank shift register 1202 and the shift register output signals SO1-SO12 in the upper bank shift register 1204 discharge. The shift register output signal SO13 in the upper bank register 1204 remains at a high voltage level because the internal node signal SN13 is at a low voltage level. The upper bank shift register 1204 provides a high voltage level output signal SO13 to the upper bank logic 1208.

The lower bank logic 1206 and the upper bank logic 1208 receive timing pulses in the timing signal BT4 to precharge the address lines 1252a-1252 h. The timing pulses in timing signal BT5 prevent the logic evaluation transistors from turning on in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. In one embodiment, address lines 1252a-1252h are precharged during a timing pulse in timing signal BT5, rather than during a timing pulse in timing signal BT 4.

The lower bank logic circuit 1206 and the upper bank logic circuit 1208 then receive timing pulses in the timing signal BT6 to turn on the logic evaluation transistors. The higher bank logic circuit 1208 receives a high voltage level shift register output signal SO13 as the higher bank input signal AI26 and low voltage level shift register output signals SO1-SO12 as the higher bank input signals AI14-AI25, respectively. In response, the higher bank logic circuit 1208 effectively pulls down the address lines corresponding to the low voltage level address signals in the higher bank address 26 to a low voltage level. The low bank logic 1206 receives the low voltage level shift register output signals SO1-SO13 as the low bank input signals AI1-AI13 and does not discharge any of the address lines 1252a-1252 h.

Each subsequent series of six timing pulses shifts the high voltage level signal from one shift register output signal SO1-SO13 in higher bank shift register 1204 to the next shift register output signal SO1-SO 13. Higher bank logic circuit 1208 receives each of the high voltage level output signals SO1-SO13 and provides a corresponding higher bank address 14-26 among the address signals A1, A2 … …, A8, from higher bank address 26 to higher bank address 14. After the shift register output signal SO1 in the upper bank shift register 1204 goes high, all of the shift register output signals SO1-SO13 are set to a low voltage level, and the address signals A1, A2 … … -A8 remain charged to the high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of the other banks.

In operation, lower bank shift register 1202 is enabled independently of upper bank shift register 1204 to provide lower bank addresses 1-13 in either the forward or reverse direction in address signals A1, A2 … … A8, and upper bank shift register 1204 is enabled independently of lower bank shift register 1202 to provide upper bank addresses 14-26 in either the forward or reverse direction in address signals A1, A2 … … A8. Also, lower bank shift register 1202 may be activated one time after another to repeatedly generate lower bank addresses 1-13 in address signals A1, A2 … … A8, and higher bank shift register 1204 may be activated one time after another to repeatedly generate higher bank addresses 14-26 in address signals A1, A2 … … A8. Additionally, lower bank shift register 1202 may be enabled to generate lower bank addresses 1-13, followed by higher bank shift register 1204 to generate higher bank addresses 14-26, or vice versa.

It should be noted that in some embodiments, lower bank shift register 1202 and lower bank logic 1206, and upper bank shift register 1204 and upper bank logic 1208, are located adjacent to each other on printhead die 40. In other embodiments, lower bank shift register 1202 and lower bank logic 1206, and upper bank shift register 1204 and upper bank logic 1208, are not located adjacent to each other on printhead die 40. In these latter embodiments, two direction circuits 1210 are provided, one near each of lower bank shift register 1202 and lower bank logic 1206, and upper bank shift register 1204 and upper bank logic 1208.

Fig. 16 is a diagram illustrating a direction circuit 1210. The direction circuit 1210 includes a reverse signal stage 1260 and a forward signal stage 1262. The inverted signal stage 1260 includes a precharge transistor 1264, an evaluation transistor 1266, and a controller transistor 1268. The forward signal stage 1262 includes a precharge transistor 1270, an evaluation transistor 1272, and a controller transistor 1274.

One side of the drain-source path and the gate of the precharge transistor 1264 are electrically coupled to the timing signal line 1224. Timing signal line 1224 provides timing signal BT4 to direction circuit 1210 as third PRE-charge signal PRE 3. The other side of the drain-source path of precharge transistor 1264 is electrically coupled to one side of the drain-source path of evaluation transistor 1266 via direction signal line 1240 b. The direction signal line 1240b provides an inversion signal DIRF to the gates of the inversion transistors in each of the shift register cells in the lower bank shift register 1202 and the upper bank shift register 1204. The gate of evaluation transistor 1266 is electrically coupled to evaluation signal line 1228, which provides a reduced voltage level BT5 timing signal to direction circuit 1210 as third evaluation signal EVAL 3. The other side of the drain-source path of evaluation transistor 1266 is electrically coupled to the drain-source path of control transistor 1268 at 1276. The drain-source path of the control transistor 1268 is also electrically coupled to a reference, such as ground, at 1278. The gate of control transistor 1268 is electrically coupled to control line 1214 to receive control signal CSYNC.

One side of the drain-source path and the gate of precharge transistor 1270 are electrically coupled to timing signal line 1224. The other side of the drain-source path of precharge transistor 1270 is electrically coupled to one side of the drain-source path of evaluation transistor 1272 via direction signal line 1240 a. A direction signal line 1240a provides a forward signal DIRF to the gates of the forward transistors in each of the lower bank shift register 1202 and the upper bank shift register 1204. The gate of evaluation transistor 1272 is electrically coupled to evaluation signal line 1248, which provides a reduced voltage level BT6 timing signal to directional circuit 1210 as fourth evaluation signal EVAL 4. The other side of the drain-source path of evaluation transistor 1272 is electrically coupled to the drain-source path of control transistor 1274 at 1280. The drain-source path of control transistor 1274 is also electrically coupled to a reference, such as ground, at 1282. The gate of control transistor 1274 is electrically coupled to direction signal line 1240b to receive the reverse signal DIRR.

The direction signals DIRF and DIRR set the shift directions in the lower bank shift register 1202 and the upper bank shift register 1204. If the forward signal DIRF is set to a high voltage level and the reverse signal DIRR is set to a low voltage level, forward transistors such as forward transistor 512 are turned on and reverse transistors such as reverse transistor 514 are turned off. Lower bank shift register 1202 and upper bank shift register 1204 shift in the forward direction. If the forward signal DIRF is set to a low voltage level and the reverse signal DIRR is set to a high voltage level, the forward transistors, such as forward transistor 512, are turned off and the reverse transistors, such as reverse transistor 514, are turned on. Lower bank shift register 1202 and upper bank shift register 1204 shift in the reverse direction. The direction signals DIRF and DIRR are set during timing pulses in the timing signals BT4, BT5, and BT 6.

In operation, timing signal line 1224 provides a timing pulse in timing signal BT4 in third PRE-charge signal PRE3 to direction circuit 1210. During the timing pulse in third PRE-charge signal PRE3, forward signal line 1240a and reverse signal line 1240b charge to a high voltage level. The resistor divider network 1226 is provided with timing pulses in the timing signal BT5, and the resistor divider network 1226 provides a reduced voltage level BT5 timing pulse in the third evaluation signal EVAL3 to the direction circuit 1210. The timing pulse in third evaluation signal EVAL3 turns on third evaluation transistor 1266. If the control pulse in control signal CSYNC is provided to the gate of control transistor 1268 at the same time that the timing pulse in third evaluation signal EVAL3 is provided to evaluation transistor 1266, then inverted signal line 1240b discharges to a low voltage level. If control signal CSYNC remains at a low voltage level while the timing pulses in third evaluation signal EVAL3 are provided to evaluation transistor 1266, then reverse signal line 1240b remains charged at a high voltage level.

The resistor divide network 1246 is supplied with timing pulses in timing signal BT6, and the resistor divide network 1246 supplies a falling voltage level BT6 timing pulse to the fourth evaluation signal EVAL4 of the directional circuit 1210. The timing pulse in fourth evaluation signal EVAL4 turns on fourth evaluation transistor 1272. If the reverse signal DIRR is at a high voltage level, the forward signal line 1240a discharges to a low voltage level. If the reverse signal DIRR is at a low voltage level, the forward signal line 1240a remains charged to a high voltage level.

Fig. 17 is a timing diagram illustrating the operation of the bank select address generator 1200 in the forward direction. The timing signals BT1-BT6 provide a series of six pulses that are repeated in a repeating series of six pulses. Each timing signal BT1-BT6 provides one pulse of the series of timing pulses.

In one series of six pulses, timing signal BT1 at 1300 contains timing pulses 1302, timing signal BT2 at 1304 contains timing pulses 1306, timing signal BT3 at 1308 contains timing pulses 1310, timing signal BT4 at 1312 contains timing pulses 1314, timing signal BT5 at 1316 contains timing pulses 1318 and timing signal BT6 at 1320 contains timing pulses 1322. Control signal CSYNC at 1324 includes a control pulse that sets the shift direction in bank select address generator 1200 and activates lower bank shift register 1202 and upper bank shift register 1204 to generate addresses 1-26.

Initially, neither lower bank shift register 1202 nor upper bank shift register 1204 are shifted, and direction circuit 1210 has not yet been set by a control pulse in control signal CSYNC 1324. The reverse signal DIRR at 1326 has been charged to a high voltage level turning on control transistor 1274, which control transistor 1274 previously pre-discharged the forward signal DIRF 1328 to a low voltage level. Internal node signal SN at 1330 in shift register cells in lower bank shift register 1202 and upper bank shift register 1204 remain charged to a high voltage level, which discharges all shift register output signals SO at 1332 to a low voltage level. Logic evaluation signal LEVAL1334 in lower bank logic 1206 and higher bank logic 1208 remains charged to a high voltage level from the previous pulse in timing signal BT6 at 1320. Also, since the shift register output signal SO1332 is at a low voltage level, the address signals A1, A2 … … A8 at 1336 remain charged to a high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of other banks.

Timing pulse 1302 in timing signal BT1 at 1300 is provided to lower bank shift register 1202 in first evaluation signal EVAL 1. Timing pulse 1302 turns on each first evaluation transistor in the shift register cell in lower bank shift register 1202. Control signal CSYNC1324 remains at a low voltage level and all shift register output signals SO1332 are at a low voltage level, which turns off each forward input transistor and each reverse input transistor in the shift register cells of lower bank shift register 1202 and upper bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1330 in the shift register cells of lower bank shift register 1202 and upper bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1330 remain at a high voltage level. Timing pulses 1306 in timing signal BT2 are not provided to bank select address generator 1200 at 1304 and each signal remains unchanged during timing pulses 1306.

Then, a timing pulse 1310 in the timing signal BT3 at 1308 is provided to the higher bank shift register 1204 in the first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. Control signal CSYNC1324 remains at a low voltage level and all shift register output signals SO1332 are at a low voltage level, which turns off each forward input transistor and each reverse input transistor in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1330 in the shift register cells of lower bank shift register 1202 and upper bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1330 remain at a high voltage level.

The timing pulse 1314 in the timing signal BT4 at 1312 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the second precharge signal PRE2, to the direction circuit 1210 in the third charge signal PRE3, and to the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1314 in second precharge signal PRE2, all of the shift register output signals SO1332 in lower and upper bank shift registers 1202 and 1204 are charged to a high voltage level at 1338. Also, during timing pulse 1314 in third PRE-charge signal PRE3, forward signal DIRF1328 charges to a high voltage level at 1340 and holds reverse signal DIRR1326 at the high voltage level. Timing pulse 1314 is provided to each address line precharge transistor and evaluation block transistor in lower bank logic 1206 and higher bank logic 1208. Timing pulse 1314 holds the address signals A1, A2 … … A8 at a high voltage level at 1336 and turns on the evaluation prevention transistors to pull the logic evaluation signal LEVAL1334 low to a low voltage level at 1342.

Timing pulses 1318 in timing signal BT5 at 1316 are provided to lower bank shift register 1202 and upper bank shift register 1204 in second evaluation signal EVAL2, to direction circuit 1210 in third evaluation signal EVAL3, and to lower bank logic circuit 1206 and upper bank logic circuit 1208. Timing pulse 1318 in second evaluation signal EVAL2 turns on each second evaluation transistor in the shift register cells of lower bank shift register 1202 and upper bank shift register 1204. Since internal node signal SN1330 is at a high voltage level to turn on each internal node transistor in the shift register cells of lower bank shift register 1202 and upper bank shift register 1204, all shift register output signals SO1332 are discharged to a low voltage level at 1344. Also, timing pulse 1318 in third evaluation signal EVAL3 turns on third evaluation transistor 1266. Control pulse 1346 in control signal CSYNC1324 turns on control transistor 1268. Since fourth evaluation transistor 1266 and control transistor 1268 are turned on, direction signal DIRR1326 is discharged to a low voltage level at 1348. Timing pulses 1318 are provided to each of the evaluation block transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. Timing pulse 1318 turns on each evaluation prevention transistor to hold logic evaluation signal LEVAL1334 at a low voltage level. The logic evaluation signal LEVAL1334 at a low voltage level turns off the address evaluation transistor.

Timing pulses 1322 in timing signal BT6 at 1320 are provided to lower bank shift register 1202 and upper bank shift register 1204 in a first precharge signal PRE1, to direction circuit 1210 in a fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208. Timing pulse 1322 in first precharge signal PRE1 maintains all internal node signals SN1330 in lower bank shift register 1202 and upper bank shift register 1204 at a high voltage level. Timing pulse 1322 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The low voltage level reverse signal DIRR1326 turns off the control transistor 1274. Since control transistor 1274 is turned off, direction signal DIRR1328 remains charged to a high voltage level. During this time, timing pulse 1322 in each logic evaluation signal LEVAL1334 charges to a high voltage level in lower bank logic 1206 and higher bank logic 1208 at 1350. Since all shift register output signals SO1332 are at a low voltage level, all address transistor pairs in the lower bank logic circuit 1206 and the upper bank logic circuit 1208 are turned off, and the address signals A1, A2 … … A8 remain at a high voltage level. High voltage level forward signal DIRF1328 and low voltage level reverse signal DIRF1326 set lower bank shift register 1202 and upper bank shift register 1204 to shift in the forward direction.

In the next series of six timing pulses, the timing signal BT1 at 1300 contains the timing pulse 1352, the timing signal BT2 at 1304 contains the timing pulse 1354, the timing signal BT3 at 1308 contains the timing pulse 1356, the timing signal BT4 at 1312 contains the timing pulse 1358, the timing signal BT5 at 1316 contains the timing pulse 1396, and the timing signal BT6 at 1320 contains the timing pulse 1362.

Timing pulse 1352 turns on each of the first evaluation transistors in the shift register cells in lower bank shift register 1202. A control pulse at 1364 in control signal CSYNC1324 turns on each of the forward input transistors in the first shift register cells of lower bank shift register 1202 and upper bank shift register 1204. Also, the forward transistor is turned on by a forward signal DIRF 1328. Since the first evaluation transistor in lower bank shift register 1202 is turned on, the forward input transistor in the first shift register cell is turned on, and the forward transistor is turned on, internal node signal SN1 in the first shift register cell in lower bank shift register 1202 discharges to a low voltage level, labeled 1366.

The first evaluation transistor in the shift register cell in upper bank shift register 1204 is not turned on by timing pulse 1352 and all internal node signals SN1330 in upper bank shift register 1204 remain at a high voltage level. Also, shift register output signal SO1332 is at a low voltage level, which turns off the forward input transistors in all other shift register cells. With the forward input transistor off, each of the other internal node signals SN2-SN13 in lower bank shift register 1202 remains at a high voltage level. The timing pulse 1354 in timing signal BT2 is not provided to bank select address generator 1200 at 1304 and each signal remains unchanged during timing pulse 1354.

Then, a timing pulse 1356 in the timing signal BT3 at 1308 is provided to the higher bank shift register 1204 in the first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. Control signal CSYNC1324 remains at a low voltage level and shift register output signal SO1332 in higher bank shift register 1204 is at a low voltage level, which turns off each forward input transistor and each inverting input transistor in higher bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1330 in the higher bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1330 in upper bank shift register 1204 remain at a high voltage level.

During the timing pulse 1358 in timing signal BT4 at 1312, all shift register output signals SO1332 charge to a high voltage level at 1368. Also during timing pulse 1358, reverse signal DIRR1326 charges to a high voltage level at 1370 and holds forward signal DIRF 1328 at the high voltage level. In addition, timing pulse 1358 holds all of the address signals A1, A2 … … A81336 at a high voltage level and pulls logic evaluation signal LEVAL1334 low to a low voltage level at 1372. Low voltage level logic evaluation signal LEVAL1334 turns off the address evaluation transistors to prevent the address transistors from pulling address signals A1, A2 … … A81336 low to a low voltage level.

Timing pulse 1360 in timing signal BT5 at 1316 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN2-SN13 in lower bank shift register 1202 are at a high voltage level, and since the internal node signals SN1-SN13 in upper bank shift register 1204 are at a high voltage level, the shift register output signals SO2-SO13 in lower bank shift register 1202 and the shift register output signals SO1-SO13 in upper bank shift register 1204 discharge to a low voltage level at 1374 during timing pulse 1360. Since internal node signal SN1 in lower bank shift register 1202 is at a low voltage level, shift register output signal SO1 in lower bank shift register 1202 remains at a high voltage, labeled 1376.

Timing pulse 1360 also turns on evaluation transistor 1266, and control pulse 1378 in control signal CSYNC1324 turns on control transistor 1268 to discharge reverse signal DIRR1326 to a low voltage level at 1380. In addition, timing pulse 1360 turns on the evaluation blocking transistors in evaluation low bank logic circuit 1206 and high bank logic circuit 1208 to maintain logic evaluation signal LEVAL1334 at a low voltage level that turns off the evaluation transistors. The shift register output signal SO1332 is asserted during timing pulse 1360, SO that one shift register output signal SO1 in the lower bank shift register 1202 is asserted to a high voltage level, and all other shift register output signals SO2-SO13 in the lower bank shift register 1202 and all shift register output signals SO1-SO13 in the upper bank shift register 1204 are asserted to a low voltage level.

The timing pulse 1362 in the timing signal BT6 at 1320 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the first precharge signal PRE1, to the direction circuit 1210 in the fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1362 in first precharge signal PRE1, internal node signal SN1 in lower bank shift register 1202 charges to a high voltage level at 1382 and maintains all other internal node signals SN1330 in lower bank shift register 1202 and higher bank shift register 1204 at the high voltage level. Timing pulse 1362 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The low voltage level reverse signal DIRR1326 turns off control transistor 1274 and direction signal DIRF1328 remains charged to a high voltage level. Also, during timing pulse 1362, each logic evaluation signal LEVAL1334 in lower bank logic 1206 and higher bank logic 1208 charges to a high voltage level at 1384. The high level shift register output signal SO1 in the lower bank shift register 1202 is received as the input signal AI1 in the lower bank logic circuit 1206. The high voltage level input signal AI1 turns on the address transistors in the lower bank logic circuit 1206 to effectively pull down the address signals in the address signals A1A 2 … … A8 to provide the lower bank address 1 at 1386. The other shift register output signals SO2-SO13 in lower bank shift register 1202 and all shift register output signals SO1-SO13 in upper bank shift register 1204 are at a low voltage level, which turn off the address transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to not discharge address signals A1, A2 … … A8. The address signals A1, A2 … … A8 establish valid values during the timing pulse 1362.

In the next series of six timing pulses, timing signal BT1 at 1300 contains timing pulse 1388, timing signal BT2 at 1304 contains timing pulse 1390, timing signal BT3 at 1308 contains timing pulse 1392, timing signal BT4 at 1312 contains timing pulse 1394, timing signal BT5 at 1316 contains timing pulse 1396 and timing signal BT6 at 1320 contains timing pulse 1398.

Timing pulse 1388 turns on each first evaluation transistor in the shift register cells in lower bank shift register 1202 to evaluate each forward input signal SIF (shown in fig. 10A) in the shift register cells in lower bank shift register 1202. The forward input signal SIF of the first shift register cell is the control signal CSYNC1324, which is at a low voltage level. The positive input signal SIF at each other shift register cell is the preceding shift register output signal SO 1332. The shift register output signal SO1 in lower bank shift register 1202 is at a high voltage level and is the forward input signal SIF for the second shift register cell in lower bank shift register 1202.

The shift register output signal SO1 in lower bank shift register 1202 turns on the forward input transistor in the second shift register cell in lower bank shift register 1202. Also, the forward transistor is turned on by a forward signal DIRF 1328. Since the first evaluation transistor in lower bank shift register 1202 is turned on, the forward input transistor in the second shift register cell is turned on, and the forward transistor is turned on, internal node signal SN2 in the second shift register cell in lower bank shift register 1202 discharges to a low voltage level, labeled 1400.

The first evaluation transistor in the shift register cell in higher bank shift register 1204 is not turned on by timing pulse 1388 and all internal node signals SN1330 in higher bank shift register 1204 remain at a high voltage level. Also, control signal CSYNC1324 and shift register output signals SO2-SO13 in lower bank shift register 1202 are at low voltage levels, which turn off the forward input transistors in the other shift register cells of lower bank shift register 1202. With the forward input transistors turned off, each of the other internal node signals SN1 and SN3-SN13 in the lower bank shift register 1202 remain at a high voltage level. The timing pulse 1390 in the timing signal BT2 is not supplied to the bank selection address generator 1200, and each signal remains unchanged during the timing pulse 1390.

Then, the timing pulse 1392 in the timing signal BT3 at 1308 is supplied to the higher bank shift register 1204 in the first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. Control signal CSYNC1324 remains at a low voltage level and shift register output signal SO1332 in higher bank shift register 1204 is at a low voltage level, which turns off each forward input transistor and each inverting input transistor in higher bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1330 in the higher bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1330 in upper bank shift register 1204 remain at a high voltage level.

The shift register output signal SO1332 is charged at 1402 and/or maintained at a high voltage level during timing pulses 1394 in timing signal BT4 at 1312. Also, during timing pulse 1394, reverse signal DIRR1326 charges to a high voltage level at 1404 and forward signal DIRF1328 is held at the high voltage level. In addition, during timing pulse 1394, address signals A1, A2 … … A81336 are charged and/or held at a high voltage level 1406 and logic evaluation signal LEVAL1334 is pulled low to a low voltage level 1408. Low voltage level logic evaluation signal LEVAL1334 turns off the address evaluation transistors to prevent the address transistors from pulling address signals A1, A2 … … A81336 low to a low voltage level. The lower bank address 1 address signal among the address signals a1, a2 … … a81336 is effective during the timing pulses 1388, 1390, and 1392.

A timing pulse 1396 in the timing signal BT5 at 1316 turns on the second evaluation transistors in the lower bank shift register 1202 and the upper bank shift register 1204. Since the internal node signals SN1 and SN3-SN13 in lower bank shift register 1202 are at high voltage levels, and since the internal node signals SN1-SN13 in upper bank shift register 1204 are at high voltage levels, timing pulse 1396 discharges shift register output signals SO1 and SO3-SO13 in lower bank shift register 1202 and shift register output signals SO1-SO13 in upper bank shift register 1204 to low voltage levels at 1410. Since internal node signal SN2 in lower bank shift register 1202 is at a low voltage level, shift register output signal SO2 in lower bank shift register 1202 remains at a high voltage, labeled 1412.

Timing pulse 1396 also turns on evaluation transistor 1266 and control pulse 1414 in control signal CSYNC1324 turns on control transistor 1268 to discharge reverse signal DIRR1326 to a low voltage level at 1416. In addition, timing pulse 1360 turns on evaluation blocking transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to maintain logic evaluation signal LEVAL1334 at a low voltage level that turns off evaluation transistors. The shift register output signal SO1332 is established during timing pulse 1396 SO that one shift register output signal SO2 in the lower bank shift register 1202 is established to a high voltage level and all other shift register output signals SO1 and SO3-SO13 in the lower bank shift register 1202 and all shift register output signals SO1-SO13 in the upper bank shift register 1204 are established to a low voltage level.

The timing pulse 1398 in the timing signal BT6 at 1320 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the first precharge signal PRE1, to the direction circuit 1210 in the fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1398 in first precharge signal PRE1, internal node signal SN2 in lower bank shift register 1202 charges to a high voltage level at 1418 and maintains all other internal node signals SN1330 in lower bank shift register 1202 and higher bank shift register 1204 at the high voltage level. Timing pulse 1398 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The low voltage level reverse signal DIRR1326 turns off control transistor 1274 and direction signal DIRF1328 remains charged to a high voltage level. During timing pulse 1398, each logic evaluation signal LEVAL1334 charges to a high voltage level at 1420 in lower bank logic circuit 1206 and higher bank logic circuit 1208. The high level shift register output signal SO2 in the lower bank shift register 1202 is received as the input signal AI1 in the lower bank logic circuit 1206. The high voltage level input signal AI2 turns on the address transistors in the lower bank logic circuit 1206 to effectively pull down the address signals in the address signals A1A 2 … … A8 to provide the lower bank address 2 at 1422. The other shift register output signals SO1 and SO3-SO13 in lower bank shift register 1202 and all shift register output signals SO1-SO13 in upper bank shift register 1204 are at a low voltage level, which turn off the address transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to not discharge address signals A1, A2 … … A8. The address signals a1, a2 … … A8 establish effective values during the timing pulse 1398.

The next series of six timing pulses in timing signals BT1-BT6 shifts the high voltage level shift register output signal SO2 to the next shift register cell in lower bank shift register 1202 to provide a high voltage level shift register output signal SO3 in lower bank shift register 1202 and lower bank address 3 in address signals A1, A2 … … A8 at 1336. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 in lower bank shift register 1202 has gone high once. The series stops after the shift register output signal SO13 in the lower bank shift register 1202 has gone high and the lower bank address 13 has been provided in the address signals A1A 2 … … A8 at 1336. To begin the next series, lower bank shift register 1202 or upper bank shift register 1204 may be activated to provide lower bank addresses 1-13 or upper bank addresses 14-26 in the forward direction or reverse direction, respectively. In this example operation, when lower bank address 13 is provided at 1424 in address signals A1, A2 … … A8 at 1336, upper bank shift register 1204 is activated to provide upper bank addresses 14-26 in the forward direction.

Of the series of six timing pulses, timing signal BT1 at 1300 contains timing pulse 1426, timing signal BT2 at 1304 contains timing pulse 1428, timing signal BT3 at 1308 contains timing pulse 1430, timing signal BT4 at 1312 contains timing pulse 1432, timing signal BT5 at 1316 contains timing pulse 1434, and timing signal BT6 at 1320 contains timing pulse 1436.

Timing pulse 1426 turns on each first evaluation transistor in the shift register cells of lower bank shift register 1202, and forward signal DIRF1328 turns on each forward transistor in lower bank shift register 1202 and upper bank shift register 1204. Control signal CSYNC1324 is at a low voltage level to turn off each of the forward input transistors in the first shift register cells of lower bank shift register 1202 and upper bank shift register 1204. Also, the shift register output signals SO1-SO12 in lower bank shift register 1202 are at a low voltage level, which turns off the forward input transistors in all other shift register cells in lower bank shift register 1202. Each internal node signal SN1-SN13 in lower bank shift register 1202 remains at a high voltage level because the forward input transistors are turned off. In addition, the first evaluation transistors in the shift register cells of upper bank shift register 1204 are not turned on by timing pulse 1352, and all of the internal node signals SN1-SN13 in upper bank shift register 1204 remain at a high voltage level. The timing pulse 1428 in timing signal BT2 at 1304 is not provided to bank select address generator 1200 and each signal remains unchanged during timing pulse 1428.

The timing pulse 1430 in timing signal BT3 at 1308 is then provided to the higher bank shift register 1204 in a first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. At 1438, a control pulse in control signal CSYNC1324 turns on each forward input transistor in the first shift register cell in lower bank shift register 1202 and upper bank shift register 1204. Also, the forward transistor is turned on by a forward signal DIRF 1328. Since the first evaluation transistor in the upper bank shift register 1204 is on, the forward input transistor in the first shift register cell is on, and the forward transistor is on, the internal node signal SN1 in the first shift register cell in the upper bank shift register 1204 discharges to a high voltage level, labeled 1440.

The first evaluation transistors in the shift register cells in the lower bank shift register 1202 are not turned on by the timing pulse 1430, and all of the internal node signals SN1-SN13 in the lower bank shift register 1202 are kept at high voltage levels. Also, shift register output signals SO1-SO12 in higher bank shift register 1204 are at a low voltage level, which turns off the forward input transistors in all other shift register cells. Each of the other internal node signals SN2-SN13 in higher bank shift register 1204 remain at a high voltage level due to the forward input transistors being turned off.

During the timing pulse 1432 in the timing signal BT4 at 1312, all shift register output signals SO1332 charge to a high voltage level at 1442. Also during timing pulse 1432, reverse signal DIRR1326 charges to a high voltage level at 1444 and holds forward signal DIRF1328 at the high voltage level. In addition, during timing pulse 1432, address signals A1, A2 … … A81336 are charged to and/or held at a high voltage level at 1446 and pull logic evaluation signal LEVAL1334 low to a low voltage level at 1448. Low voltage level logic evaluation signal LEVAL1334 turns off the address evaluation transistors to prevent the address transistors from pulling address signals A1, A2 … … A81336 low to a low voltage level.

Timing pulse 1434 in timing signal BT5 at 1316 turns on the second evaluation transistor in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN2-SN13 in the higher bank shift register 1204 are at a high voltage level, and since the internal node signals SN1-SN13 in the lower bank shift register 1202 are at a high voltage level, the shift register output signals SO2-SO13 in the higher bank shift register 1204 and the shift register output signals SO1-SO13 in the lower bank shift register 1202 discharge to a low voltage level at 1450 during the timing pulse 1434. Since the internal node signal SN1 in upper bank shift register 1204 is at a low voltage level, shift register output signal SO1 in upper bank shift register 1204 remains at a high voltage, labeled 1452.

Timing pulse 1434 also turns on evaluation transistor 1266 and control pulse 1454 in control signal CSYNC1324 turns on control transistor 1268 to discharge reverse signal DIRR1326 to a low voltage level at 1456. In addition, timing pulse 1434 turns on the evaluation blocking transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to maintain logic evaluation signal LEVAL1334 at a low voltage level that turns off the evaluation transistors. The shift register output signal SO1332 is asserted during the timing pulse 1434 SO that one shift register output signal SO1 in the higher bank shift register 1204 is asserted to a high voltage level and all other shift register output signals SO2-SO13 in the higher bank shift register 1204 and all shift register output signals SO1-SO13 in the lower bank shift register 1202 are asserted to a low voltage level.

Timing pulse 1436 in timing signal BT6 at 1320 is provided to lower bank shift register 1202 and upper bank shift register 1204 in first precharge signal PRE1, to direction circuit 1210 in fourth evaluation signal EVAL4, and to logic evaluation precharge transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208. During timing pulse 1436 in first precharge signal PRE1, internal node signal SN1 in higher bank shift register 1204 charges to a high voltage level at 1458 and maintains all other internal node signals SN1330 in lower bank shift register 1202 and higher bank shift register 1204 at the high voltage level. Timing pulse 1436 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The low voltage level reverse signal DIRR1326 turns off control transistor 1274 and direction signal DIRF1328 remains charged to a high voltage level. Also, during timing pulse 1436, each logic evaluation signal LEVAL1334 charges to a high voltage level in lower bank logic circuit 1206 and upper bank logic circuit 1208 at 1460. The high level shift register output signal SO1 in higher bank shift register 1204 is received as input signal AI14 in higher bank logic 1208. The high voltage level input signal AI14 turns on the address transistors in the higher bank logic circuit 1208 to effectively pull down the address signals in the address signals A1A 2 … … A8 to provide the higher bank address 14 at 1462. The other shift register output signals SO2-SO13 in higher bank shift register 1204 and all shift register output signals SO1-SO13 in lower bank shift register 1202 are at low voltage levels, which turn off the address transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to not discharge address signals A1, A2 … … A8. The address signals A1, A2 … … A8 have valid values during the timing pulse 1436.

Timing pulse 1464 turns on each first evaluation transistor in the shift register cells in lower bank shift register 1202 to evaluate each forward input signal SLF (shown in FIG. 10A) at the shift register cells in lower bank shift register 1202. The forward input signal SIF of the first shift register cell is the control signal CSYNC 1324, which is at a low voltage level. The positive input signal SIF at each of the other shift register cells is a preceding shift register output signal SO1-SO12, which are at a low voltage level. Since the control signal CSYNC 1324 and the shift register output signals SO1-SO13 in the lower bank shift register 1202 are at a low voltage level, the forward input transistors in the lower bank shift register 1202 are turned off, and each of the internal node signals SN1-SN13 in the lower bank shift register 1202 is maintained at a high voltage level. The first evaluation transistor in the shift register cell in upper bank shift register 1204 is not turned on by timing pulse 1464, and internal node signals SN1-SN13 in upper bank shift register 1204 remain at a high voltage level. Timing pulse 1466 in timing signal BT2 at 1304 is not provided to bank select address generator 1200 and each signal remains unchanged during timing pulse 1466.

Then, a timing pulse 1468 in the timing signal BT3 at 1308 is provided to the higher bank shift register 1204 in a first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204 to evaluate each positive-going input signal SIF (shown in fig. 10A) at the shift register cell in the higher bank shift register 1204. The forward input signal SIF of the first shift register cell is the control signal CSYNC1324, which is at a low voltage level. The positive input signal SIF at each other shift register cell is the preceding shift register output signal SO1-SO 12. Shift register output signal SO1 in higher bank shift register 1204 is at a high voltage level and is the positive input signal SIF for the second shift register cell in higher bank shift register 1204.

Shift register output signal SO1 in upper bank shift register 1204 turns on the positive input transistor in the second shift register cell of upper bank shift register 1204. Also, the forward transistor is turned on by a forward signal DIRF 1328. Since the first evaluation transistor in the upper bank shift register 1204 is turned on, the forward input transistor in the second shift register cell is turned on, and the forward transistor is turned on, the internal node signal SN2 in the second shift register cell of the upper bank shift register 1204 discharges to a low voltage level, labeled 1476.

The first evaluation transistor in the shift register cell of lower bank shift register 1202 is not turned on by timing pulse 1468 and all internal node signals SN1-SN13 in lower bank shift register 1202 remain at a low voltage level at 1478. Also, control signal CSYNC1324 and shift register output signals SO2-SO13 in higher bank shift register 1204 are at low voltage levels, which turn off the forward input transistors in the other shift register cells in higher bank shift register 1204. Each of the other internal node signals SN1 and SN3-SN13 in the upper bank shift register 1204 remain at a high voltage level at 1478 because the forward input transistors are off.

During timing pulse 1470 in timing signal BT4 at 1312, shift register output signal SO1332 is charged and/or maintained at a high voltage level at 1480. Also, during timing pulse 1470, reverse signal DIRR1326 charges to a high voltage level at 1482 and forward signal DIRF1328 is held at the high voltage level. In addition, during timing pulse 1470, address signals A1, A2 … … A81336 are charged and/or held at a high voltage level at 1484 and logic evaluation signal LEVAL1334 is pulled low to a low voltage level at 1486. Low voltage level logic evaluation signal LEVAL1334 turns off the address evaluation transistors to prevent the address transistors from pulling address signals A1, A2 … … A81336 low to a low voltage level. The higher bank address 14 address signals of address signals A1, A2 … … A81336 are active during timing pulses 1464, 1466, and 1468.

Timing pulse 1472 in timing signal BT5 at 1316 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN1 and SN3-SN13 in lower bank shift register 1204 are at a high voltage level, and since the internal node signals SN1-SN13 in upper bank shift register 1202 are at a high voltage level, shift register output signals SO1 and SO3-SO13 in upper bank shift register 1204 and shift register output signals SO1-SO13 in lower bank shift register 1202 are discharged to a low voltage level at 1488 during timing pulse 1472. Since internal node signal SN2 in higher bank shift register 1204 is at a low voltage level, shift register output signal SO2 in higher bank shift register 1204 remains at a high voltage level, labeled 1490.

Timing pulse 1472 also turns on evaluation transistor 1266 and control pulse 1492 in control signal CSYNC1324 turns on control transistor 1268 to discharge reverse signal DIRR1326 to a low voltage level at 1494. In addition, timing pulse 1472 turns on the evaluation inhibit transistors in evaluation low bank logic 1206 and high bank logic 1208 to maintain logic evaluation signal LEVAL1334 at a low voltage level that turns off the evaluation transistors. The shift register output signal SO1332 is such that during a timing pulse 1472, one shift register output signal SO2 in the higher bank shift register 1204 is at a high voltage level, while all other shift register output signals SO1 and SO3-SO13 in the higher bank shift register 1204 and all shift register output signals SO1-SO13 in the lower bank shift register 1202 are at a low voltage level.

The timing pulse 1474 in timing signal BT6 at 1320 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in a first precharge signal PRE1, to the direction circuit 1210 in a fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1474 in first precharge signal PRE1, internal node signal SN2 in higher bank shift register 1204 charges to a high voltage level at 1496, and all other internal node signals SN1330 in lower bank shift register 1202 and higher bank shift register 1204 remain at the high voltage level. Timing pulse 1474 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The low voltage level reverse signal DIRR1326 turns off control transistor 1274 and direction signal DIRF1328 remains charged to a high voltage level. During timing pulse 1474, each logic evaluation signal LEVAL1334 charges to a high voltage level at 1497 in lower bank logic circuit 1206 and higher bank logic circuit 1208. The high level shift register output signal SO2 in higher bank shift register 1204 is received as input signal AI15 in higher bank logic 1208. The high voltage level input signal AI15 turns on the address transistors in the higher bank logic circuit 1208 to effectively pull down the address signals in address signals A1, A2 … …, A8 to a low voltage level and provide the higher bank address 15 at 1498. The other shift register output signals SO1 and SO3-SO13 in higher bank shift register 1204 and all shift register outputs SO1-SO13 in lower bank shift register 1202 are at low voltage levels, which turn off the address transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 not to discharge address signals A1, A2 … … A8 at 1336. The address signals A1, A2 … … A8 at 1336 establish valid values during timing pulse 1474.

The next series of six timing pulses in timing signals BT1-BT6 shift the high voltage level shift register output signal SO2 to the next shift register cell in the higher bank shift register 1204 to provide the high voltage level shift register output signal SO3 in the higher bank shift register 1204 and the higher bank address 16 in address signals A1, A2 … … -A8 at 1336. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 in higher bank shift register 1204 has gone high once. The series stops after the shift register output signal SO13 in the higher bank shift register 1204 has gone high and the higher bank address 26 has been provided in the address signals A1A 2 … … A8 at 1336. To begin the next series of addresses, lower bank shift register 1202 or upper bank shift register 1204 may be activated to provide lower bank addresses 1-13 or upper bank addresses 14-26 in either the forward or reverse direction, respectively.

In a forward operation of lower bank shift register 1202 and providing lower bank addresses 1-13, a control pulse in control signal CSYNC1324 is provided that substantially coincides with the timing pulse in timing signal BT5 at 1316 to set the shift direction to forward. Also, the control pulse in control signal CSYNC1324 is provided substantially coincident with the timing pulse in timing signal BT1 at 1300 to initiate or initiate shifting of the high voltage signal by the shift register output signals SO1-SO13 by the bank shift register 1202.

In a forward operation of higher bank shift register 1204 and providing higher bank addresses 14-26, a control pulse in control signal CSYNC1324 is provided that substantially coincides with the timing pulse in timing signal BT5 at 1316 to set the shift direction to forward. Also, a control pulse in control signal CSYNC1324 is provided that substantially coincides with the timing pulse in timing signal BT3 at 1308 to initiate or initiate shifting of the high voltage signal by the shift register output signals SO1-SO13 in the higher bank shift register 1204.

Fig. 18 is a timing diagram illustrating the operation of the bank select address generator 1200 in the reverse direction. The timing signals BT1-BT6 provide a series of six pulses that are repeated in a repeating series of six pulses. Each timing signal BT1-BT6 is provided as one pulse in the series of timing pulses.

In one series of six pulses, timing signal BT1 at 1500 contains timing pulse 1502, timing signal BT2 at 1504 contains timing pulse 1506, timing signal BT3 at 1508 contains timing pulse 1510, timing signal BT4 at 1512 contains timing pulse 1514, timing signal BT5 at 1516 contains timing pulse 1518 and timing signal BT6 at 1520 contains timing pulse 1522. Control signal CSYNC at 1524 contains control pulses that set the shift direction in bank select address generator 1200 and enable lower bank shift register 1202 and upper bank shift register 1204 to produce addresses 1-26.

Initially, neither lower bank shift register 1202 nor upper bank shift register 1204 are shifted, and direction circuit 1210 has not yet been set by a control pulse in control signal CSYNC 1524. The reverse signal DIRR at 1526 has been charged to a high voltage level, which turns on the control transistor 1274, which control transistor 1274 has previously pre-discharged the forward signal DIRF at 1528 to a low voltage level. The internal node signals SN at 1530 in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204 remain charged to the high voltage level, which discharge all shift register output signals SO at 1532 to the low voltage level. Logic evaluation signal LEVAL1534 in lower bank logic 1206 and higher bank logic 1208 remains charged to the high voltage level from the previous pulse in timing signal BT6 at 1520. Also, since the shift register output signal SO1532 is at a low voltage level, the address signals A1, A2 … … A8 at 1536 remain charged to a high voltage level unless the logic circuits are activated again or the address lines are discharged by the logic circuits of other banks.

Timing pulses 1502 in timing signal BT1 at 1500 are provided to lower bank shift register 1202 in first evaluation signal EVAL 1. Timing pulse 1502 turns on each first evaluation transistor in the shift register cell in lower bank shift register 1202. Control signal CSYNC1524 remains at a low voltage level and all shift register output signals SO1532 are at a low voltage level, which turns off each forward input transistor and each reverse input transistor in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1530 in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1530 remain at a high voltage level. The timing pulse 1506 of the timing signal BT2 at 1504 is not provided to bank select address generator 1200 and each signal remains unchanged during the timing pulse 1506.

Then, a timing pulse 1510 in a timing signal BT3 at 1508 is provided to the higher bank shift register 1204 in a first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. Control signal CSYNC1524 remains at a low voltage level and all shift register output signals SO1532 are at a low voltage level, which turns off each forward input transistor and each reverse input transistor in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signal SN1530 in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204 from discharging to a low voltage level. All shift register internal node signals SN1530 remain at a high voltage level.

The timing pulse 1514 in the timing signal BT4 at 1512 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in a second precharge signal PRE2, to the direction circuit 1210 in a third charge signal PRE3, and to the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1514 in second PRE-charge signal PRE2, all shift register output signals SO1532 in lower bank shift register 1202 and upper bank shift register 1204 are charged to a high voltage level at 1538. Also, during timing pulse 1514 in third PRE-charge signal PRE3, forward signal DIRF1528 is charged to a high voltage level at 1540 and reverse signal DIRR1526 is held at the high voltage level. Timing pulse 1514 is provided to each address line precharge transistor and evaluation prevention transistor in lower bank logic circuit 1206 and upper bank logic circuit 1208. Timing pulse 1514 holds the address signals a1, a2 … … A8 at 1536 at a high voltage level and turns on the evaluation prevention transistors to pull logic evaluation signal LEVAL1534 low to a low voltage level at 1542.

Timing pulses 1518 in timing signal BT5 at 1516 are provided to lower bank shift register 1202 and upper bank shift register 1204 in second evaluation signal EVAL2, to direction circuit 1210 in third evaluation signal EVAL3, and to lower bank logic circuit 1206 and upper bank logic circuit 1208. Timing pulse 1518 in second evaluation signal EVAL2 turns on each second evaluation transistor in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204. Since internal node signal SN1530 is at a high voltage level to turn on each internal node transistor in the shift register cells in lower bank shift register 1202 and upper bank shift register 1204, all shift register output signals SO1532 discharge to a low voltage level at 1544. Also, timing pulse 1518 in third evaluation signal EVAL3 turns on evaluation transistor 1266. Control signal CSYNC1524 is at a low voltage level to turn off control transistor 1268, and direction signal DIRR1526 remains charged to a high voltage level. Timing pulse 1518 is provided to each evaluation inhibit transistor in lower bank logic 1206 and upper bank logic 1208. Timing pulse 1518 turns on each evaluation prevention transistor to keep logic evaluation signal LEVAL1534 at a low voltage level. Logic evaluation signal LEVAL1534 at a low voltage level turns off the address evaluation transistor.

Timing pulse 1522 in timing signal BT6 at 1520 is provided to lower bank shift register 1202 and upper bank shift register 1204 in first precharge signal PRE1, to direction circuit 1210 in fourth evaluation signal EVAL4, and to logic evaluation precharge transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208. Timing pulse 1522 in first precharge signal PRE1 maintains all internal node signals SN1530 in lower and upper bank shift registers 1202 and 1204 at a high voltage level. Timing pulse 1522 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The high voltage level inverse signal DIRR1526 turns on control transistor 1274 so as to discharge direction signal DIRF1528 to a low voltage level at 1548. During timing pulse 1522, each logic evaluation signal LEVAL1534 charges to a high voltage level at 1550 in lower bank logic circuit 1206 and upper bank logic circuit 1208. Since all the shift register output signals SO1532 are at the low voltage level, all the address transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208 are turned off, and the address signals A1, A2 … … A8 remain at the high voltage level. Low voltage level forward signal DIRF1528 and high voltage level reverse signal DIRR1526 set lower bank shift register 1202 and upper bank shift register 1204 to shift in the reverse direction.

In the next series of six pulses, timing signal BT1 at 1500 contains timing pulse 1552, timing signal BT2 at 1504 contains timing pulse 1554, timing signal BT3 at 1508 contains timing pulse 1556, timing signal BT4 at 1512 contains timing pulse 1558, timing signal BT5 at 1516 contains timing pulse 1596 and timing signal BT6 at 1520 contains timing pulse 1562.

Timing pulse 1552 turns on each first evaluation transistor in the shift register cell in lower bank shift register 1202. A control pulse of control signal CSYNC1524 at 1564 turns on each inverting input transistor in the last or thirteenth shift register cell of lower bank shift register 1202 and upper bank shift register 1204. Also, the inversion transistor is turned on by an inversion signal DIRR 1526. Since the first evaluation transistor in lower bank shift register 1202 is turned on, the inverting input transistor in the last shift register cell is turned on, and the inverting transistor is turned on, internal node signal SN13 in the thirteenth shift register cell of lower bank shift register 1202 discharges to a low voltage level, labeled 1566.

The first evaluation transistor in the shift register cell in higher bank shift register 1204 is not turned on by timing pulse 1552 and all internal node signals SN1-SN13 in higher bank shift register 1204 remain at a high voltage level. Also, shift register output signal SO1532 is at a low voltage level, which turns off the inverting input transistors in all other shift register cells in lower bank shift register 1202, e.g., shift register cells 403 a-4031. Each internal node signal SN1-SN12 in lower bank shift register 1202 remains at a high voltage level due to the inverted input transistors being turned off. The timing pulse 1554 in timing signal BT2 at 1504 is not provided to bank select address generator 1200 and each signal remains unchanged during timing pulse 1554.

Then, a timing pulse 1556 in timing signal BT3 at 1508 is provided in first evaluation signal EVAL1 to higher bank shift register 1204 to turn on each first evaluation transistor in higher bank shift register 1204. Control signal CSYNC1524 remains at a low voltage level and shift register output signal SO1532 in higher bank shift register 1204 is at a low voltage level, which turns off each forward input transistor and each inverting input transistor in higher bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signals SN1-SN13 in higher bank shift register 1204 from discharging to a low voltage level. All of the shift register internal node signals SN1-SN13 in upper bank shift register 1204 remain at a high voltage level.

During timing pulse 1558 in timing signal BT4 at 1512, all shift register output signals SO1532 are charged to a high voltage level at 1568. Also, during timing pulse 1558, reverse signal DIRR1526 is maintained at a high voltage level and forward signal DIRF1528 is charged to the high voltage level at 1570. In addition, during timing pulse 1558, all of address signals A1, A2 … … A81536 are held at a high voltage level and logic evaluation signal LEVAL1534 is pulled low to a low voltage level at 1572. Low voltage level logic evaluation signal LEVAL1534 turns off address evaluation transistors to prevent address transistors from pulling address signals A1, A2 … … A81536 low to a low voltage level.

Timing pulse 1560 in timing signal BT5 at 1516 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN1-SN12 in lower bank shift register 1202 are at a high voltage level, and since the internal node signals SN1-SN13 in upper bank shift register 1204 are at a high voltage level, the shift register output signals SO1-SO12 in lower bank shift register 1202 and the shift register output signals SO1-SO13 in upper bank shift register 1204 are discharged to a low voltage level at 1574 during timing pulse 1560. Since the internal node signal SN13 in lower bank shift register 1202 is at a low voltage level, shift register output signal SO13 in lower bank shift register 1202 remains at a high voltage, labeled 1576.

The timing pulse 1560 also turns on the evaluation transistor 1266 in the direction circuit 1210. Control signal CSYNC1524 is at a low voltage level to turn off control transistor 1268, and reverse signal DIRR1526 remains charged to a high voltage level. In addition, timing pulse 1560 turns on the evaluation blocking transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to hold logic evaluation signal LEVAL1534 at a low voltage level to turn off the evaluation transistors. The shift register output signal SO1532 is asserted during the timing pulse 1560 SO that one shift register output signal SO13 in the lower bank shift register 1202 is asserted to a high voltage level and all other shift register output signals SO1-SO12 in the lower bank shift register 1202 and all shift register output signals SO1-SO13 in the upper bank shift register 1204 are asserted to a low voltage level.

The timing pulse 1562 in the timing signal BT6 at 1520 is provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the first precharge signal PRE1, to the direction circuit 1210 in the fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. During timing pulse 1562 in first precharge signal PRE1, internal node signal SN13 in lower bank shift register 1202 charges to a high voltage level at 1582 and maintains all other internal node signals SN1530 in lower bank shift register 1202 and upper bank shift register 1204 at the high voltage level. Timing pulse 1562 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The high voltage level inverse signal DIRR1526 turns on the control transistor 1274 and at this time discharges the direction signal DIRF1528 to a low voltage level at 1580. Also, during timing pulse 1562, each logic evaluation signal LEVAL1534 in lower bank logic circuit 1206 and higher bank logic circuit 1208 charges to a high voltage level at 1584. The high level shift register output signal SO13 in the lower bank shift register 1202 is received as the input signal AI13 in the lower bank logic circuit 1206. The high voltage level input signal AI13 turns on the address transistors in the lower bank logic circuit 1206 to effectively pull down the address signals in address signals A13A 13 … … A8 at 1536 to provide the lower bank address 13 at 1586. The other shift register output signals SO2-SO12 in lower bank shift register 1202 and the shift register output signals SO1-SO13 in upper bank shift register 1204 are at low voltage levels, which turn off the address transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to not discharge address signals A1, A2 … … A8 at 1536. The address signals A1, A2 … … A8 at 1536 establish valid values during timing pulse 1562.

In the next series of six pulses, timing signal BT1 at 1500 contains timing pulse 1588, timing signal BT2 at 1504 contains timing pulse 1590, timing signal BT3 at 1508 contains timing pulse 1592, timing signal BT4 at 1512 contains timing pulse 1594, timing signal BT5 at 1516 contains timing pulse 1596 and timing signal BT6 at 1520 contains timing pulse 1598.

Timing pulse 1588 turns on each first evaluation transistor in the shift register cells in lower bank shift register 1202 to evaluate each reverse input signal SIR (shown in fig. 10A) in the shift register cells in lower bank shift register 1202. The reverse input signal SIR of the last shift register cell is the control signal CSYNC1524, which is at a low voltage level. The reverse input signal SIR at each other shift register cell is the subsequent (next-in-line) shift register output signal SO2-SO 13. The shift register output signal SO13 in the lower bank shift register 1202 is at a high voltage level and is the reverse input signal SIR of the next to last or twelfth shift register cell in the lower bank shift register 1202.

The shift register output signal SO13 in lower bank shift register 1202 turns on the inverting input transistor in the twelfth shift register cell in lower bank shift register 1202. Also, the inversion transistor is turned on by an inversion signal DIRR 1526. Since the first evaluation transistor in lower bank shift register 1202 is turned on, the inverting input transistor in the twelfth shift register is turned on, and the inverting transistor is turned on, internal node signal SN12 in the twelfth shift register of lower bank shift register 1202 discharges to a low voltage level, labeled 1600.

The first evaluation transistor in the shift register cell in higher bank shift register 1204 is not turned on by timing pulse 1588 and all internal node signals SN1-SN13 in higher bank shift register 1204 remain at a high voltage level. Also, control signal CSYNC1524 and shift register output signal SO1-S012 in lower bank shift register 1202 are at low voltage levels, which turn off the inverting input transistors in the other shift register cells of lower bank shift register 1202. Each of the other internal node signals SN1-SN11 and SN13 in the lower bank shift register 1102 remain at a high voltage level due to the inverted input transistors being turned off. Timing pulse 1590 in timing signal BT 21504 is not provided to bank select address generator 1200 and each signal remains unchanged during timing pulse 1590.

Then, a timing pulse 1592 in timing signal BT3 at 1508 is provided to the higher bank shift register 1204 in first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. Control signal CSYNC1524 remains at a low voltage level and shift register output signals SO1-SO13 in higher bank shift register 1204 are at a low voltage level, which turns off each forward input transistor and each reverse input transistor in higher bank shift register 1204. The non-conductive forward and reverse input transistors prevent the internal node signals SN1-SN13 in higher bank shift register 1204 from discharging to a low voltage level. All of the shift register internal node signals SN1-SN13 in upper bank shift register 1204 remain at a high voltage level.

During timing pulse 1594 in timing signal BT4 at 1512, shift register output signal SO1532 charges to and/or is maintained at a high voltage level at 1602. Also, during timing pulse 1594, reverse signal DIRR1526 is maintained at a high voltage level and forward signal DIRF1528 is charged to the high voltage level at 1604. In addition, during timing pulse 1594, the address signals A1, -A2 … … -A8 at 1536 are charged to and/or held at a high voltage level at 1606 and the logic evaluation signal LEVAL1534 is pulled low to a low voltage level at 1608. The low voltage level logic evaluation signal LEVAL1534 turns off the address evaluation transistors to prevent the address transistors from pulling the address signals A1A 2 … … A8 at 1536 low to a low voltage level. 1536 the lower bank address 13 address signals in address signals A1, A2 … … A8 are active during timing pulses 1588, 1590, and 1592.

Timing pulse 1596 in timing signal BT5 at 1516 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN1-SN11 and SN13 in lower bank shift register 1202 are at a high voltage level and since the internal node signals SN1-SN13 in upper bank shift register 1204 are at a high voltage level, shift register output signals SO1-SO11 and SO13 in lower bank shift register 1202 and shift register output signals SO1-SO13 in upper bank shift register 1204 are discharged to a low voltage level at 1610 during timing pulse 1596. Since internal node signal SN12 in lower bank shift register 1202 is at a low voltage level, shift register output signal SO12 in lower bank shift register 1202 remains at a low voltage level, labeled 1612.

The timing pulse 1596 also turns on the evaluation transistor 1266 in the direction circuit 1210. Control signal CSYNC1524 is at a low voltage level to turn off control transistor 1268, and reverse signal DIRR1526 remains at a high voltage level. In addition, timing pulse 1560 turns on the evaluation inhibit transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to hold logic evaluation signal LEVAL1534 at a low voltage level that turns off the evaluation transistors. Shift register output signal SO1532 is asserted during timing pulse 1596 SO that one shift register output signal SO12 in lower bank shift register 1202 is asserted to a high voltage level and all other shift register output signals SO1-SO11 and SO13 in lower bank shift register 1202 and all shift register output signals SO1-SO13 in upper bank shift register 1204 are asserted to a low voltage level.

Timing pulse 1598 in timing signal BT6 at 1520 is provided to lower bank shift register 1202 and upper bank shift register 1204 in first precharge signal PRE1, to direction circuit 1210 in fourth evaluation signal EVAL4, and to logic evaluation precharge transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208. During timing pulse 1598 in first precharge signal PRE1, internal node signal SN12 in lower bank shift register 1202 charges to a high voltage level at 1618 and maintains all other internal node signals SN1530 in lower bank shift register 1202 and upper bank shift register 1204 at the high voltage level. Timing pulse 1598 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The high voltage level reverse signal DIRR1526 turns on the control transistor 1274 and discharges the direction signal DIRF1528 to a low voltage level at 1616. Also, during timing pulse 1598, each logic evaluation signal LEVAL1534 charges to a high voltage level at 1620 in lower bank logic circuit 1206 and upper bank logic circuit 1208. The high level shift register output signal SO12 in the lower bank shift register 1202 is received as the input signal AI12 in the lower bank logic circuit 1206. The high voltage level input signal AI12 turns on the address transistors in the lower bank logic circuit 1206 to effectively pull down the address signals in address signals A1A 2 … … A8 at 1536 to provide the lower bank address 12 at 1622. The other shift register output signals SO1-SO11 and SO13 in lower bank shift register 1202 and all shift register output signals SO1-SO13 in upper bank shift register 1204 are at low voltage levels, which turn off the address transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 SO as not to discharge address signals A1, A2 … … A81536. The address signals A1, A2 … … A8 at 1536 establish valid values during timing pulse 1598.

The next series of six timing pulses in timing signals BT1-BT6 shifts the high voltage level shift register output signal SO12 to the previous shift register cell in lower bank shift register 1202 to provide a high voltage level shift register output signal S011 in lower bank shift register 1202 and lower bank address 11 in address signals A1, A2 … … A8 at 1536. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 in lower bank shift register 1202 has gone high once. The series stops after the shift register output signal SO1 in the lower bank shift register 1202 has gone high and the lower bank address 1 has been provided in the address signals A1A 2 … … A8 at 1536. To begin the next series, lower bank shift register 1202 or upper bank shift register 1204 may be activated to provide lower bank addresses 1-13 or upper bank addresses 14-26 in the forward or reverse direction, respectively. In operation of this embodiment, the upper bank shift register 1204 is enabled to provide the upper bank addresses 14-26 in the reverse direction when the lower bank address 1 is provided at 1624 of the address signals A1, -A2 … … -A8 at 1536.

Of the series of six pulses, timing signal BT1 at 1500 contains timing pulse 1626, timing signal BT2 at 1504 contains timing pulse 1628, timing signal BT3 at 1508 contains timing pulse 1630, timing signal BT4 at 1512 contains timing pulse 1632, timing signal BT5 at 1516 contains timing pulse 1634 and timing signal BT6 at 1520 contains timing pulse 1636.

Timing pulse 1626 turns on each first evaluation transistor in the shift register cells in lower bank shift register 1202, and inversion signal DIRR1526 turns on each inversion transistor in lower bank shift register 1202 and upper bank shift register 1204. Control signal CSYNC1524 is at a low voltage level to turn off each inverting input transistor in the thirteenth shift register cell in lower bank shift register 1202 and upper bank shift register 1204. Also, the shift register output signals SO2-SO13 in lower bank shift register 1202 are at a low voltage level, which turns off the inverting input transistors in all other shift register cells in lower bank shift register 1202, e.g., shift register cells 403 a-4031. Each internal node signal SN1-SN13 in lower bank shift register 1202 remains at a high voltage level due to the inverting input transistor being turned off. In addition, the first evaluation transistors in the shift register cells in upper bank shift register 1204 are not turned on by timing pulse 1552, and all internal node signals SN1-SN13 in upper bank shift register 1204 remain at a high voltage level. The timing pulse 1628 in the timing signal BT2 at 1504 is not provided to the bank select address generator 1200 and each signal remains unchanged during the timing pulse 1628.

Then, the timing pulse 1630 in the timing signal BT3 at 1508 is provided to the higher bank shift register 1204 in the first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204. A control pulse at 1638 in control signal CSYNC1524 turns on each inverting input transistor in the thirteenth shift register cell in lower bank shift register 1202 and upper bank shift register 1204. Also, the inversion transistor is turned on by an inversion signal DIRR 1526. Since the first evaluation transistor in the upper bank shift register 1204 is turned on, the inverting input transistor in the thirteenth shift register cell is turned on, and the inverting transistor is turned on, the internal node signal SN13 in the thirteenth shift register cell in the upper bank shift register 1204 discharges to a low voltage level, labeled 1640.

The first evaluation transistor in the shift register cell in lower bank shift register 1202 is not turned on by timing pulse 1630 and all internal node signals SN1-SN13 in lower bank shift register 1202 remain at a high voltage level. Also, shift register output signals SO1-SO13 in higher bank shift register 1204 are at low voltage levels, which turn off the inverting input transistors in all other shift register cells in higher bank shift register 1204. Each of the other internal node signals SN1-SN12 in higher bank shift register 1204 remain at a high voltage level due to the inverting input transistors being turned off.

During timing pulse 1632 in timing signal BT4 at 1512, all shift register output signals SO1532 charge to a high voltage level at 1642. Also, during timing pulse 1632, the reverse signal DIRR1526 is maintained at a high voltage level and the forward signal DIRF1528 is charged to the high voltage level at 1644. In addition, during timing pulse 1632, address signals A1, -A2 … … -A8 at 1536 are charged to and/or held at a high voltage level at 1646 and logic evaluation signal LEVAL1534 is pulled low to a low voltage level at 1648. Low voltage level logic evaluation signal LEVAL1534 turns off address evaluation transistors to prevent address transistors from pulling address signals A1, A2 … … A81536 low to a low voltage level.

Timing pulse 1634 in timing signal BT5 at 1516 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN1-SN12 in higher bank shift register 1204 are at a high voltage level, and since the internal node signals SN1-SN13 of lower bank shift register 1202 are at a high voltage level, timing pulse 1634 discharges shift register output signals SO1-SO12 in higher bank shift register 1204 and shift register output signals SO1-SO13 in lower bank shift register 1202 to a low voltage level at 1650. Since internal node signal SN13 in higher bank shift register 1204 is at a low voltage level, shift register output signal SO13 in higher bank shift register 1204 remains at a high voltage level, labeled 1652.

The timing pulse 1634 also turns on the evaluation transistor 1266 in the direction circuit 1210. Control signal CSYNC1524 is at a low voltage level to turn off control transistor 1268, and reverse signal DIRR1526 remains at a high voltage level. In addition, timing pulse 1634 turns on the evaluation blocking transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to hold logic evaluation signal LEVAL1534 at a low voltage level that turns off the evaluation transistors. The shift register output signal SO1532 is asserted during the timing pulse 1634 SO that one shift register output signal SO13 in the higher bank shift register 1204 is asserted to a high voltage level and all other shift register output signals SO1-SO12 in the higher bank shift register 1204 and all shift register output signals SO1-SO13 in the lower bank shift register 1202 are asserted to a low voltage level.

Timing pulses 1636 in the timing signal BT6 at 1520 are provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the first precharge signal PRE1, to the direction circuit 1210 in the fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. Timing pulse 1636 in first precharge signal PRE1 charges internal node signal SN13 in higher bank shift register 1204 to a high voltage level at 1658 and maintains all other internal node signals SN1530 in lower bank shift register 1202 and higher bank shift register 1204 at a low voltage level. The timing pulse 1636 in the fourth evaluation signal EVAL4 turns on the evaluation transistor 1272 in the direction circuit 1210. The high voltage level reverse signal DIRR1526 turns on the control transistor 1274 and discharges the direction signal DIRF1528 to a low voltage level at 1656. Timing pulse 1636 also charges each logic evaluation signal LEVAL1534 to a high voltage level at 1660 in lower bank logic 1206 and upper bank logic 1208. The high level shift register output signal SO13 in higher bank shift register 1204 is received as input signal AI26 in higher bank logic 1208. The high voltage level input signal AI26 turns on the address transistors in higher bank logic circuit 1208 to effectively pull down the address signals in address signals A1A 2 … … A8 at 1536 to provide higher bank address 26 at 1662. The other shift register output signals SO1-SO12 in higher bank shift register 1204 and all shift register output signals SO1-SO13 in lower bank shift register 1202 are at a low voltage level, which turn off the address transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to not discharge address signals A1, A2 … … A8 at 1536. The address signals A1, A2 … … A8 at 1536 establish valid values during timing pulse 1636.

In the next series of six pulses, timing signal BT1 at 1500 contains timing pulse 1664, timing signal BT2 at 1504 contains timing pulse 1666, timing signal BT3 at 1508 contains timing pulse 1668, timing signal BT4 at 1512 contains timing pulse 1670, timing signal BT5 at 1516 contains timing pulse 1672 and timing signal BT6 at 1520 contains timing pulse 1674.

Timing pulse 1664 turns on each first evaluation transistor in the shift register cells of lower bank shift register 1202 to evaluate each reverse input signal SIR (shown in fig. 10A) in the shift register cells of lower bank shift register 1202. The reverse input signal SIR of the last shift register cell is the control signal CSYNC1524, which is at a low voltage level. The reverse input signal SIR at each other shift register cell is one of the subsequent shift register output signals SO2-SO13, which is at a low voltage level. Since the control signal CSYNC1524 and the shift register output signals SO1-SO13 in the lower bank shift register 1202 are at a low voltage level, the inverting input transistors in the lower bank shift register 1202 are turned off, and each of the internal node signals SN1-SN13 in the lower bank shift register 1202 is maintained at a high voltage level. The first evaluation transistors in the shift register cells in higher bank shift register 1204 are not turned on by timing pulse 1664, and internal node signals SN1-SN13 in higher bank shift register 1204 remain at high voltage levels. The timing pulse 1666 in the timing signal BT2 at 1504 is not provided to the bank select address generator 1200 and each signal remains unchanged during the timing pulse 1666.

Then, a timing pulse 1668 in a timing signal BT3 at 1508 is provided to the higher bank shift register 1204 in a first evaluation signal EVAL1 to turn on each first evaluation transistor in the higher bank shift register 1204 to evaluate each inverted input signal SIR (shown in fig. 10A) at the shift register cells in the higher bank shift register 1204. The reverse input signal SIR of the last shift register cell is the control signal CSYNC1524, which is at a low voltage level. The reverse input signal SIR at each other shift register cell is in the subsequent shift register output signals SO2-SO 13. The shift register output signal SO13 in higher bank shift register 1204 is at a high voltage level and is the reverse input signal SIR of the next to last shift register cell in higher bank shift register 1204.

Shift register output signal SO13 in upper bank shift register 1204 turns on the inverting input transistor in the next to last shift register cell in upper bank shift register 1204. Also, the inversion transistor is turned on by an inversion signal DIRR 1526. Since the first evaluation transistor in the higher bank shift register 1204 is turned on, the inverting input transistor in the adjacent last shift register cell is turned on, and the inverting transistor is turned on, the internal node signal SN12 in the higher bank shift register 1204 adjacent the last or twelfth shift register cell discharges to a low voltage level, labeled 1676.

The first evaluation transistor in the shift register cell of the lower bank shift register 1202 is not turned on by the timing pulse 1668, and all of the internal node signals SN1-SN13 in the lower bank shift register 1202 remain at a high voltage level at 1678. Also, control signal CSYNC1524 and shift register output signals SO1-SO12 in higher bank shift register 1204 are at low voltage levels, which turn off the inverting input transistors in the other shift register cells in higher bank shift register 1204. Each of the other internal node signals SN1-SN11 and SN13 in the upper bank shift register 1204 remain at a high voltage level at 1678 due to the inverted input transistors being turned off.

Timing pulse 1670 in timing signal BT4 at 1512 charges and/or holds shift register output signal SO1532 to a high voltage level at 1680. Also, timing pulse 1670 holds reverse signal DIRR1526 at a high voltage level and charges forward signal DIRF1528 to a high voltage level at 1682. In addition, timing pulse 1670 charges and/or holds address signals A1, A2 … … A8 at 1536 to a high voltage level at 1684 and pulls logic evaluation signal LEVAL1534 low to a low voltage level at 1686. Low voltage level logic evaluation signal LEVAL1534 turns off address evaluation transistors to prevent address transistors from pulling address signals A1, A2 … … A81536 low to a low voltage level. The higher bank address 26 address signals of address signals A1, A2 … … A81536 are active during timing pulses 1664, 1666, and 1668.

Timing pulse 1672 in timing signal BT5 at 1516 turns on the second evaluation transistors in lower bank shift register 1202 and upper bank shift register 1204. Since the internal node signals SN1-SN11 and SN13 in higher bank shift register 1204 are at high voltage levels, and since the internal node signals SN1-SN13 in lower bank shift register 1202 are at high voltage levels, timing pulse 1672 discharges shift register output signals SO1-SO11 and SO13 in higher bank shift register 1204 and shift register output signals SO1-SO13 in lower bank shift register 1202 to low voltage levels at 1688. Since the internal node signal SN12 in the upper bank shift register 1204 is at a low voltage level, the shift register output signal SO12 in the upper bank shift register 1204 remains at a low voltage, labeled 1690.

The timing pulse 1672 also turns on the evaluation transistor 1266 in the direction circuit 1210. Control signal CSYNC1524 is at a low voltage level to turn off control transistor 1268, and reverse signal DIRR1526 remains charged to a high voltage level. In addition, timing pulse 1672 turns on the evaluation blocking transistors in lower bank logic circuit 1206 and upper bank logic circuit 1208 to hold logic evaluation signal LEVAL1534 at a low voltage level that turns off the evaluation transistors. The shift register output signal SO1532 is asserted during the timing pulse 1672 SO that one shift register output signal SO12 in the higher bank shift register 1204 is asserted to a high voltage level and all other shift register output signals SO1-SO11 and SO13 in the higher bank shift register 1204 and all shift register output signals SO1-SO13 in the lower bank shift register 1202 are asserted to a low voltage level.

Timing pulses 1674 in the timing signal BT6 at 1520 are provided to the lower bank shift register 1202 and the upper bank shift register 1204 in the first precharge signal PRE1, to the direction circuit 1210 in the fourth evaluation signal EVAL4, and to the logic evaluation precharge transistors in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. The timing pulse 1674 in the first precharge signal PRE1 charges the internal node signal SN12 in the higher bank shift register 1204 to a high voltage level at 1696 and holds all other internal node signals SN1530 in the lower bank shift register 1202 and the higher bank shift register 1204 at a high voltage level. Timing pulse 1674 in fourth evaluation signal EVAL4 turns on evaluation transistor 1272 in direction circuit 1210. The high voltage level inverse signal DIRR1526 turns on the control transistor 1274 and discharges the direction signal DIRF1528 to a low voltage level at 1694. The timing pulse 1674 also charges each logic evaluation signal LEVAL1534 to a high voltage level at 1697 in the lower bank logic circuit 1206 and the upper bank logic circuit 1208. The high level shift register output signal SO12 in higher bank shift register 1204 is received as input signal AI25 in higher bank logic 1208. The high voltage level input signal AI25 turns on the address transistors in the higher bank logic circuit 1208 to effectively pull down the address signals in address signals A1, A2 … … A8 at 1536 to a low voltage level and provide the higher bank address 25 at 1698. The other shift register output signals SO1-SO11 and SO13 in higher bank shift register 1204 and all shift register output signals SO1-SO13 in lower bank shift register 1202 are at low voltage levels, which turn off the address transistors in lower bank logic circuit 1206 and higher bank logic circuit 1208 to not discharge address signals A1, A2 … … A8 at 1536. The address signals A1, A2 … … A8 at 1536 establish valid values during timing pulse 1674.

The next series of six timing pulses in timing signals BT1-BT6 shifts the high voltage level shift register output signal SO12 to the previous shift register cell in the higher bank shift register 1204 to provide a high voltage level shift register output signal S011 in the higher bank shift register 1204 and the higher bank address 24 in address signals A1, A2 … … A8 at 1536. The shifting continues with each series of six timing pulses until each shift register output signal SO1-SO13 in higher bank shift register 1204 has gone high once. The series stops after the shift register output signal SO1 in the higher bank shift register 1204 has gone high and the higher bank address 14 has been provided in the address signals A1A 2 … … A8 at 1536. To begin the next series of addresses, lower bank shift register 1202 or upper bank shift register 1204 may be activated to provide lower bank addresses 1-13 or upper bank addresses 14-26, respectively, in either the forward or reverse direction.

In a reverse operation of lower bank shift register 1202 and providing lower bank address 13-1, low voltage control signal CSYNC1524 is provided substantially coincident with the timing pulse in timing signal BT5 at 1516 to set the shift direction to reverse. Also, a control pulse in control signal CSYNC1524 is provided that substantially coincides with the timing pulse in timing signal BT1 at 1500 to initiate or initiate shifting of the high voltage signal by the lower bank shift register 1202 by a shift register output signal from SO13 to SO 1.

In the reverse operation of higher bank shift register 1204 and providing higher bank addresses 26-14, the control pulse in low voltage level control signal CSYNC1524 is provided substantially coincident with the timing pulse in timing signal BT5 at 1516 to set the shift direction to reverse. Also, a control pulse in control signal CSYNC1524 is provided that substantially coincides with the timing pulse in timing signal BT3 at 1508 to initiate or initiate shifting of the high voltage signal by the higher bank shift register 1204 with the shift register output signal from SO 13-to SO 1.

Control signal CSYNC controls the operation of one or more address generators in the printhead die. Each address generator is controlled by a control pulse in control signal CSYNC that substantially coincides with a timing pulse in the timing signal to set the direction of operation and initiate operation. In one embodiment, two address generators provide valid address signals during six timing pulses in six select signals corresponding to six fire signals. One address generator provides a valid address signal during three of the six timing pulses, and the other address generator provides a valid address signal during the other three of the six timing pulses. In one embodiment, each of the two address generators is similar to address generator 400 in FIG. 9. In another embodiment, each of the two address generators is similar to bank select address generator 1200 of FIG. 15.

The timing of the control pulses in control signal CSYNC to control address generator 400 of FIG. 9 is different from the timing of the control pulses in control signal CSYNC to control bank select address generator 1200 of FIG. 15. The timing pulse (shown in FIG. 9) in timing signal T3 and timing signal BT4 (shown in FIG. 15) precharge the second stage of the shift register cells in address generator 400 and bank select address generator 1200, respectively. The second stage of the pre-charged shift register cell charges the shift register output signal SO to a high voltage level and may destroy the validity of valid, actively driven address signals. To generate the next valid address signal, the shift register output signal SO is evaluated to a valid value and the address signal is evaluated to a valid address signal. The shift register output signal SO is evaluated to a valid value during the timing pulse in the timing signal T4 in the address generator 400 and during the timing pulse in the timing signal BT5 in the bank select address generator 1200. During the timing pulse in timing signal T5 in address generator 400 and during the timing pulse in timing signal BT6 in bank select address generator 1200, the valid shift register output signal SO is provided to the logic circuit and the address signal is evaluated to a valid value to provide a valid address signal. This results in the following series.

T3/BT4	T4/BT5	T5/BT6	T6/BT1	T1/BT2	T2/BT3	T3/BT4	T4/BT5	T5/BT6	T6/BT1	T1/BT2	T2/BT3
												High SO content	Evaluation of SO	SO effective	SO effective	SO effective	SO effective	High SO content	Evaluation of SO	SO effective	SO effective	SO effective	SO effective
Address destruction		Address evaluation	Address validation	Address validation	Address validation	Address destruction		Address evaluation	Address validation	Address validation	Address validation

When the shift register output signal SO is precharged during T3 or BT4, the address signal may be precharged. In the timing signal T5 or BT6, the address signal is precharged before being evaluated as a valid address signal. Therefore, the address signals may be precharged during the timing pulse in the timing signal T3 or T4 in the address generator 400 and during the timing pulse in the timing signal BT4 or BT5 in the bank select address generator 1200. The logic evaluation signal LEVAL turns off the logic evaluation transistors in the address generator 400 and the bank selection address generator 1200 when the shift register output signal SO is charged to a high voltage level and evaluated to a valid value during the timing pulses in the timing signals T3 and T4 in the address generator 400 and the timing pulses in the timing signals BT4 and BT5 in the bank selection address generator 1200. The precharge of the address signal is added in the following sequence.

The internal node signal SN in the shift register cell needs to be valid when the shift register output signal SO is evaluated to be valid. The initial internal node signal SN may be precharged during a timing pulse in the timing signal T5 or BT6 after the shift register output signal SO becomes active. Because the shift register output signal SO is used for the input signal of the preceding or subsequent shift register unit in the address generators 400 and 1200, the internal node signal SN is evaluated before the shift register output signal SO is precharged to a high voltage level during the timing signal T3 or BT 4. The internal node signal SN is evaluated before or during the timing pulse in the timing signal T2 or BT 3. Also, the internal node signal SN, which substantially coincides with the control pulse in the control signal CSYNC, is evaluated to start the shift register. The possibility of internal node signal precharging and evaluation is increased in the following sequence.

In the address generator 400, the internal node signal SN is precharged during a timing pulse in the timing signal T1 and evaluated during a timing pulse in the timing signal T2. To start address generator 400, the control pulse in control signal CSYNC is provided during the timing pulse in timing signal T2.

The internal node signal SN for the lower bank shift register 1202 and the upper bank shift register 1204 in the bank select address generator 1200 is precharged during the timing pulse in the timing signal BT 6. The internal node signal SN in the lower bank shift register 1202 is evaluated during the timing pulse in the timing signal BT1, and the internal node signal SN in the upper bank shift register 1204 is evaluated during the timing pulse in the timing signal BT 3. To activate the lower bank shift register 1202, the control pulse in control signal CSYNC is provided during the timing pulse in timing signal BT1, and to activate the upper bank shift register 1204, the control pulse in control signal CSYNC is provided during the timing pulse in timing signal BT 3.

The direction signals DIRR and DIRF are valid when the internal node signal SN is evaluated. In the address generator 400, the inversion signal DIRR is precharged during a timing pulse in the timing signal T3, which is right after the internal node signal SN is evaluated. The reverse signal DIRR is evaluated during timing pulses in the timing signal T4. The forward signal DIRF is precharged during timing pulses in timing signal T5 and evaluated during timing pulses in timing signal T6 to provide valid direction signals DIRR and DIRF during timing pulses in timing signals T1 and T2.

In bank select address generator 1200, direction signals DIRR and DIRF are set by control pulses in control signal CSYNC during each series of six timing pulses. Two other control pulses in control signal CSYNC enable lower bank shift register 1202 and upper bank shift register 1204. Also, the internal node signal SN is evaluated during the timing pulses in the timing signals BT1 and BT3, and the direction signals DIRR and DIRF need to be valid during the timing pulses in the timing signals BT1 and BT 3.

In the bank select address generator 1200 and direction circuit 1210 of fig. 16, the direction signals DIRR and DIRF are precharged during the timing pulse in the timing signal BT4 just after the internal node signal SN in the upper bank shift register 1204 is evaluated. Direction signal DIRR is evaluated during timing pulses in timing signal BT5 and direction signal DIRF is evaluated during timing pulses in timing signal BT 6. The direction signals DIRF and DIRR are active during timing pulses in the timing signals BT1, BT2, and BT 3. The control pulse in control signal CSYNC is provided during the timing pulse in timing signal BT5 to set the shift direction and provide the address signal.

In one embodiment, the six timing pulses in the select signals SEL1, SEL2 … … SEL6 coincide with the six fire signals provided to the six fire groups. The six timing pulses in select signals SEL1, SEL2 … … SEL6 provide six possible positions for the control pulses in control signal CSYNC for controlling an address generator such as address generator 400 or bank select address generator 1200. In address generator 400, a control pulse in control signal CSYNC is used to activate shift register 402, and two control pulses in control signal CSYNC are used to set direction signals DIRR and DIRF. The control pulse in control signal CSYNC to activate shift register 402 is provided during the timing pulse in timing signal T2. The control pulses in control signal CSYNC for setting direction signal DIRR are provided during the timing pulses in timing signal T4, and the control pulses in control signal CSYNC for setting direction signal DIRF are provided during the timing pulses in timing signal T6.

In bank select address generator 1200, direction signals DIRR and DIRF are set by one control pulse or low voltage level in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT 5. Bank select address generator 1200 is enabled using two control pulses in control signal CSYNC. One control pulse in control signal CSYNC enables lower bank shift register 1202 and another control pulse in control signal CSYNC enables upper bank shift register 1204. Lower bank shift register 1202 is activated by a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT1, and upper bank shift register 1204 is activated by a control pulse in control signal CSYNC that substantially coincides with a timing pulse in timing signal BT 3. The control pulses in control signal CSYNC provided during the timing pulses in timing signals BT1, BT3, and BT5 control the operation of bank select address generator 1200.

In one embodiment, two bank select address generators 1200 are used in one printhead die 40. One of the two bank select address generators 1200 provides address signals to fire groups 1-3 and the other bank select address generator 1200 provides address signals to fire groups 4-6. The control pulse in control signal CSYNC is shifted by three timing pulses substantially coincident with the timing pulses in timing signals BT2, BT4, and BT6 to control the second bank select address generator 1200.

FIG. 19 is a block diagram illustrating an embodiment of two bank select address generators 1700 and 1702 and six fire groups 1704a-1704f in a printhead die 40. Bank select address generators 1700 and 1702 are one embodiment of control circuitry in printhead die 40. Each address generator 1700 and 1702 is similar to bank select address generator 1200, and fire groups 1704a-1704f are similar to fire groups 202a-202f illustrated in FIG. 7.

The address generator 1700 is electrically coupled to the fire groups 1704a-1704c via first address lines 1712. Address lines 1712 provide address signals A1A 2 … … A8 from bank select address generator 1700 to firing cells 120 in each fire group 1704a-1704 c. Also, bank select address generator 1700 is electrically coupled to control lines 1710. Control line 1710 receives control signal CSYNC and provides control signal CSYNC to bank select address generator 1700. In addition, bank select address generator 1700 is electrically coupled to select lines 1708a-1708 f. Select lines 1708a-1708f receive select signals SEL1, SEL2 … … SEL6 and provide select signals SEL1, SEL2 … … SEL6 to bank select address generator 1700 and the corresponding fire groups 1704a-1704 f.

Select line 1708a provides select signal SEL1 to bank select address generator 1700 as timing signal BT 1. Select line 1708b provides select signal SEL2 to bank select address generator 1700 as timing signal BT 2. Select line 1708c provides select signal SEL3 to bank select address generator 1700 as timing signal BT 3. Select line 1708d provides select signal SEL4 to bank select address generator 1700 as timing signal BT 4. Select line 1708e provides select signal SEL5 to bank select address generator 1700 as timing signal BT5, and select line 1708f provides select signal SEL6 to bank select address generator 1700 as timing signal BT 6.

Bank select address generator 1702 is electrically coupled to fire groups 1704d-1704f via first address lines 1716. Address lines 1716 provide address signals B1, B2 … … B8 from bank select address generator 1702 to the firing cells 120 in each fire group 1704d-1704 f. Also, bank select address generator 1702 is electrically coupled to control lines 1710, which receive control signal CSYNC and provide control signal CSYNC to bank select address generator 1702. In addition, bank select address generator 1702 is electrically coupled to select lines 1708a-1708 f. Select lines 1708a-1708f provide select signals SEL1, SEL2 … … SEL6 to bank select address generator 1702 and corresponding fire groups 1704a-1704 f.

Select line 1708a provides select signal SEL1 to bank select address generator 1702 as timing signal BT 4. Select line 1708b provides select signal SEL2 to bank select address generator 1702 as timing signal BT 5. Select line 1708c provides select signal SEL3 to bank select address generator 1702 as timing signal BT 6. Select line 1708d provides select signal SEL4 to bank select address generator 1702 as timing signal BT 1. Select line 1708e provides a select signal SEL5 to bank select address generator 1702 as timing signal BT2, and select line 1708f provides a select signal SEL6 to bank select address generator 1702 as timing signal BT 3.

In operation, FIRE group one (FG1) at 1704a receives pulses in address signals A1, A2 … … A8, and select signal SEL1 for enabling firing cell 120 to be activated via FIRE signal FIRE 1. FIRE group two (FG2) at 1704b receives pulses in address signals A1, A2 … … A8, and select signal SEL2 for enabling firing cell 120 to be activated by FIRE signal FIRE 2. FIRE group three (FG3) at 1704c receives pulses in address signals A1, A2 … … A8, and select signal SEL3 for enabling firing cell 120 to be activated by FIRE signal FIRE 3.

FIRE group four (FG4) at 1704d receives pulses in address signals B1, B2 … … B8, and select signal SEL4 for enabling firing cell 120 to be activated by FIRE signal FIRE 4. FIRE group five (FG5) at 1704e receives pulses in address signals B1, B2 … … B8, and select signal SEL5 for enabling firing cell 120 to be activated by FIRE signal FIRE 5. FIRE group six (FG6) at 1704f receives pulses in address signals B1, B2 … … B8, and select signal SEL6 for enabling firing cells 120 to be activated by FIRE signal FIRE 6.

Each bank select address generator 1700 and 1702 may be independently enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction. Bank select address generator 1700 may be enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction without enabling bank select address generator 1702, and bank select address generator 1702 may be enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction without enabling bank select address generator 1700. Also, bank select address generator 1700 may be enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction, while bank select address generator 1702 may be enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction.

Valid address signals A1, A2, … … A8 are used to activate the lower bank firing cells 120 in the fire groups FG1, FG2, and FG3 at 1704a-1704 c. Valid address signals B1B 2 … … B8 are used to activate the lower bank firing cells 120 in the fire groups FG4, FG5 and FG6 at 1704d-1704 f.

In one embodiment, the low or high bank firing cells are those firing cells that are connected to the same subgroup select line. In other embodiments, the low or high bank firing cells are physically close to each other. In further embodiments, where lower bank circuitry in bank select address generator 1700 is electrically coupled to different firing cells than higher bank circuitry in bank select address generator 1700, this arrangement may also be used for bank select address generator 1702.

In some embodiments, bank select address generators 1700 and 1702 include a lower bank shift register and lower bank logic, an upper bank shift register and upper bank logic, and a direction circuit in close proximity to each other. In other embodiments, bank select address generators 1700 and 1702 are each divided into two portions, a first portion including a lower bank shift register, lower bank logic circuitry, and direction circuitry, and a second portion including an upper bank shift register, upper bank logic circuitry, and direction circuitry, wherein the first portion and the second portion are not necessarily disposed adjacent to each other but are electrically coupled to each other.

FIG. 20 is a timing diagram illustrating the forward and reverse operation of bank select address generators 1700 and 1702 in printhead die 40. The control signal for forward shift is CSYNC (FWD) at 1824, and the control signal for reverse shift is CSYNC (REV) at 1826. Address signals A1-A8 at 1828 represent the address provided by bank select address generator 1700 and include a forward and reverse operation address reference. Address signals B1-B8 at 1830 are provided by bank select address generator 1702 and include forward and reverse operation address references.

The select signals SEL1, SEL2 … … SEL6 contain a series of six pulses in a repeating series of six pulses. Each select signal SEL1, SEL2 … … SEL6 provides one pulse in the series of six pulses. In one series of six pulses, select signal SEL1 at 1800 includes timing pulse 1802, select signal SEL2 at 1804 includes timing pulse 1806, select signal SEL3 at 1808 includes timing pulse 1810, select signal SEL4 at 1812 includes timing pulse 1814, select signal SEL5 at 1816 includes timing pulse 1818 and select signal SEL6 at 1820 includes timing pulse 1822.

In forward operation, control signal csync (fwd)1824 provides control pulse 1832 that substantially coincides with timing pulse 1806 in select signal SEL2 at 1804. The control pulse 1832 sets the address generator 1702 to shift in the forward direction. Also, control signal CSYNC (FWD)1824 provides control pulse 1834 that substantially coincides with timing pulse 1818 in select signal SEL5 at 1816. The control pulse 1834 sets the address generator 1700 to shift in the forward direction.

In the next series of six pulses, select signal SEL1 at 1800 includes timing pulse 1836, select signal SEL2 at 1804 includes timing pulse 1838, select signal SEL3 at 1808 includes timing pulse 1840, select signal SEL4 at 1812 includes timing pulse 1842, select signal SEL5 at 1816 includes timing pulse 1844 and select signal SEL6 at 1820 includes timing pulse 1846.

Control signals CSYNC (FWD)1824 provide control pulse 1848 that substantially coincides with timing pulse 1838 to continue to set bank select address generator 1702 to shift in the forward direction, and provide control pulse 1850 that substantially coincides with timing pulse 1844 to continue to set bank select address generator 1700 to shift in the forward direction. Also, control signal CSYNC (FWD)1824 provides control pulse 1852 that substantially coincides with timing pulse 1836 in select signal SEL1 at 1800. Control pulse 1852 enables the lower bank shift register in bank select address generator 1700 to generate addresses 1-13 in address signals A1-A8 at 1828. In addition, control signal CSYNC (FWD)1824 provides control pulse 1854 that substantially coincides with timing pulse 1842 in select signal SEL4 at 1812. Control pulse 1854 enables the lower bank shift register in bank select address generator 1702 to generate addresses 1-13 in address signals B1-B8 at 1830.

In the next or third series of six pulses, select signal SEL1 at 1800 includes timing pulse 1856, select signal SEL2 at 1804 includes timing pulse 1858, select signal SEL3 at 1808 includes timing pulse 1860, select signal SEL4 at 1812 includes timing pulse 1862, select signal SEL5 at 1816 includes timing pulse 1864 and select signal SEL6 at 1820 includes timing pulse 1866.

Control signals CSYNC (FWD)1824 provides control pulse 1868 substantially coincident with timing pulse 1858 to continue to set bank select address generator 1702 to shift in the forward direction, and provides control pulse 1870 substantially coincident with timing pulse 1864 to continue to set bank select address generator 1700 to shift in the forward direction.

Bank select address generator 1700 provides lower bank address 1 at 1872 in address signals A1-A8 at 1828. Lower bank address 1 at 1872 becomes valid and remains valid during timing pulse 1846 in select signal SEL6 at 1820 until timing pulse 1862 in select signal SEL4 at 1812. Lower bank address 1 at 1872 is valid during timing pulses 1856, 1858, and 1860 in select signals SEL1, SEL2, and SEL3 at 1800, 1804, and 1808.

Bank select address generator 1702 provides lower bank address 1 at 1874 in address signals B1-B8 at 1830. During timing pulse 1860 in select signal SEL3 at 1808, lower bank address 1 at 1874 becomes valid and remains valid until timing pulse 1876 in select signal SEL1 at 1800. Lower bank address 1 at 1874 is valid during timing pulses 1862, 1864, and 1866 in select signals SEL4, SEL5, and SEL6 at 1812, 1816, and 1820.

Address signals A1-A8 at 1828 and B1-B8 at 1830 provide the same address, i.e., lower bank address 1 at 1872 and 1874. Lower bank address 1 is provided during the series of six timing pulses beginning with timing pulse 1856 and ending with timing pulse 1866, which is the address time slot for lower bank address 1. During the next series of six pulses, beginning with timing pulse 1876, address signals A1-A8 at 1828 provide lower bank address 2 at 1878 and address signals B1-B8 at 1830 provide lower bank address 2. Bank select address generators 1700 and 1702 continue shifting to provide lower bank addresses 1-13, from lower bank address 1 to lower bank address 13 in the forward direction. When lower bank address 13 is provided, lower bank select address generator 1700 and/or bank select address generator 1702 may be enabled to provide lower bank addresses 1-13 or higher bank addresses 14-26 in either the forward or reverse direction.

In this example, when lower bank address 13 is provided at 1880 in address signals A1-A8 at 1828 and lower bank address 13 is provided at 1882 in address signals B1-B8 at 1830, select signal SEL1 at 1800 includes timing pulse 1884, select signal SEL2 at 1804 includes timing pulse 1886, select signal SEL3 at 1808 includes timing pulse 1888, select signal SEL4 at 1812 includes timing pulse 1890, select signal SEL5 at 1816 includes timing pulse 1892, and select signal SEL6 at 1820 includes timing pulse 1894.

Control signals CSYNC (FWD)1824 provide control pulse 1896 substantially coincident with timing pulse 1886 to continue setting bank select address generator 1702 to shift in the forward direction and provide control pulse 1898 substantially coincident with timing pulse 1892 to continue setting bank select address generator 1700 to shift in the forward direction. Also, control signal CSYNC (FWD)1824 provides control pulse 1900 that substantially coincides with timing pulse 1888 in select signal SEL3 at 1808. Control pulse 1900 enables the higher bank shift register in bank select address generator 1700 to generate the higher bank addresses 14-26 in address signals A1-A8 at 1828. In addition, control signal CSYNC (FWD)1824 provides control pulse 1902 that substantially coincides with timing pulse 1894 in select signal SEL6 at 1820. Control pulse 1902 enables the higher bank shift register in bank select address generator 1702 to generate the higher bank addresses 14-26 in address signals B1-B8 at 1830.

In the next series of six pulses, select signal SEL1 at 1800 includes timing pulse 1904, select signal SEL2 at 1804 includes timing pulse 1906, select signal SEL3 at 1808 includes timing pulse 1908, select signal SEL4 at 1812 includes timing pulse 1910, select signal SEL5 at 1816 includes timing pulse 1912 and select signal SEL6 at 1820 includes timing pulse 1914.

Control signals CSYNC (FWD)1824 provide control pulse 1916 substantially coincident with timing pulse 1906 to continue to set bank select address generator 1702 to shift in the forward direction, and provide control pulse 1918 substantially coincident with timing pulse 1912 to continue to set bank select address generator 1700 to shift in the forward direction.

Bank select address generator 1700 provides higher bank address 14 at 1920 of address signals A1-A8 at 1828. Higher bank address 14 at 1920 becomes active during timing pulse 1846 in select signal SEL6 at 1820 and remains active until timing pulse 1910 in select signal SEL4 at 1812. Higher bank address 14 at 1920 is valid during timing pulses 1904, 1906, and 1908 in select signals SEL1, SEL2, and SEL3 at 1800, 1804, and 1808.

Bank select address generator 1702 provides higher bank address 14 in address signals B1-B8 at 1830. Higher bank address 14 at 1922 becomes valid during timing pulse 1908 in select signal SEL3 at 1808 and remains valid until timing pulse 1924 in select signal SEL1 at 1800. Higher bank address 14 at 1922 is valid during timing pulses 1910, 1912 and 1914 in select signals SEL4, SEL5 and SEL6 at 1812, 1816 and 1820.

Address signals A1-A8 at 1828 and B1-B8 at 1830 provide the same address, i.e., higher bank address 14 at 1920 and 1922. Higher bank address 14 is provided during the series of six timing pulses beginning with timing pulse 1904 and ending with timing pulse 1914, which is the address time slot for higher bank address 14. During the next series of six pulses, beginning with timing pulse 1924, address signals A1-A8 at 1828 provide higher bank address 15 at 1926, and address signals B1-B8 at 1830 also provide higher bank address 15. Bank select address generators 1700 and 1702 continue shifting in the forward direction to provide higher bank addresses 14-26, from higher bank address 14 to higher bank address 26.

In reverse operation, during a series of six pulses in one of select signals SEL1, SEL2 … … SEL6, control signal CSYNC (REV)1826 provides a low voltage level at 1930 that substantially coincides with timing pulse 1806 in select signal SEL2 at 1804 to set bank select address generator 1702 to the backward shift. Also, control signal CSYNC (REV)1826 provides a low voltage level at 1932 that substantially coincides with timing pulse 1818 in select signal SEL5 at 1816 to set bank select address generator 1700 to shift in the reverse direction.

During the next series of six pulses, control signal CSYNC (REV)1826 provides a low voltage level at 1934 that substantially coincides with timing pulse 1838 to continue to set bank select address generator 1702 to shift in the reverse direction, and a low voltage level at 1936 that substantially coincides with timing pulse 1844 to continue to set bank select address generator 1700 to shift in the reverse direction. Also, control signal CSYNC (REV)1826 provides control pulse 1938 that substantially coincides with timing pulse 1836 in select signal SEL1 at 1800. Control pulse 1938 enables the lower bank shift register in bank select address generator 1700 to generate lower bank address 13-1 in address signals A1-A8 at 1828. In addition, control signal CSYNC (REV)1826 provides control pulse 1940 that substantially coincides with timing pulse 1842 in select signal SEL4 at 1812. Control pulse 1940 enables the lower bank shift register in bank select address generator 1702 to generate lower bank address 13-1 in address signals B1-B8 at 1830.

In the next or third series of six pulses, control signal CSYNC (REV)1826 provides a low voltage level at 1942 that substantially coincides with timing pulse 1858 to continue to set bank select address generator 1702 to shift in the reverse direction, and provides control pulse 1944 that substantially coincides with timing pulse 1864 to continue to set bank select address generator 1700 to shift in the reverse direction.

Bank select address generator 1700 provides lower bank address 13 at 1872 in address signals A1-A8 at 1828. Lower bank address 13 at 1872 becomes valid during timing pulse 1846 in select signal SEL6 at 1820 and remains valid until timing pulse 1862 in select signal SEL4 at 1812. Lower bank address 13 at 1872 is valid during timing pulses 1856, 1858, and 1860 in select signals SEL1, SEL2, and SEL3 at 1800, 1804, and 1808.

Bank select address generator 1702 provides lower bank address 13 at 1874 in address signals B1-B8 at 1830. During timing pulse 1860 in select signal SEL3 at 1808, lower bank address 13 at 1874 becomes valid and remains valid until timing pulse 1876 in select signal SEL1 at 1800. Lower bank address 13 at 1874 is valid during timing pulses 1862, 1864, and 1866 in select signals SEL4, SEL5, and SEL6 at 1812, 1816, and 1820.

Address signals A1-A8 at 1828 and B1-B8 at 1830 provide the same address, i.e., lower bank address 13 at 1872 and 1874. Lower bank address 13 is provided during the series of six timing pulses beginning with timing pulse 1856 and ending with timing pulse 1866, which is the address time slot for lower bank address 13. During the next series of six pulses, beginning with timing pulse 1876, address signals A1-A8 at 1828 provide lower bank address 12 at 1878, and address signals B1-B8 at 1830 also provide lower bank address 12. Bank select address generators 1700 and 1702 continue shifting to provide lower bank addresses 1-13 from lower bank address 1 to lower bank address 13. When lower bank address 13 is provided, lower bank select address generator 1700 and/or bank select address generator 1702 may be enabled to provide lower bank addresses 1-13 or upper bank addresses 14-26 in either the forward or reverse direction.

In this example, when lower bank address 1 is provided in address signals A1-A8 at 1828 and address signals B1-B8 at 1830, control signal CSYNC (REV)1826 provides a low voltage level at 1946 that substantially coincides with timing pulse 1886 to continue setting bank select address generator 1702 to shift in the reverse direction and a low voltage level at 1948 that substantially coincides with timing pulse 1892 to continue setting bank select address generator 1700 to shift in the reverse direction. Also, control signal CSYNC (REV)1826 provides control pulse 1950 that substantially coincides with timing pulse 1888 in select signal SEL3 at 1808. Control pulse 1950 enables the upper bank shift register in bank select address generator 1700 to generate addresses 26-14 in address signals A1-A8 at 1828. In addition, control signal CSYNC (REV)1826 provides control pulse 1952 that substantially coincides with timing pulse 1894 in select signal SEL6 at 1820. Control pulse 1952 enables the higher bank shift register in bank select address generator 1702 to generate addresses 26-14 in address signals B1-B8 at 1830.

In the next series of six pulses, control signal CSYNC (REV)1826 provides a low voltage level at 1954 that substantially coincides with timing pulse 1906 to continue setting bank select address generator 1702 to shift in the reverse direction, and provides control pulse 1956 at a low level that substantially coincides with timing pulse 1912 to continue setting bank select address generator 1700 to shift in the reverse direction.

Bank select address generator 1700 provides higher bank address 26 at 1920 of address signals A1-A8 at 1828. Higher bank address 26 at 1920 becomes active and remains active until timing pulse 1910 in select signal SEL4 at 1812 during timing pulse 1894 in select signal SEL6 at 1820. Higher bank address 26 at 1920 is valid during timing pulses 1904, 1906, and 1908 in select signals SEL1, SEL2, and SEL3 at 1800, 1804, and 1808.

Bank select address generator 1702 provides higher bank address 26 at 1922 in address signals-B1-B8 at 1830. Higher bank address 26 at 1922 becomes valid during timing pulse 1908 in select signal SEL3 at 1808 and remains valid until timing pulse 1924 in select signal SEL1 at 1800. Higher bank address 26 at 1922 is valid during timing pulses 1910, 1912 and 1914 in select signals SEL4, SEL5 and SEL6 at 1812, 1816 and 1820.

Address signals A1-A8 at 1828 and B1-B8 at 1830 provide the same address, i.e., higher bank address 26 at 1920 and 1922. Higher bank address 26 is provided during the series of six timing pulses beginning with timing pulse 1904 and ending with timing pulse 1914, which is the address time slot for higher bank address 26. During the next series of six pulses, beginning with timing pulse 1924, address signals A1-A8 at 1828 provide higher bank address 25 at 1926, and address signals B1-B8 at 1830 also provide higher bank address 25. Bank select address generators 1700 and 1702 continue shifting to provide higher bank addresses 14-26, from higher bank address 26 to higher bank address 14.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Accordingly, the invention is not to be restricted except in light of the attached claims and their equivalents.

Claims (7)

1. A fluid ejection device, comprising:

the ignition unit comprises a first bank of ignition units and a second bank of ignition units; and

a first address generator configured to selectively provide a first sequence of first address signals adapted to allow activation of firing cells of a first bank and a second sequence of second address signals adapted to allow activation of firing cells of a second bank in response to a control signal, wherein the second sequence of address signals is selectively provided independently of the first sequence of address signals,

wherein the control signal comprises a control pulse and a series of timing pulses, and the first address generator is configured to initiate the first sequence and initiate the second sequence in response to receiving the control pulse substantially coincident with a timing pulse in the series of timing pulses.

2. The fluid ejection device of claim 1, wherein one of the control signals comprises a control pulse, and the first address generator is configured to initiate the first sequence and initiate the second sequence in response to the control pulse.

3. The fluid ejection device of claim 1, wherein the control signal comprises a series of timing pulses, and the first address generator is configured to provide the first address signal and the second address signal in response to the series of timing pulses.

4. The fluid ejection device of claim 1, wherein the control signal comprises a control pulse and a series of timing pulses, and the first address generator is configured to initiate the first sequence in response to receiving a first control pulse of the control pulse that substantially coincides with a first timing pulse of the series of timing pulses.

5. The fluid ejection device of claim 4, wherein the first address generator is configured to initiate the second sequence in response to receiving a second one of the control pulses that substantially coincides with a second one of the series of timing pulses.

6. The fluid ejection device of claim 4, wherein the first address generator further comprises:

a direction circuit configured to set the first direction signal in response to receiving a third one of the control pulses that substantially coincides with a third one of the series of timing pulses.

7. The fluid injection apparatus of claim 1, wherein the firing cells comprise a third bank of firing cells and a fourth bank of firing cells, and the fluid injection apparatus further comprises:

a second address generator configured to selectively provide a third sequence of third address signals and a fourth sequence of fourth address signals in response to the control signal, wherein the third sequence of third address signals is adapted to allow the firing cells of the third bank to activate and the fourth sequence of fourth address signals is adapted to allow the firing cells of the fourth bank to activate, wherein the third sequence of address signals is selectively provided independent of the fourth sequence of address signals.