HK1103168B - Semiconductor structure with improved on resistance and breakdown voltage performance - Google Patents

Description

Semiconductor structure with improved on-resistance and breakdown voltage performance

Technical Field

The present invention relates generally to semiconductor devices, and more particularly to power switch structures and methods of making the same.

Background

MOSFETs, such as lateral Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), are often used in high voltage (i.e. above 200V) applications, such as off-line switching regulators in switching device communication systems or AC-DC voltage converters. In a typical high voltage lateral MOSFET, the source and drain regions are separated by an intermediate region, i.e. the drift region. The gate structure is positioned adjacent to the channel region of the device. In the on state, a voltage is applied to the gate to form a conductive channel region between the source and drain regions to enable current to flow through the device. In the off state, the voltage applied to the gate is sufficiently low so that no conductive channel region is formed and current therefore does not flow. During this off state, the device must withstand high voltages between the source and drain regions.

On-state resistance (R)_ON) Is an important index of the characteristics of the MOSFET switching device. The on-resistance is the ohmic resistance that exists between the input pin and the output pin of the MOSFET switch when the switch is closed and a signal passes. The on-resistance is related to how much signal attenuation the signal will cause as it passes through the device. Another important characteristic measure is the on-resistance (R)_SP) R is_SPIs R_ONProduct of surface area, i.e. R_ONArea x. Smaller R_ONThe x-area enables designers to use smaller high voltage lateral MOSFETs to meet the on-resistance requirements of a given application, which reduces the area and cost of the power integrated circuit.

One problem with conventional high voltage lateral MOSFETs is the tendency for breakdown voltage (V)_BD) Maximized technique and structure pair R_ONWith adverse effects and vice versa. For example, to withstand higher V_BDTypical lateral MOSFETs require lower doping concentrations, which increases the on-state specific resistance (R)_SP)。

To overcome this problem, several designs have been proposed in an attempt to provide high breakdown voltage and low R_ONAcceptable combinations of x areas. For example, devices have been designed with one or more areas of reduced surface field (RESURF) and/or localized doping (also referred to as superjunction structures or multiple conduction structures). These designs require expensive wafer processing, involve multiple masking and ion implantation steps, very deep diffused body regions or contacts (e.g., 30-40 microns deep), and/or expensive silicon-on-insulator substrates, which increase the cost of chip fabrication.

Thus, R for improved lateral MOSFET devices_ONThere is a need for cost-effective structures and methods that can achieve x-area performance while maintaining high blocking voltage capability and manufacturing flexibility.

Disclosure of Invention

According to an aspect of the present invention, there is provided a lateral IGFET device, including: a semiconductor substrate; a drift region of a first conductivity type formed in a portion of the semiconductor substrate; a body region of the second conductivity type formed in the semiconductor substrate adjacent the drift region; a source region of the first conductivity type formed in the body region; a drain contact region of the first conductivity type formed in the drift region; a gate structure formed adjacent to the body region; and a super junction structure formed in the drift region, the super junction structure including a pair of spaced apart filled stripe-shaped trenches, a first stripe-shaped doped region of the first conductivity type and a second stripe-shaped doped region of the second conductivity type between the pair of spaced apart filled stripe-shaped trenches, wherein a doping concentration of the first stripe-shaped doped region is higher than a doping concentration of the drift region, and wherein the first and second stripe-shaped doped regions are not overlapped at all with bottom surfaces of the pair of spaced apart filled stripe-shaped trenches.

According to another aspect of the present invention, there is provided a lateral IGFET device, comprising: a well region of the first conductivity type formed in a portion of the semiconductor substrate of the second conductivity type; a body region of the second conductivity type formed in the semiconductor substrate adjacent the well region; a source region of the first conductivity type formed in the body region; a drain contact region of the first conductivity type formed in the well region; a gate structure formed adjacent to the body region; and a super junction structure formed in the well region, the super junction structure including a pair of spaced apart isolation trenches, a first stripe-shaped doped region of the first conductivity type and a second stripe-shaped doped region of the second conductivity type between the pair of spaced apart isolation trenches, wherein the pair of spaced apart isolation trenches have a bottom surface within the well region, and wherein the first and second stripe-shaped doped regions terminate in the well region without completely overlapping the bottom surface.

According to another aspect of the present invention, there is provided a method for fabricating a lateral IGFET device, comprising the steps of: forming a well region of a first conductivity type in a portion of a semiconductor substrate of a second conductivity type; forming a body region of the second conductivity type in the semiconductor substrate adjacent to the well region; forming a source region of a first conductivity type in the body region; forming a drain contact region of the first conductivity type in the well region; forming a gate structure adjacent to the body region and the well region; forming a pair of spaced apart passivation trenches in the well region; forming a first stripe-shaped doped region of the first conductivity type between the pair of spaced-apart insulation trenches, wherein a doping concentration of the first stripe-shaped doped region is higher than a doping concentration of the well region; and forming a second stripe-shaped doped region of the second conductivity type between the pair of spaced-apart insulation trenches, wherein the first and second stripe-shaped doped regions do not overlap with bottom surfaces of the pair of spaced-apart insulation trenches at all, and wherein the pair of spaced-apart insulation trenches and the first and second stripe-shaped doped regions constitute a super junction structure.

According to another aspect of the present invention, there is provided a method for fabricating a lateral IGFET device, comprising the steps of: forming a first trench in a semiconductor substrate; forming a well region of a first conductivity type in a semiconductor substrate; forming an epitaxial semiconductor region in the first trench; forming a second trench in the epitaxial semiconductor region; forming a first doped region in a sidewall surface of the second trench, wherein the first doped region and the epitaxial semiconductor region have opposite conductivity types, wherein the epitaxial semiconductor region and the first doped region constitute a super junction structure; forming a drain contact adjacent to the super junction structure; forming a body region of the second conductivity type adjacent to the superjunction structure; forming a source region in the body region; and forming a gate structure adjacent to the body region and the well region.

Drawings

Fig. 1 shows a partially enlarged cross-sectional view of a semiconductor device according to the present invention;

fig. 2 illustrates a partially enlarged isometric cross-sectional view of a portion of the semiconductor device of fig. 1 along reference line 1-1 in accordance with a first embodiment of the present invention;

FIG. 3 illustrates an enlarged, fragmentary cross-sectional view of a portion of the semiconductor device of FIG. 1 at an early stage of manufacture;

fig. 4 shows an enlarged, partial isometric cross-sectional view of a portion of the semiconductor device of fig. 1 in accordance with a second embodiment of the present invention;

fig. 5 shows an enlarged, partial isometric cross-sectional view of a portion of the semiconductor device of fig. 1 in accordance with a third embodiment of the present invention;

FIG. 6 shows an enlarged, partial isometric cross-sectional view of a portion of another embodiment of the present invention;

FIG. 7 shows an enlarged, partial isometric cross-sectional view of a portion of another embodiment of the present invention;

FIG. 8 shows an enlarged, partial isometric cross-sectional view of a portion of another embodiment of the present invention;

FIG. 9 shows an enlarged, partial isometric cross-sectional view of a portion of another embodiment of the present invention;

FIG. 10 illustrates an enlarged, partial cross-sectional view of a semiconductor device according to various embodiments of the present invention;

fig. 11 illustrates a partially enlarged isometric cross-sectional view of a portion of the semiconductor device of fig. 10 taken along reference line 2-2 in accordance with the first embodiment;

fig. 12 illustrates a partially enlarged isometric cross-sectional view of a portion of the semiconductor device of fig. 10 along reference line 2-2 in accordance with a second embodiment;

FIGS. 13-18 are enlarged, partial cross-sectional views of a portion of a semiconductor device fabricated in accordance with the method of the present invention at various stages of manufacture;

FIG. 19 is an enlarged partial cross-sectional view of a portion of another semiconductor device fabricated in accordance with an alternative method of fabrication; while

Fig. 20 shows an enlarged partial cross-sectional view of a portion of another semiconductor device in accordance with the present invention.

Detailed Description

For ease of understanding, elements in the figures are not necessarily drawn to scale, and similar reference numerals are used appropriately in all of the figures. For clarity of the drawing, the doped regions of the device structure are shown as generally having straight edges and angularly precise corners. It is understood by those skilled in the art that due to the diffusion and activation of the dopants, the edges of the doped regions are not generally straight lines, and the corners are not generally precise angles, but are typically rounded.

Moreover, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Although these devices are explained herein as certain n-channel devices, it will be understood by those of ordinary skill in the art that p-channel devices as well as complementary devices are also possible in accordance with the present invention by appropriately changing the conductivity type of the regions. The illustrated embodiment is suitable for blocking a voltage of about 700V.

FIG. 1 illustrates a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), i.e., lateral FET, lateral MOSFET, semiconductor or switching device, structure, or cell 10, according to the present invention, the insulated gate field effect transistor 10 having an improved R_ONX area and high blocking voltage capability. MOSFET cell 10 is, for example, one of many such cells integrated in a semiconductor chip as part of a power integrated circuit. Alternatively, the MOSFET cell 10 is a single discrete transistor.

The device 10 comprises a region or substrate 11 of semiconductor material containing, for example, a doping concentration of about 1.5 x 10 per cubic centimeter¹⁴A p-type region of atoms or a substrate. Semiconductor material region 11 includes a major surface 14. The device 10 further includes a well region, i.e., a diffusion region, drift region, or extended drain region 13, which in this embodiment includes n-type conductivity. Well region 13 is formed in substrate 11 and extends from major surface 14. For example, the doping concentration of the well region 13 is about 4.0 × 10 per cubic centimeter¹⁴-1.0×10¹⁶Atomic and have a depth or thickness of about 5-15 microns.

Isolation or field regions 31 are formed on device 10, over device 10, in device 10, or overlapping device 10 to provide localized passivation regions. The isolation region 31 comprises, for example, a localized oxide of silicon (LOCOS) region, a shallow trench isolation region, a field oxide region, combinations thereof, and the like. In one embodiment, isolation region 31 comprises a thermal field oxide region formed by LOCOS techniques to a thickness of about 0.5-2.0 microns.

Device 10 also includes a p-type high voltage region (PHV), a body or diffusion region 41, and an n-type source region 43 extending from major surface 14. The body region 43 extends partially into the semiconductor material region 11. p-type doped region 44 is further formed within body region 41 and serves to reduce parasitic effects, etc. within device 10. A drain contact region 33 is formed in part of well region 13 and extends from major surface 14. The drain contact region 33 comprises n-type conductivity and is doped to provide a sufficient ohmic structure. Regions 13, 33, 41, 43, and 44 are formed using conventional masking and doping techniques.

Gate structure 46, including thin gate dielectric layer 53 and gate electrode 51, is formed adjacent to or overlapping portions of major surface 14 and body region 41. The gate dielectric layer 53 comprises, for example, silicon oxide having a thickness of about 0.01-0.1 microns. Alternatively, the gate dielectric layer 53 comprises other dielectrics such as silicon nitride, tantalum pentoxide, titanium dioxide, barium strontium titanate, or combinations thereof including combinations with silicon oxide. The gate electrode 51 comprises, for example, doped polysilicon, aluminum alloys, combinations thereof, and the like. Gate structure 46 controls the formation of channel 58 and the conduction of current in device 10.

In accordance with the present invention, device 10 also includes an area, or superjunction structure 61, that includes a pair or plurality of spaced-apart filled trenches, passivated trenches, or filled stripe-shaped trenches or recesses that at least partially (e.g., on both sides) bound or define a plurality of stripe-shaped doped regions of opposite or alternating conductivity type formed within portions of well region 13.

In one embodiment, the filled stripe-shaped trenches and the stripe-shaped doped regions are substantially parallel to each other. Region 61 provides device 10 with low on-resistance in a very small surface area while maintaining a high breakdown voltage. The regions 61 are separated from the body region 41 by a distance, for example, about 1-4 microns. Various embodiments of region 61 are described below in conjunction with fig. 2-9.

Fig. 2 shows an enlarged, partial isometric cross-sectional view of a portion of device 10 taken along reference line 1-1 in fig. 1 to illustrate a first embodiment of region 61. In the present embodiment, the region 61 comprises a plurality of filled trenches defining a plurality of stripe-shaped doped regions 64 and 66. Specifically, doped stripe regions 64 comprise the first conductivity type and are sandwiched between stripe-shaped doped regions 66, each of the second conductivity type. According to this embodiment of the invention, regions 64 and 66 extend along the sidewalls in the depth direction of trench 23, but these regions do not overlap the bottom or bottom wall of trench 23. That is, regions 64 and 66 generally terminate along sidewall portions of trench 23 and these regions do not engage or connect with the bottom surface of trench 23. The depth of regions 64 and 66 is approximately equal to the depth of trench 23. In the present embodiment, the stripe-shaped regions 64 comprise the same conductivity type as the well region 13, but with a higher doping concentration. For example, the net peak doping concentration of region 64 is about 1.0 x 10 per cubic centimeter¹⁶-3.0×10¹⁶Atomic, and region 66 has a net peak doping concentration of about 1.0 x 10 per cubic centimeter¹⁶-3.0×10¹⁶An atom.

Fig. 3 shows a partial cross-sectional view of a portion of device 10 to illustrate the formation of stripe-shaped doped regions or regions 64 and 66. In this embodiment, trench 23 is first etched from major surface 14 of device 10 into well region 13. In one embodiment, the trenches 23 are separated by a distance of about 2-7 microns, depending on the desired RESURF charge requirement. The depth of trench 23 depends on the voltage rating of device 10. For example, for R_ONX 60 ohms x square centimeter in area and a breakdown voltage of about 700V, trench 23 is about 8-10 microns deep and about 1-2 microns wide. To meet the breakdown of 700V, the drift length is about60 microns. These trenches 23 are formed using conventional photolithography and etching techniques. The trench 23 is etched, for example, with a dry etch technique using fluorine or chlorine based chemistries.

Next, a dielectric layer or passivation region 230 is formed at the bottom of trench 23. For example, the surface of the trench 23 is first covered with a nitride or masking layer, and subsequently the bottom portion is removed with an anisotropic etching technique so as to expose a portion of the well region 13. The exposed portions are then oxidized to form localized passivation regions 230, as shown at the bottom surface of trenches 23. Region 230 provides a mask or protective layer to prevent regions 64 and 66 from forming along the bottom surface of trench 23. For example, the thickness of regions 230 may each be about 0.3-0.5 microns.

Then, a dopant of the first conductivity type (e.g., n-type) is introduced into the sidewall surface of the trench 23. For example, tilted ion implantation, gas phase doping, or solid source doping, is used to introduce the doping particles into the well region 13. Fig. 3 shows a tilted implantation process as an example, wherein the arrows 4 represent a simplified approximate trajectory of dopant ions. Masking layer 16 prevents dopant ions from reaching major surface 14. In one embodiment, dopants of the first conductivity type are then diffused into well region 13 during the thermal treatment, thereby forming first conductivity type regions 64. For example, the first conductive type dopant is diffused at 1200 ℃ for about 30 minutes.

Next, a dopant of the second conductivity type (e.g., p-type) is introduced into the sidewall surface of the trench 23 (e.g., angled ion implantation, gas phase doping, or solid source doping), and then diffused into the well region 13 in a thermal process, thereby providing a second conductivity type region 66 shown in fig. 2. In one embodiment, the first conductivity type dopants introduced from adjacent trenches 23 diffuse together to form the connection or junction region 64 shown in fig. 2.

By first diffusing dopants of the first conductivity type and subsequently diffusing dopants of the second conductivity type into the first conductivity type region through the sidewall surfaces of the trench 23, fully controlled n-type and p-type regions along the depth direction and length of the drift region are obtained. Furthermore, by locating region 64 between well region 13 and region 66, proper charge balance is achieved and improved breakdown voltage characteristics are achieved. Region 64 provides a conductive path or path for current flow during on-state operation. During off-state operation, regions 64 and 66 compensate each other, thereby enhancing breakdown voltage capability.

In a subsequent step, the trenches 23 are filled with a material or dielectric material 24 such as an oxide (e.g., a thermal oxide, a deposited oxide, or a spin-on oxide), a nitride, a semi-insulating polysilicon (SIPOS), an undoped polycrystalline semiconductor material (e.g., polysilicon), combinations thereof, or the like. This provides a superjunction structure 61 within the first conductivity type (e.g., n-type) well region having a plurality (e.g., a pair) of filled trenches partially (e.g., on both sides) defining second conductivity type (e.g., p-type) doped stripe regions, first conductivity type (e.g., n-type) doped stripe regions, and second conductivity type (e.g., p-type) doped stripe regions. According to this embodiment of the invention, the second conductivity type region and the first conductivity type region are completely non-overlapping, non-surrounding, non-connected with the bottom surface of the filled trench. In one embodiment, the first and second conductivity type regions and the filled trench terminate at substantially equal depths in the drift region. In one embodiment, the fill material fills the trench 23 up to or beyond the major surface 14.

Simulation analysis of device 10 showed that it was able to block voltages higher than 700V while obtaining an R of less than 60 ohms x cm_ONResults are area.

Fig. 4 shows a partially enlarged isometric cross-sectional view of a portion of device 10 taken along reference line 1-1 in fig. 1 to illustrate a second embodiment of region 61. In this second embodiment, the order of regions 64 and 66 is reversed compared to the first embodiment of fig. 2. In the present embodiment, first, the second conductivity type region 66 is introduced into the sidewall surface of the trench 23, followed by the first conductivity type region 64 being introduced into the sidewall surface. This provides a superjunction structure 61 within the drift region of the first conductivity type (e.g., n-type) having a plurality (e.g., a pair) of filled trenches partially (e.g., on both sides) defining stripe regions of the first conductivity type (e.g., n-type) doping, stripe regions of the second conductivity type (e.g., p-type) doping, and stripe regions of the first conductivity type (e.g., n-type) doping. According to this embodiment of the invention, the second conductivity type region and the first conductivity type region are completely non-overlapping, non-surrounding, non-connected with the bottom surface of the filled trench. In one embodiment, the first and second conductivity type regions and the filled trench terminate at substantially equal depths in the drift region.

Fig. 5 shows a partially enlarged isometric cross-sectional view of a portion of a device 10 according to a third embodiment of the present invention. In this embodiment, the first conductive type region 64 is introduced into one sidewall of the trench 23, and the second conductive type region 66 is introduced into the other sidewall of the trench 23. This provides a single-sided superjunction structure 61 in which first doped stripe regions (e.g., regions 64) are formed to engage or connect one of a pair of stripe-shaped filled trenches, and in which second doped stripe regions (e.g., regions 66) are formed to engage or connect the other of a pair of stripe-shaped filled trenches, and in which the first doped stripe regions engage the second doped stripe regions. According to this embodiment of the invention, the second conductivity type region and the first conductivity type region are completely non-overlapping, non-surrounding, non-connected with the bottom surface of the filled trench. In one embodiment, the first and second conductivity type regions and the filled trench terminate at substantially equal depths in the drift region.

Fig. 6 shows a partially enlarged, isometric cross-sectional view of a portion of another embodiment of device 10. In this embodiment, an insulating layer or dielectric region 71 is formed in substrate 11 and engages or is adjacent to the bottom surface, i.e., lower surface, of trench 23. In this embodiment, the insulating layer 71 separates the substrate 11 from the semiconductor layer 111. As shown, region 61 is formed in semiconductor layer 111, and insulating layer 71 extends beyond well region 13 under body region 41. Although the region 61 embodiment of fig. 2 is shown, it is understood that any of the region 61 embodiments shown herein, for example, may be used with insulating layer 71. The insulating layer 71 comprises oxide and is approximately 3-4 microns thick, for example, and is formed by high energy ion implantation or other growth or deposition techniques. Or an SOI substrate is used.

Fig. 7 illustrates a partially enlarged isometric cross-sectional view of a portion of another embodiment of device 10. In this embodiment, a localized insulating layer or localized dielectric region 171 separates the bottom of region 61 from well region 13. Specifically, the insulating layer 171 is formed or confined within the well region 13 and is formed using an etch/epitaxial growth refill technique or an energetic ion implantation technique.

Fig. 8 shows an enlarged, partial isometric cross-sectional view of a portion of another embodiment of device 10. In this embodiment, a localized passivation region or localized dielectric region 271 is adjacent the bottom surface of each trench down in the lateral direction of the trench 23. In this embodiment, portions of well region 13 laterally separate adjacent localized passivation regions 271. For example, after forming trench 23, an isotropic etch is used to form region 271, which forms a cavity under trench 23. The cavity is then oxidized. In one embodiment, region 271 is confined or formed within well region 13. In addition, other embodiments include only a portion of the trench 23 having a localized passivation region 271 adjacent thereto.

Fig. 9 shows a partially enlarged isometric cross-sectional view of a portion of another embodiment of the device 100 of the present invention. Device 100 is similar to device 10 except that a trench gate structure 105 on the side of body region 41 facing region 61 is added as shown. In this embodiment, well region 113 extends under the active devices including body region 41 and trench-gate structure 105. The trench gate structure 105 includes a gate dielectric layer 106 and a conductive electrode 107 formed overlying the gate dielectric layer 106. The gate dielectric layer comprises the same material as gate dielectric layer 53 or other materials. Trench gate structure 105 provides a vertical channel 158 or the like to help minimize current crowding at the surface in channel 58. This further provides for a more optimal use of the region 61. In the illustrated embodiment, superjunction region 61 of fig. 2 is provided as an example. It is understood that other superjunction embodiments shown herein may be combined with trench-gate structure 105.

FIG. 10 illustrates a partial cross-sectional view of an Insulated Gate Field Effect Transistor (IGFET), i.e., a lateral FET, a lateral MOSFET, semiconductor or switching device, structure, or cell 210, according to another embodiment of the present invention, the insulated gate field effect transistor 210 having an improved R_ONX area performance and high blocking voltage capability. MOSFET cell 210 is one of many such cells integrated in a semiconductor chip as part of a power integrated circuit, for example. Alternatively, the MOSFET cell 210 is a single discrete transistor.

Device 210 is similar to device 10, except that drift region or extended drain region 213 comprises an epitaxial layer formed on substrate 11, or comprises a diffusion well region extending below body region 41, as shown in fig. 10. Alternatively, when region 213 comprises a diffusion region or well, it terminates below body region 41 or as shown in fig. 1 as region 13. One benefit of using epitaxial growth to form region 213 is that it provides a thicker layer or region and has a more controlled doping concentration profile than a diffusion well or region. With thicker regions and controlled concentration one can use deeper trenches, which provides lower on-resistance. For example, the substrate 11 includes a doping concentration of about 1.5 x 10 per cubic centimeter¹⁴A p-type substrate of atoms. And the charge concentration of region 213 under the superjunction structure is about 0.2 x 10 per square centimeter¹²-1.0×10¹²An atom.

In accordance with this embodiment of the present invention, device 210 further includes a region or superjunction structure 261 that includes a pair or plurality of spaced-apart filled trenches or filled stripe-shaped trenches or recesses that partially define a plurality of stripe-shaped doped regions of opposite or alternating conductivity types formed between and within portions of well region 213 surrounding each filled trench. In one embodiment, the filled trenches and the stripe-shaped doped regions are substantially parallel to each other. Region 261 provides device 210, etc., with low on-resistance while maintaining a high breakdown voltage. Various embodiments of region 261 are described below in conjunction with fig. 11 and 12.

Fig. 11 shows a partially enlarged isometric cross-sectional view of a portion of semiconductor device 210 along reference line 2-2 to illustrate a first embodiment of a region 261 in accordance with the present invention. In this implementation, region 261 includes a plurality of trenches 223 formed within region 213 and extending in region 213. Trenches 223 are spaced apart and extend laterally between regions 41 and 33, typically to a depth less than or equal to the depth or thickness of region 213. Drain contact region 33 is one side of superjunction region 261 and body region 41 is on the opposite side of superjunction region 261. A first conductivity type, n-type region 264 is formed in region 213 by the sidewalls and bottom surface, i.e., lower surface, of trench 223 and a second conductivity type, p-type region 266 is formed in region 213 by the same sidewalls and bottom surface, i.e., lower surface. In this embodiment, regions 264 and 266 surround trench 223, completely overlap trench 223, or are formed around trench 223, with region 264 terminating at a depth less than the depth of region 213. That is, the region 264 is separated from the substrate 11. Further, regions 264 and 266 are along the depth and length of drift region 213. For example, the peak doping concentration of both n-type region 264 and p-type region 266 is about 1.0 x 10 per cubic centimeter¹⁶-3.0×10¹⁶An atom.

Regions 264 and 266 are formed, for example, by angled ion implantation, gas phase doping, or solid source doping. As another example, the dosage is about 2.0X 10 per square centimeter¹³-5.0×10¹³Angled ion implantation of atoms forms regions 264 and 266. As another example, when the distance between adjacent trenches is about 5-7 microns, the dose is about 2.5X 10 per square centimeter¹³-4.5×10¹³Angled ion implantation of atoms forms regions 264 and 266. In one example, region 264 is diffused at about 1200 c for about 30 minutes after ion implantation. The ion implantation step at 266 is then complete and region 266 may be diffused simultaneously with body region 41.

Regions 264 and 266 form a self-compensated superjunction structure around trenches 223 and serve to minimize the effects of charge, etc. from portions of region 213 between trenches 223 and below trenches 223. Also, since regions 264 and 266 overlap the bottom surface of trench 223, additional current paths are provided as well as current paths along the sidewalls of trench 223, which reduces on-resistance. Furthermore, since the doping concentration of region 213 is much less than that of region 264, premature breakdown issues typically occurring between n-type well regions and p-type bodies are reduced.

In a subsequent step, the trench 223 is filled with a material or dielectric material 224 such as an oxide (e.g., a thermal oxide, a deposited oxide, or a spin-on oxide), a nitride, a semi-insulating polysilicon (SIPOS), an undoped polycrystalline semiconductor material (e.g., polysilicon), combinations thereof, or the like.

Fig. 12 shows a partially enlarged isometric cross-sectional view of a portion of semiconductor device 210 along reference line 2-2 to illustrate a second embodiment of region 261 in accordance with the present invention. In this embodiment, region 264 is diffused so as to extend through region 213 to contact substrate 11 and/or merge with the adjoining region 264.

As further shown in fig. 9, the device 210 shown in fig. 11 and 12 may further incorporate the trench-gate structure 105 shown in fig. 9 with the location of the modified regions 43 and 44. Furthermore, in both embodiments shown, region 261 is separated from bulk region 41. For example, regions 261 are separated by a distance of about 1-4 microns.

An alternative method for forming a superjunction device of the present invention will now be described with reference to fig. 13-19. Fig. 13 shows a partial cross-sectional view of substrate 11 in an early step of fabrication. In this embodiment, the substrate 11 comprises p-type conductivity. Next, a trench or recess 323 is etched in substrate 11, extending from major surface 14. Conventional masking and etching techniques are used for this step.

Fig. 14 shows the substrate 11 at the time of additional processing, wherein the well region 13 is formed in the substrate 11 by the surface of the trench 323. For example, n-type dopants are implanted into the surface and diffused to a desired depth. Or gas phase doping or solid source doping techniques.

Fig. 15 shows the substrate 11 after further processing. In this stage, epitaxial growth/etch-back or selective epitaxial growth techniques are used to form n-type stripe regions or n-type epitaxial regions 364 filling the trenches 323. Next, a second trench 423 is formed in the substrate 11 within the epitaxial region 364. In one embodiment, each trench 423 extends through region 364 so as to expose a portion of well region 13. In an alternative embodiment, which is explained in more detail below, the grooves 423 do not extend all the way through the region 364. Next, as described in connection with fig. 3, a localized passivation region 231 is formed at the bottom surface or lower surface of the trench 423 shown in fig. 16.

Fig. 17 shows the substrate 11 after further processing, wherein p-type stripe regions 366 are formed in the sidewalls of the trenches 423. Region 231 masks the dopants at the bottom or lower surface of trench 423. For example, angled ion implantation is used to form region 366. Or gas phase doping or solid source doping techniques. In a further step, as shown in fig. 18, trenches 223 are filled with an oxide (e.g., thermal oxide, deposited oxide, or spin-on oxide), a nitride, semi-insulating polysilicon (SIPOS), undoped polycrystalline semiconductor material (e.g., polysilicon), combinations thereof, or the like, to provide a superjunction structure in which n-type region 364 and p-type region 365 do not overlap trench 423 at all. Region 231 is left in place or removed prior to filling trench 423. In an alternative embodiment, the regions 364 are merged together in the well region 13.

Fig. 19 shows a cross-sectional view of an alternative embodiment in which a trench 523 is formed in the epitaxial region 364, but does not extend all the way through the region 364. p-type dopants are introduced into the sidewalls and bottom or lower surface of trench 523 to provide a superjunction structure in which n-type region 364 and p-type region 366 trench 523 completely overlap. In a subsequent step, the trench 523 is filled with material 424. In an alternative embodiment, the various regions 364 are merged together within well region 13.

Fig. 20 shows a cross-sectional view of superjunction structure 361 according to another embodiment of the invention, used in place of structure 61 in device 10 or structure 261 in device 210. Structure 361 includes a plurality of filled trenches 623 formed in drift, well, or epi region 213. The filled trenches 623 each include a filled portion of the trench 623 or an n-type doped region 364 formed on the sidewall and lower surface of the trench 623 and a p-type doped region 566 formed on the region 364. In one embodiment, the region 566 fills the remainder of the fill trench 623. Structure 361 is formed, for example, using the etch/epitaxial growth method described in connection with fig. 13-15. Additional trenches are then formed in each region 364 and a p-type epitaxial layer is formed over the structure, removing any excess material to provide the regions 566 and the final structure 361 shown in fig. 20.

Thus, it is apparent that there has been provided in accordance with the present invention a lateral FET structure having improved blocking voltage and on-resistance performance. This structure combines a superjunction structure that includes a plurality (at least one pair) of spaced-apart filled trenches or filled stripe-shaped trenches or recesses at least partially bounding or defining a plurality of stripe-shaped doped regions of opposite or alternating conductivity type formed in the well region or drift region.

While the invention has been described with reference to specific embodiments thereof, the invention is not to be considered as being limited to these illustrative embodiments. For example, more filled trenches may be employed including trenches having rounded corners or rounded bottom surfaces. Alternatively, combinations of the disclosed fill materials may be employed, including oxide/nitride, oxide/SIPOS, oxide/polysilicon, oxide/nitride/oxide, combinations thereof, and the like. It will be understood by those skilled in the art that various modifications and changes can be made without departing from the spirit of the invention. It is therefore intended to cover in the appended claims all such changes and modifications that are within the scope of this invention.

Claims (10)

1. A lateral IGFET device, comprising:

a semiconductor substrate;

a drift region of the first conductivity type formed in a portion of the semiconductor substrate, wherein the semiconductor substrate and the drift region are in physical contact and there is no intervening insulating layer therebetween;

a body region of the second conductivity type formed in the semiconductor substrate adjacent the drift region;

a source region of the first conductivity type formed in the body region;

a drain contact region of a first conductivity type formed in the drift region for providing a lateral IGFET device configuration;

a gate structure formed adjacent to the body region; and

a superjunction structure formed in and laterally spaced from the body region in a drift region such that a portion of the drift region is located between the superjunction structure and the body region, the superjunction structure comprising a pair of spaced apart filled stripe-shaped trenches, a first stripe-shaped doped region of a first conductivity type and a second stripe-shaped doped region of a second conductivity type between the pair of spaced apart filled stripe-shaped trenches, wherein a doping concentration of the first stripe-shaped doped region is higher than a doping concentration of the drift region, the pair of spaced apart filled stripe-shaped trenches terminating in the drift region such that another portion of the drift region is located between the substrate and a lower surface of the pair of spaced apart filled stripe-shaped trenches, and wherein the first and second stripe-shaped doped regions do not overlap at all with the lower surface of the pair of spaced apart filled stripe-shaped trenches.

2. The device of claim 1, further comprising a trench-gate structure formed adjacent to the body region.

3. The device of claim 1, wherein the first strip-shaped doped region is formed adjacent one of the pair of strip-shaped filled trenches and the second strip-shaped doped region is formed adjacent the other of the pair of strip-shaped filled trenches, and wherein the first strip-shaped doped region is adjacent the second strip-shaped doped region.

4. A lateral IGFET device, comprising:

a well region of the first conductivity type formed in a portion of the semiconductor substrate of the second conductivity type;

a body region of the second conductivity type formed in the semiconductor substrate adjacent the well region;

a source region of the first conductivity type formed in the body region;

a drain contact region of the first conductivity type formed in the well region;

a gate structure formed adjacent to the body region; and

a superjunction structure formed in the well region and laterally spaced apart from the body region such that a portion of the well region is located between the superjunction structure and the body region, the superjunction structure comprising:

a pair of spaced apart isolation trenches, wherein the pair of spaced apart isolation trenches have lower surfaces terminating in the well region;

a first localized dielectric region restrictively formed along a lower surface of the first insulation trench;

a second localized dielectric region separate and distinct from the first localized dielectric region and restrictively formed along a lower surface of the second isolation trench, wherein the first and second localized dielectric regions are restricted in a portion of the well region and are separated from the semiconductor substrate by another portion of the well region;

a first stripe-shaped doped region of the first conductivity type formed between the pair of spaced-apart isolation trenches; and

a second strip-shaped doped region of the second conductivity type formed between the pair of spaced-apart isolation trenches, wherein the first and second strip-shaped doped regions terminate in the well region without completely overlapping lower surfaces of the first and second isolation trenches.

5. The device of claim 4, further comprising a third strip-shaped doped region of the first conductivity type between the pair of spaced-apart isolation trenches, wherein the third strip-shaped doped region terminates in the well region without completely overlapping lower surfaces of the first and second isolation trenches.

6. A method for fabricating a lateral IGFET device, comprising the steps of:

forming a well region of a first conductivity type in a portion of a semiconductor substrate of a second conductivity type, wherein the semiconductor substrate and the well region are in physical contact without an intervening insulating layer therebetween;

forming a body region of the second conductivity type in the semiconductor substrate adjacent to the well region;

forming a source region of a first conductivity type in the body region;

forming, in the well region, a drain contact region of the first conductivity type to provide a lateral IGFET device configuration;

forming a gate structure adjacent to the body region and the well region;

forming a pair of spaced-apart isolation trenches in the well region laterally spaced apart from the body region such that a portion of the well region is between the pair of spaced-apart isolation trenches and the body region, and each isolation trench has a lower surface terminating in the well region;

forming a first stripe-shaped doped region of the first conductivity type between the pair of spaced-apart insulation trenches, wherein a doping concentration of the first stripe-shaped doped region is higher than a doping concentration of the well region; and

and forming a second strip-shaped doped region of the second conductivity type between the pair of spaced-apart insulation trenches, wherein the first and second strip-shaped doped regions do not overlap with lower surfaces of the pair of spaced-apart insulation trenches at all, and wherein the pair of spaced-apart insulation trenches and the first and second strip-shaped doped regions constitute a super junction structure.

7. The method of claim 6, further comprising the step of forming a third strip-shaped doped region between the pair of spaced-apart isolation trenches.

8. The method of claim 6, further comprising the step of forming a trench gate structure adjacent the body region.

9. The method of claim 6, further comprising the step of forming a dielectric layer in the semiconductor substrate adjacent the lower surface of the pair of spaced apart isolation trenches.

10. A method for fabricating a lateral IGFET device, comprising the steps of:

providing a semiconductor substrate having a well region of a first conductivity type and a first trench, wherein the first trench is located in the well region;

forming an epitaxial semiconductor region in the first trench;

forming a second trench in the epitaxial semiconductor region;

forming a first doped region in a sidewall surface of the second trench, wherein the first doped region and the epitaxial semiconductor region have opposite conductivity types, wherein the epitaxial semiconductor region and the first doped region constitute a super junction structure;

forming a drain contact adjacent to the super junction structure;

forming a body region of the second conductivity type adjacent the superjunction structure, the superjunction structure being laterally spaced from the body region such that a portion of the well region is located between the superjunction structure and the body region;

forming a source region in the body region; and

a gate structure is formed adjacent to the body region and the well region.