HK1103165A - Dmosfet and planar type mosfet - Google Patents

Description

DMOSFET and planar MOSFET

Technical Field

The present invention relates to a power MOSFET (metal oxide semiconductor-field effect transistor), and more particularly, to a structure suitable for realizing a low on-resistance and a low feedback capacitance in a low withstand voltage power MOSFET having a withstand voltage of about 100V or less and a method for manufacturing the same, and further, to a technique suitable and effective for a power supply device using the power MOSFET.

Background

For example, in a non-insulated DC/DC converter used in a power supply device such as a desktop PC, a notebook PC, or a game machine, a large current and a high frequency tend to be generated in accordance with a demand for a large current for a CPU (central processing unit) or an MPU (micro processing unit) to be driven, a reduction in size of a choke coil or an input/output capacitor as a passive component, or the like. The DC/DC converter is configured by a high-side switch and a low-side switch, and power MOSFETs are used for these switches.

These switches perform voltage conversion by alternately turning on/off the high side and the low side while synchronizing them. The high-side switch is a control switch of the DC/DC converter, and the low-side switch is a synchronous rectification switch.

Regarding the loss in the high-side switch, the switching loss occurring at the time of switching is a main loss, and it is required to reduce the feedback capacitance (Crss) while reducing the on-resistance (Ron) for the power MOSFET used for the high-side switch. Further, with respect to the loss in the low-side switch, the conduction loss is the dominant loss, and a reduction in the on-resistance (Ron) is required for the power MOSFET for the low-side switch.

In addition, the DC/DC converter described above has a problem called a self-conduction phenomenon. Self-conduction is a phenomenon in which: when the high-side switch is turned on while the low-side switch is turned off, the drain voltage of the low-side switch rises, and a charging current flows between the gate and the source of the low-side switch through a feedback capacitor between the gate and the drain of the low-side switch in accordance with the voltage change, so that the gate voltage of the low-side switch rises and exceeds a threshold voltage, thereby erroneously turning on the low-side switch. If self-conduction occurs, a large through current flows from the high-side switch to the low-side switch, and the conversion efficiency is greatly reduced. Since the gate voltage rise of the low-side switch is proportional to the ratio of the feedback capacitance to the input capacitance (Crss/Ciss) of the low-side switch, it is desirable to reduce the on-resistance of the low-side switch while also reducing the Crss/Ciss.

In the current DC/DC converter, since the operating frequency is about 300kHz and is not too high, power MOSFETs having trench structures are mainly used for both the high-side switch and the low-side switch. Since the trench power MOSFET can reduce the cell size without occurrence of a resistance component of a JFET (junction field effect transistor), a low on-resistance can be achieved. However, since the trench power MOSFET has a large feedback capacitance, there is a problem that switching loss, loss due to self-conduction, and the like become large as the frequency of the DC/DC converter increases.

As a power MOSFET for reducing the feedback capacitance, there is a planar MOSFET. However, in the planar MOSFET, since a JFET resistance component exists, it is difficult to reduce the cell size and to reduce the on-resistance.

For example, patent document 1 proposes a structure in which a JFET region is narrowed and a cell size is reduced to realize a low on-resistance by providing an N-type region having a higher concentration than a drift layer in the JFET region between channels of a planar MOSFET.

[ patent document 1 ] Japanese patent application laid-open No. 2003-298052

However, in the planar MOSFET of patent document 1, miniaturization of the cell size is insufficient, and the on-resistance is still higher than that of the trench MOSFET, and it is necessary to investigate how to further reduce the on-resistance. In addition, in the planar MOSFET, it is known that the channel layer may be shallow in order to reduce the on-resistance without being affected by the JFET resistance component, but in the planar MOSFET of patent document 1, the depth of the channel layer is about 0.8 μm, and the shallow junction is not sufficiently studied. Further, if the channel layer is made shallow, dispersion of the channel in the lateral direction is also reduced, and therefore, there is a problem that the channel layer penetrates and the withstand voltage is lowered in the structure of the planar MOSFET. Therefore, no study has been made on a planar MOSFET having a shallow trench layer with a channel depth of 0.5 μm or less, for example.

Disclosure of Invention

Accordingly, an object of the present invention is to provide a technique for a planar MOSFET that can prevent punch-through of a channel layer and realize a MOSFET having low on-resistance and low feedback capacitance even when the channel layer is shallow.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

The outline of a representative invention among the inventions disclosed in the present application will be briefly described as follows.

The present invention has the following features in order to realize low on-resistance and low feedback capacitance in a planar MOSFET, to shallow-junction a channel layer to 0.5 μm or less, and to prevent punch-through of the channel layer after dispersion in the lateral direction is reduced.

(1) In an N-channel DMOSFET (double diffused MOSFET), a P-type polysilicon electrode is used as a gate electrode.

(2) A shallow N-type layer such as an LDD (lightly doped drain) region of a CMOSFET is provided in a source region, and the source region is formed into a secondary structure.

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described below.

According to the present invention, in the planar MOSFET, the through-hole of the channel layer can be prevented even if the channel layer is shallowly connected, and therefore, a MOSFET having a low on-resistance and a low feedback capacitance can be realized.

Further, according to the present invention, the planar MOSFET is used for the high-side switch and the low-side switch of the DC/DC converter, whereby the loss of the system can be reduced.

Drawings

Fig. 1 shows a cross-sectional structure of a planar MOSFET according to embodiment 1 of the present invention.

Fig. 2 shows an example of each size of the planar MOSFET according to embodiment 1 of the present invention.

Fig. 3(a) and (b) show the difference in the energy bands of the gate electrode, the gate insulating film, and the channel layer in the thermal equilibrium state when the polysilicon of the gate electrode has different polarities in embodiment 1 of the present invention.

Fig. 4 shows the calculation results of the impurity concentration distribution on the section a-a' in fig. 1 in embodiment 1 of the present invention and the hole concentration distribution when Vds is 0V in the case of using N-type polycrystalline silicon or P-type polycrystalline silicon.

Fig. 5 shows the calculation results of the drain-source withstand voltage when the polysilicon of the gate electrode has different polarities in embodiment 1 of the present invention.

Fig. 6(a) and (b) show two-dimensional distributions of equipotential lines when a voltage of 20V is applied between the drain and the source in the case where the polysilicon of the gate electrode has different polarities in embodiment 1 of the present invention.

Fig. 7 shows the calculation results of the length of the JFET region and the on-resistance per unit area in embodiment 1 of the present invention.

Fig. 8(a) to (c) show a method for manufacturing a planar MOSFET according to embodiment 1 of the present invention.

Fig. 9(d) to (f) show a method for manufacturing the planar MOSFET according to embodiment 1 of the present invention.

Fig. 10(g) to (i) show a method for manufacturing a planar MOSFET according to embodiment 1 of the present invention.

Fig. 11(j) to (l) show a method for manufacturing a planar MOSFET according to embodiment 1 of the present invention.

Fig. 12(m) and (n) show a method for manufacturing a planar MOSFET according to embodiment 1 of the present invention.

Fig. 13 shows a cross-sectional structure of a planar MOSFET according to embodiment 2 of the present invention.

Fig. 14 shows a cross-sectional structure of a planar MOSFET according to embodiment 3 of the present invention.

Fig. 15 shows a cross-sectional structure of a planar MOSFET according to embodiment 4 of the present invention.

Fig. 16 shows a cross-sectional structure of a planar MOSFET according to embodiment 4 of the present invention.

Fig. 17 shows a cross-sectional structure of a planar MOSFET according to embodiment 5 of the present invention.

Fig. 18 shows a cross-sectional structure of a planar MOSFET according to embodiment 6 of the present invention.

Fig. 19 shows a cross-sectional structure of a planar MOSFET according to embodiment 7 of the present invention.

Fig. 20 shows a cross-sectional structure of a planar MOSFET according to embodiment 8 of the present invention.

Fig. 21 shows a cross-sectional structure of a planar MOSFET according to embodiment 9 of the present invention.

Fig. 22 shows the calculation results of the drain-source breakdown voltage in each structure according to embodiment 9 of the present invention.

Fig. 23(a) and (b) show two-dimensional distributions of equipotential lines in embodiment 9 of the present invention when a voltage of 20V is applied between the drain and source of the conventional planar MOSFET and the planar MOSFET of the present embodiment.

Fig. 24 shows a circuit configuration of a non-insulated DC/DC converter included in the power supply device according to embodiment 10 of the present invention.

Fig. 25 shows the calculation results of the drain voltage dependence of the feedback capacitances of the conventional trench MOSFET and the planar MOSFET of the present invention in embodiment 10 of the present invention.

Fig. 26 shows the calculation result of the gate voltage of the low-side switch when the conventional trench MOSFET and the planar MOSFET of the present invention are used for the low-side switch of the DC/DC converter in embodiment 10 of the present invention.

Detailed Description

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals as a rule, and redundant description thereof will be omitted.

(embodiment 1)

Embodiment 1 of the present invention will be described with reference to fig. 1 to 8. Fig. 1 shows a cross-sectional structure of a planar MOSFET according to embodiment 1 of the present invention. Fig. 2 shows an example of each size of the planar MOSFET according to embodiment 1 of the present invention.

The planar MOSFET of embodiment 1 is planar as shown in fig. 1Type N channel type DMOSFET (double diffused MOSFET) in N⁺On a substrate 1 having N^-Epitaxial layer 2 of N^-A P-type channel layer 3 and N are arranged in the epitaxial layer 2⁺The source region 4 and the body contact region 5 form a P-type polysilicon 7 of a gate electrode via a gate insulating film 6. The P-type polysilicon 7 has a structure in which a part of a portion facing the JFET region between the P-type channel layers 3 is removed, and a tungsten silicide film 8 is formed on the P-type polysilicon 7. The upper and side surfaces of the tungsten silicide film 8 and the side surfaces of the P-type polysilicon 7 are covered with an insulating film 9. The DMOSFET has a source electrode 11 on the surface and a drain electrode 10 on the back surface. The structure of fig. 1 shows a structure in which the gate electrode has a stripe shape, but may have a mesh structure such as a polygonal structure or a trapezoidal structure.

The present embodiment is characterized in that the junction depth of the P-type channel layer 3 is as shallow as 0.25 μm as shown in fig. 2. Therefore, the JFET region between the channel layers can be narrowed (to 0.5 μm in fig. 2), and as a result, the cell pitch can be reduced, and the on-resistance can be reduced. Fig. 7 shows the calculation results of the length (L) of the JFET region and the on-resistance per unit area (Ron · Aa). As shown in fig. 7, if L is made narrower than 0.5 μm, the JFET resistance component becomes large and the on-resistance of the whole starts to increase. Thus, L is not less than 0.5 μm even when it is narrowed.

In the present embodiment, since the P-type channel layer 3 is formed shallow, the dispersion in the lateral direction is small, and the channel length in fig. 2 is as small as 0.1 μm. Therefore, if a gate electrode of N-type polysilicon used as a gate electrode of a general N-channel MOSFET is used, the channel layer is pierced, and as shown in fig. 5, the withstand voltage cannot be maintained. In order to prevent the punch-through, the gate electrode using the P-type polysilicon 7 is the largest feature of the present embodiment. Fig. 3 to 6 are views for explaining a phenomenon that punch-through can be prevented by using a gate electrode of P-type polysilicon 7, and the following description will be made in order.

Fig. 3 shows the difference in the energy bands of the gate electrode, the gate insulating film, and the channel layer in the thermal equilibrium state when the polarities of the polysilicon of the gate electrode are different, and fig. 3(a) shows the energy bands of the gate electrode, the gate insulating film, and the P-type channel layer of the N-type polysilicon in the thermal equilibrium state. The fermi level of the N-type polycrystalline silicon is near the bottom of the conduction band, and in the thermal equilibrium state, the energy band of the P-type channel layer is bent downward on the surface of the gate insulating film as shown in the drawing, and holes on the surface are extracted and depleted. On the other hand, fig. 3(b) shows an energy band when a gate electrode of P-type polysilicon 7 is used as in the present embodiment. The P-type polycrystalline silicon 7 has a fermi level near the top of the valence band, and the energy band of the P-type channel layer 3 is hardly bent in a thermal equilibrium state, and does not extract holes from the surface.

Fig. 4 shows the impurity concentration distribution in the section a-a' of fig. 1 and the calculation results of the hole concentration distribution when N-type polysilicon and P-type polysilicon are used for the gate electrode and Vds is 0V. As shown in fig. 4, when N-type polysilicon is used as the gate electrode, it is understood that the hole concentration on the surface of the P-type channel layer is decreased. On the other hand, in the case where the P-type polycrystalline silicon 7 is used as the gate electrode as in the present embodiment, the hole concentration is decreased by 2 orders or more compared to the impurity concentration due to the influence of the built-in potential of the PN junction, but the hole concentration on the surface of the P-type channel layer 3 is larger than that in the case where the N-type polycrystalline silicon is used as the gate electrode, and it is found that the punch-through of the channel layer can be prevented.

Fig. 5 shows the calculation results of the drain-source withstand voltage when the polarities of the polysilicon of the gate electrodes are different. As shown in fig. 5, in the case of using N-type polysilicon, the channel layer penetrates and the leak current increases, but by using P-type polysilicon 7 as in the present embodiment, it is possible to prevent the penetration of P-type channel layer 3 and obtain a steep breakdown voltage curve.

Fig. 6 shows a two-dimensional distribution of equipotential lines when a voltage of 20V is applied between the drain and the source, in the case where the polarities of the polysilicon of the gate electrodes are different. As shown in FIG. 6(a), in the case of using the N-type polysilicon 13, the equipotential line is extended to N⁺In the source region 4, the P-type channel layer 3 is known to be penetrated. On the other hand, when the P-type polysilicon 7 is used as in the present embodiment shown in fig. 6(b), it is found that the equipotential lines do not reach N⁺The source region 4 can prevent punch-through.

As described above, as is clear from fig. 3 to 6, in the present embodiment, the use of the P-type polysilicon 7 instead of the N-type polysilicon that has been conventionally used can prevent the channel layer from being pierced by making the P-type channel layer 3 shallow.

Another feature of the present embodiment is that a portion of the gate electrode facing the JFET region is removed to reduce the input capacitance of the gate and the feedback capacitance between the gate and the drain. In addition, in the present embodiment, since the size of the gate electrode is as fine as 0.25 μm as shown in fig. 2, there is a problem that the gate resistance becomes large. Therefore, in the present embodiment, the features are: a tungsten silicide film 8 is provided as a metal film on the gate electrode.

Fig. 8 to 12 show an example of a method for manufacturing a planar MOSFET according to the present embodiment including providing a tungsten silicide film on a gate electrode.

First, N shown in FIG. 8(a) is oxidized as shown in FIG. 8(b)⁺N on the substrate 1^-On the surface of the epitaxial layer 2, a gate insulating film 6 is formed. As described later, the gate insulating film 6 may be an oxide film or an oxynitride film formed by oxidation in a nitrogen atmosphere. Further, as shown in fig. 8(c), P-type polysilicon 7 is deposited. As a method for forming the P-type polysilicon 7, the P-type polysilicon 7 may be deposited directly, or after depositing insulating polysilicon, boron (B) or boron difluoride (BF) may be performed₂) Plasma implantation and thermal diffusion are performed to form the P-type polysilicon 7.

Next, as shown in fig. 9(d), a tungsten silicide film 8 as a metal electrode is deposited. Thereafter, as shown in fig. 9(e), a gate structure in which P-type polysilicon 7 and tungsten silicide film 8 are stacked is formed on gate insulating film 6 as shown in fig. 9(f) by a photolithography process using photoresist 17 as a mask and dry etching.

Next, as shown in fig. 10(g), trench lithography (ホト) is performed using the photoresist 17a as a mask. Here, in the conventional planar MOSFET, in order to prevent punch-through, ion implantation is performed from an oblique angle, or ion implantation from an oblique direction called pocket (pocket) implantation may be performed after performing vertical ion implantation, but in the present embodiment, the planar MOSFET is characterized in that: the P-type channel layer 3 is formed by implanting only vertical ions (boron: B) by making the P-type channel layer 3 shallow and preventing punch-through using the P-type polysilicon 7. That is, As shown in fig. 10(h), the P-type channel layer 3 is formed by thermal diffusion, and then, As shown in fig. 10(i), source lithography (ホト) ion (arsenic: As) implantation is performed with the photoresist 17b As a mask.

Next, as shown in fig. 11(j), a protective film formed of the insulating film 9 is deposited. Thereafter, as shown in fig. 11(k), photolithography for obtaining body contact is performed using the photoresist 17c as a mask. Then, as shown in fig. 11(l), ion implantation of boron difluoride is performed.

Next, as shown in FIG. 12(m), N is formed by thermal diffusion⁺Source region 4 and body contact region 5. Finally, as shown in fig. 12(n), after forming a source electrode 11 made of aluminum (Al) on the surface, the back surface is polished, and gold (Au) or the like is evaporated to form a drain electrode 10, thereby completing a planar MOSFET device.

The planar MOSFET of this embodiment can be manufactured by introducing the CMOSFET process. In particular, in order to miniaturize the gate electrode process and to perform the STI process described in the embodiment described later, it is preferable to use the CMOSFET process having a rule of 0.25 μm or less.

(embodiment 2)

Embodiment 2 of the present invention will be described with reference to fig. 13. Fig. 13 shows a cross-sectional structure of a planar MOSFET according to embodiment 2 of the present invention. FIG. 13 is characterized in that: n is alternately arranged in the vertical direction relative to the grid⁺Source region 4 and body contact region 5. By arranging in this way, the cell pitch can be reduced without changing the size of the JFET region, and the on-resistance can be reduced.

(embodiment 3)

Embodiment 3 of the present invention will be described with reference to fig. 14. Fig. 14 shows a cross-sectional structure of a planar MOSFET according to embodiment 3 of the present invention. Fig. 14 is characterized in that: the oxynitride film 14 is used as the gate insulating film. In embodiment 3, P-type polycrystalline silicon 7 is used as the gate electrode, and boron (B) is used as its impurity. In the case of an oxide film which is a normal gate insulating film, if high temperature thermal diffusion is performed after deposition of P-type polysilicon, it is known that a problem of boron punch-through occurs in which boron in the P-type polysilicon passes through the oxide film and reaches a semiconductor substrate. If boron punch-through occurs, the threshold voltage of the MOSFET fluctuates.

As a method for preventing the above-mentioned boron breakthrough, it is known to use dinitrogen monoxide (N)₂O) or Nitric Oxide (NO), ammonia (NH)₃) The oxynitride film 14 may be formed by performing thermal oxidation in an atmosphere of gas or the like to introduce nitrogen into the oxide film.

In the present embodiment, since the P-type polysilicon 7 containing boron is used for the gate electrode, there is a possibility that boron punch-through may occur. Therefore, embodiment 3 is characterized in that: by using the oxynitride film 14 as at least a part of the gate insulating film, boron punch-through can be prevented.

(embodiment 4)

Embodiment 4 of the present invention will be described with reference to fig. 15 and 16. Fig. 15 and 16 show cross-sectional structures of planar MOSFETs according to embodiment 4 of the present invention. The present embodiment is characterized in that: the gate insulating film is thicker in a portion facing the JFET region than in a portion facing the P-type channel layer 3. By thickening a part of the gate insulating film, the effect of reducing the gate-drain feedback capacitance can be obtained.

Fig. 15 and 16 use a different method of forming the above-described thick gate insulating film, characterized in that: in fig. 15, an insulating film as the LOCOS oxide film 15 is formed by a LOCOS (local oxidation of silicon) process, and in fig. 16, an insulating film as the STI oxide film 16 is formed by an STI (shallow trench isolation) process. Both processes may be performed before the gate oxide process shown in fig. 8(b) described above. In the LOCOS process, a nitride film is formed using a mask, and then an oxide film is formed by thermal oxidation, so that it is difficult to fabricate a fine thick film structure.

In this embodiment, since the length of the JFET region is as small as about 0.5 μm, the STI process is preferably used. The STI process is a process generally used in the CMOS process of the rule of 0.25 μm or less, and as shown in fig. 8 to 12, the planar MOSFET of the present embodiment can be manufactured by the CMOSFET process, so that there is no problem in using the STI process.

(embodiment 5)

Embodiment 5 of the present invention will be described with reference to fig. 17. Fig. 17 shows a cross-sectional structure of a planar MOSFET according to embodiment 5 of the present invention. The present embodiment is characterized in that: a dummy gate electrode is provided on a part of a position opposed to the JFET region. The dummy gate electrode is connected to the source electrode, and when the device is reverse biased, the depletion layer also expands from the dummy gate electrode, thereby further reducing the gate-drain capacitance.

When the gate electrode is processed as shown in fig. 9(e), the dummy gate electrode can be formed by leaving the P-type polysilicon 18 and the tungsten silicide film 19 in a part of the region facing the JFET region, and can be formed without adding a new process to the process of embodiment 1.

(embodiment 6)

Embodiment 6 of the present invention will be described with reference to fig. 18. Fig. 18 shows a cross-sectional structure of a planar MOSFET according to embodiment 6 of the present invention. The present embodiment is characterized in that the schottky junction 20 is provided in a part of the JFET region. By forming a part of the JFET region as the schottky junction 20, the depletion layer is expanded from the schottky junction 20 into the JFET region, which has the effect of further reducing the gate-drain capacitance.

Further, since the schottky barrier diode obtained by the schottky junction 20 is built in, it is possible to reduce the conduction loss and recovery loss of the diode in dead time (dead time) by using the schottky barrier diode as a low-side switch of a DC/DC converter in particular.

(embodiment 7)

Embodiment 7 of the present invention will be described with reference to fig. 19. Fig. 19 shows a cross-sectional structure of a planar MOSFET according to embodiment 7 of the present invention. The present embodiment is characterized by the presence of N^-The fabrication of the P-type regions 21a, 21b in the epitaxial layer 2 provides the point of providing a planar MOSFET of super junction structure. By applying the super junction structure, there is an effect that the on-resistance of the MOSFET can be further reduced.

In the manufacturing method shown in embodiment 1, the P-type regions 21a and 21b can be formed by performing ion implantation of boron with high energy in the process of etching and implanting the contact region shown in fig. 11 (l). Although the present embodiment shows an example in which P-type regions 21a and 21b are formed by 2 times of ion implantation, they may be formed by 1 time of ion implantation, or may be formed by more times of ion implantation.

(embodiment 8)

Embodiment 8 of the present invention will be described with reference to fig. 20. Fig. 20 shows a cross-sectional structure of a planar MOSFET according to embodiment 8 of the present invention. The present embodiment is characterized in that a concentration ratio N is provided between the P-type channel layers 3^-The N-type region 22 having a high concentration of the epitaxial layer 2. By inserting the N-type region 22 of the high concentration layer, the on-resistance of the MOSFET can be further reduced.

The example of inserting N type region 22 is the same as the structure described in patent document 1, but in the present embodiment, the impurity concentration of N type region 22 can be further increased by using the gate electrode of P type polysilicon 7 as the gate electrode. That is, since the surface of N type region 22 is depleted by using P type polysilicon 7, even if the impurity concentration of N type region 22 is increased, N type region 22 can be depleted and the withstand voltage is not lowered as compared with the case of using N type polysilicon. Before the gate insulating film 6 is formed, the N-type region 22 may be formed by ion implantation over the entire surface of the device.

(embodiment 9)

Embodiment 9 of the present invention will be described with reference to fig. 21 to 23. Fig. 21 shows a cross-sectional structure of a planar MOSFET according to embodiment 9 of the present invention. In the conventional embodiment, the punch-through of the P-type channel layer 3 is prevented by using the P-type polysilicon 7 as the gate electrode, but in the present embodiment, the punch-through is prevented by: by using both N-type polysilicon 13 as gate electrode and N⁺A shallow N-type layer 12 is provided in the source region 4, to convert N into N⁺The source region 4 is made into a two-stage structure as shown in fig. 21 to prevent punch-through.

Fig. 22 shows the calculation results of the drain-source breakdown voltage in each structure. There is some increase in leakage current compared to the case of using the P-type polysilicon 7, but even if the N-type polysilicon 13 is used as the gate electrode, by using N⁺The structure of the source region 4 is a two-stage structure, which prevents punch-through and provides a steep breakdown voltage curve.

Fig. 23 shows two-dimensional distributions of equipotential lines when a voltage of 20V is applied between the drain and the source in the conventional planar MOSFET and the planar MOSFET according to the present embodiment. As shown in FIG. 23(a), in the conventional structure, the equipotential lines extend to N⁺A source region 4, and as shown in FIG. 23(b), by adding N⁺The source region 4 is formed in a two-stage structure, and it is known that the equipotential line does not reach N⁺The source region 4 can prevent punch-through.

The shallow N-type layer 12 of the present embodiment can be manufactured by the same process as the LDD (lightly doped drain) region used in the CMOS process. Even in the planar MOSFET of the present embodiment, since the planar MOSFET can be manufactured by using a CMOS process as in the manufacturing method of fig. 8 to 12, there is no problem in forming the LDD region.

In addition, the structure of the present embodiment can be similarly applied to the example in which the source region and the body contact region are alternately arranged as shown in embodiment 2, the example in which a portion of the gate insulating film facing the JFET region is thickened as shown in embodiment 4, the example in which the dummy gate electrode is formed as shown in embodiment 5, the example in which the schottky junction is formed as shown in embodiment 6, and the example in which the super junction is formed as shown in embodiment 7.

(embodiment 10)

In embodiment 10 of the present invention, the application of the planar MOSFET described above to a power supply device including a DC/DC converter will be described, and the effects of the application will be described.

Embodiment 10 of the present invention will be described with reference to fig. 24 to 26. Fig. 24 shows a circuit configuration of a non-insulated DC/DC converter included in the power supply device. The non-insulated DC/DC converter includes a control IC31, a drive IC32, a high-side switch 33, a low-side switch 34, a smoothing inductor L, a smoothing capacitor C, and the like, and is connected to the CPU/MPU.

As described above, in the high-side switch 33, the switching loss is a main loss, and in order to reduce the loss, it is important to reduce the gate-drain capacitance (Crss). Further, in the low-side switch 34, it is important to reduce the loss due to self conduction together with reducing the conduction loss, and it is important to reduce the on-resistance and the Crss/Ciss. Here, the planar MOSFET of the present invention reduces on-resistance by reducing the cell size, and also realizes reduction of Crss due to the planar structure.

Fig. 25 shows the calculation results of the drain voltage dependence of the feedback capacitances of the conventional trench MOSFET and the planar MOSFET of the present invention. It is known that the feedback capacitance can be reduced by using a planar structure. Therefore, if this structure is used for the high-side switch 33 of the DC/DC converter, the switching loss can be reduced.

Fig. 26 shows the calculation results of the gate voltage of the low-side switch when the conventional trench MOSFET and the planar MOSFET of the present invention are used for the low-side switch of the DC/DC converter. As shown in fig. 26, in the conventional trench MOSFET, the gate voltage rises to about 1.5V, and the self-turn-on phenomenon occurs. On the other hand, when the planar MOSFET of the present invention is used, the gate voltage does not rise and the self-turn-on phenomenon does not occur because Crss/Ciss can be reduced. Therefore, if the planar MOSFET of the present invention is used for the low-side switch 34, loss due to the self-turn-on phenomenon is not generated, and loss can be reduced.

The invention made by the present inventors has been specifically described above based on the embodiments of the invention, mainly on N-channel planar MOSFETs, but the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. For example, the shallow junction of the channel layer can be applied to a P-channel planar MOSFET, a trench MOSFET, and a lateral MOSFET.

The present invention relates to a power MOSFET, and more particularly, to a structure suitable for realizing a low on-resistance and a low feedback capacitance in a low withstand voltage power MOSFET having a withstand voltage of about 100V or less, a method for manufacturing the same, and a power supply device using the power MOSFET.

Claims (19)

1. An N-channel DMOSFET, comprising:

the gate electrode is formed with a P-type polysilicon electrode.

2. The DMOSFET of claim 1 wherein:

the DMOSFET is a planar MOSFET.

3. The DMOSFET of claim 2 wherein:

the junction depth of the P-type channel layer of the planar MOSFET in the longitudinal direction is 0.5 μm or less.

4. The DMOSFET of claim 3 wherein:

the P-type channel layer is formed by ion implantation and thermal diffusion from a vertical direction with respect to the semiconductor substrate.

5. The DMOSFET of claim 2 wherein:

a portion of the gate electrode facing the JFET region is removed.

6. The DMOSFET of claim 2 wherein:

in the gate electrode of the planar MOSFET, a metal electrode is provided on the P-type polysilicon electrode.

7. The DMOSFET of claim 6 wherein:

the metal electrode is a tungsten silicide film.

8. The DMOSFET of claim 2 wherein:

the source regions and the body contact regions of the planar MOSFET are alternately arranged in parallel in a direction perpendicular to the gate electrode.

9. The DMOSFET of claim 2 wherein:

at least a part of a gate insulating film between the gate electrode and the channel layer of the planar MOSFET is formed with an oxynitride film containing nitrogen in an oxide film.

10. The DMOSFET of claim 2 wherein:

a part of the gate insulating film facing the JFET region of the planar MOSFET is made thicker than a part of the gate insulating film facing the channel layer.

11. The DMOSFET of claim 2 wherein:

in a part of a region of the planar MOSFET facing the JFET region, a dummy gate electrode having the same potential as the source potential is provided via a gate insulating film.

12. The DMOSFET of claim 2 wherein:

a schottky junction is provided in a part of the JFET region of the planar MOSFET.

13. The DMOSFET of claim 2 wherein:

a P-type region for depleting the N-type epitaxial layer is formed in the N-type epitaxial layer of the planar MOSFET.

14. The DMOSFET of claim 2 wherein:

an N-type region having a higher concentration than an N-type epitaxial layer is formed between the P-type channel layers of the planar MOSFET.

15. The DMOSFET of claim 2 wherein:

the manufacturing process of the planar MOSFET adopts a CMOSFET process with the design rule less than or equal to 0.25 mu m.

16. The DMOSFET of claim 2 wherein:

the DMOSFET is applied to a power supply device including a DC/DC converter, and the DMOSFET is used as a high-side switch or a low-side switch of the DC/DC converter.

17. A planar MOSFET, characterized by:

the junction depth of a portion of the source region close to the gate electrode is shallower than the junction depth of the other source regions.

18. The planar MOSFET of claim 17, wherein:

the manufacturing process of the planar MOSFET adopts a CMOSFET process with the design rule less than or equal to 0.25 mu m.

19. The planar MOSFET of claim 17, wherein:

the planar MOSFET is applied to a power supply device including a DC/DC converter, and the planar MOSFET is used as a high-side switch or a low-side switch of the DC/DC converter.