HK1199947B

HK1199947B - Power-saving control circuit and electronic device

Info

Publication number: HK1199947B
Application number: HK15100347.3A
Authority: HK
Inventors: 李东声
Original assignee: 天地融科技股份有限公司
Filing date: 2015-01-13
Publication date: 2018-03-16

Abstract

The present invention provides a power-saving control circuit and electronic device,The power-saving control circuit includes: LDO,LDO includes: power input pinsSwitch pins and power output pins;Power on surge capacitor,Connect one end of the power surge capacitor to the power input pin,Connect the other end to the switch pin;MCU，MCU includes: MCU power pinsMCU control pins;The MCU power pin is connected to the power output pin,MCU control pin connected to switch pin;MCU，Used in normal mode,Triggered by preset triggering conditions to output a low level to the MCU control pin and enter power-saving mode;Among them,The normal mode is the mode in which the MCU outputs a high level to the MCU control pin.The present invention ensures that MCU systems with LDO minimize power consumption in low-power mode, resulting in zero power consumption when the MCU is idle or not in use.The present invention utilizes the enable control function of the LDO switch pin to automatically cut off the power supply to the MCU and restart the power supply under appropriate excitation.

Description

Power saving control circuit and electronic device

Technical Field

The invention relates to the technical field of electronics, in particular to a power-saving control circuit and electronic equipment.

Background

At present, a low power consumption mode is set in the design process of an MCU (Micro Control Unit) chip so as to save more power when the chip is idle. However, in any low power consumption mode, only part of the unused control units are turned off, and the chip still consumes power.

And an LDO (Low Drop-Out Regulator) is designed in the MCU system to provide a stable and proper voltage for the operation of the MCU chip, but in the conventional usage, the output terminal (Vout) of the LDO can only provide a stable output voltage, cannot automatically cut off its output voltage, and even cannot restart the output under proper excitation.

Therefore, how to ensure that the MCU system with LDO reduces power consumption to the maximum extent in the low power mode is an urgent problem to be solved.

Disclosure of Invention

The present invention is directed to solving one of the problems set forth above.

The invention mainly aims to provide a power-saving control circuit;

it is a further object of the present invention to provide an electronic device.

In order to achieve the purpose, the technical scheme of the invention is realized as follows:

one aspect of the present invention provides a power saving control circuit, including: an LDO, the LDO comprising: a power input pin, a switch pin and a power output pin; one end of the power-on impact capacitor is connected with the power input pin, and the other end of the power-on impact capacitor is connected with the switch pin; an MCU, the MCU comprising: an MCU power pin and an MCU control pin; the MCU power pin is connected with the power output pin, and the MCU control pin is connected with the switch pin; the MCU is used for outputting a low level to the MCU control pin to enter a power saving mode under the trigger of a preset trigger condition in a normal mode; and the normal mode is a mode in which the MCU outputs a high level to the MCU control pin.

In addition, the LDO is used for starting to work when the power supply is powered on; and the MCU is also used for outputting a high level to the MCU control pin to enter the normal mode after the LDO starts to work.

In addition, the MCU control pin is connected with the switch pin through a current limiting circuit.

In addition, the MCU control pin is grounded through an anti-jitter circuit.

In addition, the MCU control pin is connected with the switch pin through a current limiting circuit and/or an anti-jitter circuit.

In addition, the power input pin is grounded through a protection circuit.

In addition, the power input pin is grounded through a first capacitor, and the power output pin is grounded through a second capacitor.

In addition, the preset trigger condition is as follows: the MCU non-execution operation time exceeds the preset time.

In addition, the MCU further includes: triggering a pin, wherein the preset triggering condition is as follows: the trigger pin is triggered; or the MCU further comprises: a communication pin, wherein the preset trigger condition is as follows: the communication pin receives a command to enter a power saving mode.

Another aspect of the present invention provides an electronic device including the power saving control circuit.

According to the technical scheme provided by the invention, the MCU system with the LDO can reduce the power consumption to the maximum extent when in a low-power mode, so that the power consumption of the MCU is zero when the MCU is idle or does not need to work. The invention utilizes the enabling control function of the switch pin of the LDO, can automatically cut off the power supply of the MCU and restart the power supply under proper excitation.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on the drawings without creative efforts.

FIG. 1 is a schematic diagram of a power saving control circuit according to the present invention;

fig. 2 is a schematic diagram of a power saving control circuit provided in embodiment 1 of the present invention;

fig. 3 is a schematic diagram of a power saving control circuit according to embodiment 2 of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention are clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, indicate orientations or positional relationships based on those shown in the drawings, and are used only for convenience in describing the present invention and for simplicity in description, and do not indicate or imply that the referenced devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and thus, are not to be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or quantity or location.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.

Fig. 1 shows a schematic diagram of a power saving control circuit of the present invention, and referring to fig. 1, the power saving control circuit of the present invention includes: LDO, power-on impact capacitor and MCU; wherein:

the LDO includes: a power input pin, a switch pin and a power output pin; specifically, the power input pin may be connected to a power supply, and the power supply may be a power supply provided by a battery, and may be located outside the electronic device or inside the electronic device; the power supply can also be the power supply provided by the power supply pin of the USB interface or other interfaces. The entire circuit can be powered by a power supply. In addition, the power supply voltage of the power supply can be 1.8V to 5.5V, and the appropriate power supply voltage can be selected according to different requirements of different electronic equipment; the voltage output by the power output pin after the LDO can also output proper voltage according to different requirements of different electronic equipment.

One end of the power-on impact capacitor is connected with the power input pin, and the other end of the power-on impact capacitor is connected with the switch pin; specifically, when the power input pin is powered on to obtain the power supply voltage instantly, the power-on impact capacitor outputs a short high level to the switch pin of the LDO, so that the LDO starts to work and the power output pin outputs the voltage.

The MCU includes: an MCU power pin and an MCU control pin; the MCU power pin is connected with the power output pin, and the MCU control pin is connected with the switch pin; the MCU is used for outputting a low level to the MCU control pin to enter a power saving mode under the trigger of a preset trigger condition when in a normal mode; and the normal mode is a mode in which the MCU outputs a high level to the MCU control pin. Specifically, after the power-on impact capacitor starts the LDO to work, a power output pin of the LDO outputs a voltage required by the MCU, and at this time, the MCU starts to work and outputs a high level to a MCU control pin, so that a switch pin of the LDO obtains the high level, and the LDO continues to work, that is, the LDO starts to work when the power is turned on; and the MCU outputs high level to the MCU control pin to enter the normal mode after the LDO starts to work. When the electronic equipment needs to enter the power saving mode, the MCU is triggered by a preset trigger condition to output a low level to the MCU control pin to enter the power saving mode, at the moment, the MCU control pin outputs the low level to the switch pin of the LDO, the LDO stops working, the power supply to the MCU is cut off, and the MCU stops working, so that the power failure of the electronic equipment is realized, and the electric energy is saved to the maximum extent. Of course, if the electronic device needs to be powered up again, only the power input pin needs to be powered up again, for example: turning on the switch of the battery, and reinserting the USB interface.

Therefore, the power-saving control circuit can ensure that the power consumption of the MCU system with the LDO is reduced to the maximum extent when the MCU system is in a low power consumption mode, so that the power consumption of the MCU system is zero when the MCU system is idle or does not need to work. The invention utilizes the enabling control function of the switch pin of the LDO, can automatically cut off the power supply of the MCU and restart the power supply under proper excitation.

In addition, when the MCU is triggered to output a low level to the MCU control pin to enter the power saving mode under a preset trigger condition, the preset trigger condition may be, but is not limited to, the following:

the first method is as follows: the preset trigger condition may be: the time when the MCU does not execute the operation exceeds the preset time; specifically, if the MCU exceeds a certain time without any operation, the MCU assumes that the power saving mode can be entered, and if the MCU exceeds a preset time without any operation, a preset trigger condition is formed. Based on the mode, the MCU can automatically enter the power saving mode, and zero power consumption of the MCU is ensured so as to save electric energy.

The second method comprises the following steps: the MCU also includes: triggering a pin; the preset trigger conditions are as follows: the trigger pin is triggered; specifically, the MCU may further include a trigger pin, and the trigger pin may receive a trigger signal, and at this time, a preset trigger condition is formed. For example: when the key is pressed down, a trigger signal is generated, and the trigger pin of the MCU receives the trigger signal generated by the key and is triggered. Based on the mode, the MCU can be manually controlled to enter the power saving mode in idle time, the power supply can be cut off when the MCU is not used, the power consumption of the MCU can be controlled in real time, and electric energy is saved.

The third method comprises the following steps: the MCU also includes: a communication pin; the preset trigger conditions are as follows: the communication pin receives an instruction to enter a power saving mode. Specifically, the MCU may further include a communication pin, where the communication pin may receive various instructions, including an instruction to enter a power saving mode, and at this time, a preset trigger condition is formed. For example: and receiving a command for entering the power saving mode transmitted by the USB interface through a communication pin connected with the USB interface. Based on the mode, the MCU can be manually controlled to enter the power saving mode in idle time, the power supply can be cut off when the MCU is not used, the power consumption of the MCU can be controlled in real time, and electric energy is saved.

In addition, in order to further improve the stability of the power saving control circuit of the present invention, the power saving control circuit of the present invention may further include one or any combination of a current limiting circuit, an anti-jitter circuit, and a protection circuit, and the connection relationship between the respective circuits will be briefly described below, but the present invention is not limited thereto:

the MCU control pin is connected with the switch pin through the current limiting circuit;

the MCU control pin is grounded through the anti-jitter circuit;

the MCU control pin is connected with the switch pin through a current limiting circuit and/or an anti-jitter circuit;

the power input pin is grounded through the protection circuit.

The above current limiting circuit may include a resistor and other elements, the anti-jitter circuit may include a capacitor and other elements, and the protection circuit may include a resistor and/or a capacitor and other elements, but the present invention is not limited to the above elements as long as the functions of the above circuits can be realized.

Meanwhile, in order to ensure the normal work of the LDO, a power input pin of the LDO is grounded through a first capacitor, and a power output pin of the LDO is grounded through a second capacitor.

Hereinafter, two specific implementations of the power saving control circuit of the present invention are provided, but the present invention is not limited to the following two implementations.

Example 1

Fig. 2 is a schematic diagram showing a power saving control circuit provided in embodiment 1 of the present invention, and referring to fig. 2, the power saving control circuit in embodiment 1 of the present invention includes:

the POWER supply is connected with a POWER supply input pin Vin of the LDO, the POWER supply is grounded through a third capacitor C3 and a second resistor (protection circuit) R2 which are connected in parallel, the POWER supply is connected with a switch pin Ven of the LDO through a first capacitor (POWER-on impact capacitor) C1, the switch pin Ven of the LDO is connected with one end of a third resistor (current limiting circuit) R3 through a second capacitor (anti-shake circuit) C2 and a first resistor (protection circuit) R1 which are connected in parallel, the other end of the third resistor (current limiting circuit) R3 is connected with a control pin MCU-POWER of the MCU, a POWER supply output pin Vout of the LDO is grounded through a fourth capacitor C4, and the POWER supply output pin Vout of the LDO is connected with the POWER supply pin MCU-POWER.

Example 2

Fig. 3 is a schematic diagram showing a power saving control circuit provided in embodiment 2 of the present invention, and referring to fig. 3, the power saving control circuit in embodiment 2 of the present invention includes:

the POWER supply is connected with a POWER supply input pin Vin of the LDO, the POWER supply is grounded through a seventh capacitor C7 and a sixth resistor (protection circuit) R6 which are connected in parallel, the POWER supply is connected with a switch pin Ven of the LDO through a fifth capacitor (POWER-on impact capacitor) C5, the switch pin Ven of the LDO is connected with a control pin MCU-POWER of the MCU through a fifth resistor (current limiting circuit) R5, the control pin MCU-POWER of the MCU is grounded through a seventh resistor (protection circuit) R7 and a sixth capacitor (anti-shake circuit) C6 which are connected in series, a POWER supply output pin Vout of the LDO is grounded through an eighth capacitor C8, and the POWER supply output pin Vout of the LDO is connected with the POWER supply pin MCU-POWER.

A brief description of the working principle of the above-described embodiments 1 and 2 is given below:

the principle is illustrated by taking a 5V to 3.3V LDO power supply circuit as an example: when a power supply end is connected with 5V voltage, a power-on impact capacitor supplies a transient high level to a switch pin Ven end of the LDO, so that a Vout end outputs 3.3V, the MCU supplies power at the moment, a high level is supplied to an MCU control pin MCU-POWER after the power-on impact capacitor is started to work, so that the switch pin Ven end has a stable high level, and when the LDO has a stable enabling high level, the MCU stably outputs 3.3V, and the MCU stably works. And when the MCU enters a trigger condition and the LDO is to be closed, a low level is supplied to the MCU control pin MCU-POWER, so that the MCU is powered off. If the MCU is required to restart the operation, the power supply end is required to input the voltage again.

Therefore, the power consumption of the MCU is zero when the MCU is idle or does not need to work, and the low power consumption is realized to the maximum extent.

In addition, the MCU of the invention can set a plurality of power saving modes according to different power saving requirements, for example, power saving modes such as closing partial functions and the like, and the power saving mode pointed out by the invention is the mode with lowest power consumption.

In the present invention, "connected" refers to direct connection or indirect connection, and direct connection may be direct connection between elements, and indirect connection may be indirect connection between elements through other devices which do not affect the function of a circuit.

The invention also provides electronic equipment which comprises the power-saving control circuit disclosed by the invention so as to reduce the power consumption of the electronic equipment and save energy. The electronic device may be an electronic password device such as a USB KEY, an audio KEY, a bluetooth KEY, an OTP, and the like, and may have one or more functions such as electronic signature, data encryption/decryption, certificate authentication, dynamic password generation, and the like.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made in the above embodiments by those of ordinary skill in the art without departing from the principle and spirit of the present invention. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims

1. A power saving control circuit, comprising:

an LDO, the LDO comprising: a power input pin, a switch pin and a power output pin;

one end of the power-on impact capacitor is connected with the power input pin, and the other end of the power-on impact capacitor is connected with the switch pin;

an MCU, the MCU comprising: an MCU power pin and an MCU control pin; the MCU power pin is connected with the power output pin, and the MCU control pin is connected with the switch pin;

the MCU is used for outputting a low level to the MCU control pin to enter a power saving mode under the trigger of a preset trigger condition in a normal mode; and the normal mode is a mode in which the MCU outputs a high level to the MCU control pin.

2. The power saving control circuit according to claim 1,

the LDO is used for starting to work when the power supply is powered on;

and the MCU is also used for outputting a high level to the MCU control pin to enter the normal mode after the LDO starts to work.

3. The power saving control circuit according to claim 1 or 2,

the MCU control pin is connected with the switch pin through a current limiting circuit;

the MCU control pin is grounded through the anti-jitter circuit.

4. The power saving control circuit according to claim 1 or 2,

the MCU control pin is grounded through the anti-jitter circuit.

5. The power saving control circuit according to claim 1 or 2,

the MCU control pin is connected with the switch pin through a current limiting circuit and/or an anti-jitter circuit.

6. The power saving control circuit according to claim 1 or 2,

the power input pin is grounded through the protection circuit.

7. The power saving control circuit according to claim 3,

the power input pin is grounded through the protection circuit.

8. The power saving control circuit according to claim 4,

the power input pin is grounded through the protection circuit.

9. The power saving control circuit according to claim 5,

the power input pin is grounded through the protection circuit.

10. The power saving control circuit according to claim 1 or 2,

the power input pin is grounded through a first capacitor, and the power output pin is grounded through a second capacitor.

11. The power saving control circuit according to claim 3,

12. The power saving control circuit according to claim 4,

13. The power saving control circuit according to claim 5,

14. The power saving control circuit according to claim 6,

15. The power saving control circuit according to claim 1 or 2,

the preset trigger conditions are as follows: the MCU non-execution operation time exceeds the preset time.

16. The power saving control circuit according to claim 3,

17. The power saving control circuit according to claim 4,

18. The power saving control circuit according to claim 5,

19. The power saving control circuit according to claim 6,

20. The power saving control circuit according to claim 10,

21. The power saving control circuit according to claim 1 or 2,

the MCU further comprises: triggering a pin, wherein the preset triggering condition is as follows: the trigger pin is triggered; or

The MCU further comprises: a communication pin, wherein the preset trigger condition is as follows: the communication pin receives a command to enter a power saving mode.

22. The power saving control circuit according to claim 3,

23. The power saving control circuit according to claim 4,

24. The power saving control circuit according to claim 5,

25. The power saving control circuit according to claim 6,

26. The power saving control circuit according to claim 10,

27. An electronic device characterized by comprising the power saving control circuit according to any one of claims 1 to 26.